Method, device and computer readable medium for detecting read / write duration of DRAM

Abstract

This invention provides a method, apparatus, device, and computer-readable medium for detecting DRAM read / write duration. The method includes allocating a buffer of preset capacity to a target address for read / write speed detection; performing a preset number of read / write operations and recording the start and end times of each operation; determining the read / write duration based on the start and end times; and filtering the read / write duration. This embodiment, by performing read / write speed detection on a target address with a preset capacity in the buffer, can detect read / write speeds for different addresses and capacities, making the detection results more targeted. By performing multiple read / write operations, obtaining the read / write duration of each operation, and then filtering the read / write duration, the accuracy of the detection is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, specifically to a method, apparatus, device, and computer-readable medium for detecting the read / write duration of DRAM. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a computer memory technology used for temporary storage and access to data. DRAM offers advantages such as high-density storage and low cost, making it a commonly used primary memory type in computer systems. However, compared to Static Random Access Memory (SRAM), it has the disadvantage of slower read and write speeds.

[0003] In the process of continuous improvement and upgrading of DRAM, improving read and write speed is one of the key focuses, so the testing of read and write speed has become particularly important. Summary of the Invention

[0004] The summary section of this invention provides a brief overview of the concepts, which will be described in detail in the detailed description section that follows. This summary section is not intended to identify key or essential features of the claimed invention, nor is it intended to limit the scope of the claimed invention.

[0005] Some embodiments of the present invention provide a method, apparatus, device, and computer-readable medium for detecting DRAM read / write duration to address the technical problems mentioned in the background section above.

[0006] In a first aspect, some embodiments of the present invention provide a method for detecting the read / write duration of DRAM. The method includes: allocating a buffer of a preset capacity to a target address for read / write speed detection; performing a preset number of read / write operations and recording the start and end times of each read / write operation; determining the read / write duration based on the start and end times, and filtering the read / write duration.

[0007] Secondly, some embodiments of the present invention provide a DRAM read / write duration detection device, the device comprising: an allocation unit configured to allocate a buffer of a preset capacity to a target address for read / write speed detection; a recording unit configured to perform a preset number of read / write operations and record the start and end times of each read / write operation; and a screening unit configured to determine the read / write duration based on the start and end times and screen the read / write duration.

[0008] Thirdly, embodiments of this application provide an electronic device, which includes: one or more processors; a storage device for storing one or more programs; and when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any implementation of the first aspect.

[0009] Fourthly, embodiments of this application provide a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the method as described in any of the implementations of the first aspect.

[0010] Fifthly, some embodiments of the present invention provide a computer program product, including a computer program that, when executed by a processor, implements the method described in any of the implementations of the first aspect above.

[0011] The above embodiments of the present invention have the following beneficial effects: By using the DRAM read / write time detection method of the present invention to detect the read / write speed at a target address with a preset capacity in the buffer, the read / write speed can be detected under different address and capacity scenarios, making the detection results more targeted.

[0012] By performing multiple read and write operations, the read and write duration of each operation is obtained. The read and write durations are then filtered to improve the accuracy of the detection. Attached Figure Description

[0013] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0014] Figure 1 This is a flowchart of some embodiments of the DRAM read / write duration detection method according to the present invention;

[0015] Figure 2 These are schematic diagrams illustrating the structure of some embodiments of the DRAM read / write duration detection device according to the present invention;

[0016] Figure 3 This is a schematic diagram of the structure of an electronic device suitable for implementing some embodiments of the present invention. Detailed Implementation

[0017] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0019] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they may refer to a fixed connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0020] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] Please refer to the following first. Figure 1 The flowchart 100 illustrates some embodiments of a DRAM read / write duration detection method according to the present invention. The DRAM read / write duration detection method includes the following steps:

[0022] Step 101: Allocate a buffer of preset capacity for the target address for read / write speed detection.

[0023] In some embodiments, the subject executing the method may be an electronic device. This electronic device can be hardware or software. When the electronic device is hardware, it can be implemented as a distributed cluster of multiple servers or terminal devices, or as a single server or a single terminal device. When the electronic device is software, it can be installed in the hardware devices listed above. It can be implemented as, for example, multiple software programs or software modules used to provide distributed services, or as a single software program or software module. No specific limitations are imposed here.

[0024] The electronic device can divide the DRAM buffer into multiple intervals with a preset capacity. Read and write speeds are then tested on the addresses and target addresses within the selected intervals. Test data can be iterated over to the aforementioned target address.

[0025] It should be noted that the preset capacity mentioned above can be adjusted according to actual conditions or testing needs. For example, 1M or 10M can be used to obtain the read and write speed of the target address under different capacity scenarios.

[0026] Step 102: Perform a preset number of read and write operations and record the start and end times of each read and write operation.

[0027] In some embodiments, the operator can set the preset number of operations, such as 100 or 1000. The electronic device records the start and end times of each read / write operation. As an example, the start and end times of read / write operations can be recorded by connecting to DRAM via ATE (Automatic Test Equipment), MCU (Microcontroller Unit), or FPGA (Field Programmable Gate Array).

[0028] Step 103: Determine the read / write duration based on the start and end times, and then filter the read / write duration.

[0029] In some embodiments, the electronic device subtracts the start and end times of each read / write operation or directly obtains the read / write duration using devices such as the ATE described above. Next, the electronic device filters the multiple read / write durations to improve detection accuracy.

[0030] In some alternative implementations of certain embodiments, the following steps may be used during the screening process:

[0031] First, the acquired read / write durations are sequenced and numbered to obtain a sequence number set. For example, the read / write durations are sorted according to the order in which they were acquired. For instance, if 100 read / write durations are acquired, they are sorted from 1 to 100 to obtain the sequence number set.

[0032] Second, generate the correspondence curve between the above sequence number set and the above multiple read / write durations. Specifically, a coordinate system can be established using the hundred sequences in the above sequence number set as the horizontal axis and the hundred read / write durations as the vertical axis, thereby generating the correspondence curve between sequence number and read / write duration.

[0033] Third, the above-mentioned correspondence curves are fitted to obtain a fitted curve. It should be noted that the sum of the squares of the differences between the values ​​of the multiple read / write durations in the correspondence curve and the values ​​of the corresponding points in the fitted curve are minimized. For example, the best fitting effect is achieved when the sum of the squares of the differences between the values ​​of the 100 read / write durations in the correspondence curve and the values ​​of the corresponding points in the fitted curve is minimized.

[0034] Fourth, determine the difference between the value of each read / write duration in the corresponding relationship curve and the value of the corresponding point in the fitted curve, thus obtaining a set of differences. Specifically, determine the difference between the value of each read / write duration in the corresponding relationship curve and the value of the corresponding index on the vertical axis of the fitted curve. This results in a set of 100 differences.

[0035] Fifth, sort the differences in the above difference set according to their numerical values. This will result in a set of 100 differences arranged by their numerical values.

[0036] Sixth, the differences in the aforementioned set of differences are eliminated according to a preset numerical elimination rate. Those skilled in the art can determine the preset numerical elimination rate based on the actual situation. For example, the elimination rate could be 10%, which could be used to extract multiple differences from the aforementioned 100 differences.

[0037] Seventh, the data corresponding to the differences in the above difference set after removal are taken as valid data.

[0038] Eighth, use the above-mentioned valid data as the detection data for read and write operations.

[0039] Ninth, determine the read / write duration corresponding to the difference removed in step seven, and check whether this read / write duration exceeds a preset threshold. If it does, mark the corresponding acquisition timing of the read / write duration and provide feedback as special detection data to reflect the read / write function of the corresponding target address. This makes the detection process more targeted.

[0040] The aforementioned preset thresholds can be determined by those skilled in the art based on design requirements or actual circumstances.

[0041] The aforementioned preset threshold can also be obtained by analyzing read / write durations using an AI chip. The machine learning model carried by this AI chip is trained using a set of training samples.

[0042] As an example, a machine learning model can be obtained by performing the following training steps based on a training sample set: Inputting the read / write duration of at least one training sample in the training sample set into an initial machine learning model to obtain a corresponding preset threshold; comparing the preset threshold corresponding to the read / write duration of each of the at least one training sample with the corresponding preset threshold; determining the prediction accuracy of the initial machine learning model based on the comparison result; determining whether the prediction accuracy is greater than a preset accuracy threshold; in response to determining that the accuracy is greater than the preset accuracy threshold, using the initial machine learning model as the trained machine learning model; in response to determining that the accuracy is not greater than the preset accuracy threshold, adjusting the parameters of the initial machine learning model, and using unused training samples to form a training sample set, using the adjusted initial machine learning model as the initial machine learning model, and performing the above training steps again. It is understood that after the above training, the machine learning model can be used to represent the correspondence between read / write duration and preset thresholds. The aforementioned machine learning model can be a convolutional neural network model.

[0043] As an example, the aforementioned machine learning model may include read / write durations and a correspondence table. The correspondence table can be a table created by someone skilled in the art based on the correspondence between a large number of read / write durations and preset thresholds. Thus, the read / write duration is sequentially compared with multiple read / write durations in the correspondence table. If a read / write duration in the correspondence table is the same as or similar to the given read / write duration, the preset threshold corresponding to that read / write duration in the correspondence table is used as the preset threshold indicated by that read / write duration. This allows for the determination of a preset threshold based on the read / write duration.

[0044] As another example, the initial machine learning model mentioned above can be an untrained deep learning model or a deep learning model that has not been fully trained. Each layer of the initial deep learning model can have initial parameters, which can be continuously adjusted during the training process. The initial deep learning model can be various types of untrained or under-trained artificial neural networks, or a model obtained by combining multiple untrained or under-trained artificial neural networks. For example, the initial deep learning model can be an untrained convolutional neural network, an untrained recurrent neural network, or a model obtained by combining untrained convolutional neural networks, untrained recurrent neural networks, and untrained fully connected layers.

[0045] Further reference Figure 2 As a response Figure 1 The present invention provides some embodiments of a DRAM read / write duration detection device, which are similar to the implementation of the method shown. Figure 1 Corresponding to the method embodiments shown, the device can be specifically applied to various electronic devices.

[0046] like Figure 2 As shown, a DRAM read / write duration detection device 200 in some embodiments includes: an allocation unit 201, a recording unit 202, and a screening unit 203. The allocation unit 201 is configured to allocate a buffer of a preset size for a target address for read / write speed detection. The recording unit 202 is configured to perform a preset number of read / write operations and record the start and end times of each read / write operation. The screening unit 203 is configured to determine the read / write duration based on the start and end times and screen the read / write duration.

[0047] It is understandable that the units described in the device 200 are related to the reference. Figure 1 The steps in the described method correspond to each other. Therefore, the operations, features, and beneficial effects described above for the method also apply to the device 200 and the units contained therein, and will not be repeated here.

[0048] The following is for reference. Figure 3 It shows a schematic diagram of the structure of an electronic device 300 suitable for implementing some embodiments of the present invention. Figure 3 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of the present invention.

[0049] like Figure 3 As shown, the electronic device 300 may include a processing unit (also referred to as a processor, such as a central processing unit, graphics processor, etc.) 301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a storage device 308 into a random access memory (RAM) 303. The RAM 303 also stores various programs and data required for the operation of the electronic device 300. The processing unit 301, ROM 302, and RAM 303 are interconnected via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0050] Typically, the following devices can be connected to I / O interface 305: input devices 306 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 307 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 308 including, for example, magnetic tapes, hard disks, etc.; and communication devices 309. Communication device 309 allows electronic device 300 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 3 An electronic device 300 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Figure 3 Each box shown can represent a device or multiple devices as needed.

[0051] Some embodiments of the present invention also provide a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements any of the above-described methods for detecting DRAM read / write duration.

[0052] In particular, according to some embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of the present invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 309, or installed from a storage device 308, or installed from a ROM 302. When the computer program is executed by the processing device 301, it performs the functions defined in the methods of some embodiments of the present invention.

[0053] It should be noted that the computer-readable medium described in some embodiments of the present invention may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0054] In some embodiments of the present invention, the computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of the present invention, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof.

[0055] A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0056] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0057] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to: allocate a buffer of a preset size at a target address for read / write speed detection; perform a preset number of read / write operations and record the start and end times of each read / write operation; determine the read / write duration based on the start and end times, and filter the read / write duration.

[0058] Computer program code for performing operations of some embodiments of the present invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0059] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0060] The units described in some embodiments of the present invention can be implemented in software or in hardware. The described units can also be located in a processor; for example, a processor may be described as including an allocation unit, a recording unit, and a screening unit. The names of these units do not necessarily limit the unit itself; for example, an allocation unit may also be described as "a unit for detecting read / write speeds by allocating a buffer of preset size to a target address."

[0061] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0062] Some embodiments of the present invention also provide a computer program product, including a computer program that, when executed by a processor, implements any of the above-described methods for detecting DRAM read / write duration.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for detecting read / write duration of DRAM, characterized in that, The method includes: A buffer of preset size allocated to the target address is used for read / write speed detection; Perform a preset number of read and write operations, and record the start and end times of each read and write operation; The read / write duration is determined based on the start and end times, and the read / write duration is then filtered out. Specifically, the steps are as follows: The multiple read and write durations are used to obtain the timing setting sequence number, resulting in a sequence number set; Generate the correspondence curve between the sequence number set and the multiple read / write durations; The corresponding relationship curve is fitted to obtain a fitted curve; The difference between the value of each read / write duration in the corresponding relationship curve and the value of the point corresponding to that value in the fitted curve is determined to obtain a set of differences; Sort the differences in the difference set according to their numerical values; The differences in the difference set are removed according to a preset numerical removal rate. The read / write durations corresponding to the differences in the set of differences after removal are taken as valid data.

2. The DRAM read / write duration detection method according to claim 1, characterized in that, The process of determining read / write durations based on the start and end times, and then filtering the read / write durations, also includes: Determine whether the read / write time corresponding to the excluded difference exceeds the preset threshold; If so, the timing of the read / write duration markers will be obtained and then fed back.

3. The DRAM read / write duration detection method according to claim 2, characterized in that, The preset threshold is obtained by analyzing the read and write time through an artificial intelligence chip, wherein the machine learning model carried by the artificial intelligence chip is trained through a set of training samples.

4. The DRAM read / write duration detection method according to claim 3, characterized in that, The training sample set includes sample read / write duration and sample preset threshold. The machine learning model is trained using the sample read / write duration as input and the sample preset threshold as the expected output.

5. A DRAM read / write duration detection device, characterized in that, include: The allocation unit is configured as a buffer of a preset size for allocating target addresses for read / write speed detection; The recording unit is configured to perform a preset number of read and write operations and record the start and end times of each read and write operation; The screening unit is configured to determine the read / write duration based on the start and end times, and to screen the read / write duration, specifically through the following steps: The multiple read and write durations are used to obtain the timing setting sequence number, resulting in a sequence number set; Generate the correspondence curve between the sequence number set and the multiple read / write durations; The corresponding relationship curve is fitted to obtain a fitted curve; The difference between the value of each read / write duration in the corresponding relationship curve and the value of the point corresponding to that value in the fitted curve is determined to obtain a set of differences; Sort the differences in the difference set according to their numerical values; The differences in the difference set are removed according to a preset numerical removal rate. The read / write durations corresponding to the differences in the set of differences after removal are taken as valid data.

6. An electronic device, characterized in that, include: One or more processors; Storage device, on which one or more programs are stored, When the one or more programs are executed by the one or more processors, the one or more processors are able to implement the DRAM read / write duration detection method as described in any one of claims 1-4.

7. A computer-readable medium, characterized in that, It stores a computer program, wherein when the program is executed by a processor, it can implement the DRAM read / write duration detection method as described in any one of claims 1-4.

8. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, can implement the DRAM read / write duration detection method as described in any one of claims 1-4.

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