Data reading method and device of solid-state memory, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a data reading method and device for a solid-state memory, a storage medium and electronic equipment, and the data reading method for the solid-state memory comprises the steps: obtaining a data reading instruction carrying data attribute information; wherein the data reading instruction is used for reading matched data matched with the data attribute information from a storage unit of the solid-state memory; reading matched data matched with the data attribute information from the storage unit based on a set initial reference voltage; carrying out correction processing on the matched data; and in the process of correcting the matched data, adjusting the initial reference voltage, reading the matched data matched with the data attribute information from the storage unit again based on the adjusted initial reference voltage, and correcting the reread matched data to obtain the corrected matched data. And stopping reading the matched data until a correction result obtained by performing correction processing on the matched data meets a data error rate condition. And the data reading efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technologies, and more particularly, to a method and apparatus for reading data of a solid-state memory, a storage medium, and an electronic device. Background Art

[0002] With the continuous increase in data volume and the growing storage demand, the solid-state drive (SSD) market has shown a significant growth trend. Users have higher and higher requirements for the performance of SSDs, including faster data transfer speeds, higher storage densities, and better durability. How to balance both the data transfer speed and ensure the reliability and lifespan of solid-state drives has become the focus of SSD firmware development. Among them, the read retry (a method of improving the data reliability of SSDs by adjusting the reference voltage axis and re-reading) operation is a way to sacrifice data transfer speed to extend the lifespan of solid-state drives.

[0003] Due to some physical characteristics of current NAND (NOT AND Flash, a type of non-volatile memory) flash memory chips, the threshold voltage (VTH) of storage cells may change over time, resulting in bit flips in some cells (referring to a storage unit of NAND) when reading NAND data. Moreover, as the number of P / E (abbreviation for write and erase operations on NAND) cycles increases, the number of cells with bit flips also increases.

[0004] Currently, the commonly used error correction method is to first perform ECC (a module for correcting bit flips in data) error correction. When the number of bit flips exceeds the error correction capability of ECC, the threshold voltage is then adjusted for read retry. Read Retry attempts to find a suitable reference voltage (VREF) value by repeating the read operation. This reference voltage value can make the RBER of the page less than or equal to the error correction capability of ECC, thereby correctly reading the data and avoiding data loss or damage.

[0005] However, although read retry is very important for ensuring the data reliability of SSDs and plays an important role in the service life of SSDs, the read retry operation also incurs performance overhead because each read retry takes a long time, resulting in low data reading efficiency of solid-state memories. Summary of the Invention

[0006] The embodiments of the present application provide a method and apparatus for reading data of a solid-state memory, a storage medium, and an electronic device, so as to at least solve the problem of low data reading efficiency of solid-state memories in related technologies.

[0007] According to an embodiment of the present application, a method for reading data of a solid-state memory is provided, including: obtaining a data reading instruction carrying data attribute information; wherein, the data reading instruction is used to read matching data matching the data attribute information from a storage unit of the solid-state memory; reading, based on a set initial reference voltage, the matching data matching the data attribute information from the storage unit; performing correction processing on the matching data; during the process of performing correction processing on the matching data, adjusting the initial reference voltage, based on the adjusted initial reference voltage, re-reading the matching data matching the data attribute information from the storage unit, and performing correction processing on the re-read matching data, until the reading of the matching data stops when the correction result obtained by performing correction processing on the matching data meets the data error rate condition.

[0008] In an exemplary embodiment, the data attribute information includes address information of the matching data to be read; the reading, based on a set initial reference voltage, of the matching data matching the data attribute information from the storage unit includes: translating the address information of the matching data to be read to obtain a physical address of the matching data to be read in the storage unit; matching the physical address with storage area addresses of multiple data storage areas of the storage unit, and determining a target data storage area corresponding to the storage area address matching the physical address as the target data storage area of the matching data to be read; loading the set initial reference voltage to the target data storage area, determining a storage area state of the target data storage area, and reading the matching data from the target data storage area according to the storage area state; determining a scratch register associated with the target data storage area, and storing the read matching data in the scratch register; when it is determined that the data storage amount in the scratch register reaches a set data storage amount threshold, sending the matching data in the scratch register to a transmission queue; transmitting the matching data in the transmission queue to a dynamic random access memory unit of the solid-state memory by means of direct memory access; wherein, the matching data used when performing correction processing on the matching data is obtained from the dynamic random access memory unit.

[0009] In an exemplary embodiment, the correcting process for the matching data includes: starting a correction process set for the correction process, reading the matching data from the dynamic random access memory through the correction process; segmenting the matching data according to the correction process to obtain multiple segments of matching sub-data; encoding the multiple segments of matching sub-data according to the correction process to obtain encoding results corresponding to the multiple segments of matching sub-data respectively; generating check codes corresponding to the respective encoding results according to the correction process; and obtaining a correction result of the matching data according to the respective check codes.

[0010] In an exemplary embodiment, the adjusting the initial reference voltage and re-reading the matching data that matches the data attribute information from the storage unit based on the adjusted initial reference voltage includes: selecting an adjustment reference value according to a set reference voltage adjustment range; increasing or decreasing the initial reference voltage based on the adjustment reference value to obtain an adjusted initial reference voltage; and re-reading the matching data that matches the data attribute information from the storage unit based on the adjusted initial reference voltage.

[0011] In an exemplary embodiment, during the process of correcting the matching data, adjusting the initial reference voltage and re-reading the matching data that matches the data attribute information from the storage unit based on the adjusted initial reference voltage includes: starting a data re-reading process set for the data re-reading process; and through the data re-reading process, adjusting the initial reference voltage and re-reading the matching data that matches the data attribute information from the storage unit based on the adjusted initial reference voltage.

[0012] In an exemplary embodiment, stopping the reading of the matching data until the correction result obtained by correcting the matching data meets the data error rate condition includes: comparing the correction result of the matching data with a preset target correction result to determine the error rate of the correction result; and stopping the reading of the matching data when the error rate is less than or equal to a set error rate threshold.

[0013] In an exemplary embodiment, comparing the correction result of the matching data with a preset target correction result to determine the error rate of the correction result includes: determining multiple check codes according to the correction result, and determining multiple target check codes according to the target correction result; counting the total number of the multiple check codes, and counting the number of error codes among the multiple check codes; wherein the number of error codes is determined by sequentially comparing the multiple check codes with the multiple target check codes; and determining the error rate of the correction result according to the number of error codes and the total number.

[0014] According to another embodiment of the present application, there is provided a data reading device for a solid-state memory, including: an acquisition module configured to acquire a data reading instruction carrying data attribute information; wherein, the data reading instruction is used to read matching data matching the data attribute information from a storage unit of the solid-state memory; a reading module configured to read, based on a set initial reference voltage, the matching data matching the data attribute information from the storage unit; a processing module configured to perform a correction process on the matching data; the reading module is further configured to, during the process of performing the correction process on the matching data, adjust the initial reference voltage, read, based on the adjusted initial reference voltage, the matching data matching the data attribute information from the storage unit again, and perform a correction process on the re-read matching data, until the reading of the matching data stops when the correction result obtained by performing the correction process on the matching data meets the data error rate condition.

[0015] According to still another embodiment of the present application, there is further provided a computer-readable storage medium having a computer program stored therein, wherein the computer program is configured to execute the steps in any one of the above method embodiments when running.

[0016] According to still another embodiment of the present application, there is further provided an electronic device including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0017] According to still another embodiment of the present application, there is further provided a computer program product including a computer program, and the computer program, when executed by a processor, implements the steps in any one of the above method embodiments.

[0018] Through the present application, a data reading instruction carrying data attribute information is obtained; wherein, the data reading instruction is used to read matching data that matches the data attribute information from a storage unit of the solid-state memory, and based on a set initial reference voltage, read the matching data that matches the data attribute information from the storage unit; further, perform calibration processing on the matching data; and during the calibration processing of the matching data, adjust the initial reference voltage, and based on the adjusted initial reference voltage, re-read the matching data that matches the data attribute information from the storage unit, and perform calibration processing on the matching data based on the re-read matching data until the calibration result obtained by the calibration processing of the matching data meets the data error rate condition, and then stop reading the matching data. The present application can start reading the matching data during the calibration processing of the matching data, rather than waiting for the calibration result of the calibration processing to start reading the matching data, saving the waiting time and effectively improving the data reading efficiency. Description of the Drawings

[0019] Figure 1 is a hardware structure block diagram of a computer terminal for a data reading method of a solid-state memory according to an embodiment of the present application;

[0020] Figure 2 is a flowchart of a data reading method of a solid-state memory according to an embodiment of the present application;

[0021] Figure 3 is a data reading flowchart in the related art;

[0022] Figure 4 is a data re-reading flowchart in the related art;

[0023] Figure 5 is a data re-reading flowchart of a data reading method of a solid-state memory according to an embodiment of the present application;

[0024] Figure 6 is a structure block diagram of a data reading device of a solid-state memory according to an embodiment of the present application. Detailed Embodiments

[0025] The embodiments of the present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0026] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present application are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence.

[0027] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a computer terminal as an example,Figure 1 It is a hardware block diagram of a computer terminal for a data reading method of a solid-state memory according to an embodiment of the present application. As Figure 1 shown, the computer terminal may include one or more ( Figure 1 only one is shown in the figure) processors 102 (the processor 102 may include, but is not limited to, processing devices such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. Among them, the above computer terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those of ordinary skill in the art can understand that Figure 1 the structure shown is only schematic and does not limit the structure of the above computer terminal. For example, the computer terminal may further include more or fewer components than Figure 1 shown in the figure, or have a different configuration from Figure 1 shown in the figure.

[0028] The memory 104 can be used to store computer programs. For example, software programs and modules of application software, such as the computer program corresponding to the load resource allocation method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implements the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some instances, the memory 104 may further include a memory remotely set relative to the processor 102, and these remote memories can be connected to the server through a network. Examples of the above network include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0029] The transmission device 106 is used to receive or send data via a network. Specific examples of the above network may include a wireless network provided by a communication provider of the computer terminal. In one instance, the transmission device 106 includes a network adapter (abbreviated as NIC), which can be connected to other network devices through a base station and thus can communicate with the Internet. In one instance, the transmission device 106 may be a radio frequency (abbreviated as RF) module, which is used to communicate with the Internet wirelessly.

[0030] Figure 2 It is a flowchart of a data reading method of a solid-state memory according to an embodiment of the present application. Taking the application of this method to an SSD controller as an example, a solid-state memory is deployed on a computer terminal, and the solid-state memory includes an SSD controller. As Figure 2 shown, the process includes the following steps:

[0031] Step S202: Obtain a data reading instruction carrying data attribute information; wherein, the data reading instruction is used to read matching data that matches the data attribute information from a storage unit of the solid-state memory.

[0032] It should be noted that the data attribute information is information describing the characteristics, storage location, or status of the matching data to be read. In the embodiments of the present application, the data attribute information may refer to the address information of the matching data to be read. According to this address information, the specific location of the storage unit of the solid-state memory where the matching data to be read is located can be determined, and then the reading of the matching data can be carried out.

[0033] Step S204: Based on a set initial reference voltage, read matching data that matches the data attribute information from the storage unit.

[0034] In some exemplary embodiments, the data attribute information includes the address information of the matching data to be read; the reading of the matching data that matches the data attribute information from the storage unit based on the set initial reference voltage includes: translating the address information of the matching data to be read to obtain the physical address of the matching data to be read in the storage unit; matching the physical address with the storage area addresses of multiple data storage areas of the storage unit, and determining the data storage area corresponding to the storage area address that matches the physical address as the target data storage area of the matching data to be read; loading the set initial reference voltage to the target data storage area, determining the storage area state of the target data storage area, and reading the matching data from the target data storage area according to the storage area state; determining a scratch register associated with the target data storage area, and storing the read matching data in the scratch register; in the case where it is determined that the data storage amount in the scratch register reaches a set data storage amount threshold, sending the matching data in the scratch register to a transmission queue; transmitting the matching data in the transmission queue to a dynamic random access memory unit of the solid-state memory by means of direct memory access; wherein, the matching data used for calibration processing of the matching data is obtained from the dynamic random access memory unit.

[0035] It should be noted that after determining the target data storage area, the set initial reference voltage can be applied to the reading operation of the target data storage area. The initial reference voltage is a key parameter when reading data, and is used to distinguish the charge state of the target data storage area, so as to accurately read the data. After loading the initial reference voltage, the state of the target data storage area can be checked to ensure that the reading operation is carried out under the correct conditions.

[0036] Among them, the temporary register refers to the page register, which is used to store the matching data read from the storage unit. Each time the matching data read from the target data storage area will be first stored in the page register. Since the matching data read from the target data storage area is page-based, that is, the entire page of matching data is read. If a single-byte data exchange is directly performed with the external device every time after reading the matching data, the efficiency will be relatively low. Therefore, the read data can be first stored in the page register, and when the data storage amount in the page register reaches the data storage amount threshold, the transmission can be carried out, which can improve the data processing efficiency.

[0037] Among them, the direct storage and transmission method specifically refers to DMA (a method of data transmission without the access of the CPU), through which the burden on the CPU (Central Processing Unit) can be reduced, and the technical effect of high-speed transmission can also be achieved.

[0038] The dynamic random storage unit is DDR (Double Data Rate Synchronous Dynamic Random Access Memory).

[0039] It can be understood that the attribute information includes the address information of the matching data to be read. After the matching data is read, the address information can be translated to further determine the physical address of the matching data to be read in the storage unit.

[0040] In the above embodiments, during the process of reading the matching data, first determine the physical address of the matching data, then locate the target data storage area where the matching data is located, read the matching data from the target data storage area, and store the read matching data in the temporary register. When the data storage amount in the temporary register reaches the set data storage amount threshold, the matching data is sent to the transmission queue, which can effectively improve the data processing efficiency. Further, the matching data is transmitted to the dynamic random storage unit by the direct storage and transmission method, effectively improving the data reading efficiency.

[0041] Step S206, perform correction processing on the matching data.

[0042] Among them, performing correction processing on the matching data is a process of performing error correction processing on the matching data to obtain a correction result.

[0043] It can be understood that before storing any data into the storage unit of the SSD, for any data, a corresponding target check code can be generated. By comparing the correction result with the target check code, it can be determined whether the correction result of the check processing meets the requirements.

[0044] In some exemplary embodiments, the correcting the matching data includes: starting a correction processing process set for the correction processing, reading the matching data from the dynamic random access memory through the correction processing process; segmenting the matching data according to the correction processing process to obtain multiple segments of matching sub-data; encoding the multiple segments of matching sub-data according to the correction processing process to obtain encoding results respectively corresponding to the multiple segments of matching sub-data; generating check codes respectively corresponding to the encoding results according to the correction processing process; and obtaining the correction result of the matching data according to the check codes.

[0045] Specifically, the matching data read from the storage unit is stored in the dynamic random access memory, and when correcting the matching data, it is read from the dynamic random access memory. For the matching data, the matching data can be represented in the form of binary bits, and then the matching data is segmented to obtain multiple segments of matching sub-data. For each segment of matching sub-data, it is encoded to obtain an encoding result. Further, check codes respectively corresponding to the encoding results are generated, and through the check codes, the correction result of the matching data is obtained.

[0046] It should be noted that during the process of correcting the matching data, a correction processing process can be set, and when re-reading the matching data later, a data re-reading process is set, and the processes can work in parallel, improving the data reading efficiency.

[0047] In the above embodiments, the correction result of the matching data is determined by determining the check code of the matching data.

[0048] Step S208, during the process of correcting the matching data, adjust the initial reference voltage, based on the adjusted initial reference voltage, re-read the matching data that matches the data attribute information from the storage unit, and correct the re-read matching data until the correction result obtained by correcting the matching data meets the data error rate condition, then stop reading the matching data.

[0049] It should be noted that during the process of verifying and processing the matching data, the initial reference voltage will be adjusted. According to the adjusted initial reference voltage, new matching data will be read continuously. That is to say, there is no need to wait for the calibration result, nor to wait for whether the calibration result meets the data error rate condition, and the rereading of the matching data can be carried out. The reread matching data will still be calibrated to determine whether it meets the data error rate condition. Until the calibration result of any matching data meets the data misalignment rate condition, the reading of the matching data can be paused. Compared with the conventional technology, each reading of the matching data waits for the calibration result and waits for whether the calibration result meets the data error rate condition, which significantly saves the data reading time and improves the data reading efficiency.

[0050] In some exemplary embodiments, the adjusting the initial reference voltage and rereading the matching data that matches the data attribute information from the storage unit based on the adjusted initial reference voltage includes: selecting an adjustment reference value according to the set reference voltage adjustment range; increasing or decreasing the initial reference voltage based on the adjustment reference value to obtain the adjusted initial reference voltage; and rereading the matching data that matches the data attribute information from the storage unit based on the adjusted initial reference voltage.

[0051] Among them, the reference voltage adjustment range can be determined according to historical experience values or calibration values. By setting the reference voltage range through historical experience values, the trial-and-error cost can be reduced as much as possible, so as to correctly read the matching data and avoid the loss or damage of the matching data.

[0052] Specifically, within the set reference voltage adjustment range, the adjustment reference value can be selected sequentially or randomly, and the initial reference voltage can be adjusted based on the adjustment reference value to obtain the adjusted initial reference voltage; based on the adjusted initial reference voltage, reread the matching data that matches the data attribute information from the storage unit.

[0053] In some exemplary embodiments, during the process of calibrating the matching data, adjusting the initial reference voltage and rereading the matching data that matches the data attribute information from the storage unit based on the adjusted initial reference voltage includes: starting a data rereading process set for the data rereading process; through the data rereading process, adjusting the initial reference voltage and rereading the matching data that matches the data attribute information from the storage unit based on the adjusted initial reference voltage.

[0054] It should be noted that for the data rereading process, a data rereading process is set up. The initial reference voltage is adjusted by the data rereading process. Based on the adjusted initial reference voltage, matching data that matches the data attribute information is reread from the storage unit. For the calibration process, a calibration process is set up. The two processes can be executed in parallel without interfering with each other, thereby effectively improving the data reading efficiency.

[0055] In some exemplary embodiments, stopping the reading of the matching data until the calibration result obtained by calibrating the matching data meets the data error rate condition includes: comparing the calibration result of the matching data with a preset target calibration result to determine the error rate of the calibration result; stopping the reading of the matching data when the error rate is less than or equal to the set error rate threshold.

[0056] Among them, the calibration result includes multiple check codes, and the target calibration result also includes multiple target check codes; the target calibration result is specifically the true value stored in advance, that is, before the matching data is stored in the storage unit of the SSD, the matching data has been calibrated to obtain its target calibration result, that is, multiple target check codes have been obtained. In the subsequent process of determining whether the calibration result meets the misalignment condition, only by comparing the calibration result with the target calibration result can the error rate be determined.

[0057] Specifically, the error rate of the calibration result is determined by comparing the multiple check codes included in the calibration result with the multiple target check codes included in the target calibration result. The error rate threshold is set according to the actual data accuracy requirements. For example, the misalignment rate threshold is set to 0, and the reading of the matching data is stopped only when the misalignment rate is equal to 0. That is to say, the calibration result and the target calibration result need to be exactly the same; of course, the error rate threshold can also be set to 2% according to the actual situation, that is, it is allowed that there are some differences between the check codes in the calibration result and the target check codes.

[0058] In some embodiments, when determining whether the calibration result meets the data error rate condition, it may be that the check codes included in the calibration result and the target check codes included in the target calibration result are exactly the same, or it may be that as long as the check codes included in the calibration result are partially the same as the target check codes included in the target calibration result, such as 80% of the check codes are the same as the target check codes. The embodiments of the present application do not limit this here.

[0059] In the above embodiments, by determining the error rate and setting the error rate threshold, and comparing the error rate with the error rate threshold, it is possible to accurately and quickly determine whether to stop the reading of the matching data.

[0060] In some exemplary embodiments, comparing the correction result of the matching data with a preset target correction result to determine the error rate of the correction result includes: determining a plurality of check codes according to the correction result, and determining a plurality of target check codes according to the target correction result; counting the total number of the plurality of check codes, and counting the number of error codes among the plurality of check codes; wherein, the number of error codes is determined by sequentially comparing the plurality of check codes with the plurality of target check codes in order; determining the error rate of the correction result according to the number of error codes and the total number.

[0061] In some embodiments, the check codes and the target check codes can be sorted in order respectively. When comparing, the first check code and the first target check code can be taken for comparison to obtain a comparison result; the second check code and the second target check code can be taken for comparison to obtain a comparison result…, the Nth check code and the Nth target check code can be taken for comparison to obtain a comparison result, where N is not equal to 0, until all the check codes and target check codes have been compared. Count the comparison results, and determine the number of incorrect comparison results among the comparison results, where the incorrect comparison result is the result when the check code and the target check code are inconsistent.

[0062] Specifically, the number of error codes and the total number can be divided, and the quotient of the two is the determined error rate of the correction result.

[0063] In the above embodiments, when determining the error rate of the correction result, the number of error codes is determined by sequentially comparing a plurality of check codes with a plurality of target check codes in order, and then the error rate can be determined according to the quotient of the total number and the number of error codes.

[0064] Through the description of the above implementation manners, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation manner. Based on such an understanding, the technical solution of the present application, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disc), and includes several instructions for causing a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in various embodiments of the present application.

[0065] To better understand the process of the above data reading method of the solid-state memory, the implementation process of the above data reading method of the solid-state memory will be further described below in combination with optional embodiments, but it is not used to limit the technical solutions of the embodiments of the present application.

[0066] With the continuous increase in data volume and the growing storage requirements, the solid-state drive (SSD) market has shown a significant growth trend. Among them, SSD firmware is a key part to ensure the performance and stability of SSDs. With the continuous development of technology, users have higher and higher requirements for the performance of SSDs, including faster data transfer speeds, higher storage densities, and better durability. How to balance both the data transfer speed and ensure the reliability and lifespan of solid-state drives has become the focus of SSD firmware development. And among them, the read retry operation is a way to sacrifice data transfer speed to increase the lifespan of solid-state drives.

[0067] Due to some physical characteristics of current NAND flash memory chips, the threshold voltage (VTH) of storage cells may change over time, resulting in bit flips in some cells when reading NAND data. And as the number of program / erase (P / E) cycles increases, the number of cells with bit flips also increases. With the development of 3D NAND technology and multi-level cells (such as MLC, TLC, QLC), the storage density has increased, but this has also made NAND flash memory cells more prone to charge leakage, resulting in changes in the VTH level and increasing the probability of read errors. The commonly used error correction method is to first perform ECC (a module used to correct bit flips in data) error correction. When the number of bit flips exceeds the error correction ability of ECC, the threshold voltage is then adjusted to perform read retry (a way to improve the reliability of SSD data by re-reading by adjusting the reference voltage axis). The working principle of the ReadRetry mechanism is that when reading data, if the raw bit error rate (RBER) is higher than the correction ability of the error correction code (ECC), it will try to find a suitable reference voltage (VREF) value by repeating the read operation. This reference voltage value can make the RBER of the page lower than the correction ability of ECC, so as to correctly read the data and avoid data loss or damage. Read retry is to re-read using a slightly adjusted read reference voltage (VREF) value. In this way, even when the threshold voltage (VTH value) of the storage cell changes, the SSD can read the data as much as possible.

[0068] The process of read retry is usually that when the SSD controller detects a read error, it will initiate the read retry operation. In each retry step, the controller will use a slightly adjusted VREF value to try to read the data. This process will be repeated until a suitable VREF value is found such that the error rate of the read data is lower than the threshold that the error correction code (ECC) can correct, or it is determined that the data cannot be read correctly.

[0069] Reference Figure 3As shown below, it is the data reading process in conventional technology: First is Normal read (i.e., reading matching data based on the initial reference voltage). In the case of failed correction processing, read retry is carried out, which can include the first reread, the second reread... the Nth reread. Although read retry is very important for ensuring the data reliability of SSDs and plays an important role in the service life of SSDs. However, the read retry operation also brings performance overhead because each retry step requires additional time to adjust VREF and reread the data, and as the number of P / E (the abbreviations for writing and erasing operations on NAND) cycles increases, the required read retry operations increase the latency of read operations during each read operation. With the development of SSD technology, manufacturers are constantly improving the Read Retry algorithm and other related technologies to improve the accuracy and efficiency of data reading while extending the service life of SSDs.

[0070] This application proposes an optimization for the currently common read retry process. When the number of P / E cycles is too large and the required number of read retries increases, the improvement in read performance is more obvious. Currently, the process of reading data from NAND Flash (a type of non-volatile memory) by an SSD generally mainly includes reading data from the Flash array to the page register, DMA data transfer, and ECC error correction. Therefore, the time required for the current read retry process is as Figure 4 shown. Figure 4 In it: tR: The time required to read matching data from the Flash array (storage array) to the page register; tDMA: The time required for the SSD controller to transfer the matching data through the DMA module. tECC: The time required for the ECC module of the SSD controller to correct errors.

[0071] Calculated according to the current read retry process, the time required for one read operation is equivalent to the time required for n + 1 read operations. The time required for each read operation to read data from the Flash array to the page register, DMA data transfer, and ECC error correction is necessary. In the read retry process proposed in this application, the next read retry is carried out while starting ECC error correction, and the next read operation is immediately stopped until the ECC error correction is successful in a certain time. After the method proposed in the present invention, the time required for the read operation that needs to be reread next is as follows Figure 5As shown, compared with the original read retry process, the time for ECC error correction can be saved n times. Therefore, as the number of required read retries increases, the impact on improving the SSD read performance will become more obvious.

[0072] Reference Figure 5 As shown, this is the data reading process of the present application. (1) The SSD controller sends a read command to the NAND Flash, starts to read the matching data, and transfers the matching data to the DDR through the DMA module. (2) While the SSD controller performs data error correction in the ECC module, it adjusts the read reference voltage axis and sends a read command to the NAND Flash for rereading, such as Figure 5 the first rereading, the second rereading... the Nth rereading, etc. in []. (3) Repeat the operation of adjusting the read initial reference voltage for read retry. (4) Until the ECC error correction is successful in the Nth read retry, the SSD controller sends a RESET command to the NAND Flash to stop the next ongoing read retry and returns the read data.

[0073] Compared with the traditional technology, the present application proposes a new read retry process to improve the read retry efficiency. Compared with the currently common process, after the DMA data transfer is completed, the read reference voltage is directly adjusted, and a read command is sent to the NAND again. The NAND starts to read data from the Flash array into the page register. Before starting the next read retry, it does not care whether the ECC error correction is successful. The NAND reads data from the Flash array and performs ECC error correction simultaneously. When the ECC error correction is successful in the nth read retry, a RESET command is sent to the NAND to terminate the ongoing (n + 1)th read retry operation. After adopting the present invention, the two steps of ECC data error correction and reading data from the Flash array in the read retry process can be carried out simultaneously, saving the time required for the read retry process. And as the number of required read retries increases, the more time is saved, and the more obvious the impact on improving the read retry efficiency is.

[0074] The optimization method for read retry proposed in this application only requires minor modifications to the SSD firmware without changing the underlying NAND flash chips, which makes it easy to be combined with the existing read retry step technology to improve the overall read performance of the SSD. When the number of P / E cycles is excessive, the number of read retries required for a read operation in the SSD firmware will also increase. In the present invention, the ECC error correction step in the read retry process and the step of adjusting the reference voltage axis to read data from the NAND Flash are synchronized. When the ECC error correction is successful in the nth read retry operation, a RESET command is immediately sent to the NAND to terminate the current read operation. Since the ECC error correction and reading from the NAND Flash are carried out simultaneously in this application, the efficiency of the SSD read retry can be effectively improved compared with the original read retry process.

[0075] Figure 6 is a structural block diagram of a data reading device of a solid-state memory according to an embodiment of the present application, as Figure 6 shown, the device includes:

[0076] An acquisition module 62, configured to acquire a data reading instruction carrying data attribute information; wherein, the data reading instruction is used to read matching data matching the data attribute information from a storage unit of the solid-state memory;

[0077] A reading module 64, configured to read matching data matching the data attribute information from the storage unit based on a set initial reference voltage;

[0078] A processing module 66, configured to perform correction processing on the matching data;

[0079] The reading module 64 is further configured to adjust the initial reference voltage during the process of performing correction processing on the matching data, and based on the adjusted initial reference voltage, re-read the matching data matching the data attribute information from the storage unit, and perform correction processing on the re-read matching data until the correction result obtained by performing correction processing on the matching data meets the data error rate condition, and then stop reading the matching data.

[0080] Through the above device, a data reading instruction carrying data attribute information is obtained; wherein, the data reading instruction is used to read matching data matching the data attribute information from a storage unit of the solid-state memory, and based on a set initial reference voltage, read matching data matching the data attribute information from the storage unit; further, perform correction processing on the matching data; and during the process of performing correction processing on the matching data, adjust the initial reference voltage, and based on the adjusted initial reference voltage, re-read the matching data matching the data attribute information from the storage unit, and perform correction processing on the matching data based on the re-read matching data until the correction result obtained by performing correction processing on the matching data meets the data error rate condition, and then stop reading the matching data. In this application, the reading of the matching data can be started during the process of performing correction processing on the matching data, rather than waiting for the correction result of the correction processing to start reading the matching data, which saves the waiting time and effectively improves the data reading efficiency.

[0081] In an exemplary embodiment, the data attribute information includes address information of the matching data to be read; the reading module 64 is further configured to translate the address information of the matching data to be read to obtain a physical address of the matching data to be read in the storage unit; based on a match between the physical address and storage area addresses of multiple data storage areas of the storage unit, determine a target data storage area corresponding to the matching data to be read as the data storage area corresponding to the storage area address that matches the physical address; load the set initial reference voltage to the target data storage area, determine a storage area state of the target data storage area, and read the matching data from the target data storage area according to the storage area state; determine a scratch register associated with the target data storage area, and store the read matching data in the scratch register; when it is determined that the data storage amount in the scratch register reaches a set data storage amount threshold, send the matching data in the scratch register to a transmission queue; transmit the matching data in the transmission queue to a dynamic random access memory unit of the solid-state memory by means of direct memory access; wherein, the matching data used when performing correction processing on the matching data is obtained from the dynamic random access memory unit.

[0082] In an exemplary embodiment, the processing module 66 is further configured to start a calibration processing process set for calibration processing, read the matching data from the dynamic random access memory through the calibration processing process; perform segmentation processing on the matching data according to the calibration processing process to obtain multiple segments of matching sub-data; perform encoding on the multiple segments of matching sub-data according to the calibration processing process to obtain encoding results corresponding to the multiple segments of matching sub-data respectively; generate check codes corresponding to the respective encoding results according to the calibration processing process; and obtain a calibration result of the matching data according to the respective check codes.

[0083] In an exemplary embodiment, the reading module 64 is further configured to select an adjustment reference value according to a set reference voltage adjustment range; perform an increase or decrease process on the initial reference voltage based on the adjustment reference value to obtain an adjusted initial reference voltage; and re-read the matching data matching the data attribute information from the storage unit based on the adjusted initial reference voltage.

[0084] In an exemplary embodiment, the reading module 64 is further configured to start a data re-reading process set for the data re-reading process; adjust the initial reference voltage through the data re-reading process, and re-read the matching data matching the data attribute information from the storage unit based on the adjusted initial reference voltage.

[0085] In an exemplary embodiment, the reading module 64 is further configured to compare the calibration result of the matching data with a preset target calibration result to determine an error rate of the calibration result; and stop reading the matching data when the error rate is less than or equal to a set error rate threshold.

[0086] In an exemplary embodiment, the reading module 64 is further configured to determine a plurality of check codes according to the calibration result, and determine a plurality of target check codes according to the target calibration result; count a total number of the plurality of check codes, and count a number of error codes among the plurality of check codes; wherein the number of error codes is determined by sequentially comparing the plurality of check codes with the plurality of target check codes in order; and determine the error rate of the calibration result according to the number of error codes and the total number.

[0087] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any one of the above method embodiments when running.

[0088] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media that can store computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), external hard drives, magnetic disks, or optical discs.

[0089] An embodiment of the present application also provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0090] In an exemplary embodiment, the above electronic device may further include a transmission device and an input / output device. Among them, the transmission device is connected to the above processor, and the input / output device is connected to the above processor.

[0091] An embodiment of the present application also provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above method embodiments.

[0092] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above method embodiments.

[0093] An embodiment of the present application also provides a computer program. The computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the steps in any one of the above method embodiments.

[0094] Specific examples in this embodiment may refer to the examples described in the above embodiments and exemplary embodiments, and will not be repeated here.

[0095] Obviously, those skilled in the art should understand that the various modules or steps of the present application described above can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. They can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a sequence different from that here, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. In this way, the present application is not limited to any specific combination of hardware and software.

[0096] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for reading data from a solid-state memory, characterized in that: include: Acquire a data read instruction carrying data attribute information; wherein the data read instruction is used to read matching data matching the data attribute information from a storage unit of the solid-state memory; Based on the set initial reference voltage, reading matching data matching the data attribute information from the storage unit; and performing correction processing on the matching data; In the process of correcting the matching data, the initial reference voltage is adjusted, and based on the adjusted initial reference voltage, the matching data matching the data attribute information is re-read from the storage unit, and the re-read matching data is corrected until the correction result obtained by the correction processing of the matching data meets the data error rate condition, and the reading of the matching data is stopped.

2. The method according to claim 1, characterized in that The data attribute information includes address information of the matching data to be read; The step of reading matching data matching the data attribute information from the storage unit based on the set initial reference voltage includes: Translating the address information of the matching data to be read to obtain the physical address of the matching data to be read in the storage unit; Based on matching the physical address with storage area addresses of a plurality of data storage areas of the storage unit, determining the data storage area corresponding to the storage area address matching the physical address as the target data storage area of ​​the matching data to be read; loading the set initial reference voltage to the target data storage area, determining the storage area state of the target data storage area, and reading the matching data from the target data storage area according to the storage area state; Determine a temporary register associated with the target data storage area, and store the read matching data in the temporary register; When it is determined that the data storage amount in the temporary register reaches a set data storage amount threshold, the matching data in the temporary register is sent to a transmission queue; The matching data in the transmission queue is transmitted to the dynamic random access memory unit of the solid-state memory by means of direct storage transmission; wherein the matching data used in the correction processing of the matching data is obtained from the dynamic random access memory unit.

3. The method according to claim 1, characterized in that The correction processing of the matching data includes: starting a correction processing process set for the correction processing, and reading the matching data from a dynamic random access memory through the correction processing process; Segmenting the matching data according to the correction processing process to obtain multiple matching sub-data segments; encoding the multiple matching sub-data segments according to the correction processing process to obtain encoding results corresponding to the multiple matching sub-data segments; Generate a check code corresponding to each of the encoding results according to the correction processing process; According to each of the check codes, a correction result of the matching data is obtained.

4. The method according to claim 1, characterized in that: The adjusting the initial reference voltage and re-reading the matching data matching the data attribute information from the storage unit based on the adjusted initial reference voltage includes: selecting an adjustment reference value according to a set reference voltage adjustment range; Based on the adjustment reference value, increasing or decreasing the initial reference voltage to obtain an adjusted initial reference voltage; Based on the adjusted initial reference voltage, matching data matching the data attribute information is re-read from the storage unit.

5. The method according to claim 1, characterized in that In the process of correcting the matching data, adjusting the initial reference voltage, and re-reading the matching data matching the data attribute information from the storage unit based on the adjusted initial reference voltage, comprises: Start the data re-reading process set for the data re-reading process; The initial reference voltage is adjusted through the data rereading process, and matching data matching the data attribute information is reread from the storage unit based on the adjusted initial reference voltage.

6. The method according to claim 1, characterized in that The step of stopping reading the matching data until a correction result obtained by performing correction processing on the matching data satisfies a data error rate condition comprises: Comparing the correction result of the matching data with a preset target correction result to determine the error rate of the correction result; When the error rate is less than or equal to a set error rate threshold, the reading of matching data is stopped.

7. The method according to claim 6, characterized in that The comparing the correction result of the matching data with a preset target correction result to determine the error rate of the correction result includes: Determining a plurality of check codes according to the correction result, and determining a plurality of target check codes according to the target correction result; Count the total number of the multiple check codes, and count the number of error codes in the multiple check codes; wherein the number of error codes is determined by comparing the multiple check codes with the multiple target check codes in sequence; determine the error rate of the correction result based on the number of error codes and the total number.

8. A data reading device for a solid-state memory, characterized in that: include: An acquisition module, used to acquire a data read instruction carrying data attribute information; wherein the data read instruction is used to read matching data matching the data attribute information from a storage unit of the solid-state memory; A reading module, configured to read matching data matching the data attribute information from the storage unit based on a set initial reference voltage; A processing module, used for performing correction processing on the matching data; The reading module is further used to adjust the initial reference voltage during the process of correcting the matching data, re-read the matching data matching the data attribute information from the storage unit based on the adjusted initial reference voltage, and perform correction processing on the re-read matching data until the correction result obtained by the correction processing on the matching data meets the data error rate condition and stops reading the matching data.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 7 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

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