Semiconductor process method and semiconductor structure

Abstract

The invention provides a semiconductor process method and a semiconductor structure. The method comprises the following steps: growing n layers of first thin films and m layers of second thin films by a liquid source; performing ultraviolet irradiation treatment after the liquid source grows each layer of first-type film with the thickness not larger than the preset thickness; and fine polishing is carried out after the liquid source grows each layer of second-type film with the thickness larger than the preset thickness. The first film grown by the liquid source is irradiated by ultraviolet rays, and organic particles of the thin first film are photodecomposed, so that the probability of generating particles on the surface of the first film is reduced; meanwhile, fine polishing treatment is conducted on the second-class thin film growing on the liquid source, and residual surface particles, which cannot be removed by ultraviolet light, of the thick second-class thin film are removed; in addition, by controlling the ultraviolet irradiation treatment time and wavelength range, the organic particle removal effect of the first-type film is ensured, and the quality of the first-type film is avoided; and finally, by controlling the thinning thickness and speed of fine polishing and the particle size of the grinding pad, it is guaranteed that particles on the surface of the second film are removed, and the electrical performance of the second film is prevented from being affected.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a semiconductor process method and a semiconductor structure. Background Art

[0002] In the field of semiconductor manufacturing, with the continuous progress of technology, the performance and functions of integrated circuit chips have been significantly improved. According to Moore's Law, the number of circuits integrated on an integrated circuit chip approximately doubles every 18 months. This trend has promoted the rapid development of chip design and manufacturing technologies, resulting in continuous reduction of chip size and increase of integration density, while the challenges faced in the semiconductor manufacturing process have also increased day by day.

[0003] In the manufacturing of high-integration chips, the reduction of chip size has brought many technical problems, among which the most prominent one is the problem of yield improvement. Yield refers to the proportion of chips that meet the quality standards in the total number of chips produced. As the chip size decreases, the impact of surface defects in the manufacturing process on the yield becomes more significant. These surface defects include particle contamination, scratches, pits, protrusions, etc. They not only affect the electrical performance of the chips, but also may cause the chips to malfunction during subsequent use. Especially at the technology nodes of 65 nanometers and below, the surface defects generated in each process link of semiconductor manufacturing have become the main factors for yield reduction. And with the increase of process complexity, the difficulty of controlling and reducing these defects also increases accordingly, seriously affecting the yield and reliability of product chips obtained in higher-integration process technologies.

[0004] Therefore, there is an urgent need for a structure or method that can reduce the surface defects of products obtained in advanced technology nodes.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0006] In view of the above disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor process method and a semiconductor structure, which are used to solve the problems that the surface defects of products obtained in the processes of advanced technology nodes in the prior art are difficult to control and the product yield is reduced.

[0007] To achieve the above purpose, the present invention provides a semiconductor process method, and the semiconductor process method includes:

[0008] Liquid source growth of a semiconductor structure including n layers of first - type thin films and m layers of second - type thin films on a structure to be deposited, where n and m are both integers greater than or equal to 1; the thickness of each layer of the first - type thin film is not greater than a preset thickness, and the thickness of each layer of the second - type thin film is greater than the preset thickness;

[0009] After liquid source growth of each layer of the first - type thin film, ultraviolet irradiation treatment is performed on this layer of the first - type thin film; after liquid source growth of each layer of the second - type thin film, chemical - mechanical polishing treatment is performed on this layer of the second - type thin film.

[0010] Optionally, the preset thickness is 50 nanometers - 300 nanometers.

[0011] Optionally, the wavelength of the ultraviolet light wave used for ultraviolet irradiation treatment is 50 nanometers - 300 nanometers.

[0012] Optionally, the treatment time for ultraviolet irradiation treatment is 15 seconds - 30 seconds.

[0013] Optionally, the polishing rate for chemical - mechanical polishing treatment is 0.5 nanometers per second - 1 nanometer per second.

[0014] Optionally, the average particle size of the particles of the polishing pad used for chemical - mechanical polishing treatment is 100 nanometers - 300 nanometers.

[0015] Optionally, the thickness by which each layer of the second - type thin film is thinned during chemical - mechanical polishing treatment is 5 nanometers - 10 nanometers.

[0016] Optionally, the first - type thin film and / or the second - type thin film is / are grown by liquid source using plasma - enhanced chemical vapor deposition.

[0017] Optionally, the first - type thin films are all grown before the second - type thin films, and the total thickness of the n layers of the first - type thin films is not greater than 50 nanometers - 300 nanometers.

[0018] The present invention also provides a semiconductor structure, which is obtained by using any one of the above - mentioned semiconductor process methods. The semiconductor structure includes a structure to be deposited, n layers of first - type thin films and m layers of second - type thin films. The first - type thin films and the second - type thin films are both located on the structure to be deposited, and n and m are both integers greater than or equal to 1; the thickness of each layer of the first - type thin film is not greater than a preset thickness, and the thickness of each layer of the second - type thin film is greater than the preset thickness.

[0019] As above, the semiconductor process method and semiconductor structure of the present invention have the following beneficial effects:

[0020] In the present invention, after the first type of thin film with a thickness of each layer not greater than a preset thickness is provided, ultraviolet irradiation treatment is carried out, so that the organic particles on the surface of the relatively thin first type of thin film can be directly photodecomposed, realizing the planarization of the surface of the first type of thin film;

[0021] In the present invention, after the second type of thin film with a thickness greater than the preset thickness in each layer is subjected to fine polishing treatment, the surface of the relatively thick second type of thin film that is difficult for ultraviolet rays to penetrate and cure is planarized. At the same time, for the more obvious protrusions on the surface of the thicker second type of thin film, a higher-efficiency surface planarization is achieved;

[0022] In the present invention, by controlling the treatment time of the ultraviolet irradiation treatment, while ensuring the effect of the surface planarization of the first type of thin film, it can be ensured that no large stress is generated inside the first type of thin film to affect the quality of the first type of thin film;

[0023] In the present invention, by controlling the thinning thickness of the fine polishing treatment, while ensuring the effect of the planarization of the second type of thin film, it can be ensured that the second type of thin film will not be excessively thinned to affect the electrical performance of the second type of thin film. Description of the Drawings

[0024] Figure 1 It shows a schematic flow chart of the steps of the semiconductor process method according to Embodiment 1 of the present invention.

[0025] Figure 2 It shows a schematic structural diagram of the growth of the first type of thin film in step A1 of the semiconductor process method according to Embodiment 1 of the present invention.

[0026] Figure 3 It shows a schematic structural diagram of the ultraviolet irradiation treatment in step A2 of the semiconductor process method according to Embodiment 1 of the present invention.

[0027] Figure 4 It shows a schematic structural diagram of the growth of n - 1 layers of the first type of thin film in an example of step A2 of the semiconductor process method according to Embodiment 1 of the present invention.

[0028] Figure 5 It shows a schematic structural diagram of the growth of the second type of thin film in step A3 of the semiconductor process method according to Embodiment 1 of the present invention.

[0029] Figure 6 It shows a schematic structural diagram of the fine polishing of the second type of thin film in step A3 of the semiconductor process method according to Embodiment 1 of the present invention.

[0030] Figure 7 It shows a schematic structural diagram of the growth of m - 1 layers of the second type of thin film in an example of step A4 of the semiconductor process method according to Embodiment 1 of the present invention.

[0031] Figure 8It shows a schematic structural diagram presented when growing a second type of thin film inserted in an example of step A3 of the semiconductor process method according to Embodiment 1 of the present invention.

[0032] Figure 9 It shows a schematic structural diagram presented when growing a first type of thin film inserted in an example of step A4 of the semiconductor process method according to Embodiment 1 of the present invention.

[0033] Figure 10 It shows a schematic structural diagram presented by the permutation and combination in an example of step A4 of the semiconductor process method according to Embodiment 1 of the present invention.

[0034] Figure 11 It shows a schematic structural diagram presented when growing a first type of thin film in step A1 of the semiconductor process method according to Embodiment 2 of the present invention.

[0035] Figure 12 It shows a schematic structural diagram presented by the ultraviolet irradiation treatment in step A1 of the semiconductor process method according to Embodiment 2 of the present invention.

[0036] Figure 13 It shows a schematic structural diagram presented when growing a layer of the second type of thin film in step A3 of the semiconductor process method according to Embodiment 2 of the present invention.

[0037] Figure 14 It shows a schematic structural diagram presented when precisely polishing the second type of thin film in step A3 of the semiconductor process method according to Embodiment 2 of the present invention.

[0038] Figure 15 It shows a schematic structural diagram presented when growing another layer of the second type of thin film in step A3 of the semiconductor process method according to Embodiment 2 of the present invention.

[0039] Figure 16 It shows a schematic structural diagram presented when precisely polishing another layer of the second type of thin film in step A3 of the semiconductor process method according to Embodiment 2 of the present invention.

[0040] Figure 17 It shows a schematic structural diagram presented when growing the second type of thin film in step B1 of the semiconductor process method according to Embodiment 3 of the present invention.

[0041] Figure 18 It shows a schematic structural diagram presented when growing m - 1 layers of the second type of thin film in an example of step B2 of the semiconductor process method according to Embodiment 3 of the present invention.

[0042] Figure 19 It shows a schematic structural diagram presented when growing the first type of thin film in step B3 of the semiconductor process method according to Embodiment 3 of the present invention.

[0043] Figure 20It shows a schematic structural diagram of growing the n-1th layer of the first type of thin film in an example of step B4 of the semiconductor process method according to Embodiment 3 of the present invention.

[0044] Figure 21 It shows a schematic structural diagram of inserting the first type of thin film in an example of step B2 of the semiconductor process method according to Embodiment 3 of the present invention.

[0045] Figure 22 It shows a schematic structural diagram of inserting the second type of thin film in an example of step B4 of the semiconductor process method according to Embodiment 3 of the present invention.

[0046] Figure 23 It shows a schematic structural diagram of the permutation and combination in an example of step B4 of the semiconductor process method according to Embodiment 3 of the present invention.

[0047] Figure 24 It shows a schematic structural diagram of the semiconductor structure according to Embodiment 4 of the present invention.

[0048] Explanation of the reference numerals in the drawings

[0049] 1. Structure to be deposited; 2. First type of thin film; 3. Ultraviolet ray; 4. Second type of thin film; 5. Passivation layer thin film; 6. Ultra-low dielectric constant layer; 7. TEOS layer; 8. Particle. Detailed implementation manners

[0050] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] When detailing the embodiments of the present invention, for the convenience of description, the schematic diagrams showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples, which should not limit the protection scope of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.

[0052] For the convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" etc. may be used here to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings.

[0053] In the context of the present application, the structure in which the described first feature is "above" the second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0054] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex; the numerical ranges given in the present invention default to include the two boundary values of the numerical range under the condition of no special limitation.

[0055] In the field of semiconductor manufacturing, the chip size is continuously decreasing and the integration level is continuously increasing. In the manufacturing of high-integration chips, the most prominent problem brought about by the reduction of the chip size is the improvement of the yield. The reduction of the chip size makes the influence of surface particle contamination, scratches, pits, protrusions and other defects in the manufacturing process on the yield more significant, which not only affects the electrical performance of the chip, but may also cause the chip to malfunction during subsequent use. Especially at technology nodes of 65 nanometers and below, with the increase in process complexity, the difficulty of controlling and reducing these defects also increases accordingly, seriously affecting the yield and reliability of the product chips obtained in the higher-integration process.

[0056] In the semiconductor back-end metal connection process, a passivation layer, an ultra-low dielectric constant layer (ULK, UltraLow ​​k), and TEOS (Tetraethyl Orthosilicate) are usually used as dielectric layers between metal connections, and the above three dielectric layer films are all grown using the PECVD (Plasma Enhanced Chemical Vapor Deposition) process. In the process of growing the above dielectric layer films using PECVD technology, the main reaction source is usually a macromolecular organic liquid source. These organic liquid sources are prone to form tiny particles similar to bumps on the surface of the film during the growth process. The size of these tiny particles is usually between 20 and 100 nanometers, especially in the processes of advanced technology nodes such as 40 nanometers, 28 nanometers, and 14 nanometers. These tiny particles will become the main source of defects that reduce product yield. These defects will have an adverse effect on the subsequent lithography and etching processes on the grown dielectric layer films, and may cause problems such as unclear and incomplete etching patterns, thereby causing subsequent metal wiring short circuits or disconnections. The existence of these problems will greatly reduce the yield of semiconductor production, thereby affecting the efficiency of the entire production process and product quality. Therefore, in the process of growing dielectric layer films using liquid source PECVD technology, how to effectively control and reduce the generation of these tiny particles has become a key issue in improving product yield and production efficiency in the process of advanced technology nodes.

[0057] The CMP (Chemical Mechanical Planarization) process used for surface planarization in the prior art is only applicable to very thick structural layers. Therefore, those skilled in the art often do not apply CMP to the removal of surface particles of thin films, but usually use gas purge to remove particles remaining on the surface from liquid source growth. However, since some large particles remaining from liquid source growth are heavy and have a certain adhesion to the surface, the effect of using purge to remove surface particles of thin films obtained from liquid source growth in the prior art is not ideal, and many particles will still remain, causing product defects. The impact of these defects in the previous process technology is not significant, so the traditional purge method can be used to meet the requirements of surface defects. However, with the further development of semiconductor technology, especially in the technology nodes of 65 nanometers and below, the effect of the purge method in removing surface particles of thin films grown from liquid sources can no longer meet the requirements of product yield, and the surface particle size that can be processed by the existing CMP for surface planarization is also much larger than the particle size on the surface of the film.

[0058] Embodiment 1:

[0059] As Figure 1 shown, this embodiment provides a semiconductor process method, and the semiconductor process method includes:

[0060] The semiconductor process method of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the semiconductor process method protected by the present invention, and those skilled in the art can make changes according to the actual process method steps.

[0061] First, perform step A1. As Figure 2 shown, a first type of thin film 2 is grown by liquid source on a structure 1 to be deposited, and the thickness of the first type of thin film 2 is not greater than a preset thickness.

[0062] Specifically, liquid source growth generally uses an organic liquid source, and the organic liquid source often forms relatively large particulate matter during the growth process, resulting in obvious convex defects. Therefore, the present invention is mainly used to solve the problem of surface particles of the thin film obtained by organic liquid source growth, but can also be used in the process of removing surface particles of the thin film obtained by other liquid sources and performing photodecomposition treatment by ultraviolet ray 3 irradiation, all within the protection scope of the present invention.

[0063] In one embodiment, the preset thickness is 50 nanometers to 300 nanometers.

[0064] By setting the range of the preset thickness, the present invention can optimize the penetration effect of subsequent ultraviolet ray 3 irradiation treatment on the first type of thin film 2, and further ensure the removal effect of surface defects of the first type of thin film 2.

[0065] In one embodiment, the first type of thin film 2 is grown by liquid source in a manner of (PECVD) plasma enhanced chemical vapor deposition.

[0066] Specifically, other suitable methods can also be used to grow the first type of thin film 2 by liquid source, all within the protection scope of the present invention.

[0067] In one embodiment, the structure 1 to be deposited is a substrate. Specifically, the structure 1 to be deposited can also be any other semiconductor structure that needs to be provided with the first type of thin film 2 and the second type of thin film 4, all within the protection scope of the present invention.

[0068] Then, perform step A2. As Figure 3 shown, after growing the first type of thin film 2 by liquid source, the first type of thin film 2 is subjected to ultraviolet ray 3 irradiation treatment.

[0069] In one embodiment, the wavelength of the ultraviolet ray 3 used for the ultraviolet ray 3 irradiation treatment is 50 nanometers to 300 nanometers.

[0070] In one embodiment, the processing time for the ultraviolet 3 irradiation treatment is 15 seconds to 30 seconds.

[0071] In the present invention, by setting the thickness of the first type of thin film 2 grown from the liquid source in step A1 to be not greater than a preset thickness, it is ensured that the ultraviolet 3 in the ultraviolet 3 irradiation treatment in step A2 can penetrate the first type of thin film 2. Combined with the setting of the wavelength and processing time range of the ultraviolet 3 irradiation treatment, it is ensured that the organic particles 8 inside and on the surface of the first type of thin film 2 are sufficiently photodecomposed by the ultraviolet 3 irradiation treatment in step A2, avoiding the risk that the organic particles 8 not completely removed inside the first type of thin film 2 escape during subsequent high-temperature processes and form defects on the surface of the first type of thin film 2.

[0072] In one embodiment, after step A2 and before step A3, as Figure 4 shown, (n - 1) layers of the first type of thin film 2 are successively grown from the liquid source, where n is an integer greater than or equal to 1, and the thickness of each layer of the first type of thin film 2 is not greater than the preset thickness; after each layer of the first type of thin film 2 is grown from the liquid source, the ultraviolet 3 irradiation treatment is performed on this layer of the first type of thin film 2.

[0073] In one embodiment, the total thickness of the n layers of the first type of thin film 2 is not greater than 50 nanometers to 300 nanometers.

[0074] In the present invention, by restricting the total thickness of the n layers of the first type of thin film 2 when growing multiple layers of the first type of thin film 2, the thickness of the structure below the second type of thin film 4 is sufficient for subsequent chemical mechanical polishing treatment, avoiding damage to the thinner structure below due to the too small thickness of the structure below for chemical mechanical polishing treatment, and ensuring the product yield.

[0075] Next, step A3 is performed, as Figure 5 shown, a semiconductor structure of a second type of thin film 4 is grown from the liquid source on the first type of thin film 2, and the thickness of the second type of thin film 4 is greater than the preset thickness.

[0076] In one embodiment, the second type of thin film 4 is grown from the liquid source by plasma-enhanced chemical vapor deposition.

[0077] Then, step A4 is performed, as Figure 6 shown, after the second type of thin film 4 is grown from the liquid source, the second type of thin film 4 is subjected to chemical mechanical polishing treatment.

[0078] In one embodiment, the polishing rate for the chemical mechanical polishing treatment is 0.5 nanometers per second to 1 nanometer per second.

[0079] In one embodiment, the average particle size of the particles 8 of the polishing pad used during the chemical mechanical polishing treatment is 100 nanometers to 300 nanometers.

[0080] In one embodiment, the thickness of each layer of the second type of thin film 4 subjected to fine polishing is reduced by 5 nanometers to 10 nanometers.

[0081] By setting the thickness of the second type of thin film 4 grown by the liquid source in step A3 to be greater than the preset thickness, the present invention ensures that the second type of thin film 4 can use the fine polishing process in step A3 to remove the surface particles 8, and utilizes the high-precision surface flattening effect of the fine polishing process to remove the raised particles 8 accumulated due to the thickness increase caused by the transfer effect on the surface of the relatively thick second type of thin film 4, which are more serious than those of the first type of thin film 2.

[0082] Specifically, the description of the "relatively thick" of the second type of thin film 4 here is only used to distinguish it from the thickness of the first type of thin film 2; compared with the thickness commonly applicable to CMP, the thickness of the second type of thin film 4 still belongs to a relatively thin thickness.

[0083] Specifically, the fine polishing used in the present invention is the last process in the CMP polishing process after rough grinding and fine grinding. By adjusting the fine polishing process and setting the grinding rate, thinning thickness, and particle 8 size of the polishing pad for fine polishing, it can be used to remove the surface particles 8 of the second type of thin film 4 grown by the liquid source.

[0084] In one embodiment, after step A4, as Figure 7 shown, (m - 1) layers of the second type of thin film 4 are sequentially grown by the liquid source, where m is an integer greater than or equal to 1, and the thickness of each layer of the second type of thin film 4 is greater than the preset thickness; after growing each layer of the second type of thin film 4 by the liquid source, fine polishing is performed on this layer of the second type of thin film 4.

[0085] In one embodiment, before step A3, as Figure 8 shown, when a total of n layers of the first type of thin film 2 are grown by the liquid source and n > 1, between the ultraviolet ray 3 irradiation treatment of the i-th layer of the first type of thin film 2 and the growth of the (i + 1)-th layer of the first type of thin film 2 by the liquid source, steps A3 - A4 can be inserted to grow the second type of thin film 4 by the liquid source and perform fine polishing, where i is any integer greater than 1 and less than n.

[0086] In one embodiment, after step A4, as Figure 9 shown, when a total of m layers of the second type of thin film 4 are grown by the liquid source and m > 1, between the fine polishing of the i-th layer of the second type of thin film 4 and the growth of the (i + 1)-th layer of the second type of thin film 4 by the liquid source, steps A1 - A2 can be inserted to grow the first type of thin film 2 by the liquid source and perform ultraviolet ray 3 irradiation treatment, where i is any integer greater than 1 and less than m.

[0087] In one embodiment, after step A4, when growing m layers of the second type of thin film 4 from a common liquid source, after the m-th layer of the second type of thin film 4 is subjected to fine polishing treatment, various permutations and combinations of steps of growing the first type of thin film 2 from a liquid source and performing ultraviolet ray 3 irradiation treatment and / or growing the second type of thin film 4 from a liquid source and performing fine polishing treatment any number of times can be performed again, such as Figure 10 The example shown is only an example of one permutation and combination, and any other permutation and combination set according to requirements is within the protection scope of the present invention.

[0088] Preferably, as Figure 7 shown, after all the first type of thin films 2 are set, all the second type of thin films 4 are set.

[0089] By setting the growth order of the thinner first type of thin film 2 and the thicker second type of thin film 4, the first type of thin film 2 that is first subjected to ultraviolet ray 3 irradiation treatment can achieve a better surface particle 8 removal effect, so that the second type of thin film 4 set subsequently will not accumulate the particle 8 protrusions of the first type of thin film 2, thereby further improving the removal effect of the surface particles 8 of the thin film and the flatness effect of the surface, and further improving the product yield.

[0090] Specifically, if the second type of thin film 4 is set before the first type of thin film 2 is set, since the second type of thin film 4 is thicker, it is difficult to achieve the same surface particle 8 removal effect as the first type of thin film 2, resulting in protrusions caused by the accumulation of particles 8 that are not removed on the surface of the second type of thin film 4 on the surface of the first type of thin film 2, and this part of the protrusions cannot be eliminated by the ultraviolet ray 3 irradiation treatment of the first type of thin film 2, thereby causing the surface of the overall thin film structure to be uneven and resulting in product defects.

[0091] Example 2:

[0092] This embodiment provides a semiconductor process method. Other features of the semiconductor process method are the same as those in Example 1. In this embodiment, step A1-step A2 are performed once, as Figure 11 shown, a layer of the first type of thin film 2 is grown from a liquid source on a to-be-deposited structure 1, as Figure 12 shown, and the first type of thin film 2 is subjected to ultraviolet ray 3 irradiation treatment; then steps A3-A4 are repeated twice, as Figure 13 shown, a layer of the second type of thin film 4 is first grown from a liquid source on the first type of thin film 2, as Figure 14 shown, and this layer of the second type of thin film 4 is subjected to fine polishing treatment; as Figure 15 shown, another layer of the second type of thin film 4 is then grown from a liquid source on the second type of thin film 4, as Figure 16 shown, and this layer of the second type of thin film 4 is subjected to fine polishing treatment.

[0093] In one embodiment, asFigures 11 - 16 As shown, the first type of thin film 2 is a passivation layer thin film 5, and above the first type of thin film 2, there are, from bottom to top in sequence, a second type of thin film 4 including an ultra-low dielectric constant layer 6 (ULK) and a TEOS layer 7.

[0094] In one embodiment, the passivation layer thin film 5 is nitrogen-doped silicon carbide (NDC).

[0095] Specifically, the obtained semiconductor structure is a dielectric layer structure commonly used in the existing back-end metal wiring process of semiconductors. Therefore, applying this method to the existing technology better meets the general requirements in the industry. However, the present invention can also be applied to other suitable semiconductor process methods, all within the protection scope of the present invention.

[0096] Embodiment 3:

[0097] This embodiment provides a semiconductor process method. Other features of the semiconductor process method are the same as those in Embodiment 1, and the difference lies in:

[0098] First, perform step B1. As Figure 17 shown, a second type of thin film 4 is grown by liquid source on a to-be-deposited structure 1, and the thickness of the second type of thin film 4 is greater than a preset thickness.

[0099] Then, perform step B2. After growing the second type of thin film 4 by liquid source, the second type of thin film 4 is subjected to chemical mechanical polishing.

[0100] In one embodiment, after performing step B2 and before performing step B3, as Figure 18 shown, (m - 1) layers of the second type of thin film 4 are sequentially grown by liquid source, where m is an integer greater than or equal to 1, and the thickness of each layer of the second type of thin film 4 is greater than the preset thickness; after growing each layer of the second type of thin film 4 by liquid source, each layer of the second type of thin film 4 is subjected to chemical mechanical polishing.

[0101] Next, perform step B3. As Figure 19 shown, a semiconductor structure of a first type of thin film 2 is grown by liquid source on the second type of thin film 4, and the thickness of the first type of thin film 2 is not greater than the preset thickness.

[0102] Finally, perform step B4. After growing the first type of thin film 2 by liquid source, the first type of thin film 2 is subjected to ultraviolet 3 irradiation treatment.

[0103] In one embodiment, as Figure 20 shown, after performing step B4, (n - 1) layers of the first type of thin film 2 are sequentially grown by liquid source, where n is an integer greater than or equal to 1, and the thickness of each layer of the first type of thin film 2 is not greater than the preset thickness; after growing each layer of the first type of thin film 2 by liquid source, each layer of the first type of thin film 2 is subjected to ultraviolet 3 irradiation treatment.

[0104] In one embodiment, before step B3, as Figure 21 shown, when m layers of the second type of thin film 4 are grown from a common liquid source and m>1, after the i-th layer of the second type of thin film 4 is subjected to fine polishing and before the (i + 1)-th layer of the second type of thin film 4 is grown from the liquid source, steps B3-B4 can be inserted to grow the first type of thin film 2 from the liquid source and perform fine polishing. i is any integer greater than 1 and less than m.

[0105] In one embodiment, after step B4, as Figure 22 shown, when n layers of the first type of thin film 2 are grown from a common liquid source and n>1, after the i-th layer of the first type of thin film 2 is irradiated with ultraviolet rays 3 and before the (i + 1)-th layer of the first type of thin film 2 is grown from the liquid source, steps B1-B2 can be inserted to grow the second type of thin film 4 from the liquid source and perform fine polishing. i is any integer greater than 1 and less than n.

[0106] In one embodiment, after step B4, when n layers of the first type of thin film 2 are grown from a common liquid source, after the n-th layer of the first type of thin film 2 is irradiated with ultraviolet rays 3, various permutations and combinations of growing the first type of thin film 2 from the liquid source and irradiating with ultraviolet rays 3 any number of times and / or growing the second type of thin film 4 from the liquid source and performing fine polishing any number of times can be performed again. As Figure 23 shown, only an example of one permutation and combination is given, and any other permutations and combinations set according to requirements are within the protection scope of the present invention.

[0107] In the solution of this embodiment, the second type of thin film 4 is grown from the liquid source first and then the first type of thin film 2 is grown. Compared with the solutions in Embodiments 1-2, since there will still be some particle 8 residues remaining on the surface of the second type of thin film 4 after fine polishing, and these particle 8 residues will cause surface protrusions on the surface of the subsequent obtained first type of thin film 2 due to the incomplete removal of the particles 8 on the surface of the second type of thin film 4. And since this part of the surface protrusion cannot be eliminated by irradiating the first type of thin film 2 with ultraviolet rays 3, the surface flatness of the finally obtained product is relatively poor. However, irradiating each layer of the first type of thin film 2 with ultraviolet rays 3 and performing fine polishing on each layer of the second type of thin film 4 can also achieve the effect of removing the surface particles 8 of each layer of the first type of thin film 2 and the second type of thin film 4.

[0108] Embodiment 4:

[0109] This embodiment provides a semiconductor structure, which is obtained by using any one of the semiconductor process methods in Embodiments 1-3. The semiconductor structure is obtained by using any one of the above semiconductor process methods. The semiconductor structure includes a structure to be deposited 1, n layers of first-type thin films 2, and m layers of second-type thin films 4. The first-type thin films 2 and the second-type thin films 4 are both located on the structure to be deposited 1. n and m are both integers greater than or equal to 1. The thickness of each layer of the first-type thin film 2 is not greater than a preset thickness, and the thickness of each layer of the second-type thin film 4 is greater than the preset thickness.

[0110] In one embodiment, the semiconductor structure sequentially includes one layer of first-type thin film 2 and two layers of second-type thin films 4 from bottom to top.

[0111] In one embodiment, as Figure 24 shown, the one layer of first-type thin film 2 is a passivation layer thin film 5, and the two layers of second-type thin films 4 are, from bottom to top, a second-type thin film 4 of an ultra-low dielectric constant layer 6 (ULK) and a TEOS layer 7 in sequence.

[0112] In one embodiment, the passivation layer thin film 5 is nitrogen-doped silicon carbide.

[0113] Specifically, when the semiconductor structure is the above three-layer structure, the semiconductor structure is a dielectric layer structure commonly used in the metal wiring process in the back end of the semiconductor. Therefore, applying the dielectric layer structure obtained by using the semiconductor process methods in Embodiments 1-3 to the existing technology more meets the general requirements in the industry. However, the present invention can also be other suitable semiconductor structures, all within the protection scope of the present invention.

[0114] In summary, for the semiconductor process method and the semiconductor structure of the present invention, after setting the first-type thin films with a thickness not greater than the preset thickness for each layer, ultraviolet irradiation treatment can be performed, so that the organic particles on the surface of the relatively thin first-type thin films can be directly photo-decomposed, realizing the planarization of the surface of the first-type thin films. At the same time, after each layer of the second-type thin films with a thickness greater than the preset thickness, chemical mechanical polishing treatment is performed, so as to realize the planarization of the surface of the relatively thick second-type thin films that are difficult for ultraviolet rays to penetrate and cure, and at the same time, realize a more efficient surface planarization for the more obvious protrusions on the surface of the thicker second-type thin films. In addition, by controlling the treatment time of the ultraviolet irradiation treatment, while ensuring the planarization effect of the surface of the first-type thin films, it can be ensured that no large stress is generated inside the first-type thin films to affect the quality of the first-type thin films. Finally, by controlling the thinning thickness of the chemical mechanical polishing treatment, while ensuring the planarization effect of the second-type thin films, it can be ensured that the second-type thin films will not be overly thinned to affect the electrical performance of the second-type thin films.

[0115] Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0116] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor process method, characterized in that: The semiconductor process method comprises: Liquid source grows a semiconductor structure including n layers of a first type of thin film and m layers of a second type of thin film on a structure to be deposited, where n and m are both integers greater than or equal to 1; the thickness of each layer of the first type of thin film is not greater than a preset thickness, and the thickness of each layer of the second type of thin film is greater than a preset thickness; After each layer of the first type of thin film is grown by liquid source, the layer of the first type of thin film is subjected to ultraviolet irradiation treatment; after each layer of the second type of thin film is grown by liquid source, the layer of the second type of thin film is subjected to fine polishing treatment.

2. The semiconductor process method according to claim 1, characterized in that: The preset thickness is 50 nanometers to 300 nanometers.

3. The semiconductor process method according to claim 1, characterized in that: The wavelength of ultraviolet light used in the ultraviolet irradiation treatment is 50 nanometers to 300 nanometers.

4. The semiconductor process method according to claim 1, characterized in that: The ultraviolet irradiation treatment is performed for 15 seconds to 30 seconds.

5. The semiconductor process method according to claim 1, characterized in that: The polishing rate for fine polishing is 0.5 nanometers per second to 1 nanometer per second.

6. The semiconductor process method according to claim 1, characterized in that: The average particle size of the particles of the polishing pad used for fine polishing is 100 nm to 300 nm.

7. The semiconductor process method according to claim 1, characterized in that: Each layer of the second type of film that is subjected to fine polishing is thinned to a thickness of 5 nanometers to 10 nanometers.

8. The semiconductor process method according to claim 1, characterized in that: The first type of thin film and / or the second type of thin film are grown from a liquid source by plasma enhanced chemical vapor deposition.

9. The semiconductor process method according to any one of claims 1 to 8, characterized in that: The first type of thin films are all grown before the second type of thin films, and the total thickness of n layers of the first type of thin films is no greater than 50 nanometers to 300 nanometers.

10. A semiconductor structure, characterized in that: The semiconductor structure is obtained by the semiconductor process method described in any one of claims 1 to 9, and the semiconductor structure is obtained by the semiconductor process method described in any one of the above, and the semiconductor structure includes a structure to be deposited, n layers of first-type thin films and m layers of second-type thin films, the first-type thin films and the second-type thin films are both located on the structure to be deposited, and n and m are both integers greater than or equal to 1; the thickness of each layer of the first-type thin film is not greater than a preset thickness, and the thickness of each layer of the second-type thin film is greater than a preset thickness.

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