Low-loss chip packaging structure and preparation method thereof

Abstract

The invention relates to a low-loss chip packaging structure and a preparation method thereof, and relates to the technical field of semiconductors, in the preparation method of the low-loss chip packaging structure, a first rewiring structure and a second rewiring structure are prepared on two sides of a first chip respectively; according to the packaging structure, the first chip is mounted on one side of the first re-wiring structure, and then the second chip is mounted on one side of the first re-wiring structure, so that wiring is not needed after the second chip is mounted, alternate cooling and heating of the packaging structure cannot be caused, influence on the second chip cannot be caused, warping, splitting or other damage of the second chip is avoided, and the yield of the packaging structure is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a chip packaging structure with low loss and a preparation method thereof. Background Art

[0002] The packaging process is a key process in semiconductor manufacturing, which is used to protect the chip, achieve electrical connection and ensure device performance.

[0003] After mounting the functional chip in the existing packaging process, a wiring layer and pads are further formed on the other side of the functional chip to facilitate connection with the external circuit. During the process of forming the wiring layer and pads, due to process manufacturing reasons, the packaging structure will inevitably be in a state of alternating hot and cold, which will cause the functional chip to warp, crack or other damages, resulting in a low yield rate of the packaging structure. Summary of the Invention

[0004] Based on this, it is necessary to provide a chip packaging structure with low loss and a preparation method thereof for the problem of low yield rate of the packaging structure.

[0005] To achieve the above object, on the one hand, the present invention provides a preparation method of a chip packaging structure with low loss, including:

[0006] Providing a substrate, the substrate includes a first carrier plate, a first chip and a first packaging layer, the first chip is located on one side of the first carrier plate, and the first packaging layer covers the side wall of the first chip;

[0007] Forming a first redistribution structure on the side of the first chip away from the first carrier plate;

[0008] Bonding the side of the first redistribution structure away from the first packaging layer to a second carrier plate, and removing the first carrier plate;

[0009] Forming a second redistribution structure on the side of the first chip away from the second carrier plate;

[0010] Bonding the side of the second redistribution structure away from the second carrier plate to a third carrier plate, and removing the second carrier plate;

[0011] Mounting a second chip on the side of the first redistribution structure away from the third carrier plate.

[0012] In one embodiment, before forming the second redistribution structure on the side of the first chip away from the second carrier plate, it includes:

[0013] Thinning the side of the first chip away from the second carrier plate to expose the first pad of the first chip.

[0014] In one embodiment, the second re - wiring structure includes a first dielectric layer having a plurality of vias. The second re - wiring structure is formed on a side of the first chip away from the second carrier board, and includes:

[0015] Form a first dielectric material layer on a side of the first chip away from the second carrier board;

[0016] Etch the first dielectric material layer to form the first dielectric layer having a plurality of vias.

[0017] In one embodiment, after mounting the second chip on a side of the first re - wiring structure away from the third carrier board, it further includes:

[0018] Remove the third carrier board.

[0019] In one embodiment, after removing the third carrier board, it includes:

[0020] Form a conductive structure in the vias of the first dielectric layer;

[0021] Form a package pad on a side of the conductive structure away from the first chip, and the package pad is connected to the first chip through the conductive structure.

[0022] In one embodiment, after mounting the second chip on a side of the first re - wiring structure away from the third carrier board, it includes:

[0023] Form a second package layer on a side of the second chip away from the third carrier board.

[0024] In one embodiment, the first chip is a bridging chip and the second chip is a functional chip.

[0025] In one embodiment, providing the substrate includes:

[0026] Provide the first carrier board;

[0027] Mount the first chip on one side of the first carrier board;

[0028] Form a first encapsulation material layer on a side of the first carrier board where the first chip is disposed;

[0029] Using the first carrier board as a support, grind the first chip and the first encapsulation material layer to form the first encapsulation layer and expose the second pad of the first chip.

[0030] In one embodiment, before mounting the first chip on one side of the first carrier board, it includes:

[0031] Form conductive posts on one side of the first carrier substrate, and the conductive posts are on the same side as the first chip.

[0032] On the other hand, the present application also provides a chip packaging structure with low loss, and the chip packaging structure with low loss is prepared according to any one of the above preparation methods.

[0033] Compared with the prior art, the above technical solution has the following advantages:

[0034] In the chip packaging structure with low loss and its preparation method, a substrate is first provided, and the substrate includes a first carrier substrate, a first chip, and a first packaging layer. The first chip is located on one side of the first carrier substrate, and the first packaging layer covers the side wall of the first chip. A first redistribution structure is formed on the side of the first chip away from the first carrier substrate, and then a second carrier substrate is bonded to the side of the first redistribution structure away from the first packaging layer, and the first carrier substrate is removed. Then a second redistribution structure is formed on the side of the first chip away from the second carrier substrate. After bonding the side of the second redistribution structure away from the second carrier substrate to a third carrier substrate, the second carrier substrate is removed. Then a second chip is mounted on the side of the first redistribution structure away from the third carrier substrate.

[0035] In the preparation method of the chip packaging structure with low loss, since the first redistribution structure and the second redistribution structure are respectively prepared on both sides of the first chip first, and then the second chip is mounted on one side of the first redistribution structure, after the second chip is mounted, there is no need to perform wiring, so that the packaging structure will not be alternately heated and cooled, and thus will not affect the second chip, thereby avoiding warping, cracking or other damages of the second chip and improving the yield of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 It is a schematic flow chart of the preparation of a chip packaging structure with low loss provided by an embodiment of the present application;

[0038] Figure 2 It is a schematic structural diagram of a first carrier substrate provided by an embodiment of the present application;

[0039] Figure 3 It is a schematic structural diagram after forming conductive posts provided by an embodiment of the present application;

[0040] Figure 4 This is a schematic diagram of the structure after mounting the first chip provided by an embodiment of the present application;

[0041] Figure 5 This is a schematic diagram of the structure after forming the first encapsulation layer provided by an embodiment of the present application;

[0042] Figure 6 This is a schematic diagram of the structure after forming the first redistribution structure provided by an embodiment of the present application;

[0043] Figure 7 This is a schematic diagram of the structure after adhering the second carrier provided by an embodiment of the present application;

[0044] Figure 8 This is a schematic diagram of the structure after thinning the first chip provided by an embodiment of the present application;

[0045] Figure 9 This is a schematic diagram of the structure after forming the second redistribution structure provided by an embodiment of the present application;

[0046] Figure 10 This is a schematic diagram of the structure after adhering the third carrier provided by an embodiment of the present application;

[0047] Figure 11 This is a schematic diagram of the structure after removing the second carrier provided by an embodiment of the present application;

[0048] Figure 12 This is a schematic diagram of the structure after forming the first pad provided by an embodiment of the present application;

[0049] Figure 13 This is a schematic diagram of the structure after mounting the second chip provided by an embodiment of the present application;

[0050] Figure 14 This is a schematic diagram of the structure after forming the second encapsulation layer provided by an embodiment of the present application;

[0051] Figure 15 This is a schematic diagram of the structure after performing a circumferential cut on the second encapsulation layer provided by an embodiment of the present application;

[0052] Figure 16 This is a schematic diagram of the structure after removing the third carrier provided by an embodiment of the present application;

[0053] Figure 17 This is a schematic diagram of the structure after forming the encapsulation pad provided by an embodiment of the present application.

[0054] Explanation of the reference numerals: 011-first carrier; 012-third demolding layer; 013-third adhesive layer; 02-first chip; 021-second solder pad; 022-first solder pad; 023-insulating layer; 03-first packaging layer; 04-first redistribution structure; 041-second through hole; 042-second dielectric layer; 051-second carrier; 052-first demolding layer; 053-first adhesive layer; 06-second redistribution structure; 061-first through hole; 062-first dielectric layer; 071-third carrier; 072-second demolding layer; 073-second adhesive layer; 08-third solder pad; 09-second chip; 10-second packaging layer; 101-bottom-fill layer; 11-conductive column; 12-packaging pad; 13-conductive structure. DETAILED DESCRIPTION

[0055] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0057] It should be understood that when a layer is referred to as being "on," "adjacent to," or "connected to" another layer, it can be directly on, adjacent to, or connected to the other layer, or intervening layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another layer, there are no intervening layers.

[0058] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0059] In order to make the purpose, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0060] Please refer to Figure 1 , Figure 1The figure is a schematic diagram of the preparation process of a chip packaging structure with low loss provided by an embodiment of the present application; the preparation steps of the low-loss chip packaging structure include:

[0061] S10: Provide a substrate.

[0062] Among them, the substrate includes a first carrier plate 011, a first chip 02, and a first encapsulation layer 03. The first chip 02 is located on one side of the first carrier plate 011, and the first encapsulation layer 03 covers the side wall of the first chip 02 (as Figure 5 shown).

[0063] Specifically, the first carrier plate 011 can be a carrier plate for support, including but not limited to a glass carrier plate. The first chip 02 is used for bridging, and the material of the first encapsulation layer 03 can include but not limited to epoxy molding compound (EMC).

[0064] S20: Form a first redistribution structure 04 on the side of the first chip 02 away from the first carrier plate 011 (as Figure 6 shown).

[0065] The first redistribution structure 04 formed on the side of the first chip 02 away from the first carrier plate 011 can include multiple interconnected wiring layers, which is only an example in the figure.

[0066] S30: Bond the side of the first redistribution structure 04 away from the first chip 02 to the second carrier plate 051, and remove the first carrier plate 011 (as Figure 7 shown).

[0067] It should be noted that before bonding the side of the first redistribution structure 04 away from the first chip 02 to the second carrier plate 051, a first release layer 052 and a first adhesive layer 053 can be set first to facilitate the subsequent removal of the second carrier plate 051.

[0068] The second carrier plate 051 can be a carrier plate for support, including but not limited to a glass carrier plate.

[0069] It should be noted that the first carrier plate 011 can be removed by laser lift-off to peel the first carrier plate 011 from the substrate.

[0070] S40: Form a second redistribution structure 06 on the side of the first chip 02 away from the second carrier plate 051 (as Figure 9 shown).

[0071] Taking the second carrier plate 051 as a support plate, a second redistribution structure 06 is formed on the side of the first chip 02 away from the second carrier plate 051. The second redistribution structure 06 can include multiple interconnected wiring layers, without specific limitation, as long as the structure interconnection can be achieved.

[0072] S50: Bond the side of the second rewiring structure 06 away from the second carrier plate 051 to the third carrier plate 071, and remove the second carrier plate 051 (as Figure 10 , Figure 11 shown).

[0073] The third carrier plate 071 can be a carrier plate for support, including but not limited to a glass carrier plate.

[0074] Before bonding the side of the second rewiring structure 06 away from the second carrier plate 051 to the third carrier plate 071, a second release layer 072 and a second adhesive layer 073 can be provided first to facilitate the subsequent removal of the third carrier plate 071.

[0075] The second carrier plate 051 can be removed by laser lift-off. Peel off the first release layer 052 and clean the first adhesive layer 053, so as to peel off the second carrier plate 051 from the first rewiring structure 04 (as Figure 11 shown), exposing the second through-hole 041 of the first rewiring structure 04.

[0076] S60: Mount the second chip 09 on the side of the first rewiring structure 04 away from the third carrier plate 071 (as Figure 13 shown).

[0077] It should be noted that the second chip 09 can be mounted by flip-chip mounting. First, form a third solder pad 08 in the second through-hole 041 of the exposed first rewiring structure 04 (as Figure 12 shown), and then connect the second chip 09 to the first rewiring structure 04 through the third solder pad 08.

[0078] In this embodiment, since the first rewiring structure 04 and the second rewiring structure 06 are respectively fabricated on both sides of the first chip 02 first, and then the second chip 09 is mounted on one side of the first rewiring structure 04, therefore, after the second chip 09 is mounted, there is no need for further wiring, thus preventing the package structure from experiencing thermal cycling, and further preventing any impact on the second chip 09, thereby avoiding warping, cracking or other damages of the second chip 09 and improving the yield rate of the package structure.

[0079] In another embodiment of the present application, the first chip 02 is a bridging chip and the second chip 09 is a functional chip.

[0080] Specifically, the first chip 02 can be a bridging chip, which can include a bridging substrate and rewiring structures located on both sides of the bridging substrate respectively, and the bridging chip can achieve electrical connection of the structures on both sides.

[0081] The second chip 09 can be a functional chip, and the functional chip can achieve the functions of the package structure.

[0082] In this embodiment, the first chip 02 can realize the electrical connection between the second chip 09 and the external structure.

[0083] In another embodiment of the present application, as Figure 9 shown, the second re - wiring structure 06 includes a first dielectric layer 062 having a plurality of first vias 061. The second re - wiring structure 06 is formed on the side of the first chip 02 away from the second carrier board 051, and includes:

[0084] S401: Form a first dielectric material layer (not shown) on the side of the first chip 02 away from the second carrier board 051;

[0085] S402: Etch the first dielectric material layer to form a first dielectric layer 062 having a plurality of first vias 061.

[0086] Specifically, when forming the second re - wiring structure 06 on the side of the first chip 02 away from the second carrier board 051, the second re - wiring structure 06 can be a first dielectric layer 062 having a plurality of first vias 061. Using the first dielectric layer 062 as the second re - wiring structure 06 can shorten the connection distance.

[0087] When forming the first dielectric layer 062, a first dielectric material layer can be formed on the side of the first chip 02 away from the second carrier board 051, and the material of the first dielectric material layer can be polyimide (PI) material.

[0088] Then, a plurality of first vias 061 are formed on the first dielectric material layer by photolithography. The first vias 061 can expose part of the metal structure on the substrate to facilitate the formation of electrical connections in the subsequent process.

[0089] In this embodiment, setting the second re - wiring structure 06 as a first dielectric layer 062 having a plurality of first vias 061 can shorten the connection distance, achieve high - density interconnection, and save costs at the same time.

[0090] It should be noted that the first re - wiring structure 04 can also include a second dielectric layer 042 located on the side away from the first carrier board 011, and the second dielectric layer 042 can include a plurality of second vias 041 to facilitate connection with other structures.

[0091] In another embodiment of the present application, before forming the second re - wiring structure 06 on the side of the first chip 02 away from the second carrier board 051, it includes:

[0092] Thin the side of the first chip 02 away from the second carrier board 051 to expose the first pad 022 of the first chip 02 (as Figure 8 shown).

[0093] Specifically, the first chip 02 is a bridging chip, which may include a bridging substrate and redistribution structures located on both sides of the bridging substrate. It should be noted that the outermost layer of the redistribution structure of the bridging chip may include an insulating layer 023 covering the first pad 022 (as Figure 7 shown), and the insulating layer 023 can protect the first pad 022. To achieve connection, it is necessary to expose the first pad 022 of the first chip 02. Therefore, the side of the first chip 02 away from the second carrier 051 is thinned, and the thinning process includes but is not limited to grinding.

[0094] In this embodiment, thinning the side of the first chip 02 away from the second carrier 051 can expose the first pad 022 of the first chip 02, and the first pad 022 is used to connect to the second redistribution structure 06 for subsequent connection to an external circuit.

[0095] In another embodiment of the present application, after mounting the second chip 09 on the side of the first redistribution structure 04 away from the third carrier 071, it includes:

[0096] Forming a second encapsulation layer 10 on the side of the second chip 09 away from the third carrier 071 (as Figure 15 shown).

[0097] Specifically, after flip-chip mounting the second chip 09 on the first redistribution structure 04, in order to protect the second chip 09, a second encapsulation layer 10 is formed on the side of the second chip 09 away from the third carrier 071. The material of the second encapsulation layer 10 may include but is not limited to epoxy molding compound (EMC).

[0098] It should be noted that the second encapsulation layer 10 may further include an underfill layer 101 (as Figure 13 shown), which is located between the first redistribution structure 04 and the second chip 09, used to protect the solder joints when mounting the second chip 09, and at the same time provide mechanical support for the second chip 09 to improve the reliability of the packaging structure.

[0099] It should also be noted that after the second encapsulation layer 10 is formed, it at least covers the second chip 09, the substrate, and the third carrier 071 (as Figure 14 shown). For the preparation of subsequent structures, the second encapsulation layer 10 needs to be circumferentially cut to expose the third carrier 071 (as Figure 15 shown).

[0100] In this embodiment, forming the second encapsulation layer 10 can protect the second chip 09 and improve the reliability of the packaging structure.

[0101] In another embodiment of the present application, after mounting the second chip 09 on the side of the first rewiring structure 04 away from the third carrier 071, the following steps are further included:

[0102] Removing the third carrier 071 (as Figure 16 shown).

[0103] Specifically, after mounting the second chip 09, to achieve the connection between the second chip 09 and the external circuit, the third carrier 071 acting as a support plate is removed.

[0104] In this embodiment, the third carrier 071 can be removed by using a laser lift-off technique to peel off the second release layer 072 and clean the second adhesive layer 073, thereby peeling off the third carrier 071 from the second rewiring structure 06.

[0105] In another embodiment of the present application, as Figure 17 shown, after removing the third carrier 071, the following steps are included:

[0106] Forming a conductive structure 13 in the first through hole 061 of the first dielectric layer 062;

[0107] Forming a package pad 12 on the side of the conductive structure 13 away from the first chip 02, and the package pad 12 is connected to the first chip 02 through the conductive structure 13.

[0108] Specifically, after removing the third carrier 071, the first dielectric layer 062 (second rewiring structure 06) is exposed. At this time, the second adhesive layer 073 in the through hole of the first dielectric layer 062 is cleaned off, and the first pad 022 of the first chip 02 is exposed, and a conductive structure 13 is formed in the first through hole 061. The material of the conductive structure 13 can be a conductive metal material.

[0109] In this embodiment, a package pad 12 is formed on the side of the conductive structure 13 away from the first chip 02, and the package pad 12 is connected to the first chip 02 through the conductive structure 13, and the first chip 02 is connected to the second chip 09, so that the low-loss chip package structure can be conducted with the external circuit.

[0110] In another embodiment of the present application, a substrate is provided, including:

[0111] Providing a first carrier 011 (as Figure 2 shown);

[0112] Mounting a first chip 02 on one side of the first carrier 011 (as Figure 4 shown);

[0113] Forming a first encapsulation material layer (not shown) on the side of the first carrier 011 where the first chip 02 is disposed;

[0114] With the first carrier 011 as a support, the first chip 02 and the first encapsulation material layer are ground to form the first encapsulation layer 03, and the second pad 021 of the first chip 02 is exposed (as Figure 4 shown).

[0115] Specifically, to prepare the substrate, the first carrier 011 can be provided first. The first carrier 011 can include, but is not limited to, a glass carrier. The first chip 02 is mounted on one side of the first carrier 011. The first chip 02 is the bridging chip.

[0116] Then, on the side of the first carrier 011 where the first chip 02 is disposed, a first encapsulation material layer is formed, and the first encapsulation material layer covers the first chip 02. Then, with the first carrier 011 as a support, the first chip 02 and the first encapsulation material layer are ground to form the first encapsulation layer 03. During this grinding, in order to ensure electrical connection between the first chip 02 and the subsequent first redistribution structure 04, the second pad 021 of the first chip 02 needs to be exposed. Therefore, while grinding the first encapsulation material layer, the side of the first chip 02 away from the first carrier 011 is ground, so that the second pad 021 of the first chip 02 is exposed.

[0117] In this embodiment, the provided substrate can serve as a bridge for the second chip 09 to connect to an external circuit, providing a basis for subsequent mounting of the second chip 09 and formation of the encapsulation pads 12.

[0118] In another embodiment of the present application, before mounting the first chip 02 on one side of the first carrier 011, it includes:

[0119] Forming conductive pillars 11 on one side of the first carrier 011. The conductive pillars 11 are on the same side as the first chip 02 (as Figure 3 shown).

[0120] Specifically, before mounting the first chip 02 on one side of the first carrier 011, a third release layer 012 and a third adhesive layer 013 can be formed on one side of the first carrier 011 to ensure firm bonding and reliability. When removing the first carrier 011, laser lift-off technology can be used to peel off the third release layer 012 and clean the third adhesive layer 013, thereby removing the first carrier 011.

[0121] Then, conductive pillars 11 are formed on one side of the third adhesive layer 013. The conductive pillars 11 can provide mechanical support to protect the subsequently attached first chip 02. Also, the conductive pillars 11 can provide a short and direct electrical path, reducing signal transmission delay and improving the performance of the system.

[0122] Based on the preparation method of the low-loss chip packaging structure provided above, the present application also provides a low-loss chip packaging structure, which is prepared according to the above preparation method.

[0123] Since the first redistribution structure 04 and the second redistribution structure 06 are respectively prepared on both sides of the first chip 02, and then the second chip 09 is mounted on one side of the first redistribution structure 04, no further wiring is required after the second chip 09 is mounted. As a result, the packaging structure will not be affected by thermal cycling, and thus will not cause warping, chipping or other damage to the second chip 09, improving the yield rate of the packaging structure.

[0124] It should be noted that the low-loss chip packaging structure is obtained by the preparation method of the low-loss chip packaging structure described above. The specific content can be referred to each other and will not be elaborated here.

[0125] In the description of this specification, the descriptions referring to terms such as "some embodiments", "another embodiment", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0126] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0127] The above-described embodiments only represent several implementation manners of the present application. The descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for preparing a low-loss chip packaging structure, characterized in that: include: Providing a substrate, the substrate comprising a first carrier, a first chip and a first packaging layer, the first chip is located on one side of the first carrier, and the first packaging layer covers a side wall of the first chip; forming a first redistribution structure on a side of the first chip away from the first carrier; Bonding a side of the first redistribution structure away from the first packaging layer to a second carrier, and removing the first carrier; forming a second redistribution structure on a side of the first chip away from the second carrier; Bonding a side of the second redistribution structure away from the second carrier to a third carrier, and removing the second carrier; A second chip is mounted on a side of the first redistribution structure away from the third carrier board.

2. The method for preparing a low-loss chip packaging structure according to claim 1, characterized in that: Before forming the second redistribution structure on the side of the first chip away from the second carrier, the method includes: A side of the first chip away from the second carrier is thinned to expose a first pad of the first chip.

3. The method for preparing a low-loss chip packaging structure according to claim 1, characterized in that: The second redistribution structure includes a first dielectric layer having a plurality of through holes, and the second redistribution structure is formed on a side of the first chip away from the second carrier, including: forming a first dielectric material layer on a side of the first chip away from the second carrier; The first dielectric material layer is etched to form the first dielectric layer having a plurality of through holes.

4. The method for preparing a low-loss chip packaging structure according to claim 3, characterized in that: After mounting the second chip on the side of the first redistribution structure away from the third carrier board, the method further includes: The third carrier board is removed.

5. The method for preparing a low-loss chip packaging structure according to claim 4, characterized in that: After removing the third carrier board, the method comprises: forming a conductive structure in the through hole of the first dielectric layer; A packaging pad is formed on a side of the conductive structure away from the first chip, and the packaging pad is connected to the first chip through the conductive structure.

6. The method for preparing a low-loss chip packaging structure according to claim 1, characterized in that: After mounting the second chip on the side of the first redistribution structure away from the third carrier board, the method includes: A second packaging layer is formed on a side of the second chip away from the third carrier.

7. The method for preparing a low-loss chip packaging structure according to claim 1, characterized in that: The first chip is a bridge chip, and the second chip is a functional chip.

8. The method for preparing a low-loss chip packaging structure according to claim 1, characterized in that: The providing of a substrate comprises: Providing the first carrier board; Mounting the first chip on one side of the first carrier board; forming a first packaging material layer on a side of the first carrier board where the first chip is disposed; With the first carrier as support, the first chip and the first packaging material layer are ground to form the first packaging layer and expose the second pad of the first chip.

9. The method for preparing a low-loss chip packaging structure according to claim 8, characterized in that: Before mounting the first chip on one side of the first carrier, the method includes: A conductive column is formed on one side of the first carrier, and the conductive column and the first chip are located on the same side.

10. A low-loss chip packaging structure, characterized in that: The low-loss chip packaging structure is prepared according to the preparation method according to any one of claims 1-9.

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