Formation method of semiconductor structure, semiconductor structure and electronic device

Abstract

The invention discloses a forming method of a semiconductor structure, the semiconductor structure and an electronic device, and the method comprises the steps: providing a substrate which comprises a bottom metal layer, an interlayer dielectric layer, a metal hard mask layer and a first patterned oxide hard mask layer, and enabling the first patterned oxide hard mask layer to indicate a pattern used for forming a groove of an upper metal layer; forming a planarization layer on the first patterned oxide hard mask layer; forming a second patterned oxide hard mask layer defining a pattern of a through hole on the planarization layer; transferring the pattern of the through hole defined in the second patterned oxide hard mask layer into the metal hard mask layer to form a first patterned metal hard mask layer; and forming a groove and a through hole in the interlayer dielectric layer based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer. The control accuracy of the critical dimension of the through hole in the non-self-alignment direction is improved, and bridging between the through hole and the bottom layer metal is avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. Background Art

[0002] In the back-end-of-line (BEOL) process of semiconductor devices, a dual damascene process is usually used to form a dual damascene structure. Among them, the via hole is a key part of the dual damascene structure. The via hole with a high aspect ratio is not only beneficial to the contact of the interlayer metal, but also beneficial to reducing the resistance of the back-end interconnection. As the technology node shrinks below 7 nm, the critical dimension of the via hole is further reduced, so higher requirements are put forward for the control accuracy of the critical dimension of the via hole.

[0003] Among them, a via hole with different critical dimensions of length (Critical Dimension, CD) and width CD, such as a rectangular via hole, can reduce the resistance capacitor (RC) of the back-end interconnection. In the related art, when forming a dual damascene structure with a rectangular via hole by using a traditional dual damascene integrated process, the control accuracy of the critical dimension of the rectangular via hole in the non-self-alignment direction is poor, which is likely to cause bridging between the via hole and the front-layer metal, thereby affecting the performance of the semiconductor device. Summary of the Invention

[0004] In order to solve the problems of the prior art, embodiments of the present application provide a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. The technical solutions are as follows:

[0005] On the one hand, a method for forming a semiconductor structure is provided, including:

[0006] Providing a substrate, the substrate includes a bottom metal layer, an interlayer dielectric layer, a metal hard mask layer, and a first patterned oxide hard mask layer which are stacked; a plurality of first openings exposing the upper surface of the metal hard mask layer are formed in the first patterned oxide hard mask layer, and the plurality of first openings indicate the pattern of the trenches for forming the upper metal layer;

[0007] Forming a planarization layer on the first patterned oxide hard mask layer, the planarization layer fills the plurality of first openings and covers the upper surface of the first patterned oxide hard mask layer;

[0008] Forming a second patterned oxide hard mask layer on the planarization layer, the second patterned oxide hard mask layer defines the pattern of the via hole;

[0009] Transfer the pattern of the through holes defined in the second patterned oxide hard mask layer to the metal hard mask layer to form a first patterned metal hard mask layer;

[0010] Based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer, form the trench and the through hole in the interlayer dielectric layer; the bottom of the trench is in communication with the top of the through hole.

[0011] In an exemplary embodiment, an etch stop layer is formed between the interlayer dielectric layer and the metal hard mask layer; the transferring the pattern of the through holes defined in the second patterned oxide hard mask layer to the metal hard mask layer to form a first patterned metal hard mask layer includes:

[0012] Using the second patterned oxide hard mask layer as a mask, etch the planarization layer based on a first etching process until the upper surface of the metal hard mask layer is exposed;

[0013] Etch the exposed metal hard mask layer based on a second etching process and stop at the etch stop layer to form a second opening penetrating the metal hard mask layer in the defined area of the through hole in the metal hard mask layer, and the size of the second opening is smaller than the size of the first opening;

[0014] Remove the second patterned oxide hard mask layer and the planarization layer.

[0015] In an exemplary embodiment, the forming the trench and the through hole in the interlayer dielectric layer based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer includes:

[0016] Using the first patterned oxide hard mask layer as a mask, perform an etching process on the remaining metal hard mask layer exposed in the first opening to obtain a second patterned metal hard mask layer formed with the trench pattern; wherein, during the etching process, the etch stop layer exposed by the second opening in the first patterned metal hard mask layer and a part of the interlayer dielectric layer are etched to form a part of the through hole in the interlayer dielectric layer;

[0017] Using the first patterned oxide hard mask layer and the second patterned metal hard mask layer as masks, etch the interlayer dielectric layer along the trench pattern and the part of the through hole until the underlying metal layer is exposed to obtain the trench and the through hole formed in the interlayer dielectric layer.

[0018] In an exemplary embodiment, the method further includes:

[0019] Provide a semiconductor substrate in which the underlying metal layer is formed;

[0020] Form an interlayer dielectric layer and an etch stop layer in sequence on the surface of the semiconductor substrate, and the interlayer dielectric layer covers the underlying metal layer;

[0021] Form a metal hard mask layer on the etch stop layer;

[0022] Form a first oxide hard mask layer on the metal hard mask layer;

[0023] Form a first patterned photoresist layer on the first oxide hard mask layer; the first patterned photoresist layer defines a pattern for a trench for forming an upper metal layer;

[0024] Using the first patterned photoresist layer as a mask, etch the first oxide hard mask layer until the upper surface of the metal hard mask layer is exposed and stop;

[0025] Remove the remaining first patterned photoresist layer to obtain the substrate.

[0026] In an exemplary embodiment, forming a second patterned oxide hard mask layer on the planarization layer includes:

[0027] Form a second oxide hard mask layer, an anti-reflection layer, and a second patterned photoresist layer in sequence on the planarization layer; the second patterned photoresist layer defines a pattern for a via;

[0028] Using the second patterned photoresist layer as a mask, etch the anti-reflection layer and the second oxide hard mask layer in sequence;

[0029] Remove the remaining second patterned photoresist layer and the remaining anti-reflection layer to obtain the second patterned oxide hard mask layer.

[0030] In an exemplary embodiment, after forming the trench and the via in the interlayer dielectric layer, the method further includes:

[0031] Remove the first patterned oxide hard mask layer and the remaining metal hard mask layer.

[0032] In an exemplary embodiment, after removing the first patterned oxide hard mask layer and the remaining metal hard mask layer, the method further includes:

[0033] Fill the trench and the via with a conductive material.

[0034] In an exemplary embodiment, the lithography process in the forming method uses a deep ultraviolet lithography process.

[0035] In an exemplary embodiment, the critical dimension of the length of the through hole is different from the critical dimension of the width.

[0036] On the other hand, there is provided a semiconductor structure formed by using the forming method of any one of the foregoing semiconductor structures, and the semiconductor structure includes:

[0037] A semiconductor substrate, in which an underlying metal layer is formed;

[0038] An interlayer dielectric layer formed on the surface of the semiconductor substrate and covering the underlying metal layer;

[0039] A trench and a through hole formed in the interlayer dielectric layer; the bottom of the trench is communicated with the top of the through hole.

[0040] In an exemplary embodiment, the semiconductor structure further includes: a conductive material filled in the trench and the through hole.

[0041] In an exemplary embodiment, an etch stop layer is further formed on the interlayer dielectric layer, and the trench penetrates through the etch stop layer and extends into the interlayer dielectric layer.

[0042] In an exemplary embodiment, the critical dimension of the length of the through hole is different from the critical dimension of the width.

[0043] On the other hand, there is provided an electronic device, and the electronic device includes a semiconductor structure formed by using the forming method of any one of the foregoing semiconductor structures.

[0044] In the embodiment of the present application, by providing a substrate in which a metal hard mask layer is not etched, a first patterned oxide hard mask layer defining a trench pattern is formed on the metal hard mask layer, and then a planarization layer is formed on the first patterned oxide mask layer, and a second patterned oxide hard mask layer defining a through hole pattern is formed on the planarization layer. Then, the pattern of the through hole defined in the second patterned oxide hard mask layer is transferred to the metal hard mask layer to form a first patterned metal hard mask layer. Furthermore, based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer, a dual damascene structure having a trench and a through hole is formed in the interlayer dielectric layer of the substrate, so that the etching of the metal hard mask layer is after the formation of the second patterned oxide hard mask layer, thereby well controlling the critical dimension of the through hole in the non-self-aligned direction by using the metal hard mask layer, improving the control accuracy of the critical dimension of the rectangular through hole in the non-self-aligned direction, expanding the process window of such through holes, and further avoiding the bridging between the through hole and the underlying metal, and improving the performance of the semiconductor device. Description of the Drawings

[0045] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0046] Figures 1a to 1b The figure shows a partial cross-sectional view during the process of forming a dual damascene structure using the traditional dual damascene integrated process in the prior art;

[0047] Figure 1c The figure shows a schematic plan view of some square through-holes during the process of forming square through-holes using the traditional dual damascene integrated process in the prior art;

[0048] Figure 1d The figure shows a schematic plan view of rectangular through-holes during the process of forming rectangular through-holes using the traditional dual damascene integrated process in the prior art;

[0049] Figure 2 It is a schematic flow chart of the formation process of the semiconductor structure provided by the embodiment of the present application;

[0050] Figures 3 to 11 It is a cross-sectional view during the formation process of the semiconductor structure provided by the embodiment of the present application;

[0051] Figure 12 It is a cross-sectional view of a semiconductor structure provided by the embodiment of the present application; Detailed implementation manners

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0053] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily describe a specific object or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or server comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0054] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part. And when discussing the second element, component, region, layer or part, it does not mean that there must be a first element, component, region, layer or part in this application.

[0055] Figures 1a to 1b The figure shows a partial cross-sectional view during the formation of a dual-damascene structure using a traditional dual-damascene integration process. Usually, the pattern of the trench is first transferred into the metal hard mask layer and the oxide hard mask layer on the semiconductor substrate, as Figure 1a shown, the metal hard mask layer 120 and the oxide hard mask layer 130 on the semiconductor substrate 110 are both etched to form a trench pattern 140 in the metal hard mask layer 120 and the oxide hard mask layer 130; then the via pattern is transferred into the interlayer dielectric layer to form partial interconnection vias in the interlayer dielectric layer, as Figure 1bAs shown, partial through-holes 150 are formed in the interlayer dielectric layer 160, and the partial through-holes 150 communicate with the trench pattern 140 in the metal hard mask layer 120 and the oxide hard mask layer 130. Then, trenches and through-holes are formed in the interlayer dielectric layer 160, and the through-holes expose the underlying metal layer 170 in the semiconductor substrate 110.

[0056] The above traditional dual damascene integration process is more friendly for forming a dual damascene structure with square through-holes. Since the etching deviation of the square through-holes in the self-aligned direction and the non-self-aligned direction is basically the same, when using the hard masks on both sides of the trench to control the critical dimension of the square through-holes in the self-aligned direction in the above traditional process, the critical dimension in the non-self-aligned direction will also be controlled.

[0057] It should be noted that in the embodiments of the present application, the self-aligned direction (Self-Aligned Via, SAV) refers to the direction perpendicular to the metal layer, and the non-self-aligned direction (Non Self-Aligned Via, Non-SAV) refers to the direction parallel to the metal layer.

[0058] As Figure 1c shown is a plan view of some square through-holes in the process of forming square through-holes by using the traditional dual damascene integration process in the prior art. In Figure 1c this, 101 represents some square through-holes, 102 represents the hard mask layer of the upper metal layer (such as Figure 1a the metal hard mask layer 120 and the oxide hard mask layer 130 in Figure 1a ), and 103 represents the underlying metal layer (such as Figure 1c the underlying metal layer 170 in

[0059] ). It can be seen that the critical dimensions of some square through-holes 101 in both the self-aligned direction and the non-self-aligned direction are well controlled. Figure 1d However, in a metal interconnect structure realized by using through-holes with different critical dimensions of length and width, such as rectangular through-holes, the metal pitch of the upper metal layer is larger than that of the underlying metal layer. When using the traditional dual damascene integration process to form a dual damascene structure with rectangular through-holes, the self-alignment function cannot be achieved by using the hard masks on both sides of the trench, resulting in the loss of control of the critical dimension of such through-holes in the non-self-aligned direction, and ultimately causing the through-hole to bridge with the underlying metal. As Figure 1d shown is a plan view of a rectangular through-hole in the process of forming a rectangular through-hole by using the traditional dual damascene integration process in the prior art. In this, the critical dimension of the rectangular through-hole 104 in the non-self-aligned direction is out of control, resulting in the bridging of the rectangular through-hole with the underlying metal.

[0060] Based on this, an embodiment of the present application provides a method for forming a semiconductor structure. The method includes providing a substrate in which a metal hard mask layer is not etched, forming a first patterned oxide hard mask layer defining a trench pattern on the metal hard mask layer, then forming a planarization layer on the first patterned oxide mask layer, and forming a second patterned oxide hard mask layer defining a via pattern on the planarization layer. Next, the pattern of the via defined in the second patterned oxide hard mask layer is transferred to the metal hard mask layer to form a first patterned metal hard mask layer. Furthermore, based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer, a dual damascene structure having trenches and vias is formed in the interlayer dielectric layer of the substrate, such that the etching of the metal hard mask layer is performed after the formation of the second patterned oxide hard mask layer. Thus, the metal hard mask layer is used to well control the critical dimension of the via in the non-self-aligned direction, improve the control accuracy of the critical dimension of a rectangular via in the non-self-aligned direction, expand the process window of such vias, and further avoid the bridging between the via and the underlying metal, thereby enhancing the performance of the semiconductor device.

[0061] It should be noted that the above-mentioned via formed by the forming method based on the embodiment of the present application can be a via with different critical dimensions of length and width. For example, the via can be a rectangular via. For the convenience of describing the technical solution of the embodiment of the present application, the technical solution of the embodiment of the present application will be elaborated in detail below by taking the rectangular via as an example. It should be emphasized that the rectangular via in the embodiment of the present application can be a via with a regular rectangular pattern or an irregular rectangular pattern.

[0062] Please refer to Figure 2 , which shows a schematic flow chart of a method for forming a semiconductor structure provided by an embodiment of the present application. Below, in conjunction with Figures 2 to 11 , the method for forming a semiconductor structure provided by the embodiment of the present application will be described in detail.

[0063] See Figure 2 , in step S201: Provide a substrate, which includes a bottom metal layer, an interlayer dielectric layer, a metal hard mask layer, and a first patterned oxide hard mask layer stacked.

[0064] Among them, the substrate provides a process operation basis for subsequent processes. As Figure 3 shown, the substrate 300 includes a bottom metal layer 310, an interlayer dielectric layer 320 is formed on the bottom metal layer 310, a metal hard mask layer 330 is formed on the interlayer dielectric layer 320, and a first patterned oxide hard mask layer 340 is formed on the metal hard mask layer 330.

[0065] Among them, the constituent material of the bottom metal layer 310 can be copper. The constituent material of the interlayer dielectric layer 320 can be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), so that the parasitic capacitance between metal layers can be effectively reduced, thereby reducing the subsequent RC delay. The constituent material of the metal hard mask layer 330 can be titanium nitride, titanium or copper nitride.

[0066] Among them, the first patterned oxide hard mask layer 340 defines the pattern of the trench for forming the upper metal layer. Specifically, as Figure 3 shown, a plurality of first openings 341 exposing the upper surface of the metal hard mask layer 330 are formed in the first patterned oxide hard mask layer 340, and the plurality of first openings 341 indicate the pattern of the trench for forming the upper metal layer.

[0067] It should be noted that the upper metal layer here is relative to the bottom metal layer, that is, the metal layer located on the bottom metal layer and interconnected with the bottom metal layer. Since the first metal layer M1 (which can also be called M0) involves the contact layer process and usually does not adopt the dual damascene process, the upper metal layer in the embodiments of the present application does not include the first metal layer M1 / M0.

[0068] It can be understood that the substrate 300 may further include a dielectric material layer (not shown in the figure). The bottom metal layer 310 is located in the dielectric material layer and is separated by the dielectric material layer to be insulated from each other.

[0069] In a specific embodiment, the substrate 300 may further include an etch stop layer 350, and the etch stop layer 350 is formed between the interlayer dielectric layer 320 and the metal hard mask layer 330.

[0070] The density and hardness of the constituent material of the etch stop layer 350 are better than those of the constituent material of the interlayer dielectric layer 320. Since the constituent material of the interlayer dielectric layer 320 is a low-k dielectric material or an ultra-low-k dielectric material, its properties are soft and it is easy to have an over-etching phenomenon. However, the density and hardness of the etch stop layer 350 are better. Forming the etch stop layer 350 on the surface of the interlayer dielectric layer 320 enables better control of the etching progress in the subsequent etching process, so that the morphology and size of the subsequent formed trenches and vias can meet the process specifications in the subsequent etching process. Exemplarily, the constituent material of the etch stop layer 350 may include SiO 2 , SiN, SiON, SiOC, or one or more of them.

[0071] Based on this, before step S201, the method may further include forming the substrate 300, Figures 4a to 4fThe cross-sectional view during the formation of the base 300 is shown.

[0072] Refer to Figure 4a , a semiconductor substrate 410 is provided, and a bottom metal layer 420 is formed in the semiconductor substrate 410.

[0073] Among them, a dielectric material layer (not shown in the figure) is also formed in the semiconductor substrate 410, and the bottom metal layer 420 is located in the dielectric material layer and is separated by the dielectric material layer to be insulated from each other.

[0074] Functional devices (not shown in the figure) electrically connected to the bottom metal layer 420 are also formed in the semiconductor substrate 410. The functional devices may include, for example, transistors, resistor structures, capacitor structures, and the like.

[0075] Refer to Figure 4b , an interlayer dielectric layer 430 and an etch stop layer 440 are sequentially formed on the surface of the semiconductor substrate 410, wherein the interlayer dielectric layer 430 covers the bottom metal layer 420.

[0076] In a specific implementation, the interlayer dielectric layer 430 and the etch stop layer 440 can be sequentially formed on the surface of the semiconductor bulk substrate 410 by chemical vapor deposition or physical vapor deposition.

[0077] Refer to Figure 4c , a metal hard mask layer 450 is formed on the etch stop layer 430. The formation process of the metal hard mask layer 450 can be physical vapor deposition.

[0078] Refer to Figure 4d , a first oxide hard mask layer 460 is formed on the metal hard mask layer 40. The constituent material of the first oxide hard mask layer 460 can be TEOS (tetraethyl orthosilicate), and the formation process of the first oxide hard mask layer 460 can be chemical vapor deposition.

[0079] Refer to Figure 4e , a first patterned photoresist layer 470 is formed on the first oxide hard mask layer 460, and the first patterned photoresist layer 470 defines a pattern for forming a trench for the upper metal layer.

[0080] Refer to Figure 4f , using the first patterned photoresist layer 470 as a mask, the first oxide hard mask layer 460 is etched until the upper surface of the metal hard mask layer 450 is exposed and stopped, so as to form a first opening 341 in the defined area corresponding to the trench pattern of the first oxide hard mask layer 460. The first opening 341 exposes the upper surface of the metal hard mask layer 440, thereby obtaining a first patterned oxide hard mask layer, and the metal hard mask layer 450 is not damaged during this etching.

[0081] Among them, the process of etching the first oxide hard mask layer 460 can be a plasma dry etching process.

[0082] Next, the remaining first patterned photoresist layer 470 is removed to obtain the aforementioned substrate 300 of the embodiment of the present application (see Figure 3 ). The remaining first patterned photoresist layer 470 can be removed by a wet etching process or a plasma dry etching process.

[0083] In the above embodiment, the pattern of the trench is only transferred to the first oxide hard mask layer, and the metal hard mask layer is not damaged, so that the metal hard mask layer can be used to accurately control the key dimensions of the rectangular through hole in the self-alignment direction and the non-self-alignment direction during subsequent processes such as the formation of rectangular through holes.

[0084] Continuing to refer to Figure 2 , in step S203: A planarization layer is formed on the first patterned oxide hard mask layer, and the planarization layer fills a plurality of first openings and covers the upper surface of the first patterned oxide hard mask layer.

[0085] Among them, the planarization layer is mainly used to planarize the undulations caused during the etching to form the first patterned oxide hard mask layer. In the embodiment of the present application, the constituent material of the planarization layer may include a spin-on hardmask (SOH) material, such as a silicon hard mask material, a carbon hard mask material, and an organic hard mask material, etc.

[0086] As Figure 5 shown, the planarization layer 510 covers the surface of the first patterned oxide hard mask layer 340 and fills the first openings 341 in the first patterned oxide hard mask layer 340.

[0087] Specifically, the process of forming the planarization layer 510 can be chemical vapor deposition or physical vapor deposition.

[0088] Continuing to refer to Figure 2 , in step S205: A second patterned oxide hard mask layer is formed on the planarization layer, and the pattern of the through hole is defined in the second patterned oxide hard mask layer.

[0089] Specifically, referring to Figure 6a , a second oxide hard mask layer 610, an anti-reflection layer 620, and a second patterned photoresist layer 630 are sequentially formed on the planarization layer 510, and the pattern of the rectangular through hole is defined in the second patterned photoresist layer 630.

[0090] Among them, the material of the second oxide hard mask layer 610 can be silicon oxide, which can include a layer of silicon oxide or multiple layers of different silicon oxides. In the embodiments of the present application, the second oxide hard mask layer 610 may include a low temperature oxide (LTO) hard mask layer 611 and an organic dielectric coating (ODC) layer 612 formed on the low temperature oxide (LTO) hard mask layer 611. Among them, the low temperature oxide (LTO) hard mask layer 611 can be used as a stop layer for subsequent etching of the second oxide hard mask layer 610.

[0091] Referring to Figure 6b , using the second patterned photoresist layer 630 as a mask, the anti-reflection layer 620 and the second oxide hard mask layer 610 are etched in sequence to transfer the pattern of the rectangular through hole into the second oxide hard mask layer 610.

[0092] In a specific implementation, using the second patterned photoresist layer 630 as a mask, the anti-reflection layer 620 and the ODC layer 612 in the second oxide hard mask layer 610 are etched along the rectangular through hole pattern until the low temperature oxide (LTO) hard mask layer 611 is exposed and then stopped, and openings 631 are formed at corresponding positions in the ODC layer 612, thereby transferring the pattern of the rectangular through hole into the second oxide hard mask layer 610.

[0093] In practical applications, in order to achieve a better lithography effect to realize a better transfer of the rectangular through hole pattern, continue to refer to Figure 6b , an organic planarization layer (not shown in the figure) can also be formed between the second oxide hard mask layer 610 and the anti-reflection layer 620. Then, when transferring the rectangular through hole pattern to the second oxide hard mask layer 610, using the second patterned photoresist layer 630 as a mask, the anti-reflection layer 620, the organic planarization layer and the second oxide hard mask layer 610 are etched in sequence.

[0094] Referring to Figure 6c , the remaining second patterned photoresist layer 630 and the remaining anti-reflection layer 620 are removed, and then the second patterned oxide hard mask layer 650 formed on the planarization layer 510 is obtained.

[0095] It can be understood that when the organic planarization layer is formed, when the remaining second patterned photoresist layer 630 and the remaining anti-reflection layer 620 are removed, the remaining organic planarization layer is also removed.

[0096] In a specific implementation, wet etching or plasma dry etching process can be used to remove the remaining second patterned photoresist layer 630, the remaining anti-reflection layer 620, and the remaining organic planarization layer.

[0097] In the embodiments of the present application, the etching process for forming the second patterned oxide hard mask layer 650 may be a plasma dry etching process.

[0098] Continue to refer to Figure 2 , in step S207: Transfer the pattern of the through holes defined in the second patterned oxide hard mask layer to the metal hard mask layer to form a first patterned metal hard mask layer.

[0099] Specifically, refer to Figure 7a , using the second patterned oxide hard mask layer 650 as a mask, etch the planarization layer 510 based on the first etching process until the upper surface of the metal hard mask layer 330 is exposed.

[0100] Among them, the first etching process may be a plasma dry etching process suitable for oxide etching. In a specific implementation, using the second patterned oxide hard mask layer 650 as a mask, etching gas CF 4 , CHF 3 or CH 2 F 2 may be introduced, supplemented with dilution gases CO, He or Ar, and each layer is etched in sequence along the pattern of the rectangular through holes in the second patterned oxide hard mask layer 650 until the etching stops at the upper surface of the metal hard mask layer 330, so as to transfer the pattern of the rectangular through holes to the planarization layer 510 on the top surface of the metal hard mask layer 330.

[0101] Next, refer to Figure 7b , etch the exposed metal hard mask layer 330 based on the second etching process and stop at the etch stop layer 350 to form a second opening 701 penetrating the metal hard mask layer 330 in the defined area corresponding to the rectangular through holes of the metal hard mask layer 330. The size of the second opening 701 is smaller than the size of the first opening 341, so as to form a first patterned metal hard mask layer 710.

[0102] Among them, the second etching process may be a plasma dry etching process suitable for etching metals. In a specific implementation, using the second patterned oxide hard mask layer 650 as a mask, etching gas CF 4 may be introduced to etch the exposed metal hard mask layer 330 and stop at the etch stop layer 350, so as to form a second opening 701 penetrating the metal hard mask layer 330 in the defined area corresponding to the rectangular through holes of the metal hard mask layer 330, and then transfer the pattern of the rectangular through holes to the metal hard mask layer 330.

[0103] Next, refer to Figure 7c, the second patterned oxide hard mask layer 650 and the planarization layer 510 are removed. In a specific implementation, the second patterned oxide hard mask layer 650 and the planarization layer 510 can be removed by a wet etching process or a plasma dry etching process. It can be understood that since the size of the first opening 341 is larger than the size of the second opening 701, after the planarization layer 510 is removed, the first opening 341 will expose a part of the remaining metal hard mask layer.

[0104] As Figure 8 shown is a plan view of the rectangular through-hole pattern in the first patterned metal hard mask layer 710. Since the metal hard mask layer 330 has better critical dimension control ability, the expansion of the critical dimension in the non-self-aligned direction is well restricted, and finally the process window of the rectangular through-hole is expanded.

[0105] Continue to refer to Figure 2 , in step S209: Based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer, trenches and vias are formed in the interlayer dielectric layer, and the bottom of the trench is connected to the top of the via.

[0106] Among them, the trenches and vias in the interlayer dielectric layer form a dual-damascene structure, and the via can expose the underlying metal layer.

[0107] Specifically, refer to Figure 9a , using the first patterned oxide hard mask layer 340 as a mask, the remaining metal hard mask layer exposed in the first opening 341 is etched to obtain a second patterned metal hard mask layer 910 formed with a trench pattern 901.

[0108] Among them, during the process of etching the remaining metal hard mask layer exposed in the first opening 341, the etch stop layer 350 and part of the interlayer dielectric layer 320 exposed by the second opening 701 in the first patterned metal hard mask layer 710 are etched, and part of the rectangular through-hole 902 is formed in the interlayer dielectric layer 320.

[0109] As Figure 10 shown is a plan view of the part of the rectangular through-hole formed in the interlayer dielectric layer. It can be seen from the figure that the critical dimensions of the part of the rectangular through-hole 902 in the interlayer dielectric layer 320 in the self-aligned direction and the non-self-aligned direction are precisely controlled.

[0110] Next, refer to Figure 9b , using the first patterned oxide hard mask layer 340 and the second patterned metal hard mask layer 910 as masks, the interlayer dielectric layer 320 is etched along the trench pattern 901 and part of the rectangular through-hole 902 until the underlying metal layer 310 is exposed, and trenches 903 and rectangular through-holes 904 formed in the interlayer dielectric layer 320 are obtained.

[0111] Among them, the process for forming the trench 903 and the rectangular through-hole 904 can be a plasma dry etching process.

[0112] In a specific embodiment, referring to Figure 11 , after forming the trench 903 and the rectangular through-hole 904 in the interlayer dielectric layer 320, it may further include: removing the first patterned oxide hard mask layer 340 and the remaining metal hard mask layer (i.e., the second patterned metal hard mask layer 910).

[0113] Among them, the process for removing the first patterned oxide hard mask layer 340 and the remaining metal hard mask layer can be a dry etching process or a wet etching process.

[0114] In a specific embodiment, after removing the first patterned oxide hard mask layer 340 and the remaining metal hard mask layer, the method may further include: filling a conductive material (not shown in the figure) into the trench 903 and the rectangular through-hole 904.

[0115] Specifically, the trench 903 and the rectangular through-hole 904 can be first filled with the conductive material and overflow to cover the upper surface of the etch stop layer 350; then the filled conductive metal is planarized until its top surface is flush with the etch stop layer 350. Among them, the conductive material can be copper metal, and the conductive material can be deposited by physical vapor deposition. In other examples, the conductive material can also be deposited by electrochemical plating or chemical vapor deposition.

[0116] In a specific embodiment, before depositing the conductive material, a barrier layer (not shown in the figure) and a seed layer (not shown in the figure) can be sequentially formed on the inner surfaces of the trench 903 and the rectangular through-hole 904, and then the conductive material is deposited on the seed layer. Among them, the material of the barrier layer can be titanium nitride, and the barrier layer can be used to prevent the conductive material from diffusing into the adjacent interlayer dielectric layer 320. The method for forming the barrier layer can be physical vapor deposition. Among them, the material of the seed layer is the same as that of the conductive material, and the seed layer can enhance the adhesion between the conductive material and the barrier layer. The method for forming the seed layer can adopt a sputtering process or a chemical vapor deposition process.

[0117] In a specific embodiment, the lithography process in the forming method described in the embodiments of the present application can adopt a deep ultraviolet (DUV) lithography process, specifically including non-immersion ultraviolet lithography and immersion ultraviolet lithography.

[0118] In the embodiment of the present application, by providing a substrate, the metal hard mask layer in the substrate is not etched. A first patterned oxide hard mask layer defining a trench pattern is formed on the metal hard mask layer. Then, a planarization layer is formed on the first patterned oxide mask layer, and a second patterned oxide hard mask layer defining a via pattern is formed on the planarization layer. Next, the pattern of the via defined in the second patterned oxide hard mask layer is transferred to the metal hard mask layer to form a first patterned metal hard mask layer. Furthermore, based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer, a dual damascene structure having trenches and vias is formed in the interlayer dielectric layer of the substrate, such that the etching of the metal hard mask layer is performed after the formation of the second patterned oxide hard mask layer. Thus, the metal hard mask layer is used to well control the critical dimension of the via in the non-self-aligned direction, improve the control accuracy of the critical dimension of the via such as a rectangular via in the non-self-aligned direction, expand the process window of such vias, and further avoid the bridging between the via and the underlying metal, thereby enhancing the performance of the semiconductor device.

[0119] The embodiment of the present application also provides a semiconductor structure formed based on the foregoing forming method, such as Figure 12 As shown, the semiconductor structure 1200 includes:

[0120] A semiconductor substrate 1210, in which an underlying metal layer 1201 is formed;

[0121] An interlayer dielectric layer 1202 formed on the surface of the semiconductor substrate 1210 and covering the underlying metal layer 1201;

[0122] A trench 1203 and a via 1204 formed in the interlayer dielectric layer 1202, and the bottom of the trench 1203 is connected to the top of the via 1204.

[0123] Specifically, the via 1204 may expose the underlying metal layer 1201.

[0124] In a specific embodiment, the semiconductor structure of the embodiment of the present application further includes: a conductive material 1206 filled in the trench 1203 and the via 1204.

[0125] In a specific embodiment, an etch stop layer 1205 may further be formed on the interlayer dielectric layer 1202, and the trench 1203 penetrates through the etch stop layer 1205 and extends into the interlayer dielectric layer 1202.

[0126] In a specific embodiment, the via 1204 of the semiconductor structure 1200 may be a via having different critical dimensions of length and width, such as a rectangular via.

[0127] In the semiconductor structure according to the embodiments of the present application, the critical dimensions of the vias in both the self-alignment direction and the non-self-alignment direction are well controlled, thereby improving the performance of the semiconductor structure.

[0128] Correspondingly, the embodiments of the present application further provide an electronic device, which includes a semiconductor structure formed by the formation method of any one of the foregoing semiconductor structures according to the embodiments of the present application.

[0129] Since the working performance of the semiconductor structure is better, and the electronic device uses the semiconductor structure, the performance of the electronic device is correspondingly improved. Among them, the electronic device can be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or an intermediate product having the semiconductor structure, for example: a device motherboard having the semiconductor structure, etc.

[0130] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate, the substrate including a bottom metal layer, an interlayer dielectric layer, a metal hard mask layer, and a first patterned oxide hard mask layer which are stacked; a plurality of first openings exposing the upper surface of the metal hard mask layer are formed in the first patterned oxide hard mask layer, and the plurality of first openings indicate the pattern of trenches for forming an upper metal layer; forming a planarization layer on the first patterned oxide hard mask layer, the planarization layer filling the plurality of first openings and covering the upper surface of the first patterned oxide hard mask layer; forming a second patterned oxide hard mask layer on the planarization layer, the second patterned oxide hard mask layer defining the pattern of vias; transferring the pattern of the vias defined in the second patterned oxide hard mask layer to the metal hard mask layer to form a first patterned metal hard mask layer; based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer, forming the trenches and the vias in the interlayer dielectric layer; the bottom of the trenches is connected to the top of the vias.

2. The forming method according to claim 1, characterized in that, an etch stop layer is formed between the interlayer dielectric layer and the metal hard mask layer; the transferring the pattern of the vias defined in the second patterned oxide hard mask layer to the metal hard mask layer to form a first patterned metal hard mask layer includes: using the second patterned oxide hard mask layer as a mask, etching the planarization layer based on a first etching process until the upper surface of the metal hard mask layer is exposed; etching the exposed metal hard mask layer based on a second etching process and stopping at the etch stop layer to form a second opening penetrating the metal hard mask layer in a defined area of the metal hard mask layer corresponding to the vias, and the size of the second opening is smaller than the size of the first opening; removing the second patterned oxide hard mask layer and the planarization layer.

3. The forming method according to claim 2, characterized in that, the forming the trenches and the vias in the interlayer dielectric layer based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer includes: using the first patterned oxide hard mask layer as a mask, etching the remaining metal hard mask layer exposed in the first openings to obtain a second patterned metal hard mask layer formed with the trench pattern; wherein, during the etching process, the etch stop layer and a part of the interlayer dielectric layer exposed by the second opening in the first patterned metal hard mask layer are etched, and partial vias are formed in the interlayer dielectric layer; using the first patterned oxide hard mask layer and the second patterned metal hard mask layer as masks, etching the interlayer dielectric layer along the trench pattern and the partial vias until the bottom metal layer is exposed to obtain the trenches and the vias formed in the interlayer dielectric layer.

4. The forming method according to claim 2, characterized in that, the method further includes: Provide a semiconductor substrate in which a bottom metal layer is formed; Form an interlayer dielectric layer and an etch stop layer in sequence on the surface of the semiconductor substrate, and the interlayer dielectric layer covers the bottom metal layer; Form a metal hard mask layer on the etch stop layer; Form a first oxide hard mask layer on the metal hard mask layer; Form a first patterned photoresist layer on the first oxide hard mask layer; the first patterned photoresist layer defines a pattern for a trench for forming an upper metal layer; Using the first patterned photoresist layer as a mask, etch the first oxide hard mask layer until the upper surface of the metal hard mask layer is exposed and stop; Remove the remaining first patterned photoresist layer to obtain the substrate.

5. The formation method according to claim 1, wherein, forming the second patterned oxide hard mask layer on the planarization layer includes: forming a second oxide hard mask layer, an anti-reflection layer and a second patterned photoresist layer in sequence on the planarization layer; the second patterned photoresist layer defines a pattern for a via; using the second patterned photoresist layer as a mask, etch the anti-reflection layer and the second oxide hard mask layer in sequence; Remove the remaining second patterned photoresist layer and the remaining anti-reflection layer to obtain the second patterned oxide hard mask layer.

6. The formation method according to claim 1, wherein, after forming the trench and the via in the interlayer dielectric layer, the method further includes: removing the first patterned oxide hard mask layer and the remaining metal hard mask layer.

7. The formation method according to claim 6, wherein, after removing the first patterned oxide hard mask layer and the remaining metal hard mask layer, the method further includes: filling the trench and the via with a conductive material.

8. The formation method according to any one of claims 1-7, wherein, the photolithography process in the formation method uses a deep ultraviolet photolithography process.

9. The formation method according to any one of claims 1-7, wherein, the critical dimension of the length of the via is different from the critical dimension of the width.

10. A semiconductor structure, wherein, formed by using any one of the formation methods according to claims 1-9, including: a semiconductor substrate in which a bottom metal layer is formed; an interlayer dielectric layer formed on the surface of the semiconductor substrate and covering the bottom metal layer; a trench and a via formed in the interlayer dielectric layer; the bottom of the trench is connected to the top of the via.

11. The semiconductor structure according to claim 10, wherein, further includes: a conductive material filled in the trench and the via.

12. The semiconductor structure according to claim 10, wherein, an etch stop layer is further formed on the interlayer dielectric layer, and the trench penetrates through the etch stop layer and extends into the interlayer dielectric layer.

13. The semiconductor structure according to any one of claims 10-12, wherein, the critical dimension of the length of the via is different from the critical dimension of the width.

14. An electronic device, wherein, The electronic device includes a semiconductor structure formed by using the forming method according to any one of claims 1 to 9.

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