Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; a dielectric layer is formed on the substrate, a contact hole is formed in the dielectric layer, and the bottom of the contact hole is exposed out of the substrate; a conductive material layer is formed on the side wall and the bottom of the contact hole and on the dielectric layer, the contact hole is filled with the conductive material layer, and first stress exists in the conductive material layer; a sacrificial material layer is formed on the surface of the conductive material layer, second stress exists in the sacrificial material layer, and the direction of the first stress is opposite to that of the second stress; and planarizing the sacrificial material layer and the conductive material layer until the surface of the dielectric layer is exposed so as to form a conductive plug in the contact hole, and due to the balance effect of the second stress and the first stress, the warping degree of the wafer can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for forming a semiconductor structure. Background Art

[0002] Contact holes are the connection channels between devices in a chip and the first metal layer, and the connections between different devices are revealed by etching the contact holes and the metal layer. Tungsten is introduced as a via filling material into the integrated circuit manufacturing process at sub-micron and below.

[0003] As the device size of integrated circuits continues to shrink, the aspect ratio of contact holes is constantly increasing, which poses a great challenge to the existing tungsten filling process. Chemical Vapor Deposition (abbreviated as CVD) has very good step coverage and is therefore widely used in the filling process of contact holes.

[0004] However, the performance of existing contact holes needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a dielectric layer on the substrate, the dielectric layer having contact holes, and the bottom of the contact holes exposing the substrate; forming a conductive material layer on the sidewalls and bottom of the contact holes and on the dielectric layer, the conductive material layer filling the contact holes, and the conductive material layer having a first stress; forming a sacrificial material layer on the surface of the conductive material layer, the sacrificial material layer having a second stress, and the direction of the first stress being opposite to the direction of the second stress; planarizing the sacrificial material layer and the conductive material layer until the surface of the dielectric layer is exposed to form a conductive plug in the contact hole.

[0007] Optionally, the material of the conductive material layer includes a metal, and the metal includes one or more of tungsten, gold, copper, and aluminum; the material of the sacrificial material layer includes an oxide of the metal or a nitride of the metal.

[0008] Optionally, the material of the sacrificial material layer includes tungsten nitride or tungsten oxide; the formation process of the sacrificial material layer includes a first chemical vapor deposition process.

[0009] Optionally, the material of the sacrificial material layer is tungsten nitride; the process parameters of the first chemical vapor deposition process include: the reaction gases include WF 6 and NH 3 , where WF6 has a flow rate range of 200 sccm to 300 sccm, NH 3 has a flow rate range of 600 sccm to 800 sccm, the pressure range in the reaction chamber is 3 Torr to 10 Torr, and the process temperature range is 150 °C to 300 °C.

[0010] Optionally, the thickness range of the sacrificial material layer is 100 Å to 1000 Å.

[0011] Optionally, the dimension range by which the top surface of the conductive material layer protrudes above the top surface of the dielectric layer is 100 Å to 5000 Å.

[0012] Optionally, the conductive material layer includes a seed crystal material layer, a first filling material layer on the surface of the seed crystal material layer, and a second filling material layer on the surface of the first filling material layer. The first filling material layer has first grains, the second filling material layer has second grains, and the second grains are larger than the first grains.

[0013] Optionally, the sacrificial material layer has a third grain size, and the third grain size is smaller than the second grain size.

[0014] Optionally, the range of the third grain size is 10 Å to 150 Å.

[0015] Optionally, the method for forming the conductive material layer includes: forming the seed crystal material layer on the surface of the contact hole and the dielectric layer; forming the first filling material layer on the surface of the seed crystal material layer by using a second chemical vapor deposition process; forming the second filling material layer on the surface of the first filling material layer by using a third chemical vapor deposition process, and the process temperature of the third chemical vapor deposition process is higher than the process temperature of the second chemical vapor deposition process.

[0016] Optionally, the forming process of the first filling material layer includes a second chemical vapor deposition process; the process parameters of the second chemical vapor deposition process include: the reaction gas includes WF 6 and H 2 , where the flow rate range of WF 6 is 100 sccm to 500 sccm, the flow rate range of H 2 is 2000 sccm to 20000 sccm, the pressure range in the reaction chamber is 5 Torr to 50 Torr, and the process temperature range is 150 °C to 300 °C.

[0017] Optionally, the forming process of the second filling material layer includes a third chemical vapor deposition process; the process parameters of the third chemical vapor deposition process include: the reaction gas includes WF 6 and H2 , where WF 6 has a flow rate range of 100 sccm to 500 sccm, and H 2 has a flow rate range of 2000 sccm to 20000 sccm, the pressure range in the reaction chamber is 5 Torr to 50 Torr, and the process temperature range is 300 °C to 450 °C.

[0018] Optionally, before forming the conductive material layer, it further includes: forming a barrier material layer on the sidewalls and bottom of the contact hole and on the surface of the dielectric layer, and the conductive material layer is formed on the surface of the barrier material layer.

[0019] Optionally, before forming the conductive material layer, it further includes: forming a barrier material layer on the sidewalls and bottom of the contact hole and on the surface of the dielectric layer; forming a crystal growth inhibiting material layer on the surface of the barrier material layer, and the conductive material layer is formed on the surface of the crystal growth inhibiting material layer.

[0020] Optionally, the material of the crystal growth inhibiting material layer includes tungsten nitride or titanium nitride.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0022] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the conductive material layer has a first stress, and a sacrificial material layer is formed on the surface of the conductive material layer. The sacrificial material layer has a second stress, and the direction of the first stress is opposite to the direction of the second stress. Due to the balancing effect of the second stress and the first stress, it is beneficial to reduce the warpage of the wafer, improve the grinding efficiency during the planarization process, and reduce the damage to the internal device structure of the wafer caused by stress problems. Overall, it is beneficial to improve the device performance.

[0023] Furthermore, the sacrificial material layer has a third grain size, and the second filling material layer has a second grain size. The third grain size is smaller than the second grain size, so that the surface roughness of the sacrificial material layer is smaller than the surface roughness of the conductive material layer. After the planarization process, it is beneficial to reduce the surface roughness of the formed conductive plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1 to 4 is a schematic structural diagram of a semiconductor structure formation process;

[0025] Figures 5 to 10 is a schematic structural diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0027] As described in the background art, the performance of the contact holes formed by the prior art still needs to be further improved. A semiconductor structure will be described and analyzed in combination.

[0028] Figures 1 to 4 It is a schematic structural diagram of a semiconductor structure forming process.

[0029] Please refer to Figure 1 , a substrate 101 is provided; a dielectric layer 102 is formed on the substrate 101, and a contact hole 103 is formed in the dielectric layer 102; a barrier material layer 104 is formed on the surface of the contact hole 103 and the dielectric layer 102.

[0030] Please refer to Figure 2 , a tungsten seed material layer 105 is deposited on the surface of the barrier material layer 104.

[0031] Please refer to Figure 3 , a tungsten material layer 106 is deposited on the surface of the tungsten seed material layer 105 so that the contact hole 103 is filled.

[0032] Please refer to Figure 4 , a chemical mechanical polishing process is used to planarize the tungsten material layer 106, the tungsten seed material layer 105 and the barrier material layer 104 until the surface of the dielectric layer 102 is exposed, and a conductive plug 108 is formed in the contact hole 104.

[0033] In the above method for forming the contact hole, the tungsten material layer 106 is obtained by two fills. A lower growth temperature is used in the first fill to achieve a better filling effect, but the tungsten grains are smaller during the first fill. A higher growth temperature is used in the second fill to obtain larger tungsten grains to reduce the resistance of the conductive plug 108.

[0034] However, the second fill makes the tungsten material layer 106 have a large stress, resulting in a large warpage (Bow) of the wafer. In the chemical mechanical polishing (CMP) process, it is easy to affect the polishing efficiency and even cause damage to the internal device structure of the wafer due to stress problems.

[0035] To solve the above problems, in a method for forming a semiconductor structure provided by the present invention, a first stress exists in the conductive material layer, a sacrificial material layer is formed on the surface of the conductive material layer, a second stress exists in the sacrificial material layer, and the directions of the first stress and the second stress are opposite. Due to the balancing effect of the second stress and the first stress, it is beneficial to reduce the warpage of the wafer, improve the grinding efficiency during the planarization process, and reduce the damage to the internal device structure of the wafer caused by stress problems. Overall, it is beneficial to improve the device performance.

[0036] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description will be given to the specific embodiments of the present invention with reference to the accompanying drawings.

[0037] Figures 5 to 10 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0038] Please refer to Figure 5 , and provide a substrate 200; a dielectric layer 201 is formed on the substrate 200, a contact hole 202 exists in the dielectric layer 201, and the bottom of the contact hole 202 exposes the substrate 200.

[0039] In this embodiment, the substrate 200 includes a substrate (not shown in the figure) and a device layer (not shown in the figure) located on the surface of the substrate. A device structure (not shown in the figure) exists in the device layer, and the contact hole 202 exposes the device structure.

[0040] In this embodiment, the material of the substrate is silicon.

[0041] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0042] The device structure may include a metal layer, a transistor, a diode, a triode, a capacitor, an inductor, or a conductive structure, etc. In this embodiment, the device structure is a MOS transistor, and the contact hole 202 exposes the gate surface of the MOS transistor.

[0043] Subsequently, a conductive material layer is formed on the sidewalls and bottom of the contact hole 202 and on the dielectric layer 201. The conductive material layer fills the contact hole 202, and a first stress exists in the conductive material layer.

[0044] In this embodiment, the conductive material layer includes a seed crystal material layer, a first filling material layer on the surface of the seed crystal material layer, and a second filling material layer on the surface of the first filling material layer.

[0045] In this embodiment, before forming the conductive material layer, please refer to Figure 6 .

[0046] Please refer to Figure 6 , and a barrier material layer 203 is formed on the sidewall and bottom of the contact hole 202 and on the surface of the dielectric layer 201.

[0047] In this embodiment, the barrier material layer 203 includes an adhesive material layer (not shown in the figure) and an auxiliary material layer (not shown in the figure) on the surface of the adhesive material layer. The adhesive material layer is used to improve the adhesion between the conductive material layer and the contact hole, and the auxiliary material layer is used to reduce the diffusion of metal ions in the conductive material layer to the dielectric layer.

[0048] The material of the adhesive material layer may include titanium, tantalum, etc. In this embodiment, the material of the adhesive material layer is titanium.

[0049] The material of the auxiliary material layer may include titanium nitride, tantalum nitride, etc. In this embodiment, the material of the auxiliary material layer is titanium nitride.

[0050] In this embodiment, the formation process of the auxiliary material layer includes a physical vapor deposition process.

[0051] In this embodiment, the formation process of the adhesive material layer includes a physical vapor deposition process.

[0052] In this embodiment, before forming the conductive material layer, a crystal growth inhibition material layer 204 is further formed on the surface of the barrier material layer 203. Subsequently, a conductive material layer is formed on the surface of the crystal growth inhibition material layer 204. The crystal growth inhibition material layer 204 is used to inhibit the rapid growth of the conductive material layer, avoid the problem that the contact hole 202 is prematurely sealed due to too fast crystal growth speed, is beneficial to improving the uniformity of the conductive plug, and reducing the resistance of the conductive plug.

[0053] The material of the crystal growth inhibition material layer 204 includes tungsten nitride or titanium nitride. In this embodiment, the material of the crystal growth inhibition material layer is tungsten nitride.

[0054] In another embodiment, the crystal growth inhibition material layer may not be formed, and the conductive material layer may be directly formed on the surface of the barrier material layer.

[0055] In this embodiment, the formation process of the crystal growth inhibition material layer 204 includes a physical vapor deposition process.

[0056] Please refer to Figure 7 , a seed crystal material layer 205 is formed on the surface of the contact hole 202 and the dielectric layer 201.

[0057] Specifically, the seed crystal material layer is formed on the surface of the crystal growth inhibiting material layer 204. The seed crystal material layer is used to provide a seed crystal for the conductive material layer, and the material of the seed crystal material layer is the same as that of the conductive material layer.

[0058] The material of the conductive material layer includes a metal, and the metal includes one or more of tungsten, gold, copper, and aluminum. In this embodiment, the material of the conductive material layer is tungsten.

[0059] In this embodiment, the forming process of the seed crystal material layer 205 includes a physical vapor deposition process.

[0060] Please refer to Figure 8 , a first filling material layer 206 is formed on the surface of the seed crystal material layer 205 by using a second chemical vapor deposition process; a second filling material layer 207 is formed on the surface of the first filling material layer by using a third chemical vapor deposition process, and the process temperature of the third chemical vapor deposition process is higher than that of the second chemical vapor deposition process. The conductive material layer includes the seed crystal material layer 205, the first filling material layer 206 located on the surface of the seed crystal material layer 205, and the second filling material layer 207 located on the surface of the first filling material layer 206.

[0061] In this embodiment, the dimension range of the top surface of the conductive material layer being higher than the top surface of the dielectric layer 201 is 100 Å to 5000 Å.

[0062] The first filling material layer 206 has first grains, and the second filling material layer 207 has second grains, and the second grains are larger than the first grains. Here, a first chemical vapor deposition process that is conducive to filling is used to make the uniformity of the performance of the obtained conductive plug. A second chemical vapor deposition process that is conducive to grain growth is used to make the second grains larger than the first grains, which is conducive to reducing the resistance of the conductive plug.

[0063] In this embodiment, the thickness range of the first filling material layer 206 is 50 Å to 500 Å.

[0064] In this embodiment, the forming process of the first filling material layer 206 includes a second chemical vapor deposition process.

[0065] In this embodiment, the process parameters of the second chemical vapor deposition process include: the reaction gases include WF 6 and H 2 , where WF 6The flow rate ranges from 100 sccm to 500 sccm, H 2 The flow rate ranges from 2,000 sccm to 20,000 sccm, the pressure range in the reaction chamber is from 5 Torr to 50 Torr, and the process temperature range is from 150 °C to 300 °C. The process temperature in the second chemical vapor deposition process is relatively low, which is beneficial to obtaining a better filling effect.

[0066] In this embodiment, the thickness range of the second filling material layer 207 is from 50 Å to 5,000 Å.

[0067] In this embodiment, the forming process of the second filling material layer 207 includes a third chemical vapor deposition process.

[0068] In this embodiment, the process parameters of the third chemical vapor deposition process include: the reaction gases include WF 6 and H 2 wherein the flow rate range of WF 6 is from 100 sccm to 500 sccm, and the flow rate range of H 2 is from 2,000 sccm to 20,000 sccm, the pressure range in the reaction chamber is from 5 Torr to 50 Torr, and the process temperature range is from 300 °C to 450 °C. Here, the relatively optimized process temperature is 395 °C. The process temperature in the third chemical vapor deposition process is relatively high, which is beneficial to forming a second filling material layer with larger grains.

[0069] Please refer to Figure 9 , a sacrificial material layer 208 is formed on the surface of the conductive material layer, and the sacrificial material layer has a second stress, and the direction of the first stress is opposite to the direction of the second stress.

[0070] Thus, due to the balancing effect of the second stress and the first stress, it is beneficial to reduce the warpage of the wafer, improve the grinding efficiency in the subsequent planarization process, and reduce the damage to the internal device structure of the wafer caused by stress problems. Overall, it is beneficial to improve the device performance.

[0071] In this embodiment, the sacrificial material layer 208 has a third grain size, and the third grain size is smaller than the second grain size. The surface roughness of the sacrificial material layer 208 is smaller than the surface roughness of the conductive material layer, which is beneficial to reducing the surface roughness of the formed conductive plug after the planarization process.

[0072] In this embodiment, the range of the third grain size is from 10 Å to 150 Å.

[0073] Specifically, the sacrificial material layer 208 is formed on the surface of the second filling material layer 207.

[0074] The formation process of the sacrificial material layer 208 includes a first chemical vapor deposition process.

[0075] The sacrificial material layer 208 can select a suitable material according to the material of the conductive material layer, such as metal oxides or metal nitrides and other materials. In order to reduce the resistance of the conductive plug, a conductive material layer with larger grains can be selected. In order to balance the first stress of the conductive material layer, a sacrificial material layer with a phase reaction force can be used to reduce the warpage of the wafer.

[0076] In this embodiment, the material of the sacrificial material layer 208 is tungsten nitride.

[0077] In another embodiment, the material of the sacrificial material layer can be tungsten oxide.

[0078] In this embodiment, the process parameters of the first chemical vapor deposition process include: the reaction gases include WF 6 and NH 3 , where the flow rate range of WF 6 is 200 sccm to 300 sccm, the flow rate range of NH 3 is 600 sccm to 800 sccm, the pressure range in the reaction chamber is 3 Torr to 10 Torr, and the process temperature range is 150 °C to 300 °C.

[0079] Here, the first chemical vapor deposition process uses a lower process temperature, which is beneficial to obtaining tungsten nitride grains with smaller sizes, reducing the surface roughness of the sacrificial material layer 208, and obtaining a tungsten nitride material with a second stress at the same time, making the second stress opposite to the first stress, which helps to improve the warpage of the wafer.

[0080] In this embodiment, the thickness range of the sacrificial material layer 208 is 100 Å to 1000 Å. The reason for selecting this thickness range is that its second stress is sufficient to balance the influence of the first stress, and to avoid the problem of excessive stress caused by too high a thickness.

[0081] Please refer to Figure 10 , planarize the sacrificial material layer 208 and the conductive material layer until the surface of the dielectric layer 201 is exposed to form a conductive plug 209 in the contact hole 202.

[0082] The process of planarizing the sacrificial material layer 208 and the conductive material layer includes a chemical mechanical polishing process.

[0083] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A dielectric layer is formed on the substrate, wherein the dielectric layer has a contact hole, and the bottom of the contact hole exposes the substrate; forming a conductive material layer on the sidewall and bottom of the contact hole and the dielectric layer, wherein the conductive material layer fills the contact hole and has a first stress; forming a sacrificial material layer on the surface of the conductive material layer, wherein the sacrificial material layer has a second stress, and a direction of the first stress is opposite to a direction of the second stress; The sacrificial material layer and the conductive material layer are planarized until the surface of the dielectric layer is exposed to form a conductive plug in the contact hole.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the conductive material layer includes metal, and the metal includes one or more of tungsten, gold, copper and aluminum; the material of the sacrificial material layer includes oxide of the metal or nitride of the metal.

3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the sacrificial material layer includes tungsten nitride or tungsten oxide; and the formation process of the sacrificial material layer includes a first chemical vapor deposition process.

4. The method for forming a semiconductor structure according to claim 3, wherein: The material of the sacrificial material layer is tungsten nitride; the process parameters of the first chemical vapor deposition process include: the reaction gas includes WF6 and NH3, wherein the flow range of WF6 is 200sccm to 300sccm, the flow range of NH3 is 600sccm to 800sccm, the pressure range in the reaction chamber is 3Torr to 10Torr, and the process temperature range is 150℃ to 300℃.

5. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the sacrificial material layer ranges from 100 Å to 1000 Å.

6. The method for forming a semiconductor structure according to claim 1, wherein: The top surface of the conductive material layer is higher than the top surface of the dielectric layer by a dimension ranging from 100 Å to 5000 Å.

7. The method for forming a semiconductor structure according to claim 1, wherein: The conductive material layer includes a seed material layer, a first filling material layer located on the surface of the seed material layer, and a second filling material layer located on the surface of the first filling material layer. The first filling material layer has first grains, and the second filling material layer has second grains that are larger than the first grains.

8. The method for forming a semiconductor structure according to claim 7, wherein: The sacrificial material layer has a third grain size, and the third grain size is smaller than the second grain size.

9. The method for forming a semiconductor structure according to claim 8, wherein: The third grain size ranges from 10 Å to 150 Å.

10. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the conductive material layer includes: forming the seed material layer on the surface of the contact hole and the dielectric layer; forming the first filling material layer on the surface of the seed material layer using a second chemical vapor deposition process; and forming the second filling material layer on the surface of the first filling material layer using a third chemical vapor deposition process, wherein the process temperature of the third chemical vapor deposition process is greater than the process temperature of the second chemical vapor deposition process.

11. The method for forming a semiconductor structure according to claim 10, wherein: The formation process of the first filling material layer includes a second chemical vapor deposition process; the process parameters of the second chemical vapor deposition process include: the reaction gases include WF6 and H2, wherein the flow range of WF6 is 100sccm to 500sccm, the flow range of H2 is 2000sccm to 20000sccm, the pressure range in the reaction chamber is 5Torr to 50Torr, and the process temperature range is 150℃ to 300℃.

12. The method for forming a semiconductor structure according to claim 10, wherein: The formation process of the second filling material layer includes a third chemical vapor deposition process; the process parameters of the third chemical vapor deposition process include: the reaction gases include WF6 and H2, wherein the flow range of WF6 is 100sccm to 500sccm, the flow range of H2 is 2000sccm to 20000sccm, the pressure range in the reaction chamber is 5Torr to 50Torr, and the process temperature range is 300℃ to 450℃.

13. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the conductive material layer, the method further includes: forming a barrier material layer on the sidewall and bottom of the contact hole and on the surface of the dielectric layer, wherein the conductive material layer is formed on the surface of the barrier material layer.

14. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the conductive material layer, the method further includes: forming a barrier material layer on the sidewall and bottom of the contact hole and on the surface of the dielectric layer; forming a crystal growth inhibiting material layer on the surface of the barrier material layer, and the conductive material layer is formed on the surface of the crystal growth inhibiting material layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The material of the crystal growth inhibiting material layer includes tungsten nitride or titanium nitride.

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