Semiconductor structure

Abstract

The invention provides a semiconductor structure. The semiconductor structure comprises a substrate, a first protection layer, a first conductive layer, a second protection layer, a second conductive layer, a plating layer and a bump, the substrate comprises a base, at least one connecting pad and an insulating layer. The insulating layer exposes the connecting part of the at least one connecting pad. The first protective layer is disposed on the insulating layer of the substrate and exposes a portion of the connecting portion of the at least one pad. The first conductive layer is electrically connected with the connecting part exposed by the first protective layer. The second protective layer has at least one opening exposing a portion of the first conductive layer. The second conductive layer is electrically connected with the first conductive layer and has a top surface and a peripheral surface connected with the top surface. The plating layer at least completely covers the peripheral surface of the second conductive layer and extends to a part of the top surface. The bump is disposed on the second conductive layer and electrically connected to the second conductive layer. The semiconductor structure provided by the invention has better structural reliability.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure with better structural reliability. Background Art

[0002] In the current structure of wafer level chip scale package (WLCSP), if the solder balls are of good quality, the interfacial metal compound (IMC) layer in the solder balls must completely cover the top surface and the side edges of the pads, making the contact between the solder balls and the pads very tight. However, in products with poor bonding, the bonding between the solder balls and the pads is not as expected. For example, the side edges of the pads are not completely covered by the interfacial metal compound layer and are exposed, which means that the pad copper is exposed. After water vapor penetration, pure copper reacts to form copper oxide, resulting in poor bonding effect. Summary of the Invention

[0003] The present invention is directed to a semiconductor structure having better structural reliability.

[0004] According to an embodiment of the present invention, the semiconductor structure includes a substrate, a first protective layer, a first conductive layer, a second protective layer, a second conductive layer, a plating layer, and a bump. The substrate includes a base, at least one pad, and an insulating layer. At least one pad is disposed on the base, and the insulating layer covers the base and at least one pad. The insulating layer exposes a connection portion of at least one pad. The first protective layer is disposed on the insulating layer of the substrate and exposes a partial connection portion of at least one pad. The first conductive layer is disposed on the first protective layer and electrically connects to the connection portion exposed by the first protective layer. The second protective layer is disposed on the first conductive layer and has at least one opening exposing a part of the first conductive layer. The second conductive layer is disposed in at least one opening and extends onto the second protective layer. The second conductive layer is electrically connected to the first conductive layer, and the second conductive layer has a top surface and a peripheral surface connecting the top surface. The plating layer at least completely covers the peripheral surface of the second conductive layer and extends onto a part of the top surface. The bump is disposed on the second conductive layer and electrically connected to the second conductive layer.

[0005] In the semiconductor structure according to an embodiment of the present invention, the above-mentioned plating layer further extends to completely cover the top surface of the second conductive layer and is located between the bump and the second conductive layer.

[0006] In the semiconductor structure according to an embodiment of the present invention, the above-mentioned plating layer includes an electroless nickel layer, an electroless palladium layer, or an electroless nickel-palladium layer.

[0007] In the semiconductor structure according to an embodiment of the present invention, the above-mentioned plating layer has a limiting opening on the top surface of the second conductive layer, and the bump is located in the limiting opening.

[0008] In the semiconductor structure according to an embodiment of the present invention, the above-mentioned plating layer includes an electroplated nickel layer, an electroplated palladium layer, or an electroplated nickel-palladium layer.

[0009] In the semiconductor structure according to an embodiment of the present invention, the thickness of the above-mentioned plating layer is between 0.1 micrometer and 0.5 micrometers.

[0010] In the semiconductor structure according to an embodiment of the present invention, the above-mentioned first conductive layer includes a redistribution layer.

[0011] In the semiconductor structure according to an embodiment of the present invention, the material of the above-mentioned second conductive layer includes copper.

[0012] In the semiconductor structure according to an embodiment of the present invention, the orthographic projection of the above-mentioned second conductive layer on the substrate does not overlap at least one pad.

[0013] In the semiconductor structure according to an embodiment of the present invention, the above-mentioned second protective layer does not cover the second conductive layer.

[0014] Based on the above, in the design of the semiconductor structure of the present invention, the plating layer at least completely covers the peripheral surface of the second conductive layer and extends to a part of the top surface, which means that the plating layer can protect the peripheral surface of the second conductive layer to prevent it from being exposed and effectively prevent it from oxidizing. In this way, the semiconductor structure of the present invention can have better structural reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0016] Figure 2 is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention.

[0017] DESCRIPTION OF THE REFERENCE NUMERALS

[0018] 100a, 100b: semiconductor structure;

[0019] 110: substrate;

[0020] 112: base;

[0021] 114: pad;

[0022] 115: connection part;

[0023] 116: insulating layer;

[0024] 117, 122, 142: opening;

[0025] 120: first protective layer;

[0026] 130: First conductive layer;

[0027] 140: Second protective layer;

[0028] 150: Second conductive layer;

[0029] 152: Top surface;

[0030] 154: Peripheral surface;

[0031] 160a, 160b: Coatings;

[0032] 170a, 170b: Bumps;

[0033] T: Thickness. Detailed implementation manners

[0034] Now, reference will be made in detail to the exemplary embodiments of the present invention. Examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same element symbols are used in the drawings and the description to represent the same or similar parts.

[0035] The embodiments of the present invention can be combined with the attached Figure 1 and it is understood that the drawings of the present invention are also regarded as a part of the open description. It should be understood that the drawings of the present invention are not drawn to scale. In fact, the sizes of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present invention.

[0036] Figure 1 is a cross-sectional schematic view of a semiconductor structure according to an embodiment of the present invention. Please refer to Figure 1, in this embodiment, the semiconductor structure 100a includes a substrate 110, a first protective layer 120, a first conductive layer 130, a second protective layer 140, a second conductive layer 150, a plating layer 160a, and a bump 170a. The substrate 110 includes a base 112, at least one pad (schematically showing one pad 114), and an insulating layer 116. The pad 114 is disposed on the base 112, and the insulating layer 116 covers the base 112 and the pad 114. The insulating layer 116 exposes a connection portion 115 of the pad 114. The first protective layer 120 is disposed on the insulating layer 116 of the substrate 110 and exposes a partial connection portion 115 of the pad 114. The first conductive layer 130 is disposed on the first protective layer 120 and is electrically connected to the connection portion 115 exposed by the first protective layer 120. The second protective layer 140 is disposed on the first conductive layer 130 and has at least one opening (schematically showing one opening 142) that exposes a part of the first conductive layer 130. The second conductive layer 150 is disposed in the opening 142 and extends onto the second protective layer 140. The second conductive layer 150 is electrically connected to the first conductive layer 130, and the second conductive layer 150 has a top surface 152 and a peripheral surface 154 connecting the top surface 152. The plating layer 160a at least completely covers the peripheral surface 154 of the second conductive layer 150 and extends onto a part of the top surface 152. The bump 170a is disposed on the second conductive layer 150 and is electrically connected to the second conductive layer 150.

[0037] Specifically, the substrate 110 of the base 112 may be, for example, a silicon substrate, but is not limited thereto. The pad 114 is directly disposed on the base 112, and the material of the pad 114 may be, for example, copper, aluminum, or other suitable metal materials. The insulating layer 116 has an opening 117, wherein the opening 117 exposes a partial connection portion 115 of the pad 114. The first protective layer 120 is directly disposed on the insulating layer 116 of the substrate 110 and may extend into the opening 117. The material of the first protective layer 120 may be, for example, polyimide (PI), but is not limited thereto. The first protective layer 120 has an opening 122, wherein the opening 122 exposes the partial connection portion 115 exposed by the opening 117. Herein, the diameter of the opening 117 of the insulating layer 116 is larger than the diameter of the opening 122 of the first protective layer 120. The first conductive layer 130 is disposed on the first protective layer 120 and extends into the opening 122 to be structurally and electrically connected to the connection portion 115 of the pad 114. Herein, the first conductive layer 130 is, for example, a redistribution layer, and its material is, for example, copper, but is not limited thereto. The second protective layer 140 is directly disposed on the first conductive layer 130 and the first protective layer 120, and the material of the second protective layer 140 may be, for example, polyimide (PI), but is not limited thereto. In this embodiment, the second conductive layer 150 extends onto the second protective layer 140, meaning that the second protective layer 140 does not cover the second conductive layer 150. The material of the second conductive layer 150 is, for example, copper, but is not limited thereto. The orthographic projection of the second conductive layer 150 on the substrate 110 does not overlap the pad 114, that is, it is arranged in a misaligned manner. Herein, the second conductive layer 150 can be regarded as a solder pad, and the bump 170a may be, for example, a solder ball.

[0038] Please refer to Figure 1 , the plating layer 160a of this embodiment also extends to completely cover the top surface 152 of the second conductive layer 150 and is located between the bump 170a and the second conductive layer 150. That is to say, the bump 170a of this embodiment is entirely disposed on the plating layer 160a, and the plating layer 160a and the second conductive layer 150 are conformally arranged, and it completely directly coats the top surface 152 and the surrounding surface 154 of the second conductive layer 150. Herein, the plating layer 160a is, for example, an electroless nickel plating layer, an electroless palladium plating layer, or an electroless nickel palladium plating layer, meaning that the surface of the second conductive layer 150 is chemically plated. The thickness T of the plating layer 160a may be, for example, between 0.1 micrometer and 0.5 micrometers. By the plating layer 160a at least completely covering the surrounding surface 154 of the second conductive layer 150, after the bump 170a is disposed and the reflow soldering process is performed, a good interfacial metal compound layer can be formed with the bump 170a to achieve a stable bonding effect between the bump 170a and the second conductive layer 150.

[0039] Since the coating layer 160a of this embodiment completely and directly covers the top surface 152 and the surrounding surface 154 of the second conductive layer 150, it means that in addition to helping the bump 170a to firmly bond with the second conductive layer 150, the coating layer 160a can also effectively protect the surrounding surface 154 of the second conductive layer 150 to prevent it from being exposed outside, and effectively prevent oxidation from occurring. In short, the semiconductor structure 100a of this embodiment can have better structural reliability.

[0040] It must be noted here that the following embodiments follow the component numbers and some content of the foregoing embodiments, where the same numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference can be made to the foregoing embodiments, and the following embodiments will not be repeated.

[0041] Figure 2 It is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Please also refer to Figure 1 And Figure 2 , the semiconductor structure 100b of this embodiment is similar to the above-mentioned semiconductor structure 100a. The difference between the two is that in this embodiment, the coating layer 160b of the semiconductor structure 100b has a limiting opening 162 on the top surface 152 of the second conductive layer 150, and the bump 170b is located within the limiting opening 162 and can directly contact the second conductive layer 150. Herein, the coating layer 160b can be, for example, an electroplated nickel layer, an electroplated palladium layer, or an electroplated nickel-palladium layer. That is to say, in this embodiment, the coating layer 160b is electroplated on the local surface of the second conductive layer 150, so that the bump 170b can be assisted in positioning and landing within the range restricted by the limiting opening 162 of the coating layer 160b.

[0042] Since the coating layer 160b of this embodiment completely covers the surrounding surface 154 of the second conductive layer 150 and extends to a part of the top surface 152, it means that the coating layer 160a can effectively protect the surrounding surface 154 of the second conductive layer 150 to prevent it from being exposed outside, and effectively prevent oxidation from occurring. In short, the semiconductor structure 100b of this embodiment can have better structural reliability.

[0043] In summary, in the design of the semiconductor structure of the present invention, the coating layer at least completely covers the surrounding surface of the second conductive layer and extends to a part of the top surface, which means that the coating layer can protect the surrounding surface of the second conductive layer to prevent it from being exposed outside and can effectively prevent oxidation from occurring. In this way, the semiconductor structure of the present invention can have better structural reliability.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a base, at least one pad and an insulating layer, wherein the at least one pad is disposed on the base, the insulating layer covers the base and the at least one pad, and the insulating layer exposes a connection portion of the at least one pad; A first protective layer, disposed on the insulating layer of the substrate, and exposing a portion of the connecting portion of the at least one pad; A first conductive layer, disposed on the first protective layer and electrically connected to the connection portion exposed by the first protective layer; A second protection layer, disposed on the first conductive layer, and having at least one opening exposing a portion of the first conductive layer; A second conductive layer, disposed in the at least one opening and extending onto the second protective layer, the second conductive layer being electrically connected to the first conductive layer, and having a top surface and a peripheral surface connected to the top surface; a plating layer at least completely covering the peripheral surface of the second conductive layer and extending to a portion of the top surface; as well as The bump is disposed on the second conductive layer and electrically connected to the second conductive layer.

2. The semiconductor structure according to claim 1, characterized in that: The plating layer also extends to completely cover the top surface of the second conductive layer and is located between the bump and the second conductive layer.

3. The semiconductor structure according to claim 2, characterized in that: The plating layer includes a chemically plated nickel layer, a chemically plated palladium layer or a chemically plated nickel-palladium layer.

4. The semiconductor structure according to claim 1, characterized in that The plating layer has a limiting opening on the top surface of the second conductive layer, and the protrusion is located in the limiting opening.

5. The semiconductor structure according to claim 4, characterized in that: The plating layer includes an electroplated nickel layer, an electroplated palladium layer or an electroplated nickel-palladium layer.

6. The semiconductor structure according to claim 1, characterized in that The thickness of the coating is between 0.1 micrometer and 0.5 micrometer.

7. The semiconductor structure according to claim 1, characterized in that: The first conductive layer includes a redistribution layer.

8. The semiconductor structure according to claim 1, characterized in that: The material of the second conductive layer includes copper.

9. The semiconductor structure according to claim 1, characterized in that: An orthographic projection of the second conductive layer on the substrate does not overlap the at least one pad.

10. The semiconductor structure according to claim 1, wherein: The second protective layer does not cover the second conductive layer.

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