Bridging chip and preparation method thereof, and packaging structure and preparation method thereof

Abstract

The invention relates to a bridge chip and a preparation method thereof, and a packaging structure and a preparation method thereof, and relates to the technical field of semiconductors, in the bridge chip and the preparation method thereof, two sides of the formed bridge chip are respectively provided with a first rewiring structure and a second rewiring structure, and a silicon bridge substrate is arranged in the middle to form a bridge structure. The first dielectric layer and the second dielectric layer are arranged on the outermost side to protect the bonding pad from being damaged. When the bridging chip is adopted to form a packaging structure, the bridging chip of the structure adopts the first bonding pad and the second bonding pad to directly contact with other structures to realize bridging during subsequent bridging, so that direct contact between a silicon bridge substrate and an external structure is avoided, a metal material cannot migrate into a silicon substrate of the silicon bridge substrate during grinding, and the service life of the silicon bridge substrate is prolonged. The short circuit problem of the bridging chip is avoided, and the yield of the packaging structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a bridge chip and a preparation method thereof, a packaging structure and a preparation method thereof. Background Art

[0002] Packaging is a key process in semiconductor manufacturing, used to protect chips, achieve electrical connections and ensure device performance.

[0003] In the existing packaging process, the bridge chip plays the role of electrical connection. When preparing the packaging structure, the bridge chip needs to be ground to expose the conductive vias in the bridge chip to achieve electrical connection. At this time, since the conductive vias of the bridge chip are located in the silicon material, grinding will cause the metal material in the conductive vias to migrate into the bridge chip, thereby causing a short circuit in the packaging structure. Summary of the invention

[0004] Based on this, it is necessary to provide a bridge chip and a preparation method thereof, a packaging structure and a preparation method thereof to address the problem of short circuit of a packaging structure caused by migration of metal materials.

[0005] In order to achieve the above object, on the one hand, the present invention provides a bridge chip, comprising:

[0006] A silicon bridge substrate, a first redistribution structure and a second redistribution structure; the first redistribution structure and the second redistribution structure are respectively located on two sides of the silicon bridge substrate;

[0007] The first rewiring structure includes a first pad and a first dielectric layer, wherein the first pad is located on one side of the silicon bridge substrate, the first dielectric layer is located on a side of the first pad away from the silicon bridge substrate, and the first dielectric layer covers the first pad;

[0008] The second rewiring structure includes a second pad and a second dielectric layer. The second pad is located on a side of the silicon bridge substrate away from the first rewiring structure. The second dielectric layer is located on a side of the second pad away from the silicon bridge substrate, and the second dielectric layer covers the second pad.

[0009] On the other hand, the present invention also provides a packaging structure, comprising:

[0010] A first chip and a first plastic packaging layer surrounding the first chip, wherein the first chip is the chip structure obtained by removing the first dielectric layer and the second dielectric layer from the bridge chip provided in the present application;

[0011] A second chip is located on one side of the first chip and the first plastic packaging layer and is connected to the first chip;

[0012] The second plastic packaging layer is located on a side of the second chip away from the first chip and covers the second chip.

[0013] In one embodiment, the packaging structure further includes:

[0014] a third rewiring structure, located between the first chip and the second chip;

[0015] The fourth rewiring structure is located on a side of the first chip away from the second chip.

[0016] On the other hand, the present invention also provides a method for preparing a bridge chip, comprising:

[0017] Providing a silicon bridge substrate;

[0018] forming a first redistribution structure on one side of the silicon bridge substrate, wherein the first redistribution structure comprises a first pad and a first dielectric layer covering the first pad;

[0019] forming a second redistribution structure on the other side of the silicon bridge substrate, wherein the second redistribution structure comprises a second pad and a second dielectric layer covering the second pad;

[0020] The silicon bridge substrate after the first redistribution structure and the second redistribution structure are formed is cut to form a bridge chip.

[0021] In one embodiment, before forming the second redistribution structure on the other side of the silicon bridge substrate, the method includes:

[0022] providing a first carrier board;

[0023] bonding the first redistribution structure to the first carrier;

[0024] With the first carrier as support, a side of the silicon bridge substrate away from the first redistribution structure is thinned to expose the conductive through-hole structure of the silicon bridge substrate.

[0025] In one embodiment, the cutting after forming the first redistribution structure and the second redistribution structure and before forming the silicon bridge substrate comprises:

[0026] Attaching a first cutting film to a side of the second dielectric layer away from the first carrier;

[0027] The first carrier board is removed.

[0028] In one embodiment, the cutting after forming the first redistribution structure and the second redistribution structure and before forming the silicon bridge substrate further includes:

[0029] attaching a second cutting film to a side of the second dielectric layer away from the first carrier;

[0030] removing the first carrier plate;

[0031] forming a third cutting film on a side of the first dielectric layer away from the second cutting film, and removing the second cutting film;

[0032] A first cutting film is attached to a side of the second dielectric layer away from the first carrier, and the third cutting film is removed.

[0033] In one embodiment, the cutting of the silicon bridge substrate after forming the first redistribution structure and the second redistribution structure comprises:

[0034] The silicon bridge substrate after the first redistribution structure and the second redistribution structure are formed is cut based on the first cutting film.

[0035] On the other hand, the present invention also provides a method for preparing a packaging structure, comprising:

[0036] providing a second carrier board;

[0037] Mounting a third chip on one side of the second carrier board and forming a first plastic packaging layer surrounding the third chip, wherein the third chip is the bridge chip provided in this application;

[0038] Grinding the third chip and the first plastic packaging layer on a side away from the second carrier board to expose the first pad of the third chip;

[0039] Mounting a second chip on a side of the third chip away from the second carrier board, and forming a second plastic packaging layer covering the second chip;

[0040] Using the second plastic packaging layer as support, removing the second carrier board to expose the second dielectric layer of the third chip;

[0041] The second dielectric layer and the first plastic packaging layer are ground to expose the second pad of the third chip.

[0042] In one embodiment, after grinding the third chip and the first plastic encapsulation layer on a side away from the second carrier to expose the first pad of the third chip, the method further comprises:

[0043] forming a third redistribution structure on a side of the third chip away from the second carrier;

[0044] A fourth redistribution structure is formed on a side of the third chip away from the second chip.

[0045] Compared with the prior art, the above technical solution has the following advantages:

[0046] In the bridge chip and its preparation method, the two sides of the formed bridge chip have a first rewiring structure and a second rewiring structure respectively, and the silicon bridge substrate is arranged in the middle to form a bridge structure. The first dielectric layer and the second dielectric layer are arranged on the outermost side to protect the pad from being damaged. The bridge chip of this structure uses the first pad and the second pad to directly contact with other structures to achieve bridging during subsequent bridging, avoiding direct contact between the silicon bridge substrate and the external structure, and the silicon bridge substrate will not be contacted during grinding, avoiding the possibility of metal materials entering the silicon bridge substrate.

[0047] In the packaging structure and preparation method thereof, since the third chip is the bridge chip in the present application, the first rewiring structure and the second rewiring structure are located on both sides of the silicon bridge substrate, and the first pad and the second pad are used to bridge the structures on both sides, thereby avoiding direct contact with the silicon bridge substrate. Therefore, when the second dielectric layer is ground, the metal material will not migrate into the silicon substrate of the silicon bridge substrate, thereby avoiding the short circuit problem of the bridge chip and improving the yield rate of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 A schematic diagram of a preparation process of a bridge chip provided in an embodiment of the present application;

[0050] Figure 2 A schematic diagram of the structure of a silicon bridge substrate provided in an embodiment of the present application;

[0051] Figure 3 A schematic structural diagram of a first redistribution structure formed on a silicon bridge substrate provided in an embodiment of the present application;

[0052] Figure 4 A schematic diagram of a structure after bonding a first carrier board provided in an embodiment of the present application;

[0053] Figure 5 A schematic diagram of a structure of a silicon bridge substrate provided in an embodiment of the present application;

[0054] Figure 6 A schematic diagram of a structure after a second rewiring structure is formed according to an embodiment of the present application;

[0055] Figure 7 A schematic diagram of a structure after a first cutting film is attached provided in an embodiment of the present application;

[0056] Figure 8 for Figure 7 A schematic diagram of the structure after the first carrier board is removed;

[0057] Fig. 9 A schematic diagram of a structure after attaching a second cutting film provided in an embodiment of the present application;

[0058] Fig.10 A schematic diagram of a structure after a third cutting film is attached provided in an embodiment of the present application;

[0059] Fig.11 A schematic diagram of a structure of a bridge chip formed by cutting provided in an embodiment of the present application;

[0060] Fig.12 A schematic diagram of the structure of a silicon bridge substrate after being bonded to a first carrier provided in an embodiment of the present application;

[0061] Fig.13 A schematic diagram of the structure of a silicon-based initial sheet after thinning provided in an embodiment of the present application;

[0062] Fig.14 A schematic diagram of a structure after an initial conductive structure is exposed provided in an embodiment of the present application;

[0063] Fig.15 A schematic diagram of a structure after etching a silicon-based initial wafer provided in an embodiment of the present application;

[0064] Fig.16 A schematic diagram of a structure after a protective material layer is formed according to an embodiment of the present application;

[0065] Fig.17 A schematic diagram of a structure after a silicon bridge substrate is formed provided in an embodiment of the present application;

[0066] Fig.18 A schematic diagram of another structure after etching a silicon-based initial wafer provided in an embodiment of the present application;

[0067] Fig.19 A schematic diagram of another structure after forming a protective material layer provided in an embodiment of the present application;

[0068] Fig. 20 A schematic diagram of the structure of a bridge chip provided in an embodiment of the present application;

[0069] Fig.21 A schematic diagram of a preparation process of a packaging structure provided in an embodiment of the present application;

[0070] Fig. 22 A schematic diagram of the structure of a second carrier board provided in an embodiment of the present application;

[0071] Fig.23 A schematic diagram of a structure after mounting a third chip and forming a first packaging layer provided in an embodiment of the present application;

[0072] Fig.24 A schematic diagram of a structure after removing the first dielectric layer provided in an embodiment of the present application;

[0073] Fig.25 A schematic diagram of a structure after a third rewiring structure is formed according to an embodiment of the present application;

[0074] Fig.26 A schematic diagram of a structure after mounting a second chip and forming a second packaging layer provided in an embodiment of the present application;

[0075] Fig. 27 A schematic diagram of a structure after removing the second carrier board provided in an embodiment of the present application;

[0076] Fig.28 A schematic diagram of a structure after removing the second dielectric layer provided in an embodiment of the present application;

[0077] Fig.29 A schematic diagram of a structure after a fourth rewiring structure is formed according to an embodiment of the present application;

[0078] Fig.30 A schematic diagram of a structure after a conductive structure is formed according to an embodiment of the present application;

[0079] Fig.31 A schematic diagram of a structure after a third pad is formed provided in an embodiment of the present application;

[0080] Fig.32 A schematic diagram of the structure of a first chip provided in an embodiment of the present application.

[0081] Explanation of the reference numerals: 01-silicon bridge substrate; 0111-silicon initial substrate; 011-silicon substrate; 012-wiring layer; 0131-conductive initial structure; 013-conductive through-hole structure; 02-first rewiring structure; 021-first pad; 022-first insulating layer; 023-first dielectric layer; 031-first carrier; 032-first stripping layer; 033-first adhesive layer; 041-protective material layer; 04-protective layer; 05-second rewiring structure; 051-second pad; 052-second insulating layer; 053-second dielectric layer; 06-first cutting film; 061-first adhesive layer; 062-first cutting layer; 063-first stretch ring; 07-second cutting film; 071-second bonding layer; 072-second cutting layer; 073-second stretch ring; 08-third cutting film; 081-third bonding layer; 082-third cutting layer; 083-third stretch ring; 09-second carrier; 10-second demolding layer; 11-second adhesive layer; 12-metal column; 13-third chip; 14-first plastic encapsulation layer; 15-third redistribution structure; 16-second chip; 17-second plastic encapsulation layer; 18-fourth redistribution structure; 181-third dielectric layer; 182-through hole; 183-conductive structure; 19-third pad; 20-first chip. DETAILED DESCRIPTION

[0082] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0084] It should be understood that when a layer is referred to as being "on," "adjacent to," or "connected to" another layer, it can be directly on, adjacent to, or connected to the other layer, or intervening layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another layer, there are no intervening layers.

[0085] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0086] In order to make the purpose, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0087] The present application provides a bridge chip (such as Fig. 20 As shown), the bridge chip includes:

[0088] Silicon bridge substrate 01, first redistribution structure 02 and second redistribution structure 05; the first redistribution structure 02 and the second redistribution structure 05 are respectively located on two sides of the silicon bridge substrate 01;

[0089] The first rewiring structure 02 includes a first pad 021 and a first dielectric layer 023. The first pad 021 is located on one side of the silicon bridge substrate 01. The first dielectric layer 023 is located on a side of the first pad 021 away from the silicon bridge substrate 01. The first dielectric layer 023 covers the first pad 021.

[0090] The second rewiring structure 05 includes a second pad 051 and a second dielectric layer 053 . The second pad 051 is located on a side of the silicon bridge substrate 01 away from the first rewiring structure 02 . The second dielectric layer 053 is located on a side of the second pad 051 away from the silicon bridge substrate 01 , and covers the second pad 051 .

[0091] Specifically, the silicon bridge substrate 01 can connect the first pad 021 of the first rewiring structure 02 and the second pad 051 of the second rewiring structure 05. The first dielectric layer 023 can protect the first pad 021, and the second dielectric layer 053 can protect the second pad 051.

[0092] In this embodiment, the two sides of the bridge chip have a first rewiring structure 02 and a second rewiring structure 05, respectively, and the silicon bridge substrate 01 is arranged in the middle to form a bridge structure. The first dielectric layer 023 and the second dielectric layer 053 are arranged on the outermost side to protect the pads from being damaged. The bridge chip of this structure uses the first pad 021 and the second pad 051 to directly contact other structures to achieve bridging during subsequent bridging, avoiding direct contact between the silicon bridge substrate 01 and the external structure, and will not contact the silicon bridge substrate 01 during grinding, reducing the possibility of metal materials entering the silicon bridge substrate 01.

[0093] Based on the bridge chip, this application also provides a method for preparing the bridge chip, please refer to Figure 1 , Figure 1 A schematic diagram of a preparation process of a bridge chip is provided for an embodiment of the present application; the preparation steps of the bridge chip include:

[0094] S10: Provide a silicon bridge substrate 01 (such as Figure 5 as shown).

[0095] The silicon bridge substrate 01 may be a silicon substrate structure provided with a conductive through-hole structure 013, and is not specifically limited. Figure 5 The silicon bridge substrate 01 in the figure is only an example.

[0096] S20: forming a first redistribution structure 02 on one side of the silicon bridge substrate 01, wherein the first redistribution structure 02 comprises a first pad 021 and a first dielectric layer 023 (such as Figure 3 as shown).

[0097] In this step, a first pad 021 is formed on one side of the silicon bridge substrate 01. The first pad 021 may be a metal conductive material and may be connected to the silicon bridge substrate 01 to achieve circuit conduction. A first insulating layer 022 is also provided between the first pads 021 to prevent short circuits. The material of the first insulating layer 022 may be a photosensitive resin material. Then, a first dielectric layer 023 is formed on the side of the first pad 021 away from the silicon bridge substrate 01. The material of the first dielectric layer 023 may be a photosensitive resin material.

[0098] It should be noted that the photosensitive resin material may include but is not limited to polyimide (PI) material.

[0099] It should be noted that the first rewiring structure may include a plurality of interconnected wiring layers (not shown in the figure), and the plurality of wiring layers are interconnected to achieve conduction, which is only an example in the figure.

[0100] S30: forming a second redistribution structure 05 on the other side of the silicon bridge substrate 01, wherein the second redistribution structure 05 comprises a second pad 051 and a second dielectric layer 053 (such as Figure 6 as shown).

[0101] In this step, a second rewiring structure 05 is formed on the side of the silicon bridge substrate 01 away from the first rewiring structure 02, including first forming a second pad 051, and a second insulating layer 052 is also provided between the second pads 051 to prevent short circuit. The material of the second insulating layer 052 can be a photosensitive resin material. Then, a second dielectric layer 053 is formed on the side of the second pad 051 away from the silicon bridge substrate 01, and the material of the second dielectric layer 053 can be a photosensitive resin material. At this time, the first pad 021 is connected to the second pad 051 through the silicon bridge substrate 01.

[0102] S40: Cutting the silicon bridge substrate 01 after the first rewiring structure 02 and the second rewiring structure 05 are formed to form a bridge chip (eg Fig.11 as shown).

[0103] In this step, the silicon bridge substrate 01 after the first rewiring structure 02 and the second rewiring structure 05 are formed is cut as needed to form a plurality of bridge chips.

[0104] In this embodiment, the two sides of the formed bridge chip have the first rewiring structure 02 and the second rewiring structure 05, respectively, and the silicon bridge substrate 01 is set in the middle to form a bridge structure. The first dielectric layer 023 and the second dielectric layer 053 are set on the outermost side to protect the pads from being damaged. The bridge chip of this structure uses the first pad 021 and the second pad 051 to directly contact other structures to achieve bridging during subsequent bridging, avoiding direct contact between the silicon bridge substrate 01 and the external structure, and will not contact the silicon bridge substrate 01 during grinding, avoiding the possibility of metal materials entering the silicon bridge substrate 01.

[0105] In another embodiment of the present application, before step S30, the following steps are included:

[0106] S301: providing a first carrier board 031.

[0107] The first carrier plate 031 may be a carrier plate used for support, including but not limited to a glass carrier plate.

[0108] S302 : bonding the first redistribution structure 02 to the first carrier board 031 .

[0109] The silicon bridge substrate 01 can be formed in the process of preparing the first rewiring structure 02 and the second rewiring structure 05. That is, a silicon bridge substrate can be provided first, and the silicon bridge substrate at this time can include a silicon-based initial sheet 0111, a wiring layer 012, and a conductive initial structure 0131, wherein the wiring layer 012 is located on one side of the silicon-based initial sheet 0111, and the conductive initial structure 0131 extends inward from the side of the silicon-based initial sheet 0111 where the wiring layer 012 is located (e.g., Figure 2Then, after forming the first redistribution structure 02 on one side of the silicon bridge substrate (as shown in FIG. Figure 3 As shown), before forming the second rewiring structure 05, a silicon bridge substrate 01 is formed.

[0110] Prior to this, a first release layer 032 and a first adhesive layer 033 may be sequentially formed on one side of the first carrier 031, and then the first dielectric layer 023 of the first redistribution structure 02 may be bonded to the first carrier 031 through the first adhesive layer 033 (eg, Figure 4 as shown).

[0111] S303: Using the first carrier 031 as support, thinning the side of the silicon bridge substrate away from the first redistribution structure 02 to expose the conductive through-hole structure 013 (such as Figure 5 as shown).

[0112] In this step, before forming the second redistribution structure 05, the conductive via structure 013 in the silicon bridge substrate 01 needs to be exposed to achieve conduction between the first redistribution structure 02 and the second redistribution structure 05. Therefore, the first carrier 031 can be used as a support to thin the silicon bridge substrate.

[0113] It should be noted that when the silicon bridge substrate 01 is thinned to expose the conductive through-hole structure 013 , two different processes can be used.

[0114] In one process, after the first redistribution structure 02 is bonded to the first carrier 031 (eg Fig.12 As shown in FIG. 1 ), the first pre-thinning is performed on the side of the silicon-based initial wafer 0111 away from the first carrier 031 to increase the process rate (eg Fig.13 Then, a chemical mechanical polishing (CMP) process is used to expose the conductive initial structure 0131 (as shown in Fig.14 As shown), a portion of the silicon-based initial sheet 0111 is then dry-etched to make the thickness of the remaining silicon-based initial sheet 0111 smaller than the height of the conductive initial structure 0131. At this time, the protruding portion of the conductive initial structure 0131 is exposed to the outside, and the remaining silicon-based initial sheet 0111 is the silicon substrate 011 (as shown). Fig.15 Then, a protective material layer 041 (as shown) covering the conductive initial structure 0131 and the silicon substrate 011 is formed by a plasma enhanced chemical vapor deposition (PECVD) process. Fig.16As shown). The material of the protective material layer 041 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride, etc. The protective material layer 041 can prevent the subsequent grinding from damaging the silicon substrate 011. Then, the conductive initial structure 0131 and the protective material layer 041 are ground to flatten the protruding portion of the conductive initial structure 0131, and the remaining conductive initial structure 0131 forms the conductive through-hole structure 013, and the remaining protective material layer 041 forms the protective layer 04 (as shown). Fig.17 As shown). At this time, the conductive through hole structure 013 is exposed. This process can avoid the non-uniformity of the through silicon via process and the chemical mechanical polishing process.

[0115] In another process, after the first redistribution structure 02 is bonded to the first carrier 031 (eg Fig.12 As shown in FIG. 1 ), the first pre-thinning is performed on the side of the silicon-based initial wafer 0111 away from the first carrier 031 to increase the process rate (eg Fig.13 Then, a portion of the silicon-based initial sheet 0111 is dry-etched to make the thickness of the remaining silicon-based initial sheet 0111 smaller than the height of the conductive initial structure 0131. At this time, the silicon-based initial sheet 0111 on the outside of the conductive initial structure 0131 still covers the conductive initial structure 0131 (as shown in FIG. Fig.18 Then, a protective material layer 041 (as shown) covering the conductive initial structure 0131 and the silicon-based initial sheet 0111 is formed by a plasma enhanced chemical vapor deposition (PECVD) process. Fig.19 As shown). The material of the protective material layer 041 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride, etc. The protective material layer 041 can prevent the subsequent grinding from damaging the silicon-based initial wafer 0111. Then, the conductive initial structure 0131 and the protective material layer 041 are ground to flatten the protruding portion of the conductive initial structure 0131, and the remaining conductive initial structure 0131 forms the conductive through-hole structure 013, and the remaining protective material layer 041 forms the protective layer 04 (as shown). Fig.17 As shown in FIG. 1 ). At this time, the conductive through-hole structure 013 is exposed. In this process, the conductive initial structure 0131 is not exposed before the protective layer 04 is formed, and the process is cleaner. 6 Gas etching, the overall etching rate is relatively high.

[0116] It should be noted that both processes can expose the conductive through-hole structure 013 and can be selected as needed.

[0117] In this embodiment, the first carrier 031 is provided as a support layer to thin the silicon bridge substrate 01 based on the first carrier 031 , thereby exposing the conductive via structure 013 to achieve conduction between the first rewiring structure 02 and the second rewiring structure 05 .

[0118] In another embodiment of the present application, before step S40, the following steps are included:

[0119] S4011: Attach a first cutting film 06 (such as Figure 7 shown);

[0120] S4012: Remove the first carrier board 031 (such as Figure 8 as shown).

[0121] Specifically, the first cutting film 06 may be a DAF film. The first cutting film 06 is attached including: attaching a first adhesive layer 061, a first cutting layer 062 and a first tension ring 063. After attaching the first cutting film 06, the first release layer 032 is peeled off by a laser stripping process to remove the first carrier 031, and the first adhesive layer 033 and other impurities are removed by cleaning.

[0122] In this embodiment, attaching the first cutting film 06 can avoid the risk of cracks during subsequent cutting.

[0123] In another embodiment of the present application, before step S40, the method further includes:

[0124] S4021: Attach a second cutting film 07 (such as Fig. 9 shown);

[0125] S4022: removing the first carrier plate 031;

[0126] S4023: forming a third cutting film 08 on a side of the first dielectric layer 023 away from the second cutting film, and removing the second cutting film 07 (such as Fig.10 shown);

[0127] S4024: attaching the first cutting film 06 to the side of the second dielectric layer 053 away from the first carrier 031, and removing the third cutting film 08 (such as Figure 8 as shown).

[0128] Specifically, the first cutting film 06, the second cutting film 07 and the third cutting film 08 can all be DAF films. Attaching the second cutting film 07 includes attaching the second adhesive layer 071, the second cutting layer 072 and the second tension ring 073. After attaching the second cutting film 07, the first release layer 032 is peeled off by laser stripping technology to remove the first carrier 031, and cleaning is performed to remove the first adhesive layer 033 and other impurities.

[0129] In this embodiment, when the first carrier 031 is removed, wrinkles may appear on the second cutting film 07, affecting subsequent cutting and causing cracks. Therefore, the third cutting film 08 is first attached to the side of the first dielectric layer 023 away from the second cutting film 07, and attaching the third cutting film 08 includes: attaching a third adhesive layer 081, a third cutting layer 082, and a third tension ring 083. After that, the second cutting film 07 is removed, and then the first cutting film 06 is attached to the side of the second dielectric layer 053 away from the first carrier 031 again, and then the third cutting film 08 is removed. At this time, the attached first cutting film 06 does not have wrinkles, will not affect subsequent cutting, and further avoids the generation of cracks.

[0130] In another embodiment of the present application, step S40 includes:

[0131] Based on the first cutting film, the silicon bridge substrate 01 (such as Fig.11 as shown).

[0132] In this embodiment, the silicon bridge substrate 01 after forming the first rewiring structure 02 and the second rewiring structure 05 is cut based on the first cutting film, which can reduce the problem of chip cracking during cutting and improve the yield rate of the bridge chip formed after cutting.

[0133] It should be noted that the bridge chip is prepared by the above-mentioned preparation method, and the specific contents thereof can be referred to each other.

[0134] Based on the structure of the above bridge chip, the present application also provides a packaging structure, referring to Fig.30 , the packaging structure includes:

[0135] The first chip 20 and the first plastic packaging layer 14 surrounding the first chip 20, the first chip 20 is the chip structure after the first dielectric layer 023 and the second dielectric layer 053 are removed from the bridge chip provided by the present application (such as Fig.32 shown);

[0136] The second chip 16 is located on one side of the first chip 20 and the first plastic packaging layer 14 and is connected to the first chip 20;

[0137] The second plastic packaging layer 17 is located on a side of the second chip 16 away from the first chip 20 and covers the second chip 16 .

[0138] Specifically, the first chip 20 is the structure of the bridge chip provided in the present application with the first dielectric layer 023 and the second dielectric layer 053 removed, that is, the first chip 20 exposes the first pad 021 and the second pad 051 .

[0139] The first plastic encapsulation layer 14 surrounds the first chip 20 and the metal pillar 12. The second chip 16 is a functional chip mounted on the side of the first chip 20 provided with the first pad 021. A third redistribution structure 15 is formed on the side of the first chip 20 provided with the first pad 021, for connecting the first pad 021 and the second chip 16. The second plastic encapsulation layer 17 covers the second chip 16 for protecting the second chip 16.

[0140] A fourth rewiring structure 18 and a third pad 19 are also provided on one side of the first chip 20 where the second pad 051 is provided. The fourth rewiring structure 18 is used to connect the second pad 051 and the third pad 19. The third pad 19 is used to connect an external circuit.

[0141] In this embodiment, the first chip 20 in the package structure is formed by the bridge chip in this application. The first pad 021 and the second pad 051 are used to bridge the structures on both sides, avoiding direct contact with the silicon bridge substrate 01, further avoiding the short circuit problem of the bridge chip, and improving the yield rate of the package structure.

[0142] In another embodiment of the present application, the packaging structure further includes:

[0143] A third redistribution structure 15 is located between the first chip 20 and the second chip 16;

[0144] The fourth redistribution structure 18 is located on a side of the first chip 20 away from the second chip 16 .

[0145] Specifically, the third rewiring structure 15 is connected to the first pad 021 to bridge the structures on both sides. The third rewiring structure 15 may be provided with a multi-layer metal interconnection structure, and a photosensitive resin material may be provided between the metal interconnection structures. It should be noted that only a partial structure is simply illustrated in the figure.

[0146] After removing the second carrier 09 and exposing the second pad 051, a fourth redistribution structure 18 may be formed on a side of the first chip 20 away from the second chip 16 to achieve high-density interconnection. It should be noted that the fourth redistribution structure 18 may include a third dielectric layer 181, and the third dielectric layer 181 may include a through hole 182, and the through hole 182 at least exposes the second pad 051 and the metal column 12.

[0147] In this embodiment, the third rewiring structure 15 can further realize high-density interconnection and improve interconnection performance. The fourth rewiring structure 18 can be formed to connect the second pad 051 to realize the interconnection of the structures on both sides and improve the interconnection performance.

[0148] Based on the above packaging structure, the present application also provides a method for preparing the packaging structure, which uses the above bridge chip to achieve electrical connection. Fig.21 The steps of preparing the packaging structure include:

[0149] S11: Provide a second carrier board 09 (such as Fig. 22 as shown).

[0150] The second carrier plate 09 may be a carrier plate for supporting, including but not limited to a glass carrier plate.

[0151] S12: Mount a third chip 13 on one side of the second carrier 09, and form a first plastic packaging layer 14 surrounding the third chip 13. The third chip 13 is a bridge chip provided by the present application (eg, Fig.23 as shown).

[0152] The third chip 13 is a bridge chip provided in the present application. The material of the first plastic encapsulation layer 14 may include but is not limited to epoxy molding compound (EMC).

[0153] It should be noted that before the third chip 13 is mounted, a second release layer 10 and a second adhesive layer 11 can be formed in sequence on one side of the second carrier 09, and then a metal column 12 is formed on the second adhesive layer 11. The metal column 12 is used to achieve electrical connection. After that, the third chip 13 is mounted on the second adhesive layer 11, and the first plastic packaging layer 14 also surrounds the metal column 12 to protect the third chip 13 and the metal column 12.

[0154] S13: Grind the third chip 13 and the first plastic encapsulation layer 14 on one side away from the second carrier 09 to expose the first pad 021 of the third chip 13 (eg Fig.24 as shown).

[0155] The grinding may include but is not limited to a chemical mechanical polishing process. During the grinding, part of the metal pillar 12, part of the first plastic encapsulation layer 14, and the first dielectric layer 023 of the third chip 13 are simultaneously ground off, and the first dielectric layer 023 is ground off to expose the first pad 021. After the first pad 021 is exposed, the subsequent connection of the second chip 16 can be realized.

[0156] S14: Mount the second chip 16 on the side of the third chip 13 away from the second carrier 09, and form a second plastic packaging layer 17 (such as Fig.26 as shown).

[0157] The second chip 16 may be a functional chip, and the second chip 16 may be mounted using a flip chip mounting process, or may be mounted using a hybrid bonding process, and is not specifically limited. The first pad 021 of the third chip 13 is connected to the second chip 16. The second plastic encapsulation layer 17 covers the second chip 16 to protect the second chip 16. The material of the second plastic encapsulation layer 17 may include, but is not limited to, epoxy molding compound (EMC).

[0158] It should be noted that after forming the second plastic encapsulation layer 17 , a ring cutting process is further used to remove part of the second plastic encapsulation layer 17 to facilitate the area of ​​the second carrier 09 .

[0159] S15: With the second plastic encapsulation layer 17 as support, remove the second carrier 09 to expose the second dielectric layer 053 of the third chip 13 (such as Fig. 27 as shown).

[0160] The second plastic encapsulation layer 17 is used as a support layer, and the second release layer 10 is peeled off by a laser stripping process to remove the second carrier 09 , and then cleaned to remove the second adhesive layer 11 and other impurities.

[0161] S16: Grind the second dielectric layer 053 and the first plastic packaging layer 14 to expose the second pad 051 of the third chip 13 (such as Fig.28 as shown).

[0162] The grinding of the second dielectric layer 053 and the first plastic layer 14 may include but is not limited to a chemical mechanical polishing process. When the second dielectric layer 053 is ground, even if the metal material on the metal pillar 12 and the second pad 051 migrates, it will only migrate on the second insulating layer 052 of the second redistribution structure 05 and will not enter the silicon substrate 011 of the silicon bridge substrate 01, thereby avoiding the short circuit problem of the bridge chip and improving the yield rate of the packaging structure.

[0163] In this embodiment, since the third chip 13 is the bridge chip in this application, the first rewiring structure 02 and the second rewiring structure 05 are located on both sides of the silicon bridge substrate 01, and the first solder pad 021 and the second solder pad 051 are used to bridge the structures on both sides to avoid direct contact with the silicon bridge substrate 01. Therefore, when the second dielectric layer 053 is ground, the metal material will not migrate into the silicon substrate 011 of the silicon bridge substrate 01, thereby avoiding the short circuit problem of the bridge chip and improving the yield rate of the packaging structure.

[0164] In another embodiment of the present application, after step S13, the following steps are included:

[0165] A third redistribution structure 15 (eg, Fig.25 shown);

[0166] A fourth redistribution structure 18 is formed on a side of the third chip 13 away from the second chip 16. The fourth redistribution structure 18 includes a third dielectric layer 181 (eg, Fig.29 as shown).

[0167] Specifically, a third redistribution structure 15 is formed on a side of the third chip 13 away from the second carrier 09 , and the third redistribution structure 15 is connected to the first pad 021 to bridge the structures on both sides.

[0168] The third rewiring structure 15 may be provided with a multi-layer metal interconnection structure, and a photosensitive resin material may be provided between the metal interconnection structures. It should be noted that only a part of the structure is simply illustrated in the figure.

[0169] After removing the second carrier 09 and exposing the second pad 051, a fourth redistribution structure 18 may be formed on a side of the third chip 13 away from the second chip 16 to achieve high-density interconnection. It should be noted that the fourth redistribution structure 18 may include a third dielectric layer 181, and the third dielectric layer 181 may include a through hole 182, and the through hole 182 at least exposes the second pad 051 and the metal column 12.

[0170] Then, a conductive structure 183 (such as Fig.30 ), and a third pad 19 is formed on a side of the fourth rewiring structure 18 away from the third chip 13 (as shown in Fig.31 for easy connection of external circuits.

[0171] In this embodiment, the third rewiring structure 15 can further realize high-density interconnection and improve interconnection performance. The fourth rewiring structure 18 can be formed to connect the second pad 051 to realize the interconnection of the structures on both sides and improve the interconnection performance.

[0172] It should be noted that the packaging structure is prepared by the packaging structure preparation method, and the specific contents can be referenced to each other.

[0173] In the description of this specification, the description with reference to the terms "some embodiments", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0174] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0175] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A bridge chip, characterized in that: include: A silicon bridge substrate, a first redistribution structure, and a second redistribution structure; The first redistribution structure and the second redistribution structure are respectively located on two sides of the silicon bridge substrate; The first rewiring structure includes a first pad and a first dielectric layer, wherein the first pad is located on one side of the silicon bridge substrate, the first dielectric layer is located on a side of the first pad away from the silicon bridge substrate, and the first dielectric layer covers the first pad; The second rewiring structure includes a second pad and a second dielectric layer. The second pad is located on a side of the silicon bridge substrate away from the first rewiring structure. The second dielectric layer is located on a side of the second pad away from the silicon bridge substrate, and the second dielectric layer covers the second pad.

2. A packaging structure, characterized in that: include: A first chip and a first plastic packaging layer surrounding the first chip, wherein the first chip is a chip structure obtained by removing the first dielectric layer and the second dielectric layer from the bridge chip according to claim 1; A second chip is located on one side of the first chip and the first plastic packaging layer and is connected to the first chip; The second plastic packaging layer is located on a side of the second chip away from the first chip and covers the second chip.

3. The packaging structure according to claim 2, characterized in that: The packaging structure further includes: a third rewiring structure, located between the first chip and the second chip; The fourth rewiring structure is located on a side of the first chip away from the second chip.

4. A method for preparing a bridge chip, characterized in that: include: Providing a silicon bridge substrate; forming a first redistribution structure on one side of the silicon bridge substrate, wherein the first redistribution structure comprises a first pad and a first dielectric layer covering the first pad; forming a second redistribution structure on the other side of the silicon bridge substrate, wherein the second redistribution structure comprises a second pad and a second dielectric layer covering the second pad; The silicon bridge substrate after the first redistribution structure and the second redistribution structure are formed is cut to form a bridge chip.

5. The method for preparing a bridge chip according to claim 4, characterized in that: Before forming the second redistribution structure on the other side of the silicon bridge substrate, the method includes: providing a first carrier board; bonding the first redistribution structure to the first carrier; With the first carrier as support, a side of the silicon bridge substrate away from the first redistribution structure is thinned to expose the conductive through-hole structure of the silicon bridge substrate.

6. The method for preparing a bridge chip according to claim 5, characterized in that: The cutting process before the silicon bridge substrate after the first redistribution structure and the second redistribution structure are formed comprises: Attaching a first cutting film to a side of the second dielectric layer away from the first carrier; The first carrier board is removed.

7. The method for preparing a bridge chip according to claim 5, characterized in that: The cutting and forming of the first redistribution structure and the second redistribution structure before the silicon bridge substrate further includes: Attaching a second cutting film to a side of the second dielectric layer away from the first carrier; removing the first carrier plate; forming a third cutting film on a side of the first dielectric layer away from the second cutting film, and removing the second cutting film; A first cutting film is attached to a side of the second dielectric layer away from the first carrier, and the third cutting film is removed.

8. The method for preparing a bridge chip according to claim 6 or 7, characterized in that: The silicon bridge substrate after the first redistribution structure and the second redistribution structure are formed by cutting includes: The silicon bridge substrate after the first redistribution structure and the second redistribution structure are formed is cut based on the first cutting film.

9. A method for preparing a packaging structure, characterized in that: include: providing a second carrier board; Mounting a third chip on one side of the second carrier board and forming a first plastic packaging layer surrounding the third chip, wherein the third chip is the bridge chip according to claim 1; Grinding the third chip and the first plastic packaging layer on a side away from the second carrier board to expose the first pad of the third chip; Mounting a second chip on a side of the third chip away from the second carrier board, and forming a second plastic packaging layer covering the second chip; Using the second plastic packaging layer as support, removing the second carrier board to expose the second dielectric layer of the third chip; The second dielectric layer and the first plastic packaging layer are ground to expose the second pad of the third chip.

10. The method for preparing a packaging structure according to claim 9, characterized in that: After grinding the third chip and the first plastic encapsulation layer on a side away from the second carrier to expose the first pad of the third chip, the method further comprises: forming a third redistribution structure on a side of the third chip away from the second carrier; A fourth redistribution structure is formed on a side of the third chip away from the second chip.

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