Semiconductor test structure and test method thereof

Abstract

The invention provides a semiconductor test structure and a test method thereof. The structure comprises a semiconductor substrate of a first conduction type, which is provided with a doped region; the doped layer of the second conductive type is formed on the doped region; the dielectric layer is arranged on one side, deviating from the semiconductor substrate, of the doping layer; the conductive layer is arranged on one side, deviating from the semiconductor substrate, of the dielectric layer; the conducting layer comprises a plurality of conducting layer groups which are arranged at intervals in the first direction, each conducting layer group comprises at least one first conducting layer and two second conducting layers, the two second conducting layers are arranged on the two sides of the first conducting layer and are adjacent to the first conducting layer, and the distances from the two second conducting layers to the first conducting layer are equal; and the distances between the first conductive layers in each conductive layer group and the adjacent second conductive layers are different. According to the semiconductor test structure, the specific influence of the load effect on the grid size under different grid spacing is measured by using a capacitance method, and reference and effective guidance are provided for subsequent process development and device design.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor testing, and particularly relates to a semiconductor test structure and a test method thereof. Background Art

[0002] A Metal Oxide Semiconductor Field-Effect-Transistor (MOSFET for short), its main feature is to provide an oxide layer between the gate and the channel, so it has a very high input resistance. MOSFET plays an important role in many electronic devices with its advantages of high input impedance, low power consumption, fast switching speed and easy integration.

[0003] With the improvement of semiconductor integration, the characteristics of MOSFET are becoming more and more sensitive to the changes in critical dimensions caused by process non-uniformity. Among them, the critical dimensions of the gate directly affect the electrical properties of MOSFET. Affected by the etching load effect, the deviation between the designed gate size and the actual gate size after etching becomes larger and larger in sub-micron processes. Therefore, it is crucial to explore the influence law of the load effect on the actual gate size. Summary of the Invention

[0004] Aiming at the problems in the prior art, the purpose of the present invention is to provide a semiconductor test structure and a test method thereof, to explore the influence of the load effect on the actual gate size, and to provide reference and effective guidance for subsequent process development and device design.

[0005] An embodiment of the present invention provides a semiconductor test structure, including:

[0006] A semiconductor substrate of a first conductivity type, provided with a doped region;

[0007] A doped layer of a second conductivity type, formed on the doped region, and the doped layer is used for electrically connecting to a first potential;

[0008] A dielectric layer, provided on a side of the doped layer facing away from the semiconductor substrate;

[0009] A conductive layer, provided on a side of the dielectric layer facing away from the semiconductor substrate; the conductive layer includes a plurality of conductive layer groups spaced apart in a first direction, each conductive layer group includes at least one first conductive layer and two second conductive layers, the two second conductive layers are provided on both sides of the first conductive layer and adjacent to the first conductive layer, the distances from the two second conductive layers to the first conductive layer are equal, and the first conductive layer is electrically connected to a second potential; the distances between each first conductive layer and its adjacent second conductive layer in each conductive layer group are different.

[0010] In some embodiments, in the first direction, the distances between the first conductive layer in the first conductive layer group and the second conductive layers on its two sides are S0 and S1 respectively, satisfying S0 = S1 = n 1 d min ; the distances between the first conductive layer in the second conductive layer group and the second conductive layers on its adjacent two sides are S2 and S3 respectively, satisfying S2 = S3 = n 2 d min ; the distances between the first conductive layer in the third conductive layer group and the second conductive layers on its adjacent two sides are S4 and S5 respectively, satisfying: S4 = S5 = n 3 d min , where d min , n 1 , n 1 , n 3 is a positive number greater than zero.

[0011] In some embodiments, the extension lengths of the first conductive layers in the second direction are equal.

[0012] In some embodiments, it further includes a first metal pad disposed on the side of the doped layer away from the semiconductor substrate.

[0013] In some embodiments, it further includes a second metal pad disposed on the side of the first conductive layer away from the semiconductor substrate.

[0014] In some embodiments, the first conduction type is P-type and the second conduction type is N-type; or,

[0015] the first conduction type is N-type and the second conduction type is P-type.

[0016] In some embodiments, an isolation structure is provided between the doped layer and the semiconductor substrate.

[0017] In some embodiments, the conductive layer is a polysilicon layer or a metal layer.

[0018] The embodiments of the present invention further provide a testing method for a semiconductor test structure. Detecting by using the semiconductor test structure as described above includes the following steps:

[0019] A first power supply provides a first potential to the doped layer, and a second power supply provides a second potential to the first conductive layer;

[0020] Sequentially detect the capacitance values of the capacitances formed between the plurality of first conductive layers and the doped layer respectively;

[0021] According to the obtained plurality of capacitance values, obtain the first size value of each first conductive layer;

[0022] Based on the first size value of each of the obtained first conductive layers and the distance between each of the first conductive layers and the adjacent second conductive layers, a relationship model between the distribution pitch of the first conductive layers and the first size value of the first conductive layers is established.

[0023] In some embodiments, the first size value of the first conductive layer is L, and L = C * d / (ε 0 * ε 1 * W);

[0024] where C is the capacitance value formed between the first conductive layer and the doped layer, d is the thickness of the dielectric layer, ε 0 is the vacuum permittivity, ε 1 is the permittivity of the dielectric layer, and W is the second size of the first conductive layer.

[0025] The semiconductor test structure and its test method provided by the present invention have the following advantages:

[0026] When a first potential is provided to the doped layer and a second potential is provided to the first conductive layer, a capacitance is formed between the doped layer and the first conductive layer. The doped layer is the first electrode plate of the capacitance, and the first conductive layer is the second electrode plate of the capacitance; a semiconductor test platform can detect the magnitudes of the capacitance values of the capacitances formed by multiple first conductive layers and the doped layer; due to the different designed pitches of the first conductive layers in each conductive layer group, affected by the load effect, the actual sizes of the first conductive layers in each conductive layer group are finally different; successively detect the capacitance values of the capacitances formed between each first conductive layer and the doped layer, then obtain the actual size of the first conductive layer according to these capacitance values, and finally establish a relationship model between the designed pitch of the first conductive layer and the first size value of the first conductive layer under the load effect based on the obtained actual size of the first conductive layer and the designed pitch of the first conductive layer. The designed pitches of the multiple first conductive layers in the semiconductor test structure simulate the designed pitches of multiple gates, so the obtained relationship model is the relationship model between the designed pitch of the gate and the actual size of the gate under the load effect, which can provide reference and effective guidance for subsequent process development and device design, and improve the performance of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objects, and advantages of the present invention will become more apparent.

[0028] Figure 1 Shows a TEM cross-sectional view of a gate structure with a small gate pitch in the prior art;

[0029] Figure 2 Shows a TEM cross-sectional view of a gate structure with a large gate pitch in the prior art;

[0030] Figure 3 is a plan view of a semiconductor test structure according to an embodiment of the present invention;

[0031] Figure 4 is a cross-sectional view of a semiconductor test structure according to an embodiment of the present invention;

[0032] Figure 5 is a flowchart of a test method for a semiconductor test structure according to an embodiment of the present invention.

[0033] Reference numerals:

[0034] 10 semiconductor substrate 50 first metal pad

[0035] 20 doped layer 60 second metal pad

[0036] 21 heavily doped region 70 isolation structure

[0037] 30 dielectric layer 41 first conductive layer

[0038] 40 conductive layer 42 second conductive layer Detailed implementation manners

[0039] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Identical reference numerals in the figures denote identical or similar structures, and thus their repetitive description will be omitted.

[0040] In the description of this application, the references to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this application and the features of the different embodiments or examples without conflict.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of such feature. In the description of this application, "a plurality" means two or more unless specifically and clearly defined otherwise.

[0042] It should be further understood that the terms "comprising" and "including" indicate the presence of features, steps, operations, elements, components, items, categories, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, categories, and / or groups. The terms "or" and "and / or" used herein are interpreted inclusively and mean any one or any combination. Thus, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". An exception to this definition occurs only when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0043] The current methods for characterizing the size of a gate include two methods: detecting using a scanning electron microscope (SEM) and detecting using a transmission electron microscope (TEM). Among them, detecting using a scanning electron microscope is carried out after the step of forming a patterned gate; detecting using a transmission electron microscope is carried out after forming a MOSFET device, and the MOSFET device needs to be sliced. These two detection methods are time-consuming, the detection steps are cumbersome, and the detection cost is high, and it is not convenient to use to explore the influence law of the load effect on the actual gate size.

[0044] The load effect is a common phenomenon in semiconductor manufacturing, which refers to the phenomenon that during the plasma etching process, the size and density of the etched pattern will affect the etching rate and the etching profile. When the area of the etched pattern is larger and the etched pattern is denser, it will limit the transport of the reaction gas and the reaction product, reduce the gas consumption per unit volume, and lead to a decrease in the etching rate. Therefore, when the designed size of the gate is the same and the designed spacing of the gate is different, it will affect the actual size of the finally formed gate. Figure 1 Shows a TEM cross-sectional view of a gate structure with a small gate pitch; Figure 2 Shows a TEM cross-sectional view of a gate structure with a large gate pitch, Figure 1 and Figure 2 have the same designed size of the gate, but different designed spacings of the gate. As Figure 1 shown, the actual size L1 of the bottom of the gate with a small designed spacing of the gate is 207 nm, as Figure 2 shown, the actual size L2 of the bottom of the gate with a large designed spacing of the gate is 234 nm. Therefore, the size of the designed spacing of the gate affects the actual size of the obtained gate.

[0045] The size of the gate includes the gate length, which refers to the distance between the source and the drain. It directly affects the switching speed, current driving ability, and power consumption of the transistor and is a key dimension of the gate of a semiconductor device. Therefore, the embodiments of the present invention mainly explore the influence law of the designed spacing of the gate on the actual length of the gate.

[0046] To solve the problems in the prior art, the embodiments of the present invention provide a semiconductor test structure. Figure 3 FIG. shows a plan view of a semiconductor test structure provided by an embodiment of the present invention; Figure 4 FIG. shows a cross-sectional view of a semiconductor test structure provided by an embodiment of the present invention. As Figure 3 and Figure 4 shown, the semiconductor test structure includes:

[0047] A semiconductor substrate 10 of a first conductivity type, provided with a doped region;

[0048] A doped layer 20 of a second conductivity type, formed on the doped region, and the doped layer 20 is used for electrical connection to a first potential;

[0049] A dielectric layer 30, provided on a side of the doped layer 20 facing away from the semiconductor substrate 10;

[0050] A conductive layer 40, provided on a side of the dielectric layer 30 facing away from the semiconductor substrate 10; the conductive layer 40 includes a plurality of conductive layer groups spaced apart in a first direction, and each conductive layer group includes at least one first conductive layer 41 and two second conductive layers 42. The two second conductive layers 42 are provided on both sides of the first conductive layer 41 and adjacent to the first conductive layer 41, and the distances from the two second conductive layers 42 to the first conductive layer 41 are equal. The first conductive layer 41 is used for electrical connection to a second potential; the distances between each first conductive layer 41 and its adjacent second conductive layer 42 in each conductive layer group are different.

[0051] It should be noted that the first potential and the second potential are polar opposite potentials.

[0052] It should also be noted that the first conductive layer 41 includes a first dimension extending in the first direction and a second dimension extending in the second direction. The first direction is the left-right direction as seen on the paper surface, and the second direction is the up-down direction as seen on the paper surface. The first dimension of the first conductive layer 41 simulates the actual length of the gate, and the second dimension of the first conductive layer 41 simulates the actual width of the gate. In this embodiment, the extension lengths of each first conductive layer 41 in the second direction are equal, that is, the widths of the simulated gates are equal. Therefore, the designed spacing of the first conductive layer 41 is different, thereby affecting the actual first dimension of the first conductive layer 41, that is, affecting the actual length of the gate.

[0053] When a first potential is provided to the doped layer 20 and a second potential is provided to the first conductive layer 41, a capacitor is formed between the doped layer 20 and the first conductive layer 41. The doped layer 20 serves as the first electrode plate of the capacitor, and the first conductive layer 41 serves as the second electrode plate of the capacitor. The capacitance values of the capacitors formed by multiple first conductive layers 41 and the doped layer 20 can be detected using a semiconductor test station. Due to the different designed spacings of the first conductive layers 41 in each conductive layer group, affected by the load effect, the actual sizes of the first conductive layers 41 in each conductive layer group are ultimately different. The capacitance values of the capacitors formed between each first conductive layer 41 and the doped layer 20 are sequentially detected, and then the actual size of the first conductive layer 41 is obtained based on these capacitance values. Finally, based on the obtained actual size of the first conductive layer 41 and the designed spacing of the first conductive layer 41, a relationship model between the designed spacing of the first conductive layer 41 and the first size value of the first conductive layer 41 under the load effect is established. The designed spacings of the multiple first conductive layers 41 in the semiconductor test structure simulate the designed spacings of multiple gates. Therefore, the obtained relationship model is the relationship model between the designed spacing of the gate and the actual size of the gate under the load effect, which can provide reference and effective guidance for subsequent process development and device design, and improve the performance of semiconductor devices.

[0054] Further, as Figure 3 and Figure 4 shown, in this embodiment, the semiconductor test structure includes three groups of conductive layer groups, including three first conductive layers 41 and four second conductive layers 42. Specifically, in the first direction, the distances between the first conductive layer 41(1) in the first conductive layer group and the second conductive layers 42(1) and 42(2) on its two sides are S0 and S1 respectively, satisfying S0 = S1 = n 1 d min ; the distances between the first conductive layer 41(2) in the second conductive layer group and the second conductive layers 42(2) and 42(3) on its adjacent two sides are S2 and S3 respectively, satisfying S2 = S3 = n 2 d min ; the distances between the first conductive layer 41(3) in the third conductive layer group and the second conductive layers 42(3) and 42(4) on its adjacent two sides are S4 and S5 respectively, satisfying: S4 = S5 = n 3 d min , where d min , n 1 , n 1 , n 3 is a positive number greater than zero.

[0055] In this embodiment, d min is the minimum size of the gate spacing allowed by the process design rules, n1 is 90%, n2 is 100%, and n3 is 110%. n 1If it is 90%, then n 1 d min is 90% of the minimum size of the gate pitch allowed by the process design rules; n 2 If it is 100%, then n 2 d min is the minimum size of the gate pitch allowed by the process design rules; n 3 If it is 110%, then n 3 d min is 110% of the minimum size of the gate pitch allowed by the process design rules. The designs of the first conductive layer 41 and the second conductive layer 42 in the first conductive layer group are equivalent to the case where the designed pitch of the gate is relatively small, the designs of the first conductive layer 41 and the second conductive layer 42 in the second conductive layer group are equivalent to the case where the designed pitch of the gate is normal, and the designs of the first conductive layer 41 and the second conductive layer 42 in the third conductive layer group are equivalent to the case where the designed pitch of the gate is relatively large.

[0056] It should be noted that the specific number of conductive layer groups in the semiconductor test structure is not limited to the number shown above, and more conductive layer groups can be added according to actual needs to obtain more relationship data between the designed pitch of the gate and the actual length of the gate. The specific design of the pitch between each first conductive layer 41 and its adjacent second conductive layer 42 is not limited to the above examples, and various design pitches can be designed according to actual needs.

[0057] Furthermore, the material of the dielectric layer 30 can be a composite material layer composed of one or more of silicon oxide, chromium oxide, or silicon oxynitride.

[0058] The material of the conductive layer 40 can be, for example, a polysilicon layer or a metal material, and the material of the conductive layer 40 is selected according to the gate material of the actually designed semiconductor device.

[0059] Furthermore, as Figure 1 and Figure 2 shown, the semiconductor test structure further includes a first metal pad 50 disposed on the side of the doped layer 20 away from the semiconductor substrate 10. By providing the first metal pad 50 to be electrically connected to the doped layer 20, a first potential is transmitted to the doped layer 20 through the first metal pad 50. To reduce the contact resistance between the doped layer 20 and the first metal pad 50, therefore, the position where the first metal pad 50 contacts the doped layer 20 needs to be heavily doped to form a heavily doped region 21, so as to form an ohmic contact between the first metal pad 50 and the doped layer 20, and the ohmic contact can reduce the contact resistance between the doped layer 20 and the first metal pad 50.

[0060] Furthermore, as Figure 1 and Figure 2As shown, in this embodiment, the semiconductor test structure further includes a second metal pad 60 disposed on a side of the first conductive layer 41 away from the semiconductor substrate 10. By providing electrical connection between the second metal pad 60 and the first conductive layer 41, a second potential is transmitted to the first conductive layer 41 through the second metal pad 60.

[0061] Further, in one embodiment, the first conductivity type is P-type and the second conductivity type is N-type. The semiconductor test structure provided in this embodiment simulates the structure of an NMOS semiconductor device. Since the second conductivity type is N-type, the doped layer 20 is N-type. Further, when the semiconductor structure is being tested, the doped layer 20 is connected to a negative potential and the first conductive layer 41 is connected to a positive potential.

[0062] In another embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In this case, the semiconductor test structure provided simulates the structure of a PMOS semiconductor device. Since the second conductivity type is P-type, the doped layer 20 is P-type. Further, when the semiconductor structure is being tested, the doped layer 20 is connected to a positive potential and the first conductive layer 41 is connected to a negative potential.

[0063] Further, in some embodiments, an isolation structure 70 is provided between the doped layer 20 and the semiconductor substrate 10. The isolation structure is used to isolate the semiconductor substrate 10 from the doped layer 20 to avoid electrical connection between the two. As Figure 2 shown, in this embodiment, the isolation structure is a shallow trench isolation structure. The shallow trench structure is formed by etching a groove in the semiconductor substrate and filling the groove with an oxide, thereby effectively isolating the device and preventing leakage and other situations.

[0064] Further, an embodiment of the present invention also provides a test method for a semiconductor test structure, which uses the semiconductor test structure described above for detection. Figure 5 shows a flowchart of a test method for a semiconductor test structure provided by an embodiment of the present invention. As Figure 5 shown, the test method for the semiconductor test structure includes the following steps:

[0065] Step S100: A first power supply provides a first potential to the doped layer 20, and a second power supply provides a second potential to a first conductive layer 41;

[0066] Step S200: Sequentially detect the capacitance values of the capacitances formed between multiple first conductive layers 41 and the doped layer 20 respectively;

[0067] Step S300: Based on the obtained multiple capacitance values, obtain the first size value of each first conductive layer 41;

[0068] Step S400: Based on the obtained first size value of each first conductive layer 41 and the distance between each first conductive layer 41 and its adjacent second conductive layer 42, establish a relationship model between the distribution distance of the first conductive layer 41 and the first size value of the first conductive layer 41.

[0069] Among them, the distance between the first conductive layer 41 and its adjacent second conductive layer 42 is the designed spacing of the first conductive layer 41. The designed spacings of the multiple first conductive layers 41 in the semiconductor test structure simulate the designed spacings of multiple gates. Therefore, the obtained relationship model is the relationship model between the designed spacing of the gate and the actual size of the gate under the load effect, which can provide reference and effective guidance for subsequent process development and device design, and improve the performance of semiconductor devices.

[0070] Specifically, the first size value of the first conductive layer 41 is L, and L = C * d / (ε 0 * ε 1 * W);

[0071] Among them, C is the capacitance value formed between the first conductive layer 41 and the doped layer 20, d is the thickness of the dielectric layer 30, ε 0 is the vacuum permittivity, ε 1 is the permittivity of the dielectric layer 30, and W is the second size of the first conductive layer.

[0072] In summary, the semiconductor test structure and its test method provided by the present invention have the following advantages:

[0073] When a first potential is provided to the doped layer and a second potential is provided to the first conductive layer, a capacitance is formed between the doped layer and the first conductive layer. The doped layer is the first electrode plate of the capacitance, and the first conductive layer is the second electrode plate of the capacitance; a semiconductor test station can detect the magnitude of the capacitance value of the capacitance formed by multiple first conductive layers and the doped layer; due to the different designed spacings of the first conductive layers in each conductive layer group, affected by the load effect, the actual sizes of the first conductive layers in each conductive layer group are finally different; successively detect the capacitance values of the capacitances formed between each first conductive layer and the doped layer, then obtain the actual size of the first conductive layer according to these capacitance values, and finally establish a relationship model between the designed spacing of the first conductive layer and the first size value of the first conductive layer under the load effect based on the obtained actual size of the first conductive layer and the designed spacing of the first conductive layer. The designed spacings of the multiple first conductive layers in the semiconductor test structure simulate the designed spacings of multiple gates. Therefore, the obtained relationship model is the relationship model between the designed spacing of the gate and the actual size of the gate under the load effect, which can provide reference and effective guidance for subsequent process development and device design, and improve the performance of semiconductor devices.

[0074] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A semiconductor test structure, characterized in that: include: A semiconductor substrate of a first conductivity type having a doped region; A doping layer of a second conductivity type is formed on the doping region, and the doping layer is used to be electrically connected to the first potential; A dielectric layer, disposed on a side of the doped layer away from the semiconductor substrate; A conductive layer is arranged on a side of the dielectric layer away from the semiconductor substrate; the conductive layer includes a plurality of conductive layer groups spaced apart in a first direction, each of the conductive layer groups includes at least one first conductive layer and two second conductive layers, the two second conductive layers are arranged on both sides of the first conductive layer and are adjacent to the first conductive layer, the two second conductive layers are at an equal distance from the first conductive layer, and the first conductive layer is electrically connected to a second potential; the distances between each first conductive layer in each conductive layer group and the second conductive layer adjacent to it are different.

2. The semiconductor test structure according to claim 1, characterized in that: In the first direction, the distances between the first conductive layer in the first conductive layer group and the second conductive layers on both sides thereof are S0 and S1 respectively, satisfying S0=S1=n1d min ; The distances between the first conductive layer in the second conductive layer group and the second conductive layers on both sides thereof are S2 and S3 respectively, satisfying S2=S3=n2d min The distances between the first conductive layer and the second conductive layers on both sides of the third conductive layer group are S4 and S5, respectively, satisfying: S4 = S5 = n3d min , where d min , n1, n1, n3 are positive numbers greater than zero.

3. The semiconductor test structure according to claim 1, characterized in that: The extension lengths of the first conductive layers in the second direction are equal.

4. The semiconductor test structure according to claim 1, characterized in that: The invention also includes a first metal pad, which is arranged on a side of the doped layer away from the semiconductor substrate.

5. The semiconductor test structure according to claim 1, characterized in that: The invention also includes a second metal pad, which is arranged on a side of the first conductive layer away from the semiconductor substrate.

6. The semiconductor test structure according to claim 1, characterized in that: The first conductivity type is P type, and the second conductivity type is N type; or, The first conductivity type is N type, and the second conductivity type is P type.

7. The semiconductor test structure according to claim 1, characterized in that: An isolation structure is provided between the doping layer and the semiconductor substrate.

8. The semiconductor test structure according to claim 1, characterized in that: The conductive layer is a polysilicon layer or a metal layer.

9. A method for testing a semiconductor test structure, characterized in that: Testing using the semiconductor test structure according to any one of claims 1 to 8 comprises the following steps: The first power supply provides a first potential to the doped layer, and the second power supply provides a second potential to the first conductive layer; sequentially detecting capacitance values ​​of capacitors formed between the first conductive layers and the doped layers; Obtaining a first size value of each of the first conductive layers according to the obtained multiple capacitance values; According to the obtained first size value of each first conductive layer and the distance between each first conductive layer and its adjacent second conductive layer, a relationship model between the distribution spacing of the first conductive layers and the first size value of the first conductive layers is established.

10. The method for testing a semiconductor test structure according to claim 9, characterized in that: The first dimension value of the first conductive layer is L, where L=C*d / (ε0*ε1*W); Wherein, C is the capacitance value formed between the first conductive layer and the doped layer, d is the thickness of the dielectric layer, ε0 is the vacuum dielectric constant, ε1 is the dielectric constant of the dielectric layer, and W is the second size of the first conductive layer.

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