A MOS transistor chip with electrostatic protection structure

Abstract

This invention relates to the field of MOSFET chip technology, specifically to a MOSFET chip with an electrostatic discharge (ESD) protection structure. The chip includes a package housing and a package cover encapsulated on the housing. The package housing has an internal mounting slot and several pins on its perimeter. A chip substrate is disposed inside the package housing. An insulating layer is disposed on the side of the chip substrate away from the package cover, and an ESD protection layer is disposed on the side of the insulating layer away from the chip substrate. This ESD protection layer guides the ESD protection process. Compared to existing technologies, this application, by including an ESD protection layer, not only enables the ESD protection layer to quickly discharge static electricity but also provides long-term stable performance in harsh environments, improving the reliability and adaptability of ESD protection and ensuring the safety of the chip in various complex environments.

Description

Technical Field

[0001] This invention relates to the field of MOS transistor chip technology, and in particular to a MOS transistor chip with an electrostatic protection structure. Background Technology

[0002] MOSFET chips are semiconductor components widely used in electronic devices. They achieve switching functions by controlling the flow of current and are widely used in digital circuits, analog circuits, power amplifiers, and power management. However, with the increasing complexity of integrated circuits, MOSFET chips are becoming more sensitive to electrostatic discharge (ESD) and electromagnetic interference, which requires additional protection measures to ensure the stability and reliability of the chips.

[0003] In the prior art, Chinese patent document CN101515584B, "A Diode Chip Integrated Using MOS Process Structure," proposes a design and manufacturing process using a MOS process structure. Based on the P-channel device effect principle of MOC field-effect transistors, a novel gate-source short-circuit structure is designed. This results in low forward voltage drop, low forward power consumption and heat generation, strong current carrying capacity, low reverse leakage current, good reverse high-temperature characteristics, and strong anti-static and lightning protection capabilities. However, consistent with traditional methods, traditional MOS transistor chips lack an electrostatic protection structure. Static electricity can easily be conducted directly to the chip's interior through the pins, leading to static electricity accumulation or electrostatic discharge (ESD). The chip itself cannot effectively absorb and disperse ESD, easily causing direct impact of static electricity on the internal circuitry, increasing the risk of short circuits or current overloads, potentially damaging chip functionality and thus the internal circuitry. Therefore, this application discloses a MOS transistor chip with an electrostatic protection structure. Summary of the Invention

[0004] In view of this, the purpose of this invention is to propose a MOS transistor chip with an electrostatic protection structure to solve the problem that traditional MOS transistor chips lack an electrostatic protection structure and cannot effectively absorb and disperse electrostatic discharge, which easily leads to electrostatic direct impact on the internal circuit of the chip.

[0005] To achieve the above objectives, the present invention provides a MOS transistor chip with an electrostatic protection structure, including a package box and a package cover packaged on the package box. The package box has a mounting groove inside, and a number of pins are provided around the package box. A package chip substrate is provided inside the package box.

[0006] An insulating layer is provided on the side of the packaged chip substrate away from the package cover, and an electrostatic protection layer is provided on the side of the insulating layer away from the packaged chip substrate. The electrostatic protection layer is used to guide electrostatic protection.

[0007] Preferably, the electrostatic protection layer includes a shielding layer and a conductive layer. The conductive layer is used to quickly guide static electricity, and the shielding layer is used for the conductive layer to prevent damage to the conductive layer.

[0008] Preferably, the bottom of the conductive layer is made of nickel, the top of the conductive layer is made of copper, and the shielding layer is also made of nickel.

[0009] Preferably, a conductive groove is formed in the top center of the conductive layer, and the shielding layer is attached to the top of the conductive groove. Several trapezoidal conductive strips are arranged inside the conductive groove, and several shielding strips adapted to the conductive strips are arranged at the bottom of the shielding layer. The conductive strips and the shielding strips are attached to each other in an alternating manner.

[0010] Preferably, the insulating layer is made of silicon dioxide.

[0011] Preferably, the bottom of the mounting groove is provided with a U-shaped surrounding groove, and the surrounding groove is provided with dispersion grooves in the direction away from the packaging chip substrate. The dispersion grooves are opened at an angle, and the opening depth of the surrounding groove and the dispersion grooves is set to be between 0.1mm and 0.5mm.

[0012] Preferably, both the surrounding groove and the dispersion groove are filled with a composite material of silver powder and epoxy resin.

[0013] Preferably, the outer periphery of the mounting groove is further provided with a U-shaped guide block, and the outer periphery of the top surface of the conductive layer is further provided with a plurality of conductive pillars, and the guide block also penetrates the mounting groove and contacts the plurality of conductive pillars.

[0014] Preferably, an external post is provided at one corner of the encapsulation cover, and the bottom of the external post is embedded inside one side of the surrounding groove.

[0015] Preferably, the bottom of the pin is provided with a groove, the outer surface of the groove is fitted with a current limiting ring, the bottom of the current limiting ring is provided with a plurality of connecting posts, and the current limiting ring is made of nickel-chromium alloy.

[0016] The beneficial effects of this invention are:

[0017] 1. This type of MOS transistor chip with an electrostatic discharge (ESD) protection structure features an ESD protection layer. This layer, combining a copper conductive layer and a nickel shielding layer, provides efficient and long-term stable ESD protection. Copper has excellent conductivity, quickly guiding static electricity to external circuits or ground, preventing static buildup inside the chip and reducing potential damage from ESD. Nickel has strong oxidation and corrosion resistance, preventing copper from oxidizing in humid or corrosive environments and ensuring long-term stable conductivity. The shielding layer encapsulates the conductive layer, effectively preventing external physical damage and chemical corrosion, protecting the integrity of the conductive layer, and enhancing the overall mechanical strength of the structure, preventing damage from external forces. Furthermore, the combination of the nickel base layer and the copper conductive layer not only enables the ESD protection layer to quickly discharge static electricity but also provides long-term stable performance in harsh environments, improving the reliability and adaptability of ESD protection and ensuring the safety of the chip in various complex environments.

[0018] 2. This type of MOS transistor chip with electrostatic discharge (ESD) protection structure features conductive strips and shielding strips. The staggered arrangement of the conductive and shielding strips effectively optimizes the ESD discharge path. The trapezoidal structure of the conductive strips increases the contact area, providing multiple paths for ESD to pass through, preventing ESD from concentrating on a single path and causing overheating or breakdown. The staggered structure ensures that the ESD discharge path remains unobstructed, allowing ESD to be continuously released even if the package vibrates or shifts. The trapezoidal conductive strips also disperse stress and prevent electric field concentration in sharp corner areas, effectively reducing damage to the chip during ESD. At the same time, it reduces the parasitic inductance between the conductive and shielding layers, improves ESD response speed and discharge efficiency, and enhances the long-term stability and reliability of the chip.

[0019] 3. This type of MOS transistor chip with electrostatic discharge (ESD) protection structure utilizes a combination of surrounding trenches, dispersion trenches, guide blocks, and external posts. The surrounding trenches and dispersion trenches form a multi-layered ESD dispersion channel. The inclined dispersion trenches guide static electricity away from the core area of ​​the chip, reducing the damage caused by ESD. The trenches are filled with a composite material of silver powder and epoxy resin, providing excellent conductivity and ensuring that static electricity can quickly flow to the ground wire or external circuit. The guide blocks, through a U-shaped structure, contact the conductive posts, further improving the ESD discharge efficiency and forming a closed conductive loop to ensure uniform distribution of static electricity. The design of the external posts further enhances the ESD guidance path. Even if there is damage or decreased conductivity in a certain part of the surrounding trench, the external posts can still serve as a supplementary channel to ensure unobstructed ESD discharge, greatly improving the protection reliability of the package and enhancing the stability and anti-interference capability of the chip in complex environments.

[0020] 4. This type of MOS transistor chip with electrostatic protection structure incorporates a current-limiting ring. This ring effectively dissipates static electricity entering from external pins, preventing it from directly impacting the internal circuitry and reducing the risk of electrostatic discharge (ESD) damage. The current-limiting ring also directs static electricity into the metal ring or conductive polymer layer, minimizing the damage caused by ESD. Furthermore, the nickel-chromium alloy's excellent high-temperature resistance and good electrical properties make it suitable as a current-limiting material during static dissipation, helping to ensure that the chip is not damaged by short circuits or current overloads during ESD. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a three-dimensional structural diagram of the present invention;

[0023] Figure 2 This is a schematic diagram of the internal structure of the present invention;

[0024] Figure 3 For the present invention Figure 2 Enlarged structural diagram at point A in the middle;

[0025] Figure 4 This is an exploded structural diagram of the present invention;

[0026] Figure 5 For the present invention Figure 4 Enlarged structural diagram at point B;

[0027] Figure 6 This is a schematic diagram of the internal planar structure of the present invention;

[0028] Figure 7 This is a schematic diagram of the chip packaging substrate, electrostatic protection layer, and insulating layer structure of the present invention;

[0029] Figure 8 This is a schematic diagram of the shielding layer and conductive layer structure of the present invention.

[0030] The diagram is marked as follows:

[0031] 1. Encapsulation box; 2. Mounting slot; 3. Encapsulation cover; 4. Pin; 5. External post; 6. Encapsulation chip substrate; 7. Shielding layer; 8. Conductive layer; 9. Conductive groove; 10. Conductive strip; 11. Shielding strip; 12. Surrounding groove; 13. Dispersion groove; 14. Guide block; 15. Groove; 16. Current limiting ring; 17. Connecting post; 18. Insulating layer; 19. Conductive post. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0033] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] like Figures 1 to 8 As shown, a MOS transistor chip with an electrostatic discharge (ESD) protection structure includes a package box 1 and a package cover 3 packaged on the package box 1. The package box 1 has a mounting groove 2 inside, and several pins 4 are provided around the package box 1. The package chip substrate 6 is provided inside the package box 1. An insulating layer 18 is provided on the side of the package chip substrate 6 away from the package cover 3, and an ESD protection layer is provided on the side of the insulating layer 18 away from the package chip substrate 6. The ESD protection layer is used to guide ESD protection.

[0035] An insulating layer 18 and an electrostatic discharge (ESD) protection layer are disposed at the bottom of the chip substrate 6. This effectively guides external static electricity to the ground line through the ESD protection layer, preventing static electricity from directly intruding into the core area of ​​the chip. This significantly reduces the damage caused by electrostatic discharge (ESD) to the MOSFET chip, preventing the chip from failing due to static electricity accumulation during production, transportation, and actual use, and improving the overall reliability of the chip. The insulating layer 18 is located between the chip substrate and the ESD protection layer, acting as an isolation layer to ensure that static electricity does not directly contact the chip circuit, avoiding short circuits or leakage. This layered design forms a multi-layered protection structure. Even if the ESD protection layer is subjected to external impact or damage, the insulating layer 18 can still provide basic protection, improving the electrical stability of the chip in complex environments. The ESD protection layer can quickly guide static electricity to the ground line outside the chip package, thereby reducing the accumulation of electric field on the chip surface and preventing static electricity from accumulating around the chip substrate. This prevents the electric field from becoming too strong due to charge accumulation, which could cause failure of internal components of the chip.

[0036] like Figure 1 , Figure 7 , Figure 8 As shown, the electrostatic protection layer includes a shielding layer 7 and a conductive layer 8. The conductive layer 8 is used to quickly conduct static electricity, and the shielding layer 7 is used for the conductive layer 8 to prevent damage to the conductive layer 8. The bottom of the conductive layer 8 is made of nickel, and the top of the conductive layer 8 is made of copper. The shielding layer 7 is also made of nickel, and the insulating layer 18 is made of silicon dioxide.

[0037] The conductive layer 8 is made entirely of copper, with a nickel base to complement the copper base of the shielding layer 7. Copper has excellent conductivity, quickly guiding static electricity to ground or external circuits, effectively preventing static buildup inside the chip and reducing potential damage from electrostatic discharge (ESD). Nickel typically has strong oxidation and corrosion resistance; therefore, using nickel at the bottom of the conductive layer 8 prevents the copper from losing conductivity due to oxidation, especially in humid or corrosive environments. This helps extend the lifespan of the ESD protection layer. The shielding layer 7... It effectively protects the conductive layer 8 from external physical damage (such as scratches and impacts) and chemical corrosion, ensuring that the electrostatic channel maintains stable conductivity and reliability for a long time. The nickel material of the shielding layer 7 can not only protect the conductive layer 8, but also enhance the mechanical strength of the overall structure. The high hardness of the nickel material can effectively prevent damage to the electrostatic protection layer from external forces (such as vibration or drops). Furthermore, the combination of the nickel bottom layer and the copper conductive layer 8 can take into account the excellent conductivity of copper and the oxidation resistance of nickel, giving the electrostatic protection layer the dual advantages of rapid static discharge and long-term stable use, adapting to more complex environmental requirements.

[0038] A conductive groove 9 is provided in the top center of the conductive layer 8. The shielding layer 7 is attached to the top of the conductive groove 9. Several trapezoidal conductive strips 10 are provided inside the conductive groove 9. Several shielding strips 11 that are compatible with the conductive strips 10 are provided at the bottom of the shielding layer 7. The conductive strips 10 and the shielding strips 11 are attached to each other in an alternating manner.

[0039] The conductive strip 10 and shielding strip 11 are staggered and bonded together, allowing static electricity to be conducted to the ground wire through multiple paths. This avoids static electricity concentration in a single channel, preventing localized overheating or breakdown, thus improving the efficiency of static discharge. The trapezoidal design of the conductive strip 10 effectively expands the contact area of ​​the conductive layer 8, increases the static discharge path, reduces the risk of static electricity accumulation on the chip surface, and enables static electricity to be quickly discharged from the chip area. The staggered structure can maintain a tight fit even when the chip is running or the packaging is vibrating. Even with slight displacement, the static discharge path will not be interrupted, ensuring continuous static electricity discharge in various environments, improving stability and reliability. Furthermore, the trapezoidal cross-section design can disperse stress and prevent electric field concentration effects in sharp corner areas, thereby reducing local stress damage to the chip during electrostatic discharge (ESD), improving the fatigue resistance and long-term stability of the structure. Moreover, the staggered bonding structure reduces the parasitic inductance between the conductive layer 8 and the shielding layer 7, avoiding additional obstacles in the static discharge path, allowing static electricity to be conducted to the ground wire more quickly, and improving the electrostatic response speed.

[0040] like Figures 2 to 4 As shown, a U-shaped surrounding groove 12 is provided at the bottom of the mounting groove 2. Dispersion grooves 13 are provided around the surrounding groove 12 in a direction away from the packaging chip substrate 6. The dispersion grooves 13 are inclined. The depth of the surrounding groove 12 and the dispersion grooves 13 is set between 0.1mm and 0.5mm. The interior of the surrounding groove 12 and the dispersion grooves 13 are filled with silver powder and epoxy resin composite material. A U-shaped guide block 14 is also provided on the outer periphery of the mounting groove 2. Several conductive pillars 19 are also provided on the outer periphery of the top surface of the conductive layer 8. The guide block 14 also penetrates the mounting groove 2 and contacts the several conductive pillars 19.

[0041] The surrounding trench 12 and the dispersion trench 13 form a multi-layered electrostatic dispersion channel at the bottom of the mounting groove 2. The inclined dispersion trench 13 guides the static electricity away from the packaged chip substrate 6, effectively reducing the threat of static electricity to the core area of ​​the chip. The inclined structure further optimizes the static electricity diversion path, avoids static electricity concentration, and reduces the risk of local overheating or breakdown. The surrounding trench 12 and the dispersion trench 13 are filled with silver powder and epoxy resin composite material. The silver powder provides high conductivity and quickly discharges static electricity. The guide block 14 is arranged in a U-shape around the outer periphery of the mounting groove 2 and contacts the conductive post 19 to form a closed conductive circuit. The through design of the guide block 14 further enhances the efficiency of static electricity discharge, so that the static electricity is evenly distributed between each path, reducing the load of a single path and improving the reliability of discharge. The depth of the surrounding trench 12 and the dispersion trench 13 is set between 0.1mm and 0.5mm, which takes into account the compactness and functionality of the chip package, can adapt to the requirements of precision packaging, and ensures that the conductivity and dispersion ability are not affected.

[0042] An external post 5 is provided at one corner of the encapsulation cover 3, and the bottom of the external post 5 is embedded inside one side of the surrounding groove 12;

[0043] The external post 5 ensures that electrostatic discharge (ESD) protection is no longer limited to the inside of the package 1. By connecting with the surrounding trench 12, it forms a multi-layered protection path from the package cover 3 to the bottom of the mounting slot 2, ensuring that static electricity can be efficiently conducted to the ground wire. This further improves the ESD protection performance of the overall package structure. Moreover, the external post 5 provides an additional path for ESD guidance. Even if there is damage or a decrease in conductivity at a certain point in the surrounding trench 12, the external post 5 can still serve as a supplementary channel, working in conjunction with the dispersion slot 13 and the conductive post 19 to ensure effective ESD release and enhance the chip's reliability in complex environments.

[0044] like Figure 4 , Figure 5 As shown, a groove 15 is provided at the bottom of pin 4, and a current limiting ring 16 is sleeved on the outer surface of the groove 15. Several connecting posts 17 are provided at the bottom of the current limiting ring 16, and the current limiting ring 16 is made of nickel-chromium alloy.

[0045] The current-limiting ring 16 effectively dissipates static electricity entering from external pin 4, preventing static electricity from directly impacting the internal circuitry of the chip through pin 4 and reducing the risk of electrostatic discharge (ESD) damage to the chip. With the presence of the current-limiting ring 16, static electricity will preferentially flow into the metal ring or conductive polymer layer, reducing the harm of ESD to the internal circuitry of the chip. Furthermore, the nickel-chromium alloy has excellent high-temperature resistance and good resistance characteristics, making it suitable as a current-limiting material during static dissipation. This helps ensure that the chip is not damaged due to short circuits or current overloads during ESD.

[0046] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples; within the framework of the invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in the details for the sake of brevity.

[0047] This invention is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A MOS transistor chip with an electrostatic protection structure, characterized in that, include: The package box (1) and the package cover (3) packaged on the package box (1) are provided with an installation groove (2) inside the package box (1), and a number of pins (4) are provided around the package box (1). The package chip substrate (6) is provided inside the package box (1). An insulating layer (18) is provided on the side of the packaged chip substrate (6) away from the packaged cover (3). An electrostatic protection layer is provided on the side of the insulating layer (18) away from the packaged chip substrate (6). The electrostatic protection layer includes a shielding layer (7) and a conductive layer (8). The electrostatic protection layer is used to guide electrostatic protection. The bottom of the mounting groove (2) is provided with a U-shaped surrounding groove (12). The surrounding groove (12) is provided with a dispersion groove (13) in the direction away from the packaging chip substrate (6). The dispersion groove (13) is opened at an angle. The opening depth of the surrounding groove (12) and the dispersion groove (13) is set between 0.1 mm and 0.5 mm. The interior of the surrounding groove (12) and the dispersion groove (13) is filled with silver powder and epoxy resin composite material. The outer periphery of the mounting groove (2) is also provided with a U-shaped guide block (14). The outer periphery of the top surface of the conductive layer (8) is also provided with a number of conductive pillars (19). The guide block (14) also penetrates the mounting groove (2) and contacts the number of conductive pillars (19). One corner of the packaging cover (3) is provided with an external post (5). The bottom of the external post (5) is embedded in one side of the surrounding groove (12).

2. The MOS transistor chip with electrostatic protection structure according to claim 1, characterized in that, The conductive layer (8) is used to quickly guide static electricity, and the shielding layer (7) is used for the conductive layer (8) to prevent the conductive layer (8) from being damaged.

3. The MOS transistor chip with electrostatic protection structure according to claim 2, characterized in that, The bottom of the conductive layer (8) is made of nickel, the top of the conductive layer (8) is made of copper, and the shielding layer (7) is also made of nickel.

4. The MOS transistor chip with electrostatic protection structure according to claim 3, characterized in that, The conductive layer (8) has a conductive groove (9) in the middle of its top. The shielding layer (7) is attached to the top of the conductive groove (9). The conductive groove (9) has a number of trapezoidal conductive strips (10) inside. The bottom of the shielding layer (7) has a number of shielding strips (11) that are compatible with the conductive strips (10). The conductive strips (10) and the shielding strips (11) are attached to each other in an alternating manner.

5. The MOS transistor chip with electrostatic protection structure according to claim 1, characterized in that, The insulating layer (18) is made of silicon dioxide.

6. The MOS transistor chip with electrostatic protection structure according to claim 1, characterized in that, The bottom of the pin (4) is provided with a groove (15), and a current limiting ring (16) is provided on the outer surface of the groove (15). The bottom of the current limiting ring (16) is provided with several connecting posts (17), and the current limiting ring (16) is made of nickel-chromium alloy.

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