Power supply control circuit and electronic device

Abstract

The application discloses a power supply control circuit and electronic equipment, and belongs to the technical field of electronics. The power supply control circuit is used for controlling a power supply to be in a low power mode (LPM) or a normal power mode (NPM), and comprises an LPM power supply protection module, a register unit and an adjustment module. The LPM power supply protection module is used for judging whether a power supply abnormal event is triggered according to an output signal of the power supply when the power supply is in the LPM. A first bit in the register unit comprises a first identifier or a second identifier. The first identifier is used for controlling the power supply to be in the LPM. The second identifier is used for controlling the power supply to be in the NPM. The adjustment module is used for adjusting the first bit in the register unit to the second identifier before a possible power supply abnormal event is triggered according to a target signal, or adjusting the first bit in the register unit to the second identifier in the case that the power supply abnormal event is frequently triggered. The target signal comprises at least one of the output signal of the power supply and a signal in the LPM power supply protection module.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a power control circuit and an electronic device. Background Technology

[0002] The power supply itself has static power consumption, which is the power consumption to maintain its own working state. Based on the magnitude of static power consumption, the operating mode of the power supply can be divided into low power mode (LPM) and normal power mode (NPM).

[0003] Under LPM (Limited Power Management), a series of state changes are required to reduce static power consumption, such as disabling some functions like overvoltage and undervoltage protection; reducing the internal clock frequency, for example, from 26MHz to 32kHz; reducing the drive circuit capability to minimize drive circuit losses; and disabling the bias circuit function. Since the power supply output current is entirely determined by the load, under LPM, the power supply's load current capability and dynamic load current response capability decrease significantly. When the load draw exceeds the power supply device's response capability, an overcurrent (OC) event or a "Power Good" (PG) abnormal event occurs, triggering the power supply device's overcurrent protection (OCP) or PG abnormal protection, increasing the probability of the power supply system being shut down and the entire system being shut down and restarted. Summary of the Invention

[0004] The purpose of this application is to provide a power control circuit and electronic device that can reduce the probability of the power supply system being shut down and the entire system being shut down and restarted due to the protection mechanism that triggers power abnormal events in LPM mode.

[0005] In a first aspect, embodiments of this application provide a power control circuit for controlling the power supply to operate at LPM or NPM. The power control circuit includes:

[0006] The LPM power protection module is electrically connected to the output terminal of the power supply and determines whether a power abnormality event is triggered based on the output signal of the power supply when the power supply is in the LPM state.

[0007] A register unit is provided for connection to the power supply. A first bit in the register unit includes a first identifier or a second identifier, wherein the first identifier is used to control the power supply to be in the LPM mode; and the second identifier is used to control the power supply to be in the NPM mode.

[0008] An adjustment module, wherein a first end of the adjustment module is electrically connected to at least one of the output terminal of the power supply and the LPM power protection module, and a second end of the adjustment module is connected to the register unit; if the adjustment module determines that a power abnormality event may be triggered based on the target signal, it adjusts the first bit in the register unit to the second identifier before triggering the power abnormality event; or, if the adjustment module determines that a power abnormality event is frequently triggered based on the target signal, it adjusts the first bit in the register unit to the second identifier.

[0009] The target signal includes at least one of the following: the output signal of the power supply and the signal in the LPM power protection module.

[0010] Secondly, embodiments of this application provide an electronic device, which includes a power supply and a power control circuit as described in the first aspect.

[0011] In this embodiment, when the power supply is in LPM mode, an adjustment module determines whether the power supply is likely to trigger an abnormal power event, such as an OC event and / or a PG event, or whether such events are frequently triggered. Based on this, the module actively adjusts the flag in the first bit of the register unit to switch the power supply to NPM before an abnormal power event is triggered, or to restrict the power supply to NPM if abnormal power events are frequently triggered. This reduces the probability of the power supply triggering abnormal power events or frequently triggering such events in LPM mode, thereby reducing the probability of the power supply system being shut down and the entire system being shut down and restarted due to the protection mechanism for abnormal power events triggered in LPM mode. Attached Figure Description

[0012] Figure 1 This is a block diagram of the OC protection logic for power supplies in related technologies;

[0013] Figure 2 This is one of the logic block diagrams of the power control circuit in the embodiments of this application;

[0014] Figure 3 This is the second logic block diagram of the power control circuit in the embodiments of this application;

[0015] Figure 4 This is the third logic block diagram of the power control circuit in the embodiments of this application;

[0016] Figure 5 This is the fourth logic block diagram of the power control circuit in the embodiments of this application;

[0017] Figure 6 This is the fifth logic block diagram of the power control circuit in the embodiments of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0019] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0020] To facilitate understanding of the power control circuit provided in the embodiments of this application, the technologies, terms, and terminology related to this application will be explained first.

[0021] 1. LPM refers to a power supply operating mode that reduces the static power consumption of the battery by taking at least one of the following measures: shutting down some functions, reducing the operating frequency of the internal clock, reducing the driving circuit capability, and disabling the bias circuit function.

[0022] 2. NPM indicates an operating mode that does not reduce the static power consumption of the battery compared to LPM;

[0023] 3. LPM power protection module, which refers to the functional module that performs OC event trigger judgment and executes OC protection during the power supply's LPM period, and / or performs PG abnormal event trigger judgment and executes PG abnormal protection.

[0024] 4. NPM power protection module, which refers to the functional module that performs OC event trigger judgment and executes OCP during the NPM period of the power supply, and / or performs PG abnormal event trigger judgment and executes PG abnormal protection.

[0025] 5. OC event, which indicates an event where the current of the power supply or load is too high.

[0026] 6. PG abnormal event indicates an event where the power supply output voltage is unstable.

[0027] 7. A DC-DC power supply, also known as a switching power supply, uses a switching waveform to control the charging and discharging of inductors and capacitors to achieve voltage reduction or boost.

[0028] 8. Low Dropout Regulator (LDO) power supply: Based on a negative feedback system, it achieves voltage regulation by detecting and adjusting the output voltage.

[0029] 9. OC Debounce Duration: This indicates that when the overcurrent protection module detects that the power supply's output current exceeds the OC threshold voltage for a certain period of time, it will trigger an OC event and execute OCP after that period. The duration during which the power supply's output current exceeds the OC threshold voltage is the OC debounce duration. The purpose of setting this OC debounce duration is to avoid frequent false triggering of OC events caused by short-term fluctuations in the power supply's output current.

[0030] For ease of explanation, the embodiments of this application typically use the example of an LPM power protection module being an LPM overcurrent protection module and an NPM power protection module being an NPM overcurrent protection module, with the LPM overcurrent protection module and the NPM overcurrent protection module being used to perform OC event trigger judgment and execute OCP when the power supply is in LPM and NPM states, respectively. This does not constitute a specific limitation.

[0031] Of course, the LPM power protection module may also be an LPM overvoltage protection module, and the NPM power protection module may be an NPM overvoltage protection module. The LPM overvoltage protection module and the NPM overvoltage protection module are used to determine the triggering of PG abnormal events and to perform PG abnormal event protection functions when the power supply is in LPM and NPM states, respectively. The main difference between the two is that the LPM overvoltage protection module and the NPM overvoltage protection module are used to detect the power supply output voltage to determine whether a PG abnormal event is triggered, while the LPM overcurrent protection module and the NPM overcurrent protection module are used to detect the power supply output current or a voltage signal that can reflect the magnitude of the power supply output current to determine whether an OC event is triggered. The working principle of the LPM overvoltage protection module and the NPM overvoltage protection module can be found in the explanation of the LPM overcurrent protection module and the NPM overcurrent protection module in the embodiments of this application.

[0032] like Figure 1As shown, in related technologies, the OC protection of power supplies under LPM and NPM is independent of each other. Taking the OC protection of DC / DC power supplies under LPM as an example, the LPM overcurrent protection module includes a voltage detection unit 101, a reference voltage supply unit 102, a comparator 103, a delay unit 104, a combinational logic unit 105, an LPM mode OC flag register unit 106, and an OC response unit 107.

[0033] The working principle of the LPM overcurrent protection module triggering OCP is as follows: The voltage detection unit 101 detects the voltage difference across the MOSFET at the output terminal of the DC / DC power supply and compares this voltage difference with the OC threshold voltage under LPM, i.e., the reference voltage provided by the reference voltage providing unit 102. Since the output current of the DC / DC power supply is proportional to the voltage difference across the MOSFET, if the voltage difference across the MOSFET is greater than the OC threshold voltage under LPM, it indicates that the output current of the DC / DC power supply may trigger OC protection. At this time, the output state of the comparator 103 flips, that is, the digital logic signal output by the comparator 103 flips from "0" to "1". This digital logic signal "1" is delayed for a certain time by the delay unit 104. If the state of the digital logic signal is still "1" after the delay, the LPM mode OC flag bit in the LPM mode OC flag bit register unit 106 is adjusted to "1", indicating that the OC event is triggered. Once the OC event is triggered, the OC response unit 107 will shut down the power supply or even shut down the entire power supply system.

[0034] It should be noted that in related technologies, the LPM overcurrent protection module and the NPM overcurrent protection module operate independently of each other. That is, when the power supply is in LPM mode, Figure 1 The LPM overcurrent protection module at the top center is activated when the power supply is in NPM mode. Figure 1 The NPM overcurrent protection module in the lower middle section is working.

[0035] The difference between the LPM overcurrent protection module and the NPM overcurrent protection module is that the OC threshold voltage under LPM in the LPM overcurrent protection module is lower than the OC threshold voltage under NPM in the NPM overcurrent protection module, and the OC de-jittering time of the LPM overcurrent protection module, i.e., the delay time of the delay unit 104, is shorter than the OC de-jittering time of the NPM overcurrent protection module.

[0036] It is worth noting that in related technologies, software control can be used to switch the power supply from LPM to NPM. However, when the power supply is in LPM mode, if the load is too large when a load is removed, the power supply's load current capacity and load dynamic current response capability will decrease significantly. Since software control of the power supply to switch from LPM to NPM takes a certain amount of time, there is a risk that the OCP will be triggered before the power supply can switch from LPM to NPM, resulting in the power supply system being shut down and the entire system being shut down and restarted.

[0037] Specifically, while related technologies can use software to control the power supply to switch from LPM to NPM to improve the power supply's load current capacity and load dynamic current response, thereby reducing the probability of triggering OCP, the switching process from LPM to NPM can cause a significant low-voltage drop due to load withdrawal, resulting in OCP triggering. This leads to the power supply system being shut down and the entire system being shut down and restarted. At this point, the power supply switching scheme from LPM to NPM becomes ineffective.

[0038] For example, taking a power supply that is a low-dropout regulator (LDO) as an example, the load can be directly connected to the LDO or connected to the LDO via an input DC / DC converter. For the load on the DC / DC converter, the software-based switching from LPM to NPM works as follows: when the software detects that a downstream LDO load of the DC / DC power supply is about to be turned on, it first calculates the load size of the downstream LDO load and adjusts the DC / DC converter's operating mode to NPM before starting the load. This actively increases the power supply capacity of the DC / DC converter, reducing the risk of the power supply system being shut down and the entire system restarting due to OCP triggering under LPM. However, for the LDO itself, the power supply capacity is increased only after OCP is triggered, resulting in a slower response time. When the load is large and causes a significant voltage drop, OCP is triggered before the power supply capacity of the LDO is increased, causing the power supply system to be shut down and the entire system to restart.

[0039] Therefore, LDO power supplies and DC / DC power supplies in related technologies may trigger OCP due to slow power supply response speed, resulting in the power supply system being shut down and the entire system being shut down and restarted.

[0040] Furthermore, the power supply in the embodiments of this application can be a DC / DC power supply or an LDO power supply. For ease of explanation, the embodiments of this application usually use an LDO power supply as an example for illustration, which does not constitute a specific limitation.

[0041] In this embodiment, when the power supply is in LPM mode, an adjustment module determines whether the power supply is likely to trigger an abnormal power event, such as an OC event and / or a PG event, or whether such events are frequently triggered. Based on this, the module actively adjusts the flag in the first bit of the register unit to switch the power supply to NPM before an abnormal power event is triggered, or to restrict the power supply to NPM if abnormal power events are frequently triggered. This reduces the probability of the power supply triggering abnormal power events or frequently triggering such events in LPM mode, thereby reducing the probability of the power supply system being shut down and the entire system being shut down and restarted due to the protection mechanism for abnormal power events triggered in LPM mode.

[0042] The power control circuit and electronic equipment provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0043] The power control circuit provided in this embodiment is used to control the power supply 10 to be in LPM or NPM mode. (See also...) Figure 2 The power control circuit includes:

[0044] LPM power protection module 20 is electrically connected to the output terminal of power supply 10, and determines whether a power abnormality event is triggered based on the output signal of power supply 10 when power supply 10 is in the LPM state.

[0045] Register unit 30 is used to connect to power supply 10. The first bit in register unit 30 includes a first identifier or a second identifier, wherein the first identifier is used to control power supply 10 to be in the LPM; and the second identifier is used to control power supply 10 to be in the NPM.

[0046] An adjustment module 40 has a first terminal for electrical connection to at least one of the output terminal of the power supply 10 and the LPM power protection module 20, and a second terminal for connection to the register unit 30. The adjustment module 40 adjusts the first bit in the register unit 30 to the second identifier before triggering a power abnormality event based on a target signal; or, if the adjustment module 40 determines that a power abnormality event is frequently triggered based on the target signal, it adjusts the first bit in the register unit 30 to the second identifier. The target signal includes at least one of the following: the output signal of the power supply 10 and the signal in the LPM power protection module 20.

[0047] In some implementations, the power supply abnormality event includes at least one of an overcurrent (OC) event and a voltage instability event, wherein the voltage instability event may also be referred to as a "Power Good" (PG) abnormality event, i.e., the output voltage of power supply 10 is unstable.

[0048] It's worth noting that OC events typically occur when a load is unloaded, causing an increase in the output current of power supply 10, thereby triggering the overcurrent protection mechanism to shut down the power or power off. The PG signal is used to detect the stability of the power supply's output voltage. When the output voltage of power supply 10 stabilizes, the PG signal changes from low to high, indicating to the motherboard that the power supply is in normal working order. If the power supply output voltage is unstable or too low, it may cause hardware damage. The PG signal can detect such problems in time and protect the safe operation of the hardware by triggering a PG abnormal event to shut down the power or power off. Both OC and PG abnormal events are similar in that under LPM (Limited Power Management), because the power supply capacity and load dynamic current response capability of power supply 10 are reduced, the probability of the LPM power protection module 20 triggering OC and PG abnormal events increases.

[0049] For ease of explanation, the following embodiments of this application use power abnormality events as OC events and LPM power protection module 20 as an example of LPM overcurrent protection module for illustration, which does not constitute a specific limitation.

[0050] In some implementations, the register unit 30 is connected to the power supply 10, which can be achieved through an additional logic decision unit. For example, the processor system can connect to the register unit 30 via a System Power Management Interface (SPMI) to read the identifier in the first bit of the register unit 30 and control the operating mode of the power supply 10 based on the read identifier. In this case, if the processor system reads the first identifier from the first bit of the register unit 30 via the SPMI interface, the power supply 10 is controlled to be in the LPM (Level Minimum Power Mode); if the processor system reads the second identifier from the first bit of the register unit 30 via the SPMI interface, the power supply 10 is controlled to be in the NPM (Non-Minimum Power Mode).

[0051] In some implementations, after the adjustment module 40 adjusts the first bit in the register unit 30 to the second identifier, the logic judgment unit connected to the register unit 30, such as a power management integrated circuit (PMIC) or a system on chip (SoC) control unit, will control the power supply 10 to switch to NPM in the next clock cycle. Since the power supply capability and load dynamic current response capability of the power supply 10 under NPM are improved, the probability of triggering an OC event based on load withdrawal is greatly reduced when load withdrawal occurs.

[0052] In some implementations, the LPM power protection module 20 includes: a first detection unit 21, a first comparator 22, a second delay unit 23, a third logic unit 24, an LPM OC flag register unit 25, and a first OC response unit 26;

[0053] The first detection unit 21 is electrically connected to the output terminal of the power supply 10 and the first terminal of the first comparator 22, respectively. The second terminal of the first comparator 22 is used to receive the first reference electrical signal, namely the LPM OC-REF voltage. The third terminal of the first comparator 22 is electrically connected to the first terminal of the third logic unit 24 and the first terminal of the second delay unit 23, respectively. The second terminal of the second delay unit 23 is electrically connected to the second terminal of the third logic unit 24. The third terminal of the third logic unit 24 is electrically connected to the first terminal of the LPM OC flag register unit 25. The first OC response unit 26 is electrically connected to the second terminal of the LPM OC flag register unit 25.

[0054] The working principle of the LPM power protection module is the same as that of the LPM power protection module in related technologies. For example, the first detection unit 21 is used to detect the magnitude of the output signal of the power supply 10, such as the output voltage or output current, and the first comparator 22 is used to compare the magnitude of the output signal with the first reference electrical signal. If the output signal is greater than the first reference electrical signal, the first comparator 22 can output a high-level signal. The second delay unit 23 is used to delay for a certain period of time. If it is determined that the first comparator 22 still outputs a high-level signal, a high-level signal is transmitted to the second terminal of the third logic unit 24. The third logic unit 24 is used to transmit a high-level signal to the LPMOC flag register unit 25 when it receives a high-level signal at both its first and second terminals, so as to set the LPMOC flag in the LPMOC flag register unit 25 to "1", that is, an OC event occurs. The first OC response unit 26 is used to execute an OC response, such as turning off the power or shutting down, according to the LPMOC flag set to "1".

[0055] As can be seen from the above, the delay time of the LPM power protection module 20 in triggering the power protection mechanism is the same as the delay time of the second delay unit 23, and the judgment threshold of the LPM power protection module 20 is the same as the value of the first reference electrical signal.

[0056] It should be noted that, as in the above embodiment, the example given is that the first comparator 22 outputs a high level when the output signal of the power supply 10 is greater than the first reference electrical signal, and otherwise outputs a low level. In this case, the third logic unit 24 can be an AND gate logic unit. Of course, in some other possible implementations, the output signal of the first comparator 22 can be low when the output signal of the power supply 10 is greater than the first reference electrical signal. In this case, the judgment logic of the third logic unit 24 can also change accordingly, which is not specifically limited here.

[0057] Furthermore, for ease of explanation, in this embodiment of the application, the first comparator 22 outputs a high level when the output signal of the power supply 10 is greater than the first reference electrical signal, and the first comparator 22 outputs a low level otherwise. This is not intended to constitute a specific limitation.

[0058] Furthermore, in this embodiment, the example given is that the detection units, such as the first detection unit 21 and the subsequent second detection unit 44, are used to detect the voltage difference across the MOS transistor corresponding to the output current of the power supply 10. In this case, the OC threshold, i.e., the reference electrical signal, is a voltage threshold. Of course, in other possible implementations, the first detection unit 21 and the subsequent second detection unit 44 may also be used to directly detect the output current of the power supply 10. In this case, the OC threshold, i.e., the reference electrical signal, can be a current threshold, which is not a specific limitation here.

[0059] In some implementations, such as Figure 3 As shown, the power control circuit also includes:

[0060] The NPM power protection module 50 is electrically connected to the output terminal of the power supply 10 and is used to determine whether to trigger an OC event based on the output signal of the power supply 10 when the power supply 10 is in the NPM state.

[0061] Specifically, when power supply 10 switches to NPM, NPM power protection module 50 is enabled and LPM power protection module 20 is disabled; when power supply 10 is in LPM, LPM power protection module 20 is enabled and NPM power protection module 50 is disabled.

[0062] It should be noted that, since the power supply capacity and load dynamic current response capability of power supply 10 are improved under NPM, the OC de-jitter delay time of NPM power protection module 50 is longer than that of LPM power protection module 20; the reference electrical signal for NPM power protection module 50 to determine the trigger OC event is greater than that for LPM power protection module 50 to determine the trigger OC event.

[0063] In this way, the threshold for the NPM power protection module 50 to trigger an OC event is higher than the threshold for the LPM power protection module 20 to trigger an OC event, which makes the probability of the power supply 10 triggering an OC event under NPM lower than the probability of the power supply 10 triggering an OC event under LPM, thereby reducing the probability of the power supply 10 shutting down or powering off due to OCP under NPM.

[0064] The NPM power protection module 50 has the same structure and working principle as the existing NPM power protection module, for example: Figures 2 to 6 As shown, the NPM power protection module 50 includes:

[0065] The system comprises a third detection unit 51, a third comparator 52, a third delay unit 53, a fourth logic unit 54, an NPM OC flag register unit 55, and a second OC response unit 56.

[0066] The third detection unit 51 is electrically connected to the output terminal of the power supply 10 and the first terminal of the third comparator 52, respectively. The second terminal of the third comparator 52 is used to receive the third reference electrical signal, namely the NPM OC-REF voltage. The third terminal of the third comparator 52 is electrically connected to the first terminal of the fourth logic unit 54 and the first terminal of the third delay unit 53, respectively. The second terminal of the third delay unit 53 is electrically connected to the second terminal of the fourth logic unit 54. The third terminal of the fourth logic unit 54 is electrically connected to the first terminal of the NPM OC flag register unit 55. The second OC response unit 56 is electrically connected to the second terminal of the NPM OC flag register unit 55.

[0067] The working principle of the NPM power protection module is the same as that of the NPM power protection module in related technologies. For example, the third detection unit 51 is used to detect the magnitude of the output signal of the power supply 10, such as the output voltage or output current, and the third comparator 52 is used to compare the magnitude of the output signal with the first reference electrical signal. If the output signal is greater than the first reference electrical signal, the third comparator 52 can output a high-level signal. The third delay unit 53 is used to delay for a certain period of time. If it is determined that the third comparator 52 still outputs a high-level signal, a high-level signal is transmitted to the second terminal of the fourth logic unit 54. The fourth logic unit 54 is used to transmit a high-level signal to the NPMOC flag register unit 55 when it receives a high-level signal at both its first and second terminals, so as to set the NPM OC flag in the NPM OC flag register unit 55 to "1", that is, an OC event occurs. The second OC response unit 56 is used to execute an OC response, such as turning off the power or shutting down, according to the NPM OC flag set to "1".

[0068] As can be seen from the above, the delay time of the NPM power protection module 50 triggering the power protection mechanism is the same as the delay time of the third delay unit 53, and the judgment threshold of the NPM power protection module 50 is the same as the value of the third reference electrical signal.

[0069] It should be noted that the third reference voltage is greater than the first reference voltage, that is, the OC judgment threshold of NPM is higher than the OC judgment threshold of LPM. In addition, the delay duration of the third delay unit 53 can be longer than the delay duration of the second delay unit 23, so that the OC de-jittering time under NPM is longer.

[0070] In some implementations, the adjustment module 40 can be hardware connected to the register unit 30, so that the adjustment module 40 can rewrite the identifier of the first bit in the register unit 30 by transmitting hardware signals to the register unit 30.

[0071] For example: Figure 2 , Figure 3 , Figure 4 or Figure 5 As shown, the adjustment module 40 is used to transmit a first signal or a second signal to the register unit 30 according to the target signal;

[0072] When the adjustment module 40 transmits the first signal to the register unit 30, the identifier of the first bit in the register unit 30 remains unchanged; when the adjustment module 40 transmits the second signal to the register unit 30, the register unit 30 adjusts the first bit to the second identifier in response to the first signal.

[0073] For example: if the first signal is a low-level signal and the second signal is a high-level signal, when the register unit 30 obtains a low-level signal from the adjustment module 40, the first bit will remain unchanged, and the working state of the power supply 10 will remain unchanged; or, when the register unit 30 obtains a high-level signal from the adjustment module 40, the first bit will be adjusted to the second flag, and the working state of the power supply 10 will be switched to NPM.

[0074] In this embodiment, by interconnecting the hardware signals between the adjustment module 40 and the register unit 30, the identifier of the first bit in the register unit 30 can be quickly adjusted according to the logic state of the adjustment module 40.

[0075] Of course, in other embodiments, the adjustment module 40 can be software connected to the register unit 30, such as by setting an intermediate signal processing module to obtain the output signal of the adjustment module 40 and rewrite the identifier of the first bit in the register unit 30 according to the output signal of the adjustment module 40.

[0076] In some implementations, if the adjustment module 40 determines that an OC event may be triggered, the adjustment module 40 adjusts the first bit in the register unit 30 to the second identifier before the LPM power protection module 20 triggers the OC event to execute OCP. This is to switch the power supply 10 to NPM in advance before the LPM power protection module 20 actually triggers the OC event, thereby improving the power supply capacity and load dynamic current response capability of the power supply 10 and reducing the probability of triggering the OC event.

[0077] To determine whether an OC event might be triggered, the adjustment module 40 can use at least one of the following methods:

[0078] Method 1: The first terminal of the adjustment module 40 is electrically connected to the output terminal of the power supply 10. In this way, the adjustment module 40 can detect the output signal of the power supply 10, such as output voltage or output current. When the power supply is in LPM mode, it compares the magnitude or rate of change of the output signal of the power supply 10 with the OC threshold value under LPM to determine whether an OC event may be triggered based on the comparison result. For example: assuming the OC threshold value under LPM is the LPM OC threshold voltage, if the voltage value corresponding to the output current of the power supply 10 is greater than this LPM OC threshold voltage, it is determined that an OC event may be triggered.

[0079] As an optional implementation method, such as Figure 4 As shown, the adjustment module 40 includes: a first logic unit 41, a first delay unit 42, a second logic unit 43, a second detection unit 44, and a second comparator 45;

[0080] The second detection unit 44 is electrically connected to the output terminal of the power supply 10 and the first terminal of the second comparator 45 respectively. The second terminal of the second comparator 45 is used to receive the second reference electrical signal, namely the LPM PRE-OC REF voltage. The third terminal of the second comparator 45 is electrically connected to the first terminal of the first logic unit 41.

[0081] The second terminal of the first logic unit 41 is electrically connected to the first terminal of the first delay unit 42 and the first terminal of the second logic unit 43, respectively. The second terminal of the first delay unit 42 is electrically connected to the second terminal of the second logic unit 43. The third terminal of the second logic unit 43 is electrically connected to the register unit 30.

[0082] Specifically, when the output signal of power supply 10 is greater than the second reference electrical signal, the third terminal of the second comparator 45 outputs a third signal; when the output signal of power supply 10 is less than or equal to the second reference electrical signal, the third terminal of the second comparator 45 outputs a fourth signal.

[0083] When the first logic unit 41 receives the third signal, the first logic unit 41 transmits a first intermediate signal to the first delay unit 42 and the second logic unit 43. After receiving the first intermediate signal and delaying for a first duration, the first delay unit 42 outputs a second intermediate signal. The second logic unit 43 outputs the second signal based on the received first intermediate signal and the second intermediate signal.

[0084] When the first logic unit 41 receives the fourth signal, the first logic unit 41 transmits the third intermediate signal to the first delay unit 42 and the second logic unit 43. After receiving the third intermediate signal and delaying for a first duration, the first delay unit 42 outputs the fourth intermediate signal. The second logic unit 43 outputs the first signal based on the received third intermediate signal and the fourth intermediate signal.

[0085] Wherein, the first duration is shorter than the delay duration of the trigger power protection mechanism of the LPM power protection module 20, and / or the preset threshold value is less than the judgment threshold of the LPM power protection module 20.

[0086] The judgment threshold of the LPM power protection module 20 is the same as the value of the first reference electrical signal. The delay duration of the LPM power protection module's trigger power protection mechanism can be equal to the delay duration of the second delay unit 23.

[0087] In some implementations, the first logic unit 41 can be set to an initial state so that the initial state of the identifier of the first bit in the register unit 30 can be controlled by setting the initial state of the first logic unit 41. For example, the user can adjust the default working state of the power supply after each power-on by setting the software. The initial state of the first logic unit 41 can be to output a low-level signal, that is, the first logic unit 41 outputs a low-level signal each time it is powered on, so that the first delay unit 42 and the second logic unit 43 output a low-level signal, that is, the first signal, to the register unit 30. At this time, the register unit 30 does not change the identifier of the first bit. In this way, the initial state of the identifier of the first bit in the register unit 30 is not affected by the adjustment module 40.

[0088] In some implementations, the second reference signal may be less than the first reference signal. In this case, the adjustment module 40 independently determines whether an OC event may be triggered, and the threshold for the adjustment module 40 to determine whether an OC event may be triggered is lower than the threshold for the LPM power protection module 20 to determine whether an OC event may be triggered. In this way, the adjustment module 40 can switch to NPM in advance before the LPM power protection module 20 actually triggers an OC event.

[0089] In other embodiments, the second reference signal can be equal to the first reference signal, and the first duration is shorter than the OC dejitter duration of the LPM power protection module 20. For example, the OC dejitter duration of the LPM power protection module 20 is 32μs, and the first duration is 2μs, so that there is an order of magnitude time difference between the first duration and the OC dejitter duration of the LPM power protection module 20. In this way, the adjustment module 40 independently determines whether an OC event may be triggered, although the threshold for the adjustment module 40 to determine whether an OC event may be triggered is the same as that for the LPM power protection module 20. However, the delay for the adjustment module 40 to determine whether an OC event may be triggered is shorter, allowing the adjustment module 40 to switch to NPM in advance before the LPM power protection module 20 actually triggers an OC event.

[0090] In some embodiments, the second reference signal may be smaller than the first reference signal, and the first duration may be shorter than the OC de-jitter duration of the LPM power protection module 20. In this case, the threshold for the adjustment module 40 to determine whether an OC event may be triggered is lower than the threshold for the LPM power protection module 20 to determine whether an OC event may be triggered, and the delay for the adjustment module 40 to determine whether an OC event may be triggered is shorter. In this way, the adjustment module 40 can more reliably switch to NPM before the LPM power protection module 20 actually triggers an OC event.

[0091] Method 2: The LPM power protection module 20 has a logic unit for determining whether an OC event is triggered. In order to prevent accidental or frequent triggering of OC events, the LPM power protection module 20 will wait for a period of time after detecting a possible OC event, i.e., after the OC debouncing time, before actually triggering the OCP. Based on this principle, the first end of the adjustment module 40 can be connected to the logic unit in the LPM power protection module 20 for determining whether an OC event is triggered, so as to reuse the logic unit in the LPM power protection module 20 for determining whether an OC event may occur. If the determination result is that an OC event may occur, the adjustment module 40 will adjust the first bit in the register unit 30 to the second flag before the OC debouncing time of the LPM power protection module 20, so as to adjust the power supply 10 to NPM before the LPM power protection module 20 actually triggers the OCP.

[0092] As an optional implementation method, such as Figure 2 or Figure 3 As shown, the adjustment module 40 includes: a first logic unit 41, a first delay unit 42, and a second logic unit 43;

[0093] The first terminal of the first logic unit 41 is used to receive the third signal or the fourth signal. The second terminal of the first logic unit 41 is electrically connected to the first terminal of the first delay unit 42 and the first terminal of the second logic unit 43, respectively. The second terminal of the first delay unit 42 is electrically connected to the second terminal of the second logic unit 43. The third terminal of the second logic unit 43 is electrically connected to the register unit 30.

[0094] The third signal and the fourth signal are related to the output signal of the power supply 10, and the third signal is used to indicate that the output signal of the power supply 10 is greater than a preset threshold value, and the fourth signal is used to indicate that the output signal of the power supply 10 is less than or equal to the preset threshold value.

[0095] When the first logic unit 41 receives the third signal, the first logic unit 41 transmits a first intermediate signal to the first delay unit 42 and the second logic unit 43. After receiving the first intermediate signal and delaying for a first duration, the first delay unit 42 outputs a second intermediate signal. The second logic unit 43 outputs the second signal based on the received first intermediate signal and the second intermediate signal.

[0096] When the first logic unit 41 receives the fourth signal, the first logic unit 41 transmits the third intermediate signal to the first delay unit 42 and the second logic unit 43. After receiving the third intermediate signal and delaying for a first duration, the first delay unit 42 outputs the fourth intermediate signal. The second logic unit 43 outputs the first signal based on the received third intermediate signal and the fourth intermediate signal.

[0097] The first duration is shorter than the OC dejitter duration of the LPM power protection module 20.

[0098] In some implementations, the third and fourth signals may come from the LPM power protection module 20. For example, when the LPM power protection module 20 determines that the output signal of the power supply 10 is greater than or equal to the first reference electrical signal, it inputs the third signal to the first terminal of the first logic unit 41 before waiting for the OC dejittering time; when the LPM power protection module 20 determines that the output signal of the power supply 10 is less than the first reference electrical signal, it inputs the fourth signal to the first terminal of the first logic unit 41.

[0099] As an optional implementation, the preset threshold value is the same as the value of the first reference electrical signal; the first terminal of the first logic unit 41 is electrically connected to the third terminal of the first comparator 22;

[0100] Specifically, when the output signal of the power supply 10 is greater than the first reference electrical signal, the third terminal of the first comparator 22 outputs the third signal; when the output signal of the power supply 10 is less than or equal to the first reference electrical signal, the third terminal of the first comparator 22 outputs the fourth signal.

[0101] In this embodiment, the logic unit in the LPM power protection module 20 that determines whether an OC event is triggered can be reused to determine whether an OC event may occur. The first duration of the first delay unit 42 is shorter than the OC dejitter duration of the LPM power protection module 20. In this way, if the determination result is that an OC event may occur, the adjustment module 40 can adjust the first bit in the register unit 30 to the second flag before the OC dejitter duration of the LPM power protection module 20, so as to adjust the power supply 10 to NPM before the LPM power protection module 20 actually triggers the OCP.

[0102] It should be noted that in the embodiments of this application, the third signal can be a high-level signal and the fourth signal can be a low-level signal. The first logic unit 41 receiving the third signal can be the first logic unit 41 receiving a high-level signal. The first logic unit 41 receiving the fourth signal can be the first logic unit 41 receiving a low-level signal or not receiving a high-level signal. If no level signal is obtained, that is, the obtained level signal is 0.

[0103] like Figure 2 , Figure 3 and Figure 4In the illustrated embodiment, the adjustment module 40 adjusts the identifier of the first bit in the register unit 30 based on whether the output signal of the power supply 10 will trigger the OC event of the LPM power protection module 20. That is, if the output signal of the power supply 10 will trigger the OC event of the LPM power protection module, the identifier of the first bit in the register unit 30 is adjusted to the second identifier in advance, so as to switch the power supply to NPM before the LPM power protection module 20 triggers the OC event.

[0104] In other embodiments, the adjustment module 40 may also adjust the identifier of the first bit in the register unit 30 based on information such as the number and / or probability of the LPM power protection module 20 triggering OC events. For example, if the number of times the LPM power protection module 20 triggers OC events reaches a preset number or the number of times the LPM power protection module 20 adds OC events within a specified time reaches a preset number, the adjustment module 40 may adjust the identifier of the first bit in the register unit 30 to the second identifier, thereby limiting the power supply 10 to work under NPM and reducing the probability of subsequent OC events by improving the power supply capacity and load dynamic current response capability of the power supply 10.

[0105] As an optional implementation method, such as Figure 5 As shown, the adjustment module 40 includes:

[0106] The first OC trigger counting unit 46 has its first end electrically connected to the LPM power protection module 20 and its second end electrically connected to the register unit 30.

[0107] The first OC trigger counting unit 46 is used to count the number of times the LPM power protection module 20 triggers an OC event. When the count value of the first OC trigger counting unit 46 is greater than or equal to a first preset value, the first OC trigger counting unit 46 transmits the second signal to the register unit 30; when the count value of the first OC trigger counting unit 46 is less than the first preset value, the first OC trigger counting unit 46 transmits the first signal to the register unit 30.

[0108] In some implementations, the second end of the first OC trigger counting unit 46 may be directly or indirectly connected to the register unit 30.

[0109] Where the second end of the first OC trigger counting unit 46 can be directly electrically connected to the register unit 30, the first OC trigger counting unit 46 can rewrite the identifier of the first bit in the register unit 30 by transmitting hardware signals to the register unit 30.

[0110] Of course, the second end of the first OC trigger counting unit 46 can be connected to the register unit 30 or indirectly, such as by connecting the second end of the first OC trigger counting unit 46 to the register unit 30 through other logic units or processors, so that the count value of the first OC trigger counting unit 46 can be used as the basis for other logic units or processors to rewrite the identifier of the first bit in the register unit 30.

[0111] In some implementations, the first signal may be a low-level signal or a non-overflow signal output by the first OC trigger counting unit 46, or the first signal may be a "0" signal, that is, the first OC trigger counting unit 46 has no output signal. In this case, the identifier of the first bit in the register unit 30 remains unchanged.

[0112] In some implementations, the first preset value may be the upper limit of the count of the first OC trigger counting unit 46. That is, when the count of the first OC trigger counting unit 46 reaches the upper limit, an overflow signal is sent to the register unit 30 so that the register unit 30 adjusts the identifier of the first bit in the register unit 30 to the second identifier based on the received overflow signal. At this time, the second signal is the overflow signal when the first OC trigger counting unit 46 reaches the upper limit.

[0113] In this embodiment, the first OC trigger counting unit 46 counts the number of times the LPM power protection module 20 triggers OC events, and the hardware signal when the counting result is greater than the first preset value is used to rewrite the identifier of the first bit in the register unit 30 to the second identifier.

[0114] As an optional implementation method, such as Figure 6 As shown, the adjustment module 40 includes:

[0115] The second OC trigger counting unit 47 has its first end electrically connected to the LPM power protection module 20. The second OC trigger counting unit 47 is used to count the number of times the LPM power protection module 20 triggers an OC event.

[0116] The power control circuit also includes: a processor 60;

[0117] The processor 60 is used to read the count value of the second OC trigger counting unit 47, and when the count value of the second OC trigger counting unit 47 is greater than or equal to the second preset value, the processor 60 controls the first bit in the register unit 30 to be the second identifier; when the count value of the second OC trigger counting unit 47 is less than the second preset value, the identifier of the first bit in the register unit 30 remains unchanged.

[0118] In some implementations, the processor 60 can be connected to the second OC trigger counter unit 47 and the register unit 30 via an SPMI interface, respectively. The processor 60 reads the count value of the second OC trigger counter unit 47 through the SPMI interface connected to the second OC trigger counter unit 47, and compares the count value with a second preset value. If the count value is determined to be greater than or equal to the second preset value, the processor 60 rewrites the first bit in the register unit 30 to the second identifier through the SPMI interface connected to the register unit 30; otherwise, the processor 60 does not write the identifier of the first bit in the register unit 30.

[0119] In some implementations, the second preset value is pre-stored in the processor 60, for example, it can be pre-stored in the processor 60 by means of factory pre-configuration or user dynamic setting.

[0120] It should be noted that the second OC trigger counting unit 47 is used to count the number of times the LPM power protection module 20 triggers an OC event. That is, whenever the LPM power protection module 20 triggers an OC event, the count value of the second OC trigger counting unit 47 is incremented by 1 until the upper limit of the count of the second OC trigger counting unit 47 is reached.

[0121] In some implementations, after the second OC trigger counting unit 47 reaches the upper limit of the count, the count of the second OC trigger counting unit 47 can be cleared to restart the counting.

[0122] In other embodiments, after the count value of the second OC trigger counting unit 47 reaches the second preset value, the processor 60 can, based on the count value read from the second OC trigger counting unit 47 reaching the second preset value, rewrite the first bit in the register unit 30 to the second identifier, and at the same time clear the count value of the second OC trigger counting unit 47 to zero, so that the second OC trigger counting unit 47 can start counting again.

[0123] It should be noted that in some embodiments, the processor 60 can also perform more complex logic processing on the count value read by the second OC trigger counting unit 47, and in addition to rewriting the identifier of the first bit in the register unit 30, the processor 60 can also adjust the parameters in the LPM power protection module 20 and the adjustment module 40.

[0124] For example, the processor 60 sets three thresholds from small to large: the first threshold, the second threshold, and the third threshold. When the count value of the second OC trigger counting unit 47 is greater than or equal to the first threshold and less than the second threshold, the judgment threshold of the LPM power protection module 20, i.e., the first reference electrical signal, is increased. When the count value of the second OC trigger counting unit 47 is greater than or equal to the second threshold and less than the third threshold, the de-jittering duration of the LPM power protection module 20, i.e., the delay duration of the second delay unit 23, is increased. When the count value of the second OC trigger counting unit 47 is greater than or equal to all three thresholds, the judgment threshold and de-jittering duration of the LPM power protection module 20 are restored to their initial state, and the first bit in the register unit 30 is adjusted to the second identifier.

[0125] In this embodiment, the processor 60 performs software control on the identifier of the first bit in the register unit 30 according to the output signal of the adjustment module 40. Its response speed is slower than that of the previous embodiment, which adjusts the identifier of the first bit in the register unit 30 according to the logic state of the adjustment module 40.

[0126] It is worth noting that when the LPM power protection module 20 triggers an OC event, the third logic unit 24 transmits a high-level signal to the LPM OC flag register unit 25 to set the LPM OC flag in the LPM OC flag register unit 25 to "1". Based on this principle, the OC trigger counting unit in this embodiment, namely the first OC trigger counting unit 46 or the second OC trigger counting unit 47, can be electrically connected to the third logic unit 24 so that when the third logic unit 24 outputs a high level, the count of the first OC trigger counting unit 46 or the second OC trigger counting unit 47 is incremented by 1.

[0127] In other embodiments, when the LPM power protection module 20 triggers an OC event, the OC flag bit in the LPM OC flag register unit 25 is "1". Based on this principle, the OC trigger counting unit in this embodiment, namely the first OC trigger counting unit 46 or the second OC trigger counting unit 47, can be electrically connected to the LPM OC flag register unit 25 so that when the OC flag bit in the LPM OC flag register unit 25 changes from "0" to "1", the count of the first OC trigger counting unit 46 or the second OC trigger counting unit 47 is incremented by 1.

[0128] In some embodiments, when the LPM power protection module 20 triggers an OC event, the first OC response unit 26 will turn off the power or shut down directly. Based on this principle, the OC trigger counting unit in this embodiment, namely the first OC trigger counting unit 46 or the second OC trigger counting unit 47, can also be electrically connected to the first OC response unit 26, or used to be electrically connected to the output terminal of the power supply 10, so that the count of the first OC trigger counting unit 46 or the second OC trigger counting unit 47 is incremented by 1 each time the first OC response unit 26 turns off the power or shuts down.

[0129] It is worth noting that in related technologies, whenever the power supply triggers an OC or "Power Good" (PG) anomaly protection mechanism, the power supply and PMIC are shut down. Furthermore, the current OC event / PG anomaly event can only be recorded once; multiple recordings of the power supply's OC / PG anomaly events are not possible. This is because the event is reset to zero after a single trigger. This reset occurs when the system restarts, executing a default code preset state, which resets all hardware configuration parameters to the default code state, making it impossible to recognize historical anomalies. However, in this embodiment, by adding a first OC trigger counting unit 46 or a second OC trigger counting unit 47, the number of triggers for both the current and historical OC events can be recorded.

[0130] It should be noted that cases of OC (Overclocking) reported in practical applications are usually sporadic and non-reproducible, and are abnormal situations that are triggered only when multiple conditions are combined in a specific user scenario. In this embodiment, the power supply 10 can be restricted to NPM (Non-Period Power) after the number of OC events has accumulated to a certain number. Compared with the previous embodiment, which switched the power supply 10 to NPM in advance every time it was predicted that the power supply 10 would trigger an OC event under LPM, this can reduce the power consumption waste caused by the power supply 10 continuously working under NPM.

[0131] In this embodiment, when the power supply is in LPM mode, an adjustment module determines whether the power supply is likely to trigger abnormal events, such as OC events and / or PG events, or whether OC events and / or PG events are frequently triggered. Based on this, the module actively adjusts the flag in the first bit of the register unit to switch the power supply to NPM before an OC event and / or PG event is triggered, or to restrict the power supply to NPM if OC events and / or PG events are frequently triggered. This reduces the probability of the power supply triggering OC events and / or PG events or frequently triggering OC events and / or PG events in LPM mode, thereby reducing the probability of the power supply system being shut down and the entire system being shut down and restarted due to OCP and / or PG abnormality protection being triggered in LPM mode.

[0132] This application also provides an electronic device, which includes a power supply 10 and the components described in this application. Figures 2 to 6 The power control circuit provided in any of the embodiments.

[0133] In some implementations, the electronic device can be a terminal, or it can be any other device besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television set (TV), ATM, or self-service machine, etc. This application does not specifically limit the scope of the implementation.

[0134] The electronic device provided in this application embodiment utilizes, as... Figures 2 to 6 The power control circuit provided in any embodiment controls the power supply 10 to be in LPM or NPM mode, which can reduce the probability of the power supply system being shut down and the entire system being shut down and restarted due to the protection mechanism that triggers power abnormality events in LPM mode. It has the same characteristics as... Figures 2 to 6 The power control circuit provided in any of the embodiments has the same beneficial effects, and will not be repeated here to avoid repetition.

[0135] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0136] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A power supply control circuit, characterized in that, The power control circuit, used to control the power supply to operate in either low-power mode (LPM) or normal-power mode (NPM), includes: The LPM power protection module is electrically connected to the output terminal of the power supply and determines whether a power abnormality event is triggered based on the output signal of the power supply when the power supply is in the LPM state. A register unit is provided for connection to the power supply. A first bit in the register unit includes a first identifier or a second identifier, wherein the first identifier is used to control the power supply to be in the LPM mode; and the second identifier is used to control the power supply to be in the NPM mode. An adjustment module, wherein a first end of the adjustment module is electrically connected to at least one of the output terminal of the power supply and the LPM power protection module, and a second end of the adjustment module is connected to the register unit; if the adjustment module determines that a power abnormality event may be triggered based on the target signal, it adjusts the first bit in the register unit to the second identifier before triggering the power abnormality event; or, if the adjustment module determines that a power abnormality event is frequently triggered based on the target signal, it adjusts the first bit in the register unit to the second identifier. The target signal includes at least one of the following: the output signal of the power supply and the signal in the LPM power protection module.

2. The power control circuit according to claim 1, characterized in that, The adjustment module is used to transmit a first signal or a second signal to the register unit according to the target signal; When the adjustment module transmits the first signal to the register unit, the identifier of the first bit in the register unit remains unchanged; when the adjustment module transmits the second signal to the register unit, the register unit adjusts the first bit to the second identifier in response to the second signal.

3. The power control circuit according to claim 2, characterized in that, The adjustment module includes: a first logic unit, a first delay unit, and a second logic unit; The first terminal of the first logic unit is used to receive a third signal or a fourth signal. The second terminal of the first logic unit is electrically connected to the first terminal of the first delay unit and the first terminal of the second logic unit, respectively. The second terminal of the first delay unit is electrically connected to the second terminal of the second logic unit. The third terminal of the second logic unit is electrically connected to the register unit. The third signal and the fourth signal are related to the output signal of the power supply, and the third signal is used to indicate that the output signal of the power supply is greater than a preset threshold value, and the fourth signal is used to indicate that the output signal of the power supply is less than or equal to the preset threshold value. When the first logic unit receives the third signal, the first logic unit transmits a first intermediate signal to the first delay unit and the second logic unit. After receiving the first intermediate signal and delaying for a first duration, the first delay unit outputs a second intermediate signal. The second logic unit outputs the second signal based on the received first intermediate signal and the second intermediate signal. When the first logic unit receives the fourth signal, the first logic unit transmits a third intermediate signal to the first delay unit and the second logic unit. After receiving the third intermediate signal and delaying for a first duration, the first delay unit outputs the fourth intermediate signal. The second logic unit outputs the first signal based on the received third intermediate signal and the fourth intermediate signal. Wherein, the first duration is shorter than the delay duration of the power protection mechanism triggered by the LPM power protection module, and / or the preset threshold value is less than the judgment threshold of the LPM power protection module.

4. The power control circuit according to claim 3, characterized in that, The LPM power protection module includes: a first detection unit, a first comparator, a second delay unit, a third logic unit, an LPM OC flag register unit, and a first OC response unit; The first detection unit is electrically connected to the output terminal of the power supply and the first terminal of the first comparator, respectively. The second terminal of the first comparator is used to receive a first reference electrical signal. The third terminal of the first comparator is electrically connected to the first terminal of the third logic unit and the first terminal of the second delay unit, respectively. The second terminal of the second delay unit is electrically connected to the second terminal of the third logic unit. The third terminal of the third logic unit is electrically connected to the first terminal of the LPM OC flag register unit. The first OC response unit is electrically connected to the second terminal of the LPM OC flag register unit. The delay duration of the LPM overcurrent protection module triggering the power protection mechanism is the same as the delay duration of the second delay unit, and the judgment threshold of the LPM overcurrent protection module is the same as the value of the first reference electrical signal.

5. The power control circuit according to claim 4, characterized in that, The preset threshold value is the same as the value of the first reference electrical signal; the first terminal of the first logic unit is electrically connected to the third terminal of the first comparator; Specifically, when the output signal of the power supply is greater than the first reference electrical signal, the third terminal of the first comparator outputs the third signal; when the output signal of the power supply is less than or equal to the first reference electrical signal, the third terminal of the first comparator outputs the fourth signal.

6. The power control circuit according to claim 4, characterized in that, The adjustment module further includes: a second detection unit and a second comparator; The second detection unit is electrically connected to the output terminal of the power supply and the first terminal of the second comparator, respectively. The second terminal of the second comparator is used to receive the second reference electrical signal, and the third terminal of the second comparator is electrically connected to the first terminal of the first logic unit. Wherein, the preset threshold value is the second reference electrical signal; when the output signal of the power supply is greater than the second reference electrical signal, the third terminal of the second comparator outputs the third signal; when the output signal of the power supply is less than or equal to the second reference electrical signal, the third terminal of the second comparator outputs the fourth signal.

7. The power control circuit according to claim 6, characterized in that, The second reference electrical signal is less than or equal to the first reference electrical signal.

8. The power control circuit according to claim 2, characterized in that, The adjustment module includes: A first OC trigger counting unit, the first end of the first OC trigger counting unit is electrically connected to the LPM power protection module, and the second end of the first OC trigger counting unit is electrically connected to the register unit; The first OC trigger counting unit is used to count the number of times the LPM overcurrent protection module triggers an OC event. When the count value of the first OC trigger counting unit is greater than or equal to a first preset value, the first OC trigger counting unit transmits the second signal to the register unit; when the count value of the first OC trigger counting unit is less than the first preset value, the first OC trigger counting unit transmits the first signal to the register unit.

9. The power control circuit according to claim 1, characterized in that, The adjustment module includes: The second OC trigger counting unit has its first terminal electrically connected to the LPM power protection module. The second OC trigger counting unit is used to count the number of times the LPM overcurrent protection module triggers an OC event. The power control circuit further includes: a processor; The processor is used to read the count value of the second OC trigger counter unit, and when the count value of the second OC trigger counter unit is greater than or equal to a second preset value, the processor controls the first bit in the register unit to be the second identifier; when the count value of the second OC trigger counter unit is less than the second preset value, the identifier of the first bit in the register unit remains unchanged.

10. The power control circuit according to claim 8, characterized in that, The LPM overcurrent protection module includes: a first detection unit, a first comparator, a second delay unit, a third logic unit, an LPM OC flag register unit, and a first OC response unit; The first detection unit is electrically connected to the output terminal of the power supply and the first terminal of the first comparator, respectively. The second terminal of the first comparator is used to receive the first reference electrical signal. The third terminal of the first comparator is electrically connected to the first terminal of the third logic unit and the first terminal of the second delay unit, respectively. The second terminal of the second delay unit is electrically connected to the second terminal of the third logic unit. The third terminal of the third logic unit is electrically connected to the first terminal of the LPM OC flag register unit. The first OC response unit is electrically connected to the second terminal of the LPM OC flag register unit. The first OC trigger counting unit is electrically connected to the third terminal of the third logic unit.

11. The power control circuit according to claim 9, characterized in that, The LPM overcurrent protection module includes: a first detection unit, a first comparator, a second delay unit, a third logic unit, an LPM OC flag register unit, and a first OC response unit; The first detection unit is electrically connected to the output terminal of the power supply and the first terminal of the first comparator, respectively. The second terminal of the first comparator is used to receive the first reference electrical signal. The third terminal of the first comparator is electrically connected to the first terminal of the third logic unit and the first terminal of the second delay unit, respectively. The second terminal of the second delay unit is electrically connected to the second terminal of the third logic unit. The third terminal of the third logic unit is electrically connected to the first terminal of the LPM OC flag register unit. The first OC response unit is electrically connected to the second terminal of the LPM OC flag register unit. The second OC trigger counting unit is electrically connected to the third terminal of the third logic unit.

12. An electronic device, characterized in that, include: The power supply and the power control circuit as described in any one of claims 1 to 11.

Images