Multi-source energy collection circuit and power system

Abstract

The invention discloses a multi-source energy collection circuit and an electric power system, the multi-source energy collection circuit is used for being connected with a temperature difference thermal battery and a photovoltaic battery, and the collection circuit comprises a first switch tube, a second switch tube and a power level sub-circuit; the drain electrode of the first switch tube is connected with the temperature difference thermal battery; the drain electrode of the second switch tube is connected with the photovoltaic cell; the first input end of the power stage sub-circuit is connected with the source electrode of the first switch tube; the first input end of the power stage sub-circuit is connected with the source electrode of the second switch tube; the grid electrode of the first switch tube and the grid electrode of the second switch tube are connected with a sampling control signal. The circuit can be widely applied to the technical field of electronic circuits.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to a multi-source energy harvesting circuit and a power system. Background Art

[0002] With the rapid development of the Internet of Things (IoT) and wireless sensor nodes (WSN) in various fields, integrated circuit design faces an increasing demand for low power consumption and high efficiency. Traditional batteries have limitations in providing stable power supply, especially in remote or difficult-to-reach areas. The difficulty of battery replacement and charging makes the continuous operation of equipment challenging. Therefore, energy harvesting technology has gradually become a viable solution. The diversity of renewable energy provides a wealth of options for energy harvesting, including thermal energy, light energy, and piezoelectric energy. These energy sources can be effectively converted into electrical energy through corresponding transducers. For example, thermal energy generators (TEGs) are used to convert thermal energy into electrical energy, while photovoltaic generators (PVs) are used to convert light energy into electrical energy. Although the feasibility of single-source energy harvesting systems has been fully verified, reliance on a single energy source may lead to short-term interruptions in power supply due to the inherent instability of ambient energy. Therefore, there are still technical problems that need to be solved in related technologies. Summary of the invention

[0003] The purpose of this application is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] To this end, an object of an embodiment of the present application is to provide a multi-source energy collection circuit and power system, which can improve energy conversion efficiency.

[0005] In order to achieve the above-mentioned technical objectives, the technical solution adopted in the embodiments of the present application includes: a multi-source energy collection circuit for connecting to a thermoelectric cell and a photovoltaic cell, the collection circuit including: a first switch tube, a second switch tube and a power stage sub-circuit; the drain of the first switch tube is connected to the thermoelectric cell; the drain of the second switch tube is connected to the photovoltaic cell; the first input end of the power stage sub-circuit is connected to the source of the first switch tube; the first input end of the power stage sub-circuit is connected to the source of the second switch tube; the gate of the first switch tube and the gate of the second switch tube are connected to the sampling control signal.

[0006] In addition, a multi-source energy harvesting circuit according to the above embodiment of the present invention may also have the following additional technical features:

[0007] Furthermore, in an embodiment of the present application, the multi-source energy collection circuit also includes a logic control module; the logic control module is connected to the power stage subcircuit.

[0008] Further, in the embodiment of the present application, the power stage subcircuit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, a first capacitor, a second capacitor, a third capacitor, a first inductor and an energy storage device;

[0009] One end of the first capacitor and the drain of the fifth field effect transistor are connected to the source of the second switch tube;

[0010] The drain of the first field effect transistor, the drain of the third field effect transistor and the drain of the fourth field effect transistor are connected to the other end of the first capacitor;

[0011] One end of the second capacitor, the source of the first field effect transistor and the drain of the second field effect transistor are connected to the source of the first switch transistor;

[0012] The source of the fifth field effect transistor, the source of the second field effect transistor, the drain of the sixth field effect transistor and the source of the seventh field effect transistor are connected to one end of the first inductor;

[0013] The source of the third field effect transistor, the drain of the seventh field effect transistor and the drain of the ninth field effect transistor are connected to one end of the third capacitor;

[0014] The drain of the eighth field effect transistor, the source of the ninth field effect transistor, and the source of the tenth field effect transistor are connected to the other end of the first inductor;

[0015] The drain of the tenth field effect transistor is connected to one end of the energy storage device;

[0016] The other end of the energy storage device, the other end of the second capacitor, the source of the fourth field effect transistor, the source of the sixth field effect transistor, the source of the eighth field effect transistor and the other end of the third capacitor are all grounded;

[0017] The gate of the first field effect transistor, the gate of the second field effect transistor, the gate of the third field effect transistor, the gate of the fourth field effect transistor, the gate of the fifth field effect transistor, the gate of the sixth field effect transistor, the gate of the seventh field effect transistor, the gate of the eighth field effect transistor, the gate of the ninth field effect transistor, and the gate of the tenth field effect transistor are connected to the logic control module.

[0018] Furthermore, in an embodiment of the present application, the energy storage device is a capacitor.

[0019] Furthermore, in an embodiment of the present application, the logic control module includes a zero-crossing comparator, a mode selector, an output voltage detector, a clock generator, a pulse width modulator, a sampling signal generator, a driver, and a sampling comparator; the zero-crossing comparator, the mode selector, the sampling signal generator, and the pulse width modulator are connected to the driver; the driver is connected to the power stage sub-circuit; the output voltage detector, the sampling comparator, the pulse width modulator, and the clock generator are connected to the mode selector.

[0020] Further, in the embodiment of the present application, the sampling signal generator includes a fourth capacitor, a first counter, a trigger, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate and a first NOR gate;

[0021] The input end of the first counter is connected to the driver; the output end of the first counter is connected to the clock end of the trigger;

[0022] The first input terminal of the trigger is connected to an external signal; the second input terminal of the trigger is connected to the output terminal of the third NOT gate; the input terminal of the third NOT gate is connected to the driver;

[0023] The output end of the trigger is connected to the input end of the first NOT gate; the first input end of the first NOR gate and the input end of the second NOT gate are connected to the output end of the first NOT gate;

[0024] The output end of the second NOT gate and one end of the fourth capacitor are connected to the second input end of the first NOR gate; the input end of the fourth NOT gate is connected to the output end of the first NOR gate; the input end of the fourth NOT gate serves as the output end of the sampling signal generator.

[0025] Further, in the embodiment of the present application, the pulse width modulator includes a fifth AND gate, a coarse adjustment module, a fine adjustment module and a modulation module;

[0026] The coarse adjustment module and the fine adjustment module are connected to the modulation module; the modulation module and the first enable signal are connected to the fifth AND gate; and the output end of the fifth AND gate is connected to the driver.

[0027] Further, in the embodiment of the present application, the coarse adjustment module includes a first OR gate, a fifth NOT gate, a reset signal detector and a second counter;

[0028] A second enable signal is connected to the first input terminal of the first OR gate, and a third enable signal is connected to the second input terminal of the first OR gate;

[0029] The input end of the fifth NOT gate and the first input end of the reset signal detector are connected to the output end of the first OR gate; the output end of the fifth NOT gate is connected to the second input end of the reset signal detector; the third input end of the reset signal detector is connected to the second signal;

[0030] The output end of the reset signal detector is connected to the input end of the second counter; and the output end of the second counter is connected to the modulation module.

[0031] Further, in an embodiment of the present application, the fine adjustment module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a first operational amplifier, a second operational amplifier, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a second OR gate, a third OR gate, and a first register;

[0032] One end of the first resistor is connected to the first voltage signal; one end of the second resistor is connected to the second voltage signal, one end of the third resistor is connected to the third voltage signal, and one end of the fourth resistor is connected to the fourth voltage signal;

[0033] The other end of the first resistor and one end of the fifth capacitor are connected to the non-inverting input terminal of the first operational amplifier; the other end of the second resistor and one end of the sixth capacitor are connected to the inverting input terminal of the first operational amplifier;

[0034] The other end of the third resistor and one end of the seventh capacitor are connected to the non-inverting input terminal of the second operational amplifier; the other end of the fourth resistor and one end of the eighth capacitor are connected to the inverting input terminal of the second operational amplifier;

[0035] The first output terminal of the first operational amplifier is connected to the first input terminal of the first AND gate; the second input terminal of the first AND gate is connected to the second enable signal;

[0036] The first output terminal of the second operational amplifier is connected to the first input terminal of the third AND gate; the second input terminal of the third AND gate is connected to the third enable signal;

[0037] The second output terminal of the first operational amplifier is connected to the first input terminal of the second AND gate; the second input terminal of the second AND gate is connected to the second enable signal;

[0038] The second output terminal of the second operational amplifier is connected to the first input terminal of the fourth AND gate; the second input terminal of the fourth AND gate is connected to the third enable signal;

[0039] The output end of the second AND gate is connected to the first input end of the second OR gate; the output end of the third AND gate is connected to the first input end of the third OR gate; the second input end of the second OR gate is connected to the fourth enable signal; the second input end of the third OR gate is connected to the fifth enable signal;

[0040] The output end of the second OR gate and the output end of the third OR gate are connected to the first register; the output end of the first register is connected to the modulation module; the other end of the fifth capacitor, the other end of the sixth capacitor, the other end of the seventh capacitor and the other end of the eighth capacitor are all grounded.

[0041] In addition, the present application also provides a power system, including the multi-source energy collection circuit described above.

[0042] The advantages and benefits of the present application will be partially given in the following description, and partially become apparent from the following description, or be understood through the practice of the present application:

[0043] The collection circuit of the present application includes: a first switch tube, a second switch tube and a power stage subcircuit; the drain of the first switch tube is connected to the thermoelectric battery; the drain of the second switch tube is connected to the photovoltaic cell; the first input end of the power stage subcircuit is connected to the source of the first switch tube; the first input end of the power stage subcircuit is connected to the source of the second switch tube; the gate of the first switch tube and the gate of the second switch tube are connected to the sampling control signal. The present application extracts the energy of the thermoelectric battery and the photovoltaic cell synchronously by combining the thermoelectric battery and the photovoltaic cell with the switch tube and the power stage subcircuit. On the basis of reducing the output ripple and improving the tracking efficiency, the energy conversion efficiency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the circuit structure of a multi-source energy harvesting circuit in a specific embodiment of the present invention;

[0045] Figure 2 A schematic diagram of the circuit structure of a multi-source energy harvesting circuit in another specific embodiment of the present invention;

[0046] Figure 3 A schematic diagram of a logic control module in a specific embodiment of the present invention;

[0047] Figure 4 A schematic diagram of the circuit structure of a sampling signal generator in a specific embodiment of the present invention;

[0048] Figure 5 The figure is a schematic diagram of the circuit structure of a pulse width modulator in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0049] The embodiments of the present invention are described in detail below with reference to the accompanying drawings to illustrate the principles and processes of the multi-source energy harvesting circuit and the power system in the embodiments of the present invention.

[0050] Reference Figure 1 , the present application provides a multi-source energy harvesting circuit and a power system. Figure 1 The present application provides a multi-source energy collection circuit. The circuit can be used to connect with a thermoelectric cell and a photovoltaic cell. The circuit may include: a first switch tube M N1 , the second switch tube M N2 And the power stage sub-circuit 1; the first switch tube M N1 The drain of the second switch tube M is connected to the temperature difference thermal battery; N2 The drain of the power stage sub-circuit 1 is connected to the photovoltaic cell; the first input terminal of the power stage sub-circuit 1 is connected to the first switch tube M N1 The first input terminal of the power stage sub-circuit 1 is connected to the source of the second switch tube M N2 The source of the first switch tube M N1 The gate of the second switch tube M N2 The gate and sampling control signal S PV and S TE Connection: First switch tube M N1 It can be a thermal energy sampling switch; the second switch tube M N2 It can be a sampling switch for photovoltaic energy.

[0051] Further, in the embodiments of the present application, refer to Figure 2 The multi-source energy harvesting circuit also includes a logic control module 2 ; the logic control module 2 is connected to the power stage sub-circuit 1 .

[0052] Further, in the embodiments of the present application, refer to Figure 1 The power stage sub-circuit 1 includes a first field effect transistor M N3 , the second field effect tube M N4 , the third field effect tube M N5 , the fourth field effect tube M N6 、Fifth Field Effect Transistor M N7 、The sixth field effect tube M N8 、The seventh field effect tube M N9 , the eighth field effect tube M N10 、Ninth field effect tube M P1 , the tenth field effect tube M P2 , the first capacitor C PV , the second capacitor C TEG , the third capacitor C ST O , a first inductor L and an energy storage device C OUT ;

[0053] The first capacitor C PV One end and the fifth field effect tube M N7 The drain of the second switch tube M N2 The source connection of

[0054] The first field effect tube M N3 The drain of the third field effect tube M N5 The drain of the fourth field effect transistor M N 6 The drain and the first capacitor C PV The other end is connected;

[0055] The second capacitor C TEG One end of the first field effect tube M N3 The source of the second field effect transistor M N4 The drain of the first switch tube M N1 The source connection of

[0056] The fifth field effect tube M N7 The source of the second field effect tube M N4 The source of the sixth field effect tube M N8 The drain of the seventh field effect transistor M N9 The source of is connected to one end of the first inductor L;

[0057] The third field effect tube M N5 The source of the seventh field effect tube M N9 The drain of the ninth field effect transistor MP1 and the third capacitor C STO One end of the connection;

[0058] The eighth field effect tube M N1 0 drain, the ninth field effect tube M P1 The source of the tenth field effect tube M P2 The source of is connected to the other end of the first inductor L;

[0059] The tenth field effect tube M P2 The drain and energy storage device C OUT One end of the connection;

[0060] Energy Storage Devices C OUT The other end of the second capacitor C TEG The other end of the fourth field effect tube M N6 The source of the sixth field effect tube M N8 The source of the eighth field effect tube M N10 The source of the third capacitor C STO The other end of is grounded;

[0061] The first field effect tube M N3The gate of the second field effect tube M N4 The gate of the third field effect tube M N5 The gate of the fourth field effect tube M N6 The gate of the fifth field effect tube M N7 The gate of the sixth field effect tube M N8 The gate of the seventh field effect tube M N9 The gate of the eighth field effect tube M N10 The gate of the ninth field effect tube M P1 The gate of the tenth field effect tube M P2 The gate is connected to the logic control module 2.

[0062] Further, in the embodiments of the present application, refer to Figure 1 , energy storage device C OUT For capacitance.

[0063] Further, in the embodiments of the present application, refer to Figure 3 The logic control module 2 includes a zero-crossing comparator 21, a mode selector 22, an output voltage detector 23, a clock generator 24, a pulse width modulator 25, a sampling signal generator 26, a driver 27, and a sampling comparator 28; the zero-crossing comparator 21, the mode selector 22, the sampling signal generator 26, and the pulse width modulator 25 are connected to the driver 27; the driver 27 is connected to the power stage sub-circuit 1; the output voltage detector 23, the sampling comparator 28, the pulse width modulator 25, and the clock generator 24 are connected to the mode selector 22.

[0064] Further, in the embodiments of the present application, refer to Figure 4 , the sampling signal generator 26 includes a fourth capacitor, a first counter CO1, a trigger D1, a first NOT gate N1, a second NOT gate N2, a third NOT gate N3, a fourth NOT gate N4 and a first NOR gate ON1;

[0065] The input end of the first counter CO1 is connected to the driver 27; the output end of the first counter CO1 is connected to the clock end of the trigger D1;

[0066] The first input terminal of the trigger D1 is connected to the external signal; the second input terminal of the trigger D1 is connected to the output terminal of the third NOT gate N3; the input terminal of the third NOT gate N3 is connected to the driver 27;

[0067] The output end of the trigger D1 is connected to the input end of the first NOT gate N1; the first input end of the first NOR gate ON1 and the input end of the second NOT gate N2 are connected to the output end of the first NOT gate N1;

[0068] The output end of the second NOT gate N2 and one end of the fourth capacitor are connected to the second input end of the first NOR gate ON1; the input end of the fourth NOT gate N4 is connected to the output end of the first NOR gate ON1; the input end of the fourth NOT gate N4 serves as the output end of the sampling signal generator 26.

[0069] Further, in the embodiments of the present application, refer to Figure 5 , the pulse width modulator 25 includes a fifth AND gate AN5, a coarse adjustment module 31, a fine adjustment module 32 and a modulation module 33;

[0070] The coarse adjustment module 31 and the fine adjustment module 32 are connected to the modulation module 33 ; the modulation module 33 and the first enable signal ENIN are connected to the fifth AND gate AN5 ; and the output end of the fifth AND gate AN5 is connected to the driver 27 .

[0071] Further, in the embodiments of the present application, refer to Figure 5 , the coarse adjustment module 31 includes a first OR gate O1, a fifth NOT gate N5, a reset signal detector CE1 and a second counter CO2;

[0072] The second enable signal ENPV is connected to the first input terminal of the first OR gate O1, and the third enable signal EN TEG is connected to the second input terminal of the first OR gate O1;

[0073] The input terminal of the fifth NOT gate N5 and the first input terminal of the reset signal detector CE1 are connected to the output terminal of the first OR gate O1; the output terminal of the fifth NOT gate N5 is connected to the second input terminal of the reset signal detector CE1; the third input terminal of the reset signal detector CE1 is connected to the second signal SIGNAL;

[0074] The output end of the reset signal detector CE1 is connected to the input end of the second counter CO2 ; the output end of the second counter CO2 is connected to the modulation module 33 .

[0075] Further, in the embodiments of the present application, refer to Figure 5 The fine adjustment module 32 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth capacitor C1, a sixth capacitor C2, a seventh capacitor C3, an eighth capacitor C4, a first operational amplifier COM1, a second operational amplifier COM2, a first AND gate AN1, a second AND gate AN2, a third AND gate AN3, a fourth AND gate AN4, a second OR gate O2, a third OR gate O3, and a first register J1;

[0076] One end of the first resistor R1 is connected to the first voltage signal; one end of the second resistor R2 is connected to the second voltage signal, one end of the third resistor R3 is connected to the third voltage signal, and one end of the fourth resistor R4 is connected to the fourth voltage signal;

[0077] The other end of the first resistor R1 and one end of the fifth capacitor C1 are connected to the non-inverting input terminal of the first operational amplifier COM1; the other end of the second resistor R2 and one end of the sixth capacitor C2 are connected to the inverting input terminal of the first operational amplifier COM1;

[0078] The other end of the third resistor R3 and one end of the seventh capacitor C3 are connected to the non-inverting input terminal of the second operational amplifier COM2; the other end of the fourth resistor R4 and one end of the eighth capacitor C4 are connected to the inverting input terminal of the second operational amplifier COM2;

[0079] The first output terminal of the first operational amplifier COM1 is connected to the first input terminal of the first AND gate AN1; the second input terminal of the first AND gate AN1 is connected to the second enable signal EN PV connect;

[0080] The first output terminal of the second operational amplifier COM2 is connected to the first input terminal of the third AND gate AN3; the second input terminal of the third AND gate AN3 is connected to the third enable signal EN TEG connect;

[0081] The second output terminal of the first operational amplifier COM1 is connected to the first input terminal of the second AND gate AN2; the second input terminal of the second AND gate AN2 is connected to the second enable signal EN PV connect;

[0082] The second output terminal of the second operational amplifier COM2 is connected to the first input terminal of the fourth AND gate AN4; the second input terminal of the fourth AND gate AN4 is connected to the third enable signal EN TEG connect;

[0083] The output end of the second AND gate AN2 is connected to the first input end of the second OR gate O2; the output end of the third AND gate AN3 is connected to the first input end of the third OR gate O3; the second input end of the second OR gate O2 is connected to the fourth enable signal DN3; the second input end of the third OR gate O3 is connected to the fifth enable signal UP2;

[0084] The output end of the second OR gate O2 and the output end of the third OR gate O3 are connected to the first register J1; the output end of the first register J1 is connected to the modulation module 33; the other end of the fifth capacitor C1, the other end of the sixth capacitor C2, the other end of the seventh capacitor C3 and the other end of the eighth capacitor C4 are all grounded.

[0085] The specific implementation principle of this application is described below with reference to the accompanying drawings:

[0086] In this embodiment, the thermoelectric cell TEG and the photovoltaic cell PV can be connected to the energy collection circuit. The power stage circuit includes ten transistors as power switches, four off-chip capacitors as input and output capacitors, and an off-chip inductor. The logic control module includes a zero-crossing comparator, an output voltage detector, a mode selector, a clock generator, a pulse width modulator, a sampling signal generator, a digital logic & driving circuit, and a sampling comparator. Figure 1 The zero-crossing comparator is used to detect the synchronization point where the inductor current is discharged to 0. The voltage V on both sides of the inductor L is detected in each cycle. L With energy storage device C OUT The voltage on both sides V OUT (or C STO The voltage on both sides V STO ), thereby avoiding the reverse flow of the inductor current. The sampling comparator finds the maximum power point through the open-circuit voltage method and adjusts the input voltage to make it fluctuate around the maximum power point. The digital logic and drive circuit consists of a digital circuit to generate a drive signal for driving the switch tube. The clock generator consists of a ring oscillator, a frequency divider and a delay device, and the generated clock signal is applied to the system. The mode selector consists of a digital circuit and a dynamic comparator, which is used to dynamically switch the circuit working mode according to the input and output states. The system has three different working modes: dual-input single-output mode (DISO), three-input single-output mode (SISO), and three-phase buck-boost mode (TPBB). There are three switch configurations in the proposed TPBB mode, namely PV forced collection mode mode (PFHM), PV-TEG stacking (PTPB) mode, and PV-CSTO stacking mode (PSPB). The controller dynamically switches between the above modes by identifying the corresponding enable signal to match the load power demand. Under light load conditions, when the output voltage is higher than the upper limit (V REFH ), the system enters DISO mode and stores the excess energy in C STO or skip switching operations to avoid energy waste. REFH ) and lower limit (V REFL ) between, if V CPV 、V CTEG Above the corresponding MPP, the system transfers the extracted energy to the load; if no transducer is available and V STO Greater than the lower limit (V REFS ), the storage capacitor will become part of the input energy to transfer energy to the output; under heavy load conditions, the transducer energy is not enough to fully power the load, and the output voltage is lower than the lower limit (V REFL ), the system works in TPBB mode. In this mode, the system is forced to extract energy from PV (although V CPVIn order to make the load enter the stable voltage range faster, when V CTEG When V is greater than the corresponding MPP, the system collects energy from PV and TEG at the same time; CTEG is less than the corresponding MPP and V STO Greater than the lower limit (V REFS ), the system collects energy from PV and STO simultaneously. If all transducers are unavailable and the output does not require energy, the converter skips operation to avoid energy waste.

[0087] In addition, in order to stabilize the output voltage and improve the conversion efficiency of the system circuit under the premise of maximizing the input power, the power stage circuit adopts series stacking technology. When the load power demand is high and the output voltage is lower than the lower limit of the design value, combined with the input conditions, by connecting PV and TEG (or C STO ) are combined in series stacking to extract PV and TEG (or C STO ) energy. On the basis of reducing output ripple and improving tracking efficiency, the energy conversion efficiency is improved to a certain extent.

[0088] In order to maximize the input power, the power stage circuit uses a pulse width modulator, see Figure 2 . A dual modulation technique combining coarse and fine tuning is used to effectively track the source internal resistance. Coarse tuning of one cycle is achieved by an enable signal 4-bit counter, and after the coarse tuning is completed, the static comparator and register perform fine tuning. Therefore, the duty cycle can be calibrated after several cycles to obtain maximum energy. The coarse tuning end signal is generated by a detector, which consists of two D flip-flops. When UP or DN changes, the detector can sense this transition and set the signal set to a high level. In fine tuning, the static comparator controls two registers so that increments and decrements can be detected. One register increases the duty cycle with Q<3:0>, while the other register decreases the duty cycle with Q<7:0>. This ultimately generates a turn-on time for the power switch that matches the source internal resistance. In order to reduce average power consumption, the static comparator only works when SET is high.

[0089] In order to achieve continuous regulation of the output voltage and avoid energy waste, the power stage circuit adopts clockless sampling technology. When the switch G8 count reaches 512 times, the circuit will generate an overflow signal, and combined with the control logic, generate a sampling signal through the sampling time generator, thereby ensuring that sampling is only performed during the inductor discharge period, avoiding the energy loss and output voltage imbalance problems in the traditional open circuit voltage method.

[0090] The main working process of the circuit of this application is as follows:

[0091] 1. This embodiment connects the voltage signals output by the transducer TEG and PV to the power stage circuit. The logic control module switches the power tube by identifying the corresponding enable signal, so that the system circuit dynamically switches between different modes, forms different energy flow paths, and provides high-quality power supply for the subsequent circuit.

[0092] 2. The series stacking technology is used to further increase the maximum output power of the circuit. By combining the on-time controller, it can solve the internal resistance matching problem under multiple input sources to a certain extent and widen the internal resistance tracking range. The pre-charging technology is used to reduce energy waste and improve the situation where the system transient response deteriorates due to a surge in load power.

[0093] This application has the following beneficial effects:

[0094] 1. This application adopts a multi-working mode solution. By identifying the corresponding enable signal, the system circuit dynamically switches between multiple working modes to match the load power demand and improve the energy conversion efficiency.

[0095] 2. This application adopts series stacking technology. Combining the load power demand and input conditions, it can achieve the simultaneous extraction of multiple source energies in one switching cycle. On the basis of reducing output ripple and improving tracking efficiency, the energy conversion efficiency is improved to a certain extent.

[0096] 3. The present application samples dual modulation technology, and uses a dual modulation technology combining coarse adjustment and fine adjustment to dynamically adjust the on-time of the switch tube, which to a certain extent solves the internal resistance matching problem under multiple input sources and broadens the internal resistance tracking range.

[0097] 4. This application uses clock-free sampling technology to accurately control the system sampling time during the inductor discharge period, avoiding the energy loss problem in the traditional open circuit voltage method and achieving continuous output voltage regulation.

[0098] In addition, the present application also provides a power system. The power system may include the aforementioned multi-source energy collection circuit. It is understandable that the present power system has the same technical effect as the aforementioned multi-source energy collection circuit.

[0099] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0100] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0101] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the described embodiments. Technical personnel familiar with the field may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A multi-source energy harvesting circuit, characterized in that: Used to connect with thermoelectric cells and photovoltaic cells, the collection circuit includes: A first switch tube, a second switch tube and a power stage sub-circuit; The drain of the first switch tube is connected to the temperature difference thermal battery; the drain of the second switch tube is connected to the photovoltaic cell; the first input end of the power stage sub-circuit is connected to the source of the first switch tube; the first input end of the power stage sub-circuit is connected to the source of the second switch tube; the gate of the first switch tube and the gate of the second switch tube are connected to the sampling control signal.

2. The multi-source energy harvesting circuit according to claim 1, characterized in that: The multi-source energy collection circuit further includes a logic control module; the logic control module is connected to the power stage subcircuit.

3. The multi-source energy harvesting circuit according to claim 2, characterized in that: The power stage subcircuit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, a first capacitor, a second capacitor, a third capacitor, a first inductor and an energy storage device; One end of the first capacitor and the drain of the fifth field effect transistor are connected to the source of the second switch tube; The drain of the first field effect transistor, the drain of the third field effect transistor and the drain of the fourth field effect transistor are connected to the other end of the first capacitor; One end of the second capacitor, the source of the first field effect transistor and the drain of the second field effect transistor are connected to the source of the first switch transistor; The source of the fifth field effect transistor, the source of the second field effect transistor, the drain of the sixth field effect transistor and the source of the seventh field effect transistor are connected to one end of the first inductor; The source of the third field effect transistor, the drain of the seventh field effect transistor and the drain of the ninth field effect transistor are connected to one end of the third capacitor; The drain of the eighth field effect transistor, the source of the ninth field effect transistor, and the source of the tenth field effect transistor are connected to the other end of the first inductor; The drain of the tenth field effect transistor is connected to one end of the energy storage device; The other end of the energy storage device, the other end of the second capacitor, the source of the fourth field effect transistor, the source of the sixth field effect transistor, the source of the eighth field effect transistor and the other end of the third capacitor are all grounded; The gate of the first field effect transistor, the gate of the second field effect transistor, the gate of the third field effect transistor, the gate of the fourth field effect transistor, the gate of the fifth field effect transistor, the gate of the sixth field effect transistor, the gate of the seventh field effect transistor, the gate of the eighth field effect transistor, the gate of the ninth field effect transistor, and the gate of the tenth field effect transistor are connected to the logic control module.

4. The multi-source energy harvesting circuit according to claim 3, characterized in that: The energy storage device is a capacitor.

5. The multi-source energy harvesting circuit according to claim 2, characterized in that: The logic control module includes a zero-crossing comparator, a mode selector, an output voltage detector, a clock generator, a pulse width modulator, a sampling signal generator, a driver, and a sampling comparator; the zero-crossing comparator, the mode selector, the sampling signal generator, and the pulse width modulator are connected to the driver; the driver is connected to the power stage subcircuit; The output voltage detector, the sampling comparator, the pulse width modulator, and the clock generator are connected to the mode selector.

6. The multi-source energy harvesting circuit according to claim 5, characterized in that: The sampling signal generator includes a fourth capacitor, a first counter, a trigger, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate and a first NOR gate; The input end of the first counter is connected to the driver; the output end of the first counter is connected to the clock end of the trigger; The first input terminal of the trigger is connected to an external signal; the second input terminal of the trigger is connected to the output terminal of the third NOT gate; the input terminal of the third NOT gate is connected to the driver; The output end of the trigger is connected to the input end of the first NOT gate; the first input end of the first NOR gate and the input end of the second NOT gate are connected to the output end of the first NOT gate; The output end of the second NOT gate and one end of the fourth capacitor are connected to the second input end of the first NOR gate; the input end of the fourth NOT gate is connected to the output end of the first NOR gate; the input end of the fourth NOT gate serves as the output end of the sampling signal generator.

7. The multi-source energy harvesting circuit according to claim 5, characterized in that: The pulse width modulator comprises a fifth AND gate, a coarse adjustment module, a fine adjustment module and a modulation module; The coarse adjustment module and the fine adjustment module are connected to the modulation module; the modulation module and the first enable signal are connected to the fifth AND gate; and the output end of the fifth AND gate is connected to the driver.

8. The multi-source energy harvesting circuit according to claim 7, characterized in that: The coarse adjustment module includes a first OR gate, a fifth NOT gate, a reset signal detector and a second counter; A second enable signal is connected to the first input terminal of the first OR gate, and a third enable signal is connected to the second input terminal of the first OR gate; The input end of the fifth NOT gate and the first input end of the reset signal detector are connected to the output end of the first OR gate; the output end of the fifth NOT gate is connected to the second input end of the reset signal detector; the third input end of the reset signal detector is connected to the second signal; The output end of the reset signal detector is connected to the input end of the second counter; and the output end of the second counter is connected to the modulation module.

9. The multi-source energy harvesting circuit according to claim 7, characterized in that: The fine adjustment module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a first operational amplifier, a second operational amplifier, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a second OR gate, a third OR gate, and a first register; One end of the first resistor is connected to the first voltage signal; one end of the second resistor is connected to the second voltage signal, one end of the third resistor is connected to the third voltage signal, and one end of the fourth resistor is connected to the fourth voltage signal; The other end of the first resistor and one end of the fifth capacitor are connected to the non-inverting input terminal of the first operational amplifier; the other end of the second resistor and one end of the sixth capacitor are connected to the inverting input terminal of the first operational amplifier; The other end of the third resistor and one end of the seventh capacitor are connected to the non-inverting input terminal of the second operational amplifier; the other end of the fourth resistor and one end of the eighth capacitor are connected to the inverting input terminal of the second operational amplifier; The first output terminal of the first operational amplifier is connected to the first input terminal of the first AND gate; the second input terminal of the first AND gate is connected to the second enable signal; The first output terminal of the second operational amplifier is connected to the first input terminal of the third AND gate; the second input terminal of the third AND gate is connected to the third enable signal; The second output terminal of the first operational amplifier is connected to the first input terminal of the second AND gate; the second input terminal of the second AND gate is connected to the second enable signal; The second output terminal of the second operational amplifier is connected to the first input terminal of the fourth AND gate; the second input terminal of the fourth AND gate is connected to the third enable signal; The output end of the second AND gate is connected to the first input end of the second OR gate; the output end of the third AND gate is connected to the first input end of the third OR gate; the second input end of the second OR gate is connected to the fourth enable signal; the second input end of the third OR gate is connected to the fifth enable signal; The output end of the second OR gate and the output end of the third OR gate are connected to the first register; the output end of the first register is connected to the modulation module; the other end of the fifth capacitor, the other end of the sixth capacitor, the other end of the seventh capacitor and the other end of the eighth capacitor are all grounded.

10. A power system, characterized in that: A multi-source energy harvesting circuit comprising any one of claims 1-9.

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