Amplification circuit and doherty amplification circuit

Abstract

The invention relates to an amplifier circuit and a Doherty amplifier circuit. The invention provides an amplifier circuit capable of improving characteristics. An amplifier circuit includes: a transistor (Q1) including an input terminal to which a high-frequency signal is input and an output terminal to which an amplified high-frequency signal is output; an inductor (L) connected in parallel with the transistor between the input terminal and the output terminal; and a capacitor (C) connected in parallel with the transistor between the input terminal and the output terminal, and connected in series with the inductor.

Description

Technical Field

[0001] The present invention relates to an amplifier circuit and a Doherty amplifier circuit. Background Art

[0002] As an amplifier circuit, an N-way (N is 3 or more) Doherty amplifier circuit using a main amplifier and two or more peak amplifiers is known (for example, Patent Document 1, Patent Document 2).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: U.S. Patent No. 8022760 Specification

[0006] Patent Document 2: U.S. Patent No. 10601375 Specification

[0007] The maximum gain of an amplifier circuit such as a Doherty amplifier circuit can be increased by suppressing the feedback capacitance of a transistor. Summary of the Invention

[0008] An object of the present disclosure is to improve characteristics.

[0009] One embodiment of the present disclosure is an amplifier circuit including: a transistor having an input terminal for inputting a high-frequency signal and an output terminal for outputting an amplified high-frequency signal; an inductor connected in parallel with the transistor between the input terminal and the output terminal; and a capacitor connected in parallel with the transistor between the input terminal and the output terminal and connected in series with the inductor.

[0010] Advantages of the Invention

[0011] According to the present disclosure, characteristics can be improved. Brief Description of the Drawings

[0012] Figure 1 It is a block diagram of the amplifier circuit of Example 1.

[0013] Figure 2 It is a circuit diagram of Circuit A.

[0014] Figure 3 It is a circuit diagram of Circuit B.

[0015] Figure 4 It is a circuit diagram of Circuit C.

[0016] Figure 5 It is a graph showing the maximum gain gmax with respect to frequency in Circuit C.

[0017] Figure 6It is a diagram showing the maximum gain gmax with respect to frequency in circuit C.

[0018] Figure 7 It is a circuit diagram of circuit D.

[0019] Figure 8 It is a diagram showing the maximum gain gmax with respect to frequency in circuit D.

[0020] Figure 9 It is a block diagram of the Doherty amplifier circuit of Embodiment 2.

[0021] Figure 10 It is a top view of the semiconductor device of Embodiment 2.

[0022] Explanation of reference numerals:

[0023] 10: Main amplifier;

[0024] 11: Amplifier;

[0025] 12, 14: Peak amplifiers;

[0026] 16: Divider;

[0027] 18: Combiner;

[0028] 20a, 20b, 20c: Semiconductor chips;

[0029] 21a, 21b, 21c: Substrates;

[0030] 22a, 22b, 22c, 23a, 23b, 23c, 42, 44: Pads;

[0031] 24a, 24b, 24c: Capacitive components;

[0032] 25: Dielectric substrate;

[0033] 26: Electrode;

[0034] 27a, 27b, 27c, 28a, 28b, 28c: Leads;

[0035] 30, 31, 32, 33, 34, 35: Matching circuits;

[0036] 36, 37, 38, 39: Bias circuits;

[0037] 40: Passive chip;

[0038] 41: Substrate;

[0039] 46, 47, 48, 49a, 49b: Bonding wires;

[0040] 50: Package;

[0041] 51: Substrate;

[0042] 52: Equivalent circuit;

[0043] 100: Amplifier circuit;

[0044] 102: Doherty amplifier circuit;

[0045] C, C2, C3: Capacitor, capacitance;

[0046] Cgd: Gate-drain capacitance (feedback capacitance);

[0047] L, L1, L2, L3: Inductor, inductance;

[0048] Q1, Q2, Q3: Transistor;

[0049] Sin: Input signal;

[0050] Sout: Output signal;

[0051] Tin: Input terminal;

[0052] Tout: Output terminal. Detailed implementation manners

[0053] [Description of the embodiments of the present disclosure]

[0054] First, the content of the embodiments of the present disclosure will be listed for description.

[0055] (1) One embodiment of the present disclosure is an amplifier circuit, comprising: a transistor having an input terminal for inputting a high-frequency signal and an output terminal for outputting the amplified high-frequency signal; an inductor connected in parallel with the transistor between the input terminal and the output terminal; and a capacitor connected in parallel with the transistor between the input terminal and the output terminal, and the capacitor is connected in series with the inductor. Thereby, the inductor compensates the feedback capacitance of the transistor. Thereby, the gain of the amplifier circuit can be improved and the characteristics can be improved.

[0056] (2) In the above (1), it may also be that when the feedback capacitance of the transistor is set as Cgd, the inductance of the inductor is set as L, the capacitance of the capacitor is set as C, and the center frequency of the operating frequency band is set as f0, 1 / ((2π × f0) 2 × Cgd) + 1 / ((2π × f0) 2 × C) ≤ L ≤ 10 / ((2π × f0) 2 × Cgd) + 10 / ((2π × f0) 2 × C). Thereby, the inductor compensates the feedback capacitance. Thereby, the characteristics can be improved.

[0057] (3) In (2) above, it can also be that 1 / (2π×f0×C) < 2π×f0×L. Thus, the series circuit of the inductor and the capacitor can be made inductive.

[0058] (4) In (3) above, it can also be that C > Cgd. Thus, the capacitor can be used as a DC cut-off.

[0059] (5) In any one of (1) to (4) above, it can also be that the maximum gain at the center frequency of the operating frequency band between the input terminal and the output terminal is greater than the maximum gain at the center frequency between the input terminal and the output terminal when the inductor and the capacitor are not provided. Thus, the gain can be increased.

[0060] (6) In any one of (1) to (5) above, it can also be that the transistor is an FET, the input terminal is the gate of the FET, and the output terminal is the drain of the FET. Thus, the characteristics of the FET can be improved.

[0061] (7) It can also be a Doherty amplifier circuit, comprising: a main amplifier having the amplifier circuit according to any one of (1) to (6) above; and a peak amplifier. Thus, the characteristics of the Doherty amplifier circuit can be improved.

[0062] (8) In (7) above, it can also be that the peak amplifier does not have an inductor and a capacitor connected in parallel between the input terminal and the output terminal of the transistor. Thus, miniaturization can be achieved.

[0063] [Details of the Embodiments of the Present Disclosure]

[0064] With reference to the accompanying drawings, specific examples of the amplifier circuit and the Doherty amplifier circuit of the embodiments of the present disclosure will be described. It should be noted that the present disclosure is not limited to these examples, but is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0065] [Embodiment 1]

[0066] Figure 1 is a block diagram of the amplifier circuit of Embodiment 1. The frequency of the high-frequency signal amplified by the amplifier circuit 100 is, for example, 0.5 GHz or more and 100 GHz or less. When the amplifier circuit 100 is used as a high-output high-frequency amplifier circuit used in a mobile communication base station, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less.

[0067] As Figure 1As shown, in the amplifier circuit 100 of Embodiment 1, an amplifier 11 is connected between an input terminal Tin and an output terminal Tout. The amplifier 11 includes a transistor Q1. The transistor Q1 is, for example, an FET (Field Effect Transistor). The source S, gate G, and drain D of the transistor Q1 are electrically connected to a reference potential such as a ground potential, the input terminal Tin, and the output terminal Tout, respectively. The amplifier 11 amplifies a high-frequency signal input to the input terminal Tin and outputs the amplified harmonic signal to the output terminal Tout.

[0068] The transistor Q1 is, for example, an FET (Field Effect Transistor), and is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0069] Between the input terminal Tin and the output terminal Tout, a capacitor C and an inductor L are connected in parallel with the amplifier 11, and the capacitor C and the inductor L are connected in series. The inductor L compensates for the feedback capacitance (e.g., gate-drain capacitance Cgd) of the transistor Q1. The capacitor C is a capacitor for DC blocking.

[0070] [Simulation]

[0071] To describe the operation of Embodiment 1, hereinafter, the simulation in several circuits A to D will be described.

[0072] [Circuit A]

[0073] Figure 2 is the circuit diagram of Circuit A. As Figure 2 shown, between the input terminal Tin and the output terminal Tout, an inductor L1 is connected in parallel with the gate-drain capacitance Cgd. At the resonance frequency of the parallel resonance circuit of the gate-drain capacitance Cgd and the inductor L1, the impedance between the input terminal Tin and the output terminal Tout increases. Thus, the gate-drain capacitance Cgd can be compensated. When the center frequency of the operating band is set to f0, the inductance of the inductor L1 is set to L1, and the capacitance of the gate-drain capacitance Cgd is set to Cgd, at the center frequency f0, the inductance L1 when the parallel resonance circuit resonates is given by Equation 1.

[0074] L1 = 1 / ((2π × f0) 2 × Cgd) (Equation 1)

[0075] When f0 = 2.1 GHz and Cgd = 0.246 pF, L1 = 23.1 nH.

[0076] [Circuit B]

[0077] Figure 3 is the circuit diagram of Circuit B. As Figure 3 shown, between the input terminal Tin and the output terminal Tout, a capacitor C2 is connected in series with an inductor L2 and in parallel with the gate-drain capacitance Cgd. In Circuit A, a DC current flows in parallel through the inductor L1 and the gate-drain capacitance Cgd. Therefore, the capacitor C2 is used for DC blocking. In Circuit B, the inductance L2 of the inductor L2 corresponding to the capacitor C2 is made greater than the inductance L1 of the inductor L1. The relationship among L1, L2, and C2 is given by Equation 2.

[0078] 2π×f0×L1 = 2π×f0×L2 - 1 / (2π×f0×C2) (Equation 2)

[0079] According to Equation 2, the inductance L2 of the inductor L2 is given by Equation 3.

[0080] L2 = 1 / ((2π×f0) 2 ×Cgd) + 1 / ((2π×f0) 2 ×C2) (Equation 3)

[0081] When f0 = 2.1 GHz, Cgd = 0.246 pF, and C2 = 0.5 pF, L2 = 34.7 nH.

[0082] [Circuit C]

[0083] Figure 4 is the circuit diagram of Circuit C. In Circuit C, an inductor L3 and a capacitor C3 are connected in parallel with the gate-drain capacitance Cgd of the equivalent circuit 52 of the transistor. The equivalent circuit 52 is a FET equivalent circuit.

[0084] In the equivalent circuit 52, the drain-source current is represented by a current source Id. A current source Id and a drain-source capacitance Cds are connected in parallel between the node N1 and the node N2. The node N1 is connected to the source S via a source resistance Rs and a source inductance Ls. The node N2 is connected to the drain D via a drain resistance Rd and a drain inductance Ld. The node N3 is connected to the gate G via a gate resistance Rg and a gate inductance Lg. A gate-drain capacitance Cgd is connected between the node N2 and the node N3. A gate-source capacitance Cgs and a channel resistance Ri are connected in series between the node N3 and the node N1.

[0085] In Circuit C, between the node N2 and the node N3, an inductor L3 and a capacitor C3 are connected in parallel with the gate-drain capacitance Cgd.

[0086] As the inductor L3 and the capacitor C3, the values of the inductor L2 and the capacitor C2 in circuit B are used for simulation. The equivalent circuit 52 uses the equivalent circuit of the GaN HEMT. Cds = 0.246 pF.

[0087] Figure 5 is a graph showing the maximum gain gmax with respect to frequency in circuit C. "Circuit C" is the simulation result of circuit C, and "without L3, C3" is the simulation result of the circuit without using the inductor L3 and the capacitor C3. As Figure 5 shown, in circuit C, although the maximum gain becomes extremely large near 4.7 GHz, the maximum gain at the center frequency f0 = 2.1 GHz is lower than that of the circuit without setting L3 and C3.

[0088] Therefore, the values of the inductor L3 and the capacitor C3 are optimized. Figure 6 is a graph showing the maximum gain gmax with respect to frequency in circuit C. The inductance of the inductor L3 is 91 nH, and the capacitance of the capacitor C3 is 1 pF. As Figure 6 shown, in Figure 6 it, compared with Figure 5 the frequency at which the maximum gain becomes extremely large in circuit C decreases, approximately 2.7 GHz. Accordingly, the maximum gain at the center frequency f0 = 2.1 GHz is approximately 2 dB higher than that of the circuit without setting L3 and C3.

[0089] [Circuit D]

[0090] In an actual amplifier circuit, the inductor L and the capacitor C are connected in parallel with the transistor Q1 between the gate G and the drain D. Figure 7 is the circuit diagram of circuit D. In circuit D, between the node N4 between the gate G and the input terminal Tin and the node N5 between the drain D and the output terminal Tout, the inductor L and the capacitor C are connected in parallel with the equivalent circuit 52.

[0091] Figure 8 is a graph showing the maximum gain gmax with respect to frequency in circuit D. "Without L, C" is the simulation result of the circuit without using the inductor L and the capacitor C. The inductance of the inductor L is 91 nH, and the capacitance of the capacitor C is 1 pF. As Figure 8 shown, the frequency at which the maximum gain becomes extremely large in circuit D is approximately 2.7 GHz, which is the same level as that of Figure 6 circuit C. The maximum gain at the center frequency f0 = 2.1 GHz is approximately 2 dB higher than that of the circuit without setting L and C.

[0092] When f0 = 2.1 GHz, Cgd = 0.246 pF, and C2 = 1 pF, when calculating L2 according to Equation 3, it is 28.8 nH. In Circuit C and Circuit D, it is considered that due to the influence of other elements of the equivalent circuit 52, L and L3 are larger than L2 calculated according to Equation 3.

[0093] As Figure 1 and Figure 7 shown, the inductor L is connected in parallel with the transistor Q1 between the gate G (input terminal) and the drain D (output terminal) of the transistor Q1. The capacitor C is connected in parallel with the transistor Q1 between the gate G and the drain D, and the capacitor C is connected in series with the inductor L. Thus, the inductor L compensates for the feedback capacitance (gate-drain capacitance Cgd) of the transistor Q1. Thereby, the gain of the amplifier circuit 100 having the transistor Q1 can be increased, and the characteristics can be improved.

[0094] If the influence of elements other than the gate-drain capacitance Cgd of the equivalent circuit 52 is small, the inductance L of the inductor L is the value calculated by Equation 3. If the influence of elements other than the gate-drain capacitance Cgd of the equivalent circuit 52 is large, the inductance L of the inductor L is larger than the value calculated by Equation 3. Thus,

[0095] 1 / ((2π × f0) 2 × Cgd) + 1 / ((2π × f0) 2 × C) ≤ L.

[0096] Thus, the inductor L compensates for the gate-drain capacitance Cgd. Thereby, the characteristics can be improved.

[0097] In the case where the influence of elements other than the gate-drain capacitance Cgd of the equivalent circuit 52 is large,

[0098] it can be set as 1 / ((2π × f0) 2 × Cgd) + 1 / ((2π × f0) 2 × C) < L,

[0099] or it can also be set as 2 / ((2π × f0) 2 × Cgd) + 2 / ((2π × f0) 2 × C) ≤ L.

[0100] When the inductance L is large, the resonance frequency with the gate-drain capacitance Cgd is lower than the center frequency f0. Thus, the gain is reduced. From this viewpoint,

[0101] it can be set as L ≤ 10 / ((2π × f0) 2 × Cgd) + 10 / ((2π × f0) 2 × C),

[0102] It can also be set as L ≤ 8 / ((2π × f0) 2 × Cgd) + 8 / ((2π × f0) 2 × C),

[0103] It can also be set as L ≤ 6 / ((2π × f0) 2 × Cgd) + 6 / ((2π × f0) 2 × C).

[0104] In order to make the series circuit of capacitor C and inductor L inductive,

[0105] It can be set as 1 / (2π × f0 × C) < 2π × f0 × L.

[0106] It can be set as 1 / (2π × f0 × C) ≤ π × f0 × L / 2,

[0107] It can also be set as 1 / (2π × f0 × C) ≤ π × f0 × L / 4.

[0108] It can also be set as 1 / (2π × f0 × C) ≥ 2π × f0 × L / 20.

[0109] Since capacitor C is used for DC cut-off, the capacitance C is relatively large to some extent. For example, it can be set as C > Cgd.

[0110] It can be set as C ≥ 1.5 × Cgd,

[0111] It can also be set as C ≥ 2 × Cgd,

[0112] It can also be set as C ≤ 10 × Cgd.

[0113] As Figure 8 shown, the maximum gain gmax at the center frequency f0 between the gate G and the drain D is greater than the maximum gain gmax0 at the center frequency f0 when the inductor L and the capacitor C are not provided. Thus, the gain can be improved.

[0114] Compared with gmax0, the maximum gain gmax can be set as 0.5 dB or more, and can be set as 1 dB or more.

[0115] Transistor Q1 can also not be a FET. As long as the inductor L and the capacitor C are connected in parallel with the feedback capacitance of transistor Q1. In the case where transistor Q1 is a FET and is a source-grounded amplifier circuit, the equivalent circuit of transistor Q1 is Figure 7 equivalent circuit 52. In this case, by providing the inductor L and the capacitor C, the gain can be particularly improved.

[0116] [Example 2]

[0117] Example 2 is an example in which the amplifier circuit of Example 1 is used in a Doherty amplifier circuit. Figure 9 It is a block diagram of the Doherty amplifier circuit of Example 2.

[0118] As Figure 9 shown, in the Doherty amplifier circuit 102, a main amplifier 10, a peak amplifier 12, and a peak amplifier 14 are connected in parallel between a distributor 16 and a combiner 18. In this way, the Doherty amplifier circuit 102 is a three-way amplifier circuit. The Doherty amplifier circuit 102 may also be an N-way Doherty amplifier circuit having one or more than three peak amplifiers.

[0119] A high-frequency signal is input as an input signal Sin to an input terminal Tin. The distributor 16 distributes the input signal Sin input to the input terminal Tin into a signal S1, a signal S2, and a signal S3. The distributor 16 is, for example, a Wilkinson-type distributor.

[0120] The path of the input signal S1 includes a matching circuit 30, a bias circuit 36, the main amplifier 10, a bias circuit 39, and a matching circuit 33. The path of the input signal S2 includes a matching circuit 31, a bias circuit 37, the peak amplifier 12, and a matching circuit 34. The path of the input signal S3 includes a matching circuit 32, a bias circuit 38, the peak amplifier 14, and a matching circuit 35.

[0121] The matching circuits 30 to 32 respectively match the impedance when looking from the distributor 16 to the matching circuits 30 to 32 with the impedance when looking from the matching circuits 30 to 32 to the main amplifier 10, the peak amplifier 12, and the peak amplifier 14, respectively. The bias circuits 36 to 38 respectively supply gate bias voltages VG1 to VG3 to the gates G of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14, respectively, to suppress leakage of the signals S1 to S3 to the bias terminals.

[0122] The main amplifier 10, the peak amplifier 12, and the peak amplifier 14 respectively amplify the signals S1, S2, and S3, and respectively output amplified signals S4, S5, and S6. The bias circuit 39 supplies a drain bias voltage VD to the drain D of the main amplifier 10 to suppress leakage of the signal S4 to the bias terminal. The matching circuits 33 to 35 respectively match the impedance when looking from the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 to the matching circuits 33 to 35 with the impedance when looking from the matching circuits 33 to 35 to the combiner 18. The combiner 18 combines the signals S4 to S6 and outputs the combined signal as an output signal Sout to an output terminal Tout.

[0123] The main amplifier 10 operates in class A or AB, and the peak amplifiers 12 and 14 operate in class C. When the input power of the input signal Sin is small, the main amplifier 10 operates while the peak amplifiers 12 and 14 do not. When the input power increases, the main amplifier 10 and the peak amplifier 12 operate while the peak amplifier 14 does not. When the input power further increases, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 all operate.

[0124] Figure 10 is a top view of the semiconductor device of Example 2. In Figure 10 the lid of the package 50 is not shown. The thickness direction of the substrate 51 of the package 50 is defined as the Z direction, the direction from the leads 27a to 27c to the leads 28a to 28c is defined as the X direction, and the direction orthogonal to the X direction and the Z direction is defined as the Y direction.

[0125] As Figure 10 shown, in the semiconductor device 104, the package 50 has a conductive substrate 51 at least on the upper surface. The substrate 51 is, for example, a conductive substrate such as a laminated substrate of copper and molybdenum. A reference potential such as a ground potential is supplied to the substrate 51. The semiconductor chips 20a to 20c, the capacitive components 24a to 24c, and the passive chip 40 are mounted on the substrate 51.

[0126] On one side in the X direction of the substrate 51, the leads 27a to 27c are provided with an insulating layer (not shown) therebetween. On the + side in the X direction of the substrate 51, the leads 28a to 28c are provided with an insulating layer (not shown) therebetween. The leads 27a to 27c and the leads 28a to 28c are, for example, metal layers or metal plates such as copper. The signals S1 to S3 are respectively input to the leads 27a to 27c, and the signals S4 to S6 are respectively output from the leads 28a to 28c.

[0127] The semiconductor chip 20a includes a substrate 21a, a transistor Q1, pads 22a and 23a provided on the upper surface of the substrate 21a, and electrodes (not shown) provided on the lower surface of the substrate 21a. The pads 22a, 23a, and the electrodes on the lower surface are electrically connected to the gate G, drain D, and source S of the transistor Q1, respectively. The semiconductor chip 20b includes a substrate 21b, a transistor Q2, pads 22b and 23b provided on the upper surface of the substrate 21b, and electrodes provided on the lower surface of the substrate 21b. The pads 22b, 23b, and the electrodes on the lower surface are electrically connected to the gate G, drain D, and source S of the transistor Q2, respectively. The semiconductor chip 20c includes a substrate 21c, a transistor Q3, pads 22c and 23c provided on the upper surface of the substrate 21c, and electrodes provided on the lower surface of the substrate 21c. The pads 22c, 23c, and the electrodes on the lower surface are electrically connected to the gate G, drain D, and source S of the transistor Q3, respectively.

[0128] The substrates 21a to 21c are semiconductor substrates. When the transistors Q1 to Q3 are GaN HEMTs, the substrates 21a to 21c are, for example, silicon carbide (SiC) substrates, sapphire substrates, or gallium nitride (GaN) substrates. When the transistors Q1 to Q3 are LDMOSs, the substrates 21a to 21c are, for example, silicon (Si) substrates. The pads 22a to 22c, the pads 23a to 23c, and the electrodes on the lower surface are, for example, metal layers such as gold layers.

[0129] The capacitive components 24a to 24c include a dielectric substrate 25, an electrode 26 provided on the upper surface of the dielectric substrate 25, and an electrode provided on the lower surface of the dielectric substrate 25. A capacitor is formed by the electrode 26 and the electrode on the lower surface with the dielectric substrate 25 in between. The dielectric substrate 25 is, for example, an alumina substrate or a barium titanate substrate. The electrode 26 is, for example, a metal layer such as a gold layer.

[0130] Bonding wires 46 electrically connect the leads 27a to 27c and the electrodes 26 of the capacitive components 24a to 24c, respectively. Bonding wires 47 electrically connect the electrodes 26 of the capacitive components 24a to 24c and the pads 22a to 22c, respectively. Bonding wires 48 electrically connect the pads 23a to 23c and the leads 28a to 28c, respectively. The bonding wires 46 to 48 are, for example, metal wires such as gold wires or aluminum wires.

[0131] The bonding wires 46 and 47 function as inductors, and the capacitive components 24a to 24c function as capacitors. The bonding wires 46, 47, and the capacitive components 24a to 24c correspond to the matching circuits 30 to 32 of the T-type LCL circuit.

[0132] A passive chip 40 is provided in the + direction in the Y direction of the semiconductor chip 20a. The passive chip 40 includes a substrate 41, pads 42 provided on the upper surface of the substrate 41, and pads 44. A capacitor C and an inductor L are connected in series between the pad 42 and the pad 44. A bonding wire 49a electrically connects the pad 22a and the pad 42. A bonding wire 49b electrically connects the pad 23a and the pad 44. Thus, the inductor L and the capacitor C can be connected in parallel with the transistor Q1.

[0133] As shown in the second embodiment, the inductor L and the capacitor C can also be connected in parallel with at least one of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 of the Doherty amplifier circuit 102. In particular, mainly the main amplifier 10 amplifies the input signal Sin. Therefore, the inductor L and the capacitor C are connected in parallel with the main amplifier 10. Thus, characteristics such as the gain of the Doherty amplifier circuit 102 can be improved.

[0134] The peak amplifier 12 and the peak amplifier 14 do not have an inductor and a capacitor connected in parallel with the transistors Q2 and Q3 between the gate G and the drain D of the transistors Q2 and Q3. The peak amplifier 12 and the peak amplifier 14 operate only when the input power is large. Therefore, the inductor L and the capacitor C may not be provided in the peak amplifier 12 and the peak amplifier 14. Thus, miniaturization can be achieved.

[0135] The three-way Doherty amplifier circuit has been described as an example, but it may also be a two-way Doherty amplifier circuit without the peak amplifier 14. In addition, it may also be an N-way Doherty amplifier circuit where N is 4 or more. In this case, only N - 1 peak amplifiers need to be provided.

[0136] The embodiments disclosed herein should be considered as illustrative in all respects and not restrictive. The scope of the present disclosure is shown by the claims, rather than by the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. An amplifier circuit comprising: A transistor having an input terminal for inputting a high-frequency signal and an output terminal for outputting an amplified high-frequency signal; an inductor connected in parallel with the transistor between the input terminal and the output terminal; as well as A capacitor is connected in parallel with the transistor between the input terminal and the output terminal, and the capacitor is connected in series with the inductor.

2. The amplifier circuit according to claim 1, wherein: When the feedback capacitance of the transistor is set to Cgd, the inductance of the inductor is set to L, the capacitance of the capacitor is set to C, and the center frequency of the operating frequency band is set to f0, 1 / ((2π×f0) 2 ×Cgd)+1 / ((2π×f0) 2 ×C)≤L≤10 / ((2π×f0) 2 ×Cgd)+10 / ((2π×f0) 2 ×C)。 3. The amplifier circuit according to claim 2, wherein: 1 / (2π×f0×C)<2π×f0×L.

4. The amplifier circuit according to claim 3, wherein: C>Cgd.

5. The amplifier circuit according to any one of claims 1 to 4, wherein: A maximum gain at a center frequency of an operating frequency band between the input terminal and the output terminal is greater than a maximum gain at the center frequency between the input terminal and the output terminal when the inductor and the capacitor are not provided.

6. The amplifier circuit according to any one of claims 1 to 4, wherein: The transistor is a FET, The input terminal is a gate of the FET, and the output terminal is a drain of the FET.

7. A Doherty amplifier circuit, comprising: A main amplifier comprising the amplification circuit according to any one of claims 1 to 4; and Peaking amplifier.

8. The Doherty amplifier circuit according to claim 7, wherein: The peak amplifier does not include an inductor and a capacitor connected in parallel to the transistor between the input terminal and the output terminal of the transistor.

Images