Sampling and holding circuit and multiplication digital-to-analog converter using same

Abstract

The invention provides a sample-and-hold circuit and a multiplication digital-to-analog converter employing the same. The sample hold circuit is provided with a first input end, a second input end, a first output end and a second output end, the first input end receives a first input signal, and the second input end receives a second input signal. The sample hold circuit includes an operational amplifier, first and second switched capacitor circuits, and a level shift circuit. The operational amplifier has first and second input nodes and first and second output nodes. The first switched capacitor circuit is coupled to the first input terminal, the first output terminal and the first input node. The second switched capacitor circuit is coupled to the second input terminal, the second output terminal and the second input node. The level shift circuit is configured to level shift a voltage of the first output node and a voltage of the second output node according to at least the first input signal and the second input signal.

Description

Technical Field

[0001] The invention relates to a sampling and holding circuit, in particular to a sampling and holding circuit with a correlated level shifting (CLS) function and a multiplication digital-to-analog converter using the sampling and holding circuit. Background Art

[0002] See also Figure 1A , Figure 1A The invention is a circuit diagram of a conventional correlated level shifting (CLS) switched capacitor (SC) circuit. Figure 1A The circuit includes an operational amplifier 110, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a switch SW1, a switch SW2, a switch SW3, a switch SW4, and a switch SW5. The related level shift circuit 120 includes a capacitor C3, a switch SW4, and a switch SW5.

[0003] Figure 1B Three clocks, namely clock CLK1, clock CLKe and clock CLK2, are shown. Figure 1A The circuit operates according to the three clocks. More specifically, when the sampling phase Φs ends, the switch SW1 changes from conducting to non-conducting, the switch SW2 is switched to a reference voltage (e.g., ground) by the input signal Vin, and the switch SW3 is switched to the capacitor C3 and the capacitor C4 by the input signal Vin. During the estimation phase Φe, the switch SW4 is switched to the reference voltage, and the switch SW5 is conducting. During the amplification phase Φh, the switch SW4 is switched to the operational amplifier 110, and the switch SW5 is non-conducting.

[0004] As mentioned above, during the estimation phase Φe, the capacitor C3 and the capacitor C4 are charged to the output voltage Vo of the operational amplifier 110. During the amplification phase Φh, the voltage at the output terminal of the operational amplifier 110 is level-shifted to zero as the AC signal.

[0005] The use of the related level shifting technique can effectively reduce the required output swing of the operational amplifier 110, so the gain of the operational amplifier 110 can be reduced, thereby reducing the power consumption and area of ​​the operational amplifier 110. However, Figure 1AThe circuit requires three clocks, which causes practical difficulties and prevents the circuit speed from being improved. In addition, when the related level shifting technique is applied to the multiplying DAC (MDAC) of the pipeline ADC (pipeline ADC, also known as pipelined ADC), another clock CLK3 is required (such as Figure 2 As shown, it is used to control the sub-ADC, which also increases the practical difficulties and reduces the circuit speed. Summary of the invention

[0006] In view of the deficiencies of the prior art, an object of the present invention is to provide a sample-and-hold circuit and a multiplication digital-to-analog converter using the same, so as to improve the deficiencies of the prior art.

[0007] An embodiment of the present invention provides a sampling and holding circuit. The sampling and holding circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal receives a first input signal, and the second input terminal receives a second input signal. The sampling and holding circuit includes an operational amplifier, a first switching capacitor circuit, a second switching capacitor circuit, and a level shifting circuit. The operational amplifier has a first input node, a second input node, a first output node, and a second output node. The first switching capacitor circuit is coupled to the first input terminal, the first output terminal, and the first input node. The second switching capacitor circuit is coupled to the second input terminal, the second output terminal, and the second input node. The level shifting circuit is coupled to the first output node, the first output terminal, the second output node, and the second output terminal, and is used to level-shift the voltage of the first output node and the voltage of the second output node according to at least the first input signal and the second input signal.

[0008] Another embodiment of the present invention provides a multiplying digital-to-analog converter (MDAC), which has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first output terminal and a second output terminal, wherein the first input terminal receives a first input signal, the second input terminal receives a second input signal, the third input terminal receives the second input signal, and the fourth input terminal receives the first input signal. The multiplying digital-to-analog converter includes an operational amplifier, a first switching capacitor circuit, a second switching capacitor circuit, a level shifting circuit, a first load capacitor, a second load capacitor, a first switch, a second switch, an analog-to-digital converter and a selection circuit. The operational amplifier has a first input node, a second input node, a first output node and a second output node. The first switching capacitor circuit couples the first input terminal, the third input terminal, the first output terminal and the first input node. The second switching capacitor circuit couples the second input terminal, the fourth input terminal, the second output terminal and the second input node. The level shift circuit is coupled to the first output node, the first output terminal, the second output node and the second output terminal, and is used to level shift the voltage of the first output node and the voltage of the second output node. The first load capacitor has a first terminal and a second terminal, and the first terminal is electrically connected to the first output terminal. The second load capacitor has a third terminal and a fourth terminal, and the third terminal is electrically connected to the second output terminal. The first switch is coupled to the second terminal and receives a first reference voltage. The second switch is coupled to the fourth terminal and receives a second reference voltage. The analog-to-digital converter is used to generate a selection signal according to the first input signal and the second input signal. The selection circuit is coupled to the analog-to-digital converter and is used to determine the first reference voltage and the second reference voltage from a plurality of preset voltages according to the selection signal.

[0009] The technical means embodied in the embodiments of the present invention can improve at least one of the disadvantages of the prior art. Therefore, the present invention is easier to design and improves the circuit speed compared to the prior art.

[0010] The features, practices and effects of the present invention are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a circuit diagram of an existing related level shift capacitor switching circuit;

[0012] Figure 1B A waveform diagram showing multiple clocks;

[0013] Figure 2 A waveform diagram showing multiple clocks;

[0014] Figure 3 is a circuit diagram of an embodiment of a sample-and-hold circuit of the present invention;

[0015] Figure 4 It is a waveform diagram of the clock of the present invention;

[0016] Figure 5 yes Figure 3 A circuit diagram of an embodiment of a level shift circuit;

[0017] Figure 6 is a circuit diagram of another embodiment of the sample and hold circuit of the present invention;

[0018] Figure 7 yes Figure 6 A circuit diagram of an embodiment of a level shift circuit;

[0019] Figure 8 yes Figure 6 A circuit diagram of another embodiment of a level shift circuit;

[0020] Fig. 9 is a circuit diagram of another embodiment of the sample and hold circuit of the present invention;

[0021] Fig.10 yes Fig. 9 A circuit diagram of an embodiment of a level shift circuit;

[0022] Fig.11 is a circuit diagram of another embodiment of the sample and hold circuit of the present invention;

[0023] Fig.12 is a functional block diagram of an embodiment of a multiplying digital-to-analog converter of the present invention; and

[0024] Fig.13 It is another waveform diagram of the clock of the present invention. DETAILED DESCRIPTION

[0025] The technical terms used in the following descriptions refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification.

[0026] The disclosure of the present invention includes a sample-hold circuit and a multiplying digital-to-analog converter. Since some of the components included in the sample-hold circuit and the multiplying digital-to-analog converter of the present invention may be known components individually, the details of the known components will be omitted in the following description without affecting the full disclosure and feasibility of the device invention.

[0027] In the following description, a signal at a high level represents active, and at a low level represents inactive, and enabling / disabling a signal represents pulling up / lowering the level of the signal. However, this is only an implementation or illustrative example and is not intended to limit the present invention. In other words, in different implementations, a signal at a high level may represent inactive, and at a low level may represent active, and enabling / disabling a signal represents pulling down / higher the level of the signal. Level conversion or logic level conversion represents a signal changing from enabled (active) to disabled (inactive), or vice versa.

[0028] See also Figure 3 , Figure 3 3 is a circuit diagram of an embodiment of a sample-and-hold circuit of the present invention. The sample-and-hold circuit 300 has an input terminal Vin1, an input terminal Vin2, an input terminal Vin3, an output terminal Vp2, and an output terminal Vn2, and includes an operational amplifier 310, a level shift circuit 320, a switch capacitor circuit 330p, and a switch capacitor circuit 330n. The switch capacitor circuit 330p includes a capacitor C1p, a switch Ss0p, a switch Ss1p, a switch Ss2p, and a switch Ss3p. The switch capacitor circuit 330n includes a capacitor C1n, a switch Ss0n, a switch Ss1n, a switch Ss2n, and a switch Ss3n.

[0029] Input signals Vsp1 and Vsn1 are input to the sample-and-hold circuit 300 via input terminals Vin1 and Vin2, respectively. Input signals Vsp1 (=Vdc+dV1) and Vsn1 (=Vdc-dV1) may be a differential signal pair, wherein Vdc is a common mode voltage of the two and dV1 is a signal component.

[0030] The input terminal Vin3 receives a DC voltage Vcm_Vp0_Vn0 . The DC voltage Vcm_Vp0_Vn0 may be an input common mode voltage of the operational amplifier 310 (ie, a common mode voltage of the input node Vp0 and the input node Vn0 , for example, a DC voltage that does not cause saturation of the operational amplifier 310 ).

[0031] The switched capacitor circuit 330p is coupled or electrically connected to the input terminal Vin1, the input terminal Vin3, the output terminal Vp2 and the input node Vp0. The switched capacitor circuit 330n is coupled or electrically connected to the input terminal Vin2, the input terminal Vin3, the output terminal Vn2 and the input node Vn0.

[0032] Both ends of the capacitor C1p (capacitor C1n) are a node N1p (node ​​N1n) and a node N2p (node ​​N2n), respectively.

[0033] One end of the switch Ss0p (switch Ss0n) is coupled or electrically connected to the input end Vin3 (ie, receives the DC voltage Vcm_Vp0_Vn0); the other end of the switch Ss0p (switch Ss0n) is coupled or electrically connected to the node N1p (node ​​N1n).

[0034] One end of the switch Ss1p (switch Ss1n) is coupled or electrically connected to the input terminal Vin1 (input terminal Vin2) (ie, receives the input signal Vsp1 (input signal Vsn1)); the other end of the switch Ss1p (switch Ss1n) is coupled or electrically connected to the node N2p (node ​​N2n).

[0035] One end of the switch Ss2p (switch Ss2n) is coupled or electrically connected to the node N1p (node ​​N1n); the other end of the switch Ss2p (switch Ss2n) is coupled or electrically connected to the input end (more specifically, the input node Vp0 (input node Vn0)) of the operational amplifier 310. The input node Vp0 and the input node Vn0 are the inverting input end and the non-inverting input end of the operational amplifier 310, respectively.

[0036] One end of the switch Ss3p (switch Ss3n) is coupled or electrically connected to the node N2p (node ​​N2n); the other end of the switch Ss3p (switch Ss3n) is coupled or electrically connected to the output end Vp2 (output end Vn2).

[0037] The level shift circuit 320 is coupled or electrically connected to the output node Vp1, the output node Vn1, the output terminal Vp2, the output terminal Vn2, the input terminal Vin1 (to receive the input signal Vsp1), and the input terminal Vin2 (to receive the input signal Vsn1). The output node Vp1 and the output node Vn1 are respectively the non-inverting output terminal and the inverting output terminal of the operational amplifier 310. The level shift circuit 320 level shifts the voltage of the output node Vp1 and the voltage of the output node Vn1 according to at least the input signal Vsp1 and the input signal Vsn1.

[0038] See also Figure 4 , Figure 4 The sampling and holding circuit 300 operates according to the clock CLK1 and the clock CLK2.

[0039] During the sampling phase Φs (i.e., when the clock CLK1 is at a first level (e.g., a high level) and the clock CLK2 is at a second level (e.g., a low level)), the switches Ss0p, Ss1p, Ss0n, and Ss1n are turned on, and the switches Ss2p, Ss3p, Ss2n, and Ss3n are not turned on, so that the capacitors C1p and C1n sample the input signals Vsp1 and Vsn1, respectively. After the sampling phase Φs ends, the voltage across the capacitor C1p Vxp and the voltage across the capacitor C1n Vxn are respectively as shown in equations (1) and (2).

[0040] Vxp=Vdc+dV1-Vcm_Vp0_Vn0 (1)

[0041] Vxn=Vdc-dV1-Vcm_Vp0_Vn0 (2)

[0042] During the amplification phase Φh (i.e., when the clock CLK1 is at the second level and the clock CLK2 is at the first level), the switches Ss0p, Ss1p, Ss0n, and Ss1n are not turned on, and the switches Ss2p, Ss3p, Ss2n, and Ss3n are turned on, so that the voltages maintained at the output terminals Vp2 and Vn2 are as shown in equations (3) and (4), respectively.

[0043] Vp2=Vp0+Vxp=(Vcm_Vp0_Vn0+dV2)+(Vdc+dV1-Vcm_Vp0_Vn0)=Vdc+dV1+dV2(3)

[0044] Vn2=Vn0+Vxn=(Vcm_Vp0_Vn0-dV2)+(Vdc-dV1-Vcm_Vp0_Vn0)=Vdc-dV1-dV2(4)

[0045] Here, dV2 is a signal component of the input signal of the operational amplifier 310 .

[0046] See also Figure 5 , Figure 5 is a circuit diagram of an embodiment of the level shift circuit 320 of the present invention. The level shift circuit 320 includes a switched capacitor circuit 410p and a switched capacitor circuit 410n. The switched capacitor circuit 410p (switched capacitor circuit 410n) includes a capacitor C2p (capacitor C2n), a switch Ss4p (switch Ss4n), a switch Ss5p (switch Ss5n), a switch Ss6p (switch Ss6n), and a switch Ss7p (switch Ss7n).

[0047] Both ends of the capacitor C2p (capacitor C2n) are a node N3p (node ​​N3n) and a node N4p (node ​​N4n), respectively.

[0048] One end of the switch Ss4p (switch Ss4n) receives the DC voltage Vcm_Vp1_Vn1; the other end of the switch Ss4p (switch Ss4n) is coupled or electrically connected to the node N3p (node ​​N3n). The DC voltage Vcm_Vp1_Vn1 may be the output common mode voltage of the operational amplifier 310 (i.e., the common mode voltage of the output node Vp1 and the output node Vn1, for example, may be a DC voltage that does not cause saturation of the operational amplifier 310).

[0049] One end of the switch Ss5p (switch Ss5n) is coupled or electrically connected to the input end Vin1 (input end Vin2); the other end of the switch Ss5p (switch Ss5n) is coupled or electrically connected to the node N4p (node ​​N4n).

[0050] One end of the switch Ss6p (switch Ss6n) is coupled or electrically connected to the node N3p (node ​​N3n); the other end of the switch Ss6p (switch Ss6n) is coupled or electrically connected to the output node Vp1 (output node Vn1).

[0051] One end of the switch Ss7p (switch Ss7n) is coupled or electrically connected to the node N4p (node ​​N4n); the other end of the switch Ss7p (switch Ss7n) is coupled or electrically connected to the output terminal Vp2 (output terminal Vn2).

[0052] See also Figure 3 to Figure 5 During the sampling phase Φs, switches Ss4p, Ss5p, Ss4n and Ss5n are turned on, and switches Ss6p, Ss7p, Ss6n and Ss7n are not turned on, so that capacitor C2p and capacitor C2n sample input signal Vsp1 and input signal Vsn1, respectively. After the sampling phase Φs ends, the voltage across capacitor C2p Vyp and the voltage across capacitor C2n Vyn are shown in equations (5) and (6), respectively.

[0053] Vyp=Vdc+dV1-Vcm_Vp1_Vn1 (5)

[0054] Vyn=Vdc-dV1-Vcm_Vp1_Vn1 (6)

[0055] During the amplification phase Φh, the switches Ss4p, Ss5p, Ss4n, and Ss5n are not turned on, and the switches Ss6p, Ss7p, Ss6n, and Ss7n are turned on, so that the capacitors C1p and C2p are connected in series, and the capacitors C1n and C2n are connected in series. Therefore, during the amplification phase Φh, the voltages on the output nodes Vp1 and Vn1 are respectively as shown in equations (7) and (8) (equation (7) is derived from equations (3) and (5), and equation (8) is derived from equations (4) and (6)).

[0056] Vp1=Vp2-Vyp=(Vdc+dV1+dV2)-(Vdc+dV1-Vcm_Vp1_Vn1)=dV2+Vcm_Vp1_Vn1(7)

[0057] Vn1=Vn2-Vyn=(Vdc-dV1-dV2)-(Vdc-dV1-Vcm_Vp1_Vn1)=-dV2+Vcm_Vp1_Vn1(8)

[0058] It can be seen from equations (7) and (8) that, through the level shifting achieved by the level shifting circuit 320 (through the cross voltage Vyp and the cross voltage Vyn), the voltage on the output node Vp1 and the voltage on the output node Vn1 do not include the signal component dV1 of the input signal Vsp1 and the input signal Vsn1. In addition, in the case of the related level shifting, because the signal swing at the output end of the operational amplifier 310 appears in the level shifting circuit 620, the AC signal (i.e., the signal component dV2) of the output node Vp1 and the output node Vn1 is very small. Therefore, the output node Vp1 and the output node Vn1 of the operational amplifier 310 actually only have a DC component, achieving the effect of the related level shifting.

[0059] See also Figure 6 , Figure 66 is a circuit diagram of another embodiment of the sample-and-hold circuit of the present invention. The sample-and-hold circuit 600 includes a level shift circuit 620. The sample-and-hold circuit 600 is similar to the sample-and-hold circuit 300, except that: one end of the switch Ss0p is coupled or electrically connected to the input terminal Vin1, and the input terminal Vin1 receives the input signal Vsp1; one end of the switch Ss0n is coupled or electrically connected to the input terminal Vin2, and the input terminal Vin2 receives the input signal Vsn1; one end of the switch Ss1p and one end of the switch Ss1n are coupled or electrically connected to the input terminal Vin3, and the input terminal Vin3 receives the DC voltage Vcm_Vp2_Vn2; and the level shift circuit 620 is slightly different from the level shift circuit 320. The DC voltage Vcm_Vp2_Vn2 can be a common mode voltage of the output terminal Vp2 and the output terminal Vn2. The level shift circuit 620 level-shifts a voltage of an output node Vp1 and a voltage of an output node Vn1 according to at least an input signal Vsp1 and an input signal Vsn1 .

[0060] See also Figure 7 , Figure 7 is a circuit diagram of an embodiment of the level shift circuit 620 of the present invention. The level shift circuit 620 includes a switch capacitor circuit 710p and a switch capacitor circuit 710n. The switch capacitor circuit 710p (switch capacitor circuit 710n) is similar to the switch capacitor circuit 410p (switch capacitor circuit 410n), except that the switch Ss4p (switch Ss4n) receives the input signal Vsp1 (input signal Vsn1) instead of the DC voltage Vcm_Vp1_Vn1, and the switch Ss5p (switch Ss5n) receives the DC voltage Vcm_Vp1_Vn1 instead of the input signal Vsp1 (input signal Vsn1).

[0061] Figure 6 and Figure 7 The circuit is also based on Figure 4 A person skilled in the art with ordinary knowledge can obtain Figure 3 to Figure 5 Discussions Figure 6 and Figure 7 The operation details are not described here.

[0062] See also Figure 8 , Figure 8is a circuit diagram of another embodiment of the level shift circuit 620 of the present invention. The level shift circuit 620 includes a switch capacitor circuit 810p and a switch capacitor circuit 810n. The switch capacitor circuit 810p (switch capacitor circuit 810n) is similar to the switch capacitor circuit 710p (switch capacitor circuit 710n), except that the switch Ss5p (switch Ss5n) receives a DC voltage Vcm0 instead of a DC voltage Vcm_Vp1_Vn1. The DC voltage Vcm0 can be a DC voltage of any level. Figure 8 The circuit and Figure 7 The circuit has substantially the same effect.

[0063] See also Fig. 9 , Fig. 9 1 is a circuit diagram of another embodiment of the sample-and-hold circuit of the present invention. The sample-and-hold circuit 900 includes a level shift circuit 920. The sample-and-hold circuit 900 is similar to the sample-and-hold circuit 300, except that: the sample-and-hold circuit 900 includes four input terminals (input terminal Vin1, input terminal Vin2, input terminal Vin3 and input terminal Vin4, receiving input signals Vsp1, input signal Vsn1, input signal Vsp2 and input signal Vsn2 respectively); the switch capacitor circuit 330n is coupled or electrically connected to the input terminal Vin4, but is not electrically connected to the input terminal Vin3; one end of the switch Ss0p is coupled or electrically connected to the input terminal Vin1; one end of the switch Ss0n is coupled or electrically connected to the input terminal Vin2; one end of the switch Ss1p is coupled or electrically connected to the input terminal Vin3; one end of the switch Ss1n is coupled or electrically connected to the input terminal Vin4; and the level shift circuit 920 is slightly different from the level shift circuit 320. The level shift circuit 920 level-shifts the voltage of the output node Vp1 and the voltage of the output node Vn1 according to the input signal Vsp1 , the input signal Vsn1 , the input signal Vsp2 , and the input signal Vsn2 .

[0064] See also Fig.10 , Fig.10 1 is a circuit diagram of an embodiment of a level shift circuit 920 of the present invention. The level shift circuit 920 includes a switch capacitor circuit 1010p and a switch capacitor circuit 1010n. The switch capacitor circuit 1010p (switch capacitor circuit 1010n) is similar to the switch capacitor circuit 810p (switch capacitor circuit 810n), except that the switch Ss5p (switch Ss5n) receives the input signal Vsp2 (input signal Vsn2) instead of the DC voltage Vcm0.

[0065] Fig. 9 and Fig.10 The circuit is also based on Figure 4 A person skilled in the art with ordinary knowledge can obtain Figure 3 to Figure 5Discussions Fig. 9 and Fig.10 The input signal Vsp1 and the input signal Vsn1 may be a pair of differential signals, and the input signal Vsp2 and the input signal Vsn2 may be another pair of differential signals.

[0066] In some embodiments, Vsp1 = Vsn2 + Vcm1 , and Vsn1 = Vsp2 + Vcm1 , where Vcm1 is a DC voltage of any level.

[0067] In other embodiments, Vsp2 = Vsn1 and Vsn2 = Vsp1 , so that the voltage at the output terminal Vp2 includes twice the signal component dV1 (ie, +2dV1 or −2dV1 ).

[0068] See also Fig.11 , Fig.11 1 is a circuit diagram of another embodiment of the sampling and holding circuit of the present invention. The sampling and holding circuit 1100 is similar to the sampling and holding circuit 900, except that the sampling and holding circuit 1100 further includes a load capacitor CLp, a load capacitor CLn, a switch Ss8p, and a switch Ss8n. The two ends of the load capacitor CLp (load capacitor CLn) are the output terminal Vp2 (output terminal Vn2) and the node Vp3 (node ​​Vn3), respectively. One end of the switch Ss8p (switch Ss8n) is coupled or electrically connected to the node Vp3 (node ​​Vn3); the other end of the switch Ss8p (switch Ss8n) receives the reference voltage VR2 (reference voltage VR1). The signals (or voltages) on the output terminal Vp2 and the output terminal Vn2 are coupled to the circuit of the lower level (i.e., the circuit coupling or electrically connecting the node Vp3 and the node Vn3, not shown) through the load capacitor CLp and the load capacitor CLn, respectively.

[0069] Fig.11 The sample-and-hold circuit 1100 can be combined with an analog-to-digital converter (ADC) and a selection circuit to implement a multiplying DAC (MDAC) of a pipeline ADC (also called a pipelined ADC). Fig.12 , Fig.12 is a functional block diagram of an embodiment of a multiplication digital-to-analog converter of the present invention. Fig.11 , Fig.12 The multiplying digital-to-analog converter 1200 further includes an ADC 1210 and a selection circuit 1220 .

[0070] The ADC 1210 generates a selection signal SEL according to the input signal Vsp1 and the input signal Vsn1 .

[0071] The selection circuit 1220 selects one of the preset voltage Vx, the preset voltage Vy and the preset voltage Vcm as the reference voltage VR1 and / or the reference voltage VR2 according to the selection signal SEL. The preset voltage Vx may be Vcm+Vz, the preset voltage Vy may be Vcm-Vz, and Vz is a DC voltage. For example, VR1=Vx and VR2=Vy, or VR1=VR2=Vcm. A person skilled in the art with ordinary knowledge can understand the operation principle of the ADC 1210 and the selection circuit 1220 based on a conventional multiplication digital-to-analog converter, so it will not be described in detail.

[0072] Fig.12 The multiplication digital-to-analog converter 1200 may correspond to a conventional 1.5-bit multiplication digital-to-analog converter (ie, the signal component dV1 of the input signal Vsp1 and the input signal Vsn1 is amplified by 2 times. Fig.10 The input signals Vsp2 and Vsn2 are equal to the input signals Vsn1 and Vsp1, respectively. However, because the reference voltages VR1 and VR2 are applied to the load capacitors CLp and CLn (rather than to the sampling capacitors of the conventional multiplication digital-to-analog converter), and the load capacitors CLp and CLn are relatively small (smaller than the sampling capacitors of the conventional multiplication digital-to-analog converter), the driving capabilities of the preset voltages Vx, Vy, and Vcm can be relatively small, thereby reducing the power consumption of the entire multiplication digital-to-analog converter.

[0073] See also Fig.13 , Fig.13 It is another waveform diagram of the clock of the present invention. Fig.12 The multiplication digital-to-analog converter 1200 also operates according to the clock CLK3. Figure 4 , Fig.13 A phase Φb is also included (i.e., when the clock CLK3 is at the first level, and the clocks CLK1 and CLK2 are at the second level), and the phase Φb is between the sampling phase Φs and the amplification phase Φh. During the phase Φb, the ADC 1210 generates a selection signal SEL, and the selection circuit 1220 generates a reference voltage VR1 and a reference voltage VR2 according to the selection signal SEL. The switch Ss8p and the switch Ss8n are turned on in the amplification phase Φh, and are not turned on in the sampling phase Φs and the phase Φb. In the sampling phase Φs and the amplification phase Φh, the clock CLK3 is at the second level.

[0074] See also Figure 2 and Fig.13Since the multiplying digital-to-analog converter 1200 uses the level shift circuit 920 proposed by the present invention, the existing estimated phase Φe is not required, which greatly simplifies the circuit design and improves the circuit speed.

[0075] Please note that in the above-mentioned figures, the shapes, sizes and proportions of the components are merely for illustration purposes, and are provided for those skilled in the art with ordinary knowledge to understand the present invention, and are not intended to limit the present invention.

[0076] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. A person skilled in the art with ordinary knowledge may make changes to the technical features of the present invention based on the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to that defined in the claims of the present invention.

[0077] [Explanation of symbols]

[0078] 110, 310: Operational amplifier

[0079] 120: Related level shift circuit

[0080] C1, C2, C3, C4, C1n, C1p, C2n, C2p: capacitors

[0081] SW1, SW2, SW3, SW4, SW5, Ss0n, Ss0p, Ss1n, Ss1p, Ss2n, Ss2p, Ss3n, Ss3p, Ss4n, Ss4p, Ss5n, Ss5p, Ss6n, Ss6p, Ss7n, Ss7p, Ss8n, Ss8p: switch

[0082] Vin, Vsn1, Vsp1, Vsn2, Vsp2: input signal

[0083] Vo: output voltage

[0084] CLK1, CLK2, CLKe, CLK3: clock

[0085] Φe: estimated phase

[0086] Φh: Amplification phase

[0087] Φs: sampling phase

[0088] 300, 600, 900, 1100: Sample and hold circuit

[0089] 320, 620, 920: Level shift circuit

[0090] 330n, 330p, 410n, 410p, 710n, 710p, 810n, 810p, 1010n, 1010p: Switched capacitor circuits

[0091] N1n, N1p, N2n, N2p, N3n, N3p, N4n, N4p, Vn3, Vp3: Node

[0092] Vcm_Vp0_Vn0, Vcm_Vp1_Vn1, Vcm_Vp2_Vn2, Vcm0: DC voltage

[0093] Vin1, Vin2, Vin3, Vin4: input terminals

[0094] Vn0, Vp0: input nodes

[0095] Vn1, Vp1: output nodes

[0096] Vn2, Vp2: output end

[0097] Vxn, Vxp, Vyn, Vyp: cross voltage

[0098] CLn, CLp: Load capacitors

[0099] VR1, VR2: reference voltage

[0100] 1200: Multiplying Digital-to-Analog Converter

[0101] 1210: ADC (Analog-to-Digital Converter)

[0102] 1220: Select Circuit

[0103] SEL: Select signal

[0104] Vcm, Vx, Vy: preset voltage

[0105] Φb: Phase

Claims

1. A sampling and holding circuit, comprising a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input terminal receives a first input signal, the second input terminal receives a second input signal, and the sampling and holding circuit include: an operational amplifier having a first input node, a second input node, a first output node, and a second output node; A first switched capacitor circuit coupled to the first input terminal, the first output terminal and the first input node; A second switched capacitor circuit coupled to the second input terminal, the second output terminal and the second input node; as well as The level shift circuit is coupled to the first output node, the first output terminal, the second output node and the second output terminal, and is used for level shifting the voltage of the first output node and the voltage of the second output node according to at least the first input signal and the second input signal.

2. The sample-and-hold circuit according to claim 1, in, The first switched capacitor circuit comprises: a first capacitor having a first terminal and a second terminal; A first switch coupled to the first end; A third switch coupled to the second end; a fifth switch coupled between the first terminal and the first input node; and a seventh switch, coupled between the second terminal and the first output terminal; The second switched capacitor circuit comprises: a second capacitor having a third terminal and a fourth terminal; A second switch coupled to the third terminal; a fourth switch coupled to the fourth terminal; a sixth switch coupled between the third terminal and the second input node; and The eighth switch is coupled between the fourth terminal and the second output terminal.

3. The sample-and-hold circuit as claimed in claim 2, in, The first switch and the second switch receive a first DC voltage, the third switch is further coupled to the first input terminal, the fourth switch is further coupled to the second input terminal, and the level shift circuit includes: a third capacitor having a fifth terminal and a sixth terminal; a fourth capacitor having a seventh terminal and an eighth terminal; a ninth switch, coupled to the fifth terminal and receiving a second DC voltage; a tenth switch coupled to the seventh terminal and receiving the second DC voltage; an eleventh switch coupled between the sixth terminal and the first input terminal; A twelfth switch coupled between the eighth terminal and the second input terminal; A thirteenth switch is coupled between the fifth terminal and the first output node; A fourteenth switch is coupled between the seventh terminal and the second output node; A fifteenth switch is coupled between the sixth terminal and the first output terminal; and The sixteenth switch is coupled between the eighth terminal and the second output terminal.

4. The sample-and-hold circuit as claimed in claim 3, in, The sample-and-hold circuit operates according to a first clock and a second clock. When the first clock is at a first level and the second clock is at a second level, the first switch, the second switch, the third switch, the fourth switch, the ninth switch, the tenth switch, the eleventh switch, and the twelfth switch are turned on, and the fifth switch, the sixth switch, the seventh switch, the eighth switch, the thirteenth switch, the fourteenth switch, the fifteenth switch, and the sixteenth switch are not turned on. When the first clock is at the second level and the second clock is at the first level, the first switch, the second switch, the third switch, the fourth switch, the ninth switch, the tenth switch, the eleventh switch, and the twelfth switch are not turned on, and the fifth switch, the sixth switch, the seventh switch, the eighth switch, the thirteenth switch, the fourteenth switch, the fifteenth switch, and the sixteenth switch are turned on.

5. The sample-and-hold circuit as claimed in claim 2, in, The first switch is also coupled to the first input terminal, the second switch is also coupled to the second input terminal, the third switch and the fourth switch receive a first DC voltage, and the level shift circuit includes: a third capacitor having a fifth terminal and a sixth terminal; a fourth capacitor having a seventh terminal and an eighth terminal; a ninth switch, coupled between the fifth terminal and the first input terminal; a tenth switch coupled between the seventh terminal and the second input terminal; an eleventh switch, coupled to the sixth terminal and receiving a second DC voltage; a twelfth switch coupled to the eighth terminal and receiving the second DC voltage; A thirteenth switch is coupled between the fifth terminal and the first output node; A fourteenth switch is coupled between the seventh terminal and the second output node; A fifteenth switch is coupled between the sixth terminal and the first output terminal; and The sixteenth switch is coupled between the eighth terminal and the second output terminal.

6. The sample-and-hold circuit as claimed in claim 5, in, The second DC voltage is a common mode voltage of the first output node and the second output node.

7. The sample-and-hold circuit as claimed in claim 6, in, The sample-and-hold circuit operates according to a first clock and a second clock. When the first clock is at a first level and the second clock is at a second level, the first switch, the second switch, the third switch, the fourth switch, the ninth switch, the tenth switch, the eleventh switch, and the twelfth switch are turned on, and the fifth switch, the sixth switch, the seventh switch, the eighth switch, the thirteenth switch, the fourteenth switch, the fifteenth switch, and the sixteenth switch are not turned on. When the first clock is at the second level and the second clock is at the first level, the first switch, the second switch, the third switch, the fourth switch, the ninth switch, the tenth switch, the eleventh switch, and the twelfth switch are not turned on, and the fifth switch, the sixth switch, the seventh switch, the eighth switch, the thirteenth switch, the fourteenth switch, the fifteenth switch, and the sixteenth switch are turned on.

8. The sample-and-hold circuit as claimed in claim 2, in, The sampling and holding circuit further includes a third input terminal and a fourth input terminal, the third input terminal receives a third input signal, the fourth input terminal receives a fourth input signal, the first switch is also coupled to the first input terminal, the second switch is also coupled to the second input terminal, the third switch is also coupled to the third input terminal, the fourth switch is also coupled to the fourth input terminal, and the level shift circuit includes: a third capacitor having a fifth terminal and a sixth terminal; a fourth capacitor having a seventh terminal and an eighth terminal; a ninth switch, coupled between the fifth terminal and the first input terminal; a tenth switch coupled between the seventh terminal and the second input terminal; an eleventh switch coupled between the sixth terminal and the third input terminal; A twelfth switch coupled between the eighth terminal and the fourth input terminal; A thirteenth switch is coupled between the fifth terminal and the first output node; A fourteenth switch is coupled between the seventh terminal and the second output node; A fifteenth switch is coupled between the sixth terminal and the first output terminal; and The sixteenth switch is coupled between the eighth terminal and the second output terminal.

9. The sample-and-hold circuit as claimed in claim 8, in, The first input signal and the second input signal are a first differential signal pair, and the third input signal and the fourth input signal are a second differential signal pair.

10. A multiplication digital-to-analog converter, comprising a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first output terminal, and a second output terminal, wherein the first input terminal receives a first input signal, the second input terminal receives a second input signal, the third input terminal receives the second input signal, and the fourth input terminal receives the first input signal, wherein the multiplication digital-to-analog converter include: an operational amplifier having a first input node, a second input node, a first output node, and a second output node; A first switched capacitor circuit coupled to the first input terminal, the third input terminal, the first output terminal and the first input node; A second switched capacitor circuit coupled to the second input terminal, the fourth input terminal, the second output terminal and the second input node; A level shift circuit, coupled to the first output node, the first output terminal, the second output node and the second output terminal, for level shifting a voltage of the first output node and a voltage of the second output node; A first load capacitor having a first end and a second end, the first end being electrically connected to the first output end; A second load capacitor has a third terminal and a fourth terminal, wherein the third terminal is electrically connected to the second output terminal; A first switch, coupled to the second end and receiving a first reference voltage; A second switch, coupled to the fourth terminal and receiving a second reference voltage; an analog-to-digital converter, configured to generate a selection signal according to the first input signal and the second input signal; as well as The selection circuit is coupled to the analog-to-digital converter and is used for determining the first reference voltage and the second reference voltage from a plurality of preset voltages according to the selection signal.

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