Electric bicycle power carrier communication bus architecture

Abstract

The invention relates to the technical field of carrier communication, in particular to an electric bicycle power carrier communication bus architecture. The system comprises an integrated service digital network bus, a bus interface, a controller, a carrier modulator and a carrier demodulator, a data bus and a power bus are combined into a whole by the integrated service digital network bus; the controller, the carrier modulator and the carrier demodulator form a vehicle-mounted control unit; the vehicle-mounted control unit is connected with the integrated service digital network bus through the bus interface unit; the bus interface unit comprises a first filter and a second filter; the first filter is used for isolating a low-resistance power supply from a high-speed data stream, so that relatively large inductive reactance is presented between the two wires at a carrier frequency; the second filter is used for blocking power current. According to the invention, the power bus and the data transmission bus are combined, so that the electric control bus architecture of the electric bicycle is simplified; the spectrum conflict problem of power supply and data transmission is solved; the data transmission signal channel can avoid power supply interference, improves communication anti-interference performance, and has the advantages of being simple in structure and low in cost.

Description

Technical Field

[0001] The present invention relates to the technical field of carrier communication, and in particular to an electric bicycle power supply carrier communication bus architecture. Background Art

[0002] As a new energy product, electric bicycles have become the main means of transportation for the public and are becoming more and more popular. Speed ​​and convenience are the main advantages of electric bicycles, which should be reflected through driving control. Almost all driving operations of electric bicycles can be controlled electronically, including speed regulation, braking, light changes, speed measurement, etc. If the control signal transmission delay is too large, or there is a transmission error, it will cause vehicle action delays or errors, which will cause safety accidents. Therefore, the data transmission speed needs to be fast enough, and it is best to be anti-interference and have an error correction mechanism. Electric vehicles transmit control instructions through wires. If there are many on-board operating devices, many wires are needed to interconnect. In order to simplify the circuit and facilitate expansion, the new trend is to simplify multiple pairs of control lines into a bus. All data and commands are transmitted and interacted on the bus, which makes design, manufacturing, and maintenance more convenient and improves reliability.

[0003] like Figure 1 As shown, the early data transmission communication architecture of electric bicycles in the prior art is to separate the power line and the data line, the power line is dedicated, the data transmission adopts a point-to-point UART transmission line, and all slave nodes and the master control node are laid with dedicated data transmission and reception lines, which is a star structure. The advantages of this architecture are: the power line and the data line are separated, the mutual interference between the power line and the data line is relatively light, the master node and each slave node can simultaneously transmit data in both directions, the baud rate is configurable, the real-time performance is strong, the network is reliable and robust, and the software is easy to maintain.

[0004] In order to simplify the network and reduce costs, the data transmission architecture of electric bicycles has evolved into a two-way interconnection network based on RS-485 bus, such as Figure 2 As shown. The RS-485 bus uses two-wire differential transmission, and the common-mode interference resistance is further enhanced. All nodes are gathered into a pair of serial buses. According to the master-slave relationship or priority, the half-duplex time-division multiplexing bus has a high data transmission rate, clear and concise network connection, excellent scalability, and simple production and later maintenance. Since each node shares the bus in time-sharing, a network access mechanism is required to restrict the node's occupancy of the bus, and the software is more complex. For the serial bus, it can be a dedicated control bus that only transmits data; it can also integrate power and data and transmit them on a pair of wires, that is, a one-wire bus.

[0005] The most basic one-line bus is Figure 3As shown in the figure; the power supply transmits direct current, has a small output impedance, a large current, and occupies the low-end frequency spectrum; while the control data is a high-speed alternating signal flow, has a large output impedance, and a small current. If a one-line-through bus is adopted, it is necessary to separate the two energy flows in the frequency domain so that they do not affect each other.

[0006] The existing technologies have the following disadvantages: 1. Among the existing several data transmission buses for electric bicycles, the star network is suitable for applications with fewer nodes. It has weak scalability, requires a lot of wires, has a high cost, and is not convenient for production and later maintenance. 2. Although the RS-485 bus adopts differential form and has a good ability to suppress common-mode interference, if the interference between in-vehicle devices is too large, it may also cause transmission errors. However, since it transmits baseband waveforms and is sensitive to low-frequency band interference, the RS-485 transmission line must be a dedicated line and cannot share the line with the power supply. In this way, a double-track system needs to be adopted to separate the power supply line from the data bus, so that the power supply and the data signal go their own ways. 3. The one-line-through bus needs to handle the electrical differences between the power supply and the data signal. The most basic bus interface is as Figure 4 shown in the figure; this simple bus interface has weak anti-interference ability, small isolation degree between the power supply channel and the data transmission channel, obvious interference of the power supply on the data transmission signal, and is prone to data transmission failure.

[0007] Based on this, there is an urgent need for a new power line carrier communication bus architecture for electric bicycles. Summary of the Invention

[0008] The object of the present invention is to address the problems in the background technology and propose a power line carrier communication bus architecture for electric bicycles. The present invention combines the power supply and the data transmission bus to simplify the electric control bus architecture of the electric bicycle; solves the spectrum conflict problem between the power supply and the data transmission; the data transmission signal channel can avoid power supply interference, improve the anti-interference performance of communication, and has the advantages of simple structure and low cost.

[0009] The technical solution of the present invention is a power line carrier communication bus architecture for electric bicycles, including a one-line-through bus, a bus interface, a controller, a carrier modulator, and a carrier demodulator;

[0010] The one-line-through bus combines the data bus and the power supply bus into one;

[0011] The controller, the carrier modulator, and the carrier demodulator form an in-vehicle control unit; the in-vehicle control unit is connected to the one-line-through bus through the bus interface unit;

[0012] The bus interface unit includes a first filter and a second filter; the first filter is used to isolate the low-impedance power supply from the high-speed data stream so that a large inductive reactance is presented between the two wires at the carrier frequency;

[0013] The second filter is used to block the passage of the power supply current.

[0014] Preferably, the POTS bus is a carrier - type POTS bus.

[0015] Preferably, the first filter includes a low - pass filter and / or a band - stop filter.

[0016] Preferably, the second filter includes a high - pass filter and / or a band - pass filter.

[0017] Preferably, the bus interface transmits the carrier signal in an unbalanced manner.

[0018] Preferably, the bus interface includes capacitors C1, C3, C5, C7, C9, inductors L1, L3, L5, and diodes D1, D3;

[0019] The output terminals of the carrier modulator and the carrier demodulator are connected in series with capacitor C5 and inductor L5; the internal power supply is connected to the POTS bus after being in series with inductor L3; one end of capacitor C7 is connected to the input terminal of inductor L3, and the other end is grounded; capacitor C3 is connected in parallel across the two ends of inductor L3; the output terminal of inductor L5 is connected to the output terminal of inductor L3;

[0020] The positive electrode of diode D1 is connected to the input terminal of capacitor C5, and the negative electrode is connected to VCC; the positive electrode of diode D3 is grounded, and the negative electrode is connected to the input terminal of capacitor C5;

[0021] The input terminal of inductor L1 is connected to the positive electrode of the centralized power supply, and the output terminal is connected to the POTS bus; capacitor C1 is connected in parallel across the two ends of inductor L1; one end of capacitor C9 is connected to the input terminal of inductor L1, and the other end is grounded.

[0022] Preferably, the bus interface transmits the carrier signal in a balanced manner.

[0023] Preferably, the bus interface includes capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, inductors L1, L2, L3, L4, L5, L6, and diodes D1, D2, D3, D4;

[0024] The positive electrodes of the carrier modulator and the carrier demodulator are connected in series with capacitor C5 and inductor L5, and the output terminal of inductor L5 is connected to the output terminal of inductor L3; the positive electrode of the internal power supply is connected to the positive electrode of the POTS bus after being in series with inductor L3; capacitor C3 is connected in parallel across the two ends of inductor L3; one end of capacitor C8 is connected to the positive electrode of the internal working power supply, and the other end is grounded; one end of capacitor C7 is connected to the input terminal of inductor L3, and the other end is grounded;

[0025] The positive electrode of diode D1 is connected to the input terminal of capacitor C5, and the negative electrode is connected to VCC; the positive electrode of diode D3 is grounded, and the negative electrode is connected to the input terminal of capacitor C5;

[0026] The negative electrodes of the carrier modulator and the carrier demodulator are connected in series with a capacitor C6 and an inductor L6, and the output end of the inductor L6 is connected to the output end of the inductor L4; the negative electrode of the internal power supply is connected in series with the inductor L4 and then connected to the negative electrode of a one-line-through bus; the capacitor C4 is connected in parallel across the two ends of the inductor L4.

[0027] The positive electrode of the diode D2 is connected to the input end of the capacitor C6, and the negative electrode is connected to VCC; the positive electrode of the diode D4 is grounded, and the negative electrode is connected to the input end of the capacitor C6.

[0028] The positive electrode of the centralized power supply is connected to the inductor L1, and the negative electrode is connected to the inductor L2; the negative electrode of the inductor L1 is connected to the positive electrode of the one-line-through bus; the negative electrode of the inductor L2 is connected to the negative electrode of the one-line-through bus; the capacitor C1 is connected in parallel across the two ends of the inductor L1; the capacitor C2 is connected in parallel across the two ends of the inductor L2; the capacitor C9 is connected in parallel across the two ends of the centralized power supply.

[0029] Preferably, the capacitor C7 is a high-frequency bypass capacitor, which is connected in parallel between the positive electrode of the internal working power supply and the ground; the inductor L3, the capacitor C3, the inductor L5, and the capacitor C5 form a band-pass filter.

[0030] Preferably, the controller outputs the data to be sent in a serial manner to the carrier modulator. The carrier modulator maps each data bit into a high-frequency signal corresponding to the carrier frequency. After boosting to sufficient power, it is then sent into the bus through the band-pass filter.

[0031] The high-frequency carrier signal on the bus first passes through the band-pass filter to suppress out-of-band interference, and then passes through the carrier demodulator to map the modulation information of the carrier signal back to the data bit and send it to the controller in a serial manner.

[0032] Compared with the prior art, the present invention has the following beneficial technical effects:

[0033] In the present invention, the inductive low-pass at the power supply end is changed to an L / C band-stop filter (L / C parallel resonance), and the high-frequency bypass from the power supply side to GND is carried out, so that the L / C parallel resonance circuit of the power supply end L / C band-stop filter has a second function and becomes the parallel resonance part of the band-pass filter of the internal carrier modem signal interface.

[0034] The interface filter adopts a two-pole maximally flat band-pass structure and utilizes the symmetry of each node to adapt to the high and low impedance conversion problems existing in the modulator (low output impedance) and the demodulator (higher input impedance) due to time-division multiplexing interfaces, and preferably solves the electromagnetic compatibility problem between the power supply and the data transmission communication. Description of the Drawings

[0035] Figure 1 It is a schematic diagram of the star data transmission network and power supply architecture for an electric bicycle.

[0036] Figure 2Schematic diagram of the RS-485 bus and power supply architecture for an electric bicycle;

[0037] Figure 3 Schematic diagram of the one-line-through bus for an electric bicycle;

[0038] Figure 4 Schematic diagram of the basic interface circuit of the one-line-through bus;

[0039] Figure 5 Block diagram of the data transmission basic unit of the present invention;

[0040] Figure 6 Schematic diagram of the frequency spectrum distribution of the one-line-through bus in the present invention;

[0041] Figure 7 Schematic diagram of the filtering interface circuit of the unbalanced transmission bus in the implementation example of the present invention;

[0042] Figure 8 Schematic diagram of the filtering interface circuit of the balanced (differential) transmission mode bus in the implementation example of the present invention;

[0043] Figure 9 Schematic diagram of the high-frequency AC equivalent circuit of the carrier transceiver channel in the implementation example of the present invention;

[0044] Figure 10 Frequency characteristic curve of the band-pass filter on the modulator-demodulator side in the implementation example of the present invention;

[0045] Figure 11 Frequency characteristic curve of the notch filter on the power supply side in the implementation example of the present invention;

[0046] Figure 12 Equivalent high-frequency AC path diagram of the centralized power supply interfering with the modem in the implementation example of the present invention;

[0047] Figure 13 Schematic diagram of the unbalanced transmission bus interface in the implementation example of the present invention;

[0048] Figure 14 Schematic diagram of the high-frequency impedance of the bus network (1 transmitting, N-1 receiving) in the implementation example of the present invention. Detailed implementation manner

[0049] In order to further simplify the interconnection architecture of the electric bicycle, reduce costs, reduce complexity, and improve maintainability, the present implementation example provides the following technical solution, an electric bicycle power line carrier communication bus architecture, including a one-line-through bus, a bus interface, a controller, a carrier modulator, and a carrier demodulator;

[0050] The POTS (Plain Old Telephone Service) bus combines the data bus and the power bus into one; the controller, the carrier modulator, and the carrier demodulator form the vehicle control unit; the vehicle control unit is connected to the POTS bus through the bus interface unit; the bus interface unit includes a first filter and a second filter; the first filter is used to isolate the low-impedance power supply from the high-speed data stream, so that a large inductive reactance is presented between the two wires at the carrier frequency; the second filter is used to block the power current from passing through.

[0051] As Figure 5 shown, the controller (or microprocessor), the carrier modulator, and the carrier demodulator are the core components of data transmission, and the bus interface is the key unit of the bus, which is the intermediate bridge between the power supply and data transmission, and at the same time adapts to the power flow and data signal flow.

[0052] As Figure 6 shown, the power motor of the electric bicycle generates a rotating magnetic field through an electronic switch, and the high-order harmonics of the switching frequency can reach several hundred kHz. If the power supply and the data signal flow are transmitted on the same pair of wires, then the data signal must avoid power interference, and the spectra of the two cannot overlap. To meet this requirement, the data symbol can be modulated onto a carrier with a higher frequency, and filtering and notch filtering techniques can be used to avoid spectral overlap.

[0053] Generally, the DC power supply has a low-pass characteristic, and a large filter capacitor is connected in parallel between the positive and negative poles of the power supply, presenting a low impedance to the high-frequency AC component. In order to allow the carrier signal to be transmitted normally without being bypassed by the low-impedance power supply, an inductor in the order of μH needs to be connected in series at the power supply end to isolate the low-impedance power supply from the high-speed data stream, so that a large inductive reactance is presented between the two wires at the carrier frequency.

[0054] For the carrier part, a small coupling capacitor is used, presenting a high-pass characteristic, which can block the power current from passing through. The POTS bus can use twisted pair as the transmission medium. The characteristic impedance of the power twisted pair is generally less than 110Ω, and the output impedance of the carrier unit is roughly matched with the twisted pair. To improve the anti-interference ability, band-pass and band-stop filters can be added, as Figure 7 shown; the bus interface uses an unbalanced method to transmit the carrier signal:

[0055] The bus interface includes capacitors C1, C3, C5, C7, C9, inductors L1, L3, L5, diodes D1, D3;

[0056] Capacitors C5 and inductor L5 are connected in series at the output ends of the carrier modulator and the carrier demodulator; the internal power supply is connected to the POTS bus after being connected in series with inductor L3; one end of capacitor C7 is connected to the input end of inductor L3, and the other end is grounded; capacitor C3 is connected in parallel across inductor L3; the output end of inductor L5 is connected to the output end of inductor L3;

[0057] The positive electrode of diode D1 is connected to the input end of capacitor C5, and the negative electrode is connected to VCC; the positive electrode of diode D3 is grounded, and the negative electrode is connected to the input end of capacitor C5;

[0058] The input end of inductor L1 is connected to the positive electrode of the centralized power supply, and the output end is connected to a single-line bus; capacitor C1 is connected in parallel across inductor L1; one end of capacitor C9 is connected to the input end of inductor L1, and the other end is grounded.

[0059] To improve the ability to resist common-mode interference, the carrier signal can also be transmitted in a balanced (differential) manner, and the corresponding bus interface is as Figure 8 shown:

[0060] The bus interface includes capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, inductors L1, L2, L3, L4, L5, L6, diodes D1, D2, D3, D4;

[0061] The positive electrodes of the carrier modulator and the carrier demodulator are connected in series with capacitor C5 and inductor L5, and the output end of inductor L5 is connected to the output end of inductor L3; the positive electrode of the internal power supply is connected in series with inductor L3 and then connected to the positive electrode of the single-line bus; capacitor C3 is connected in parallel across inductor L3; one end of capacitor C8 is connected to the positive electrode of the internal working power supply, and the other end is grounded; one end of capacitor C7 is connected to the input end of inductor L3, and the other end is grounded;

[0062] The positive electrode of diode D1 is connected to the input end of capacitor C5, and the negative electrode is connected to VCC; the positive electrode of diode D3 is grounded, and the negative electrode is connected to the input end of capacitor C5;

[0063] The negative electrodes of the carrier modulator and the carrier demodulator are connected in series with capacitor C6 and inductor L6, and the output end of inductor L6 is connected to the output end of inductor L4; the negative electrode of the internal power supply is connected in series with inductor L4 and then connected to the negative electrode of the single-line bus; capacitor C4 is connected in parallel across inductor L4;

[0064] The positive electrode of diode D2 is connected to the input end of capacitor C6, and the negative electrode is connected to VCC; the positive electrode of diode D4 is grounded, and the negative electrode is connected to the input end of capacitor C6;

[0065] The positive electrode of the centralized power supply is connected to inductor L1, and the negative electrode is connected to inductor L2; the negative electrode of inductor L1 is connected to the positive electrode of the single-line bus; the negative electrode of inductor L2 is connected to the negative electrode of the single-line bus; capacitor C1 is connected in parallel across inductor L1; capacitor C2 is connected in parallel across inductor L2; capacitor C9 is connected in parallel across the centralized power supply.

[0066] Working principle:

[0067] 1) Carrier transmission and reception

[0068] The controller outputs the data to be sent in a serial manner to the carrier modulator. The carrier modulator maps each data bit into a high-frequency signal corresponding to the carrier frequency. After boosting to sufficient power, it is then sent into the bus through a band-pass filter.

[0069] The high-frequency carrier signal from the bus first passes through a band-pass filter to suppress out-of-band interference, and then passes through a demodulator to demap the modulation information of the carrier signal back to the data bit, and is transmitted to the controller in a serial manner.

[0070] In this exemplary embodiment, C7 is a high-frequency bypass capacitor. At the modem port, a band-pass filter is composed of L3, C3, L5, and C5, and the center of the passband is the carrier center frequency; at the centralized power supply port, L1 and C1 are in parallel resonance at the carrier center frequency, which can also suppress out-of-band spectral components and reduce EMI. Figure 9 It is the high-frequency AC equivalent circuit of the carrier transceiver channel.

[0071] Such as Figure 10 As shown, the modulator and the demodulator share a bus interface, output a low impedance during transmission, and input a higher impedance during reception. For N nodes, at any time, only 1 node is allowed to transmit, and N - 1 nodes receive. The structure of the high-frequency network remains unchanged, the interfaces of each node are symmetrical, the bus impedance remains unchanged, and the transmission characteristics are also basically unchanged. When the number of nodes N is large, if the number of nodes is increased or decreased slightly, the change in the bus impedance is small, and the impact on the overall transmission characteristics is also slight. Figure 11 It is the frequency characteristic curve of the power supply side notch filter, and the stopband bandwidth can be adjusted by adjusting the Q value of the L / C resonant circuit.

[0072] 2) Power supply interference suppression

[0073] There are three measures to enhance the anti-interference ability: cascading a band-pass filter at the carrier interface, keeping the carrier frequency away from the interference spectrum, and preferably selecting the carrier modulation method. Among several common modulation methods, ASK has a weak anti-interference ability, while FSK and PSK have a strong anti-interference ability.

[0074] Cascading a band-stop filter at the power supply port can suppress the EMI near the carrier frequency. The high-frequency AC path from the centralized power supply EMI to the modem is as Figure 12 shown.

[0075] 3) Bus scheduling

[0076] All nodes share the bus in a time-division multiplexing manner. Polling can be used, or according to the priority level, the bus can be occupied through carrier sensing, or according to the amount of up / down data, N carrier frequencies (N≥1, and the frequencies are non-integer multiples) can be used, that is, N logical channels are included.

[0077] The following uses a specific example to introduce this solution in detail:

[0078] Embodiment Example 1

[0079] The implementation circuit of the unbalanced transmission bus interface is as Figure 13 shown.

[0080] (1) Input and output impedance

[0081] Take N = 7 nodes, and each node is connected in parallel to the bus at a short distance. The output of the carrier modulator is of low impedance, the input impedance of the carrier demodulator is Ri, 1 node transmits, and N - 1 nodes receive. The transmission impedance is taken as Ro = 65Ω, and Ri / (N - 1) = 65Ω, then Ri is taken as 390Ω. See Figure 14 shown.

[0082] (2) Modem port filter:

[0083] The center frequency of the band - pass filter is taken as f0 = 1.8MHz, BW - 3dB = 1.1MHz, BW - 20dB = 3.1MHz;

[0084] Out - of - band rejection: about 30dB@0.5MHz, about 15dB@2*f0.

[0085] (3) Power interference suppression (within the carrier signal band):

[0086] Interference suppression for the centralized power supply terminal: about 35dB@f0±100kHz;

[0087] The ringing amplitude generated by the 5A switching pulse current of the centralized power supply at the demodulator end is about 60mVpp, and the ringing duration is about 2us.

[0088] Interference suppression for the internal working power supply terminal: about 30dB@f0±100kHz;

[0089] The ringing amplitude generated by the 0.5A switching pulse current of the internal working power supply at the demodulator end is about 20mVpp, and the ringing duration is about 1us.

[0090] The present invention combines the data transmission communication bus and the power bus, greatly simplifying the bus of the electric bicycle; at the same time, the bus interface can enhance the anti - interference ability of data transmission communication; the circuit is simple and the cost is low.

[0091] The above - mentioned embodiments of the present invention have been described in detail in conjunction with the accompanying drawings. However, the present invention is not limited thereto. Various changes can be made without departing from the spirit of the present invention within the scope of knowledge possessed by those skilled in the relevant technical field.

Claims

1. An electric bicycle power carrier communication bus architecture, characterized in that: It includes a one-line bus, a bus interface, a controller, a carrier modulator and a carrier demodulator; The one-line bus combines the data bus and the power bus into one; The controller, carrier modulator and carrier demodulator form a vehicle control unit; the vehicle control unit is connected to a one-line bus through a bus interface unit; The bus interface unit includes a first filter and a second filter; the first filter is used to isolate the low-impedance power supply from the high-speed data stream, so that the two wires present a large inductive reactance at the carrier frequency; The second filter is used to block the power supply current from passing through.

2. The electric bicycle power carrier communication bus architecture according to claim 1 is characterized in that: The one-line bus is a carrier type one-line bus.

3. The electric bicycle power carrier communication bus architecture according to claim 1 is characterized in that: The first filter includes a low pass filter and / or a band stop filter.

4. The electric bicycle power carrier communication bus architecture according to claim 1, characterized in that: The second filter includes a high pass filter and / or a band pass filter.

5. The electric bicycle power carrier communication bus architecture according to claim 3 or 4, characterized in that: The bus interface uses an unbalanced method to transmit the carrier signal.

6. The electric bicycle power carrier communication bus architecture according to claim 5, characterized in that: The bus interface includes capacitors C1, C3, C5, C7, C9, inductors L1, L3, L5, diodes D1, D3; The output ends of the carrier modulator and the carrier demodulator are connected in series with capacitor C5 and inductor L5; the internal power supply is connected in series with inductor L3 and then connected to a one-line bus; one end of capacitor C7 is connected to the input end of inductor L3 and the other end is grounded; capacitor C3 is connected in parallel to both ends of inductor L3; the output end of inductor L5 is connected to the output end of inductor L3; The positive electrode of the diode D1 is connected to the input end of the capacitor C5, and the negative electrode is connected to VCC; the positive electrode of the diode D3 is grounded, and the negative electrode is connected to the input end of the capacitor C5; The input end of the inductor L1 is connected to the positive electrode of the centralized power supply, and the output end is connected to a one-line bus; the capacitor C1 is connected in parallel to both ends of the inductor L1; one end of the capacitor C9 is connected to the input end of the inductor L1, and the other end is grounded.

7. The electric bicycle power carrier communication bus architecture according to claim 3 or 4, characterized in that: The bus interface uses a balanced method to transmit carrier signals.

8. The electric bicycle power carrier communication bus architecture according to claim 7, characterized in that: The bus interface includes capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, inductors L1, L2, L3, L4, L5, L6, and diodes D1, D2, D3, D4; The positive electrodes of the carrier modulator and the carrier demodulator are connected in series with capacitor C5 and inductor L5, and the output end of inductor L5 is connected to the output end of inductor L3; the positive electrode of the internal power supply is connected in series with inductor L3 and then connected to the positive electrode of a one-line bus; capacitor C3 is connected in parallel to both ends of inductor L3; one end of capacitor C8 is connected to the positive electrode of the internal working power supply, and the other end is grounded; one end of capacitor C7 is connected to the input end of inductor L3, and the other end is grounded; The positive electrode of the diode D1 is connected to the input end of the capacitor C5, and the negative electrode is connected to VCC; the positive electrode of the diode D3 is grounded, and the negative electrode is connected to the input end of the capacitor C5; The negative electrodes of the carrier modulator and the carrier demodulator are connected in series with capacitor C6 and inductor L6, and the output end of inductor L6 is connected to the output end of inductor L4; the negative electrode of the internal power supply is connected in series with inductor L4 and then connected to the negative electrode of a one-line bus; capacitor C4 is connected in parallel with both ends of inductor L4; The positive electrode of the diode D2 is connected to the input end of the capacitor C6, and the negative electrode is connected to VCC; the positive electrode of the diode D4 is grounded, and the negative electrode is connected to the input end of the capacitor C6; The positive pole of the centralized power supply is connected to the inductor L1, and the negative pole is connected to the inductor L2; the negative pole of the inductor L1 is connected to the positive pole of the one-line bus; the negative pole of the inductor L2 is connected to the negative pole of the one-line bus; the capacitor C1 is connected in parallel at both ends of the inductor L1; the capacitor C2 is connected in parallel at both ends of the inductor L2; and the capacitor C9 is connected in parallel at both ends of the centralized power supply.

9. The electric bicycle power carrier communication bus architecture according to claim 6 or 8, characterized in that: Capacitor C7 is a high-frequency bypass capacitor connected in parallel between the positive electrode of the internal working power supply and the ground; inductor L3, capacitor C3, inductor L5, and capacitor C5 form a bandpass filter.

10. The electric bicycle power carrier communication bus architecture according to claim 1, characterized in that: The controller outputs the data to be sent in serial form to the carrier modulator, which maps each data bit into a high-frequency signal corresponding to the carrier frequency. After it is pushed to sufficient power, it is sent to the bus through a bandpass filter. The high-frequency carrier signal on the bus first passes through a bandpass filter to suppress out-of-band interference, and then passes through a carrier demodulator to map the modulation information of the carrier signal back to the data bit and transmit it to the controller in a serial manner.

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