Message processing system and chip
By introducing an instruction acquisition module, an instruction cache queue, a first instruction processing module and a second instruction processing module in the message processing system, general instructions and network acceleration instructions are solved, and more efficient network acceleration instruction processing is achieved.
Patent Information
- Application Number
- CN202311593590.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-24
- Publication Date
- 2025-05-27
AI Technical Summary
The existing network message processing method implemented by general-purpose processors is less efficient and has limited flexibility.
A message processing system is provided, including an instruction acquisition module, an instruction cache queue, a first instruction processing module and a second instruction processing module. The system can process general instructions and network acceleration instructions, process them through instruction pipelines, and improve the processing efficiency of network acceleration instructions.
On the premise of ensuring the general flexibility of message processing, the processing efficiency of network acceleration instructions is significantly improved and the overall performance of network message processing is improved.
Smart Images
Figure CN120050347A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of data processing, and particularly to a message processing system and a chip. Background Art
[0002] With the development of data processing technology, a technology for processing network messages has emerged. By introducing a processor, the processing of message commands can be implemented through the processor.
[0003] In traditional technologies, the processing of network messages is usually implemented using general-purpose processors such as many-core processors. However, the flexibility of using general-purpose processors to process network messages is limited. Therefore, in the existing processing methods for network messages implemented by general-purpose processors, the processing efficiency of network messages is relatively low. Summary of the Invention
[0004] Based on this, in view of the above technical problems, it is necessary to provide a message processing system and a chip that can improve the processing efficiency of network messages.
[0005] The first aspect of the present invention provides a message processing system, including:
[0006] An instruction acquisition module, configured to acquire a message instruction address, obtain an instruction packet according to the message instruction address, and determine a target message instruction from the instruction packet and send it to an instruction cache queue; the target message instruction is a general instruction or a network acceleration instruction, where the general instruction refers to a RISCV standard instruction and / or an extended instruction, and the network acceleration instruction refers to a custom instruction generated based on the general instruction;
[0007] An instruction cache queue, configured to cache the target message instruction;
[0008] A first instruction processing module, configured to receive and decode the general instruction sent by the instruction cache queue, and process the decoded general instruction through an instruction pipeline;
[0009] A second instruction processing module, configured to receive and decode the network acceleration instruction sent by the instruction cache queue, and process the decoded network acceleration instruction through the instruction pipeline.
[0010] Preferably, the second instruction processing module includes:
[0011] A first instruction decoding module, configured to decode the network acceleration instruction to obtain a first decoded instruction;
[0012] An instruction pipeline logic processing module, configured to receive the first decoded instruction and send the first decoded instruction to the second instruction decoding module;
[0013] The second instruction decoding module is used to receive the first decoded instruction and decode the first decoded instruction to obtain a corresponding access address;
[0014] The Inbuffer module is used to store the cell data and Meta information of the packet. The Inbuffer module is used to receive and in response to the corresponding access address, output the corresponding packet data to the instruction pipeline logic processing module. Among them, the Inbuffer module supports the network acceleration instruction to extract data in units of bits;
[0015] The instruction pipeline logic processing module is used to receive the first decoded instruction and the data sent by the Inbuffer module, perform processing, and send the processing result to the corresponding target address.
[0016] Preferably, the Inbuffer module includes:
[0017] The Packet Buffer module is used to store the cell data of the packet. Among them, the Packet Buffer module supports the network acceleration instruction to extract the stored data in units of bits;
[0018] The Meta Buffer module is used to store the Meta information of the packet. The Meta Buffer module supports the network acceleration instruction to extract data in units of bits.
[0019] Preferably, the second instruction processing module further includes a Fast RegFile module,
[0020] The instruction pipeline logic processing module is further used to receive the first decoded instruction and in response to the first decoded instruction, send the access address in the first decoded instruction to the Fast RegFile module;
[0021] The Fast RegFile module is used to receive and in response to the access address output by the instruction pipeline logic processing module, output the corresponding access address to the Inbuffer module;
[0022] The Inbuffer module is further used to receive the access address output by the Fast RegFile module and output the corresponding packet data to the instruction pipeline logic processing module;
[0023] The instruction pipeline logic processing module is used to receive the packet data and perform processing.
[0024] Preferably, the second instruction processing module further includes a thread decoding module and an Outbuffer module:
[0025] A thread decoding module, configured to receive instructions sent by the instruction pipeline logic processing module, decode the instructions, and write the decoded packet data into the Outbuffer module;
[0026] The Outbuffer module is configured to store the packet data written by the thread decoding module.
[0027] Preferably, the system further includes a state machine processing module, wherein,
[0028] The thread decoding module is configured to receive instructions sent by the instruction pipeline logic processing module, decode the instructions, and send the decoded instructions to the state machine processing module;
[0029] The state machine processing module is configured to receive and process the instructions sent by the thread decoding module, and in response to the instructions, read out the corresponding packet data from the Outbuffer and send it to the corresponding target address.
[0030] Preferably, the Outbuffer module includes: a New Header Buffer module and a New Meta Buffer module, wherein
[0031] The New Header Buffer module is configured to store the head information of the assembled packet,
[0032] The New Meta Buffer module is configured to store the Meta information of the assembled packet.
[0033] Preferably, the Inbuffer module further includes a Result Buffer module, and the Outbuffer module further includes a Key Buffer module,
[0034] The Key Buffer module is configured to output the content in the Key Buffer to the lookup matching module for lookup in response to the received lookup instruction;
[0035] The Result Buffer module is configured to receive and save the lookup matching result returned by the lookup matching module,
[0036] wherein, the Result Buffer module supports indexing and extracting data in units of bits.
[0037] Preferably, the first instruction processing module and the second instruction processing module share the first instruction decoding module and the instruction pipeline logic processing module, and the first instruction processing module further includes a register file module;
[0038] The first instruction decoding module is further configured to decode the general instruction to obtain a second decoded instruction;
[0039] The instruction pipeline logic processing module is further configured to receive the second decoded instruction, and in response to the second decoded instruction, send the access address in the second decoded instruction to the register file module;
[0040] The register file module is configured to receive the access address sent by the pipeline logic processing module, and in response to the access address, send message data to the instruction pipeline logic processing module;
[0041] The instruction pipeline logic processing module is further configured to receive the message data sent by the register file module, perform processing, and send the processing result to the corresponding target address.
[0042] A second aspect of the present application provides a chip, including the foregoing message processing system.
[0043] The message processing system provided by the present application simultaneously carries a first instruction processing module and a second instruction processing module. Through the first instruction processing module, general instructions can be processed, and through the second instruction processing module, network acceleration instructions can be processed. In this way, the processing efficiency of network acceleration instructions can be improved while ensuring the general flexibility of message processing. Description of the Drawings
[0044] Figure 1 It is a schematic structural diagram of a message processing system in an embodiment;
[0045] Figure 2 It is a schematic structural diagram of a message processing system in an embodiment
[0046] Figure 3 It is a schematic structural diagram of an Inbuffer module in an embodiment;
[0047] Figure 4 It is a schematic structural diagram of an Outbuffer module in an embodiment. Detailed Embodiments
[0048] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0049] In one embodiment, as Figure 1-2As shown, a message processing system is provided. This system can be implemented by a multi-core and multi-threaded network processor NPU (Network Process Unit). The system includes: an instruction acquisition module 101, an instruction cache queue, a first instruction processing module 102, and a second instruction processing module 103. Among them, the instruction acquisition module 101 is used to acquire the message instruction address, obtain an instruction packet according to the message instruction address, and determine a target message instruction from the instruction packet and send it to the instruction cache queue; the target message instruction includes general instructions and network acceleration instructions. The instruction cache queue is used to cache the target message instructions. The first instruction processing module 102 is used to receive the general instructions from the instruction cache queue and decode them, and process the decoded general instructions through an instruction pipeline. The second instruction processing module 103 is used to receive the network acceleration instructions from the instruction cache queue and decode them, and process the decoded network acceleration instructions through the instruction pipeline.
[0050] In a specific embodiment, the general instructions include the basic instruction set in The RISC-V Instruction Set Manual Volume I and the extended instruction set based on this. The network acceleration instructions are user-defined instructions for accelerating network message processing, such as IO operation instructions, fast bit data extraction instructions, data fast transfer instructions, etc. This message processing system can support the operation of these network acceleration instructions.
[0051] The message processing system provided in this application is equipped with a first instruction processing module and a second instruction processing module at the same time. Through the first instruction processing module, general instructions can be processed, and at the same time, through the second instruction processing module, user-defined network acceleration instructions can be processed. In this way, the processing efficiency of network acceleration instructions can be improved while ensuring the general flexibility of message processing.
[0052] The instruction acquisition module is used to schedule a thread from each thread in the Ready state according to a scheduling policy to execute, obtain the address of the next instruction to be executed according to the information provided by the scheduled thread, use this address to obtain an instruction packet from the instruction cache queue module, and send the obtained instruction packet to the instruction cache queue module after verification, unpacking, screening, scanning, and serialization.
[0053] In a specific embodiment, the second instruction processing module includes a first instruction decoding module, an instruction pipeline logic processing module, a second instruction decoding module, and an Inbuffer module. The first instruction decoding module is configured to decode the network acceleration instruction to obtain a first decoded instruction, and send the first decoded instruction to the instruction pipeline logic processing module. The instruction pipeline logic processing module receives the first decoded instruction, and when determining that the first decoded instruction is an instruction that needs to access the second decoded instruction, sends the first decoded instruction to the second decoded instruction for further decoding to obtain the access address information of the Inbuffer module. The Inbuffer module receives the access address information and sends the corresponding packet data to the instruction pipeline logic processing module. The instruction pipeline logic processing module receives the first decoded instruction and the packet data sent by the Inbuffer module and processes them, and sends the processed instruction and data to the corresponding target address. Specifically, the target address can be a thread decoding module, a register file module, a Fast RegFile module, etc.
[0054] Specifically, the first decoding module is the first-level decoding for entering the pipeline logic processing module, that is, all instructions entering the instruction pipeline logic processing module need to be decoded by the first decoding module. The first decoding module uses the decoding method "object DecodeLogic" in the mature rocket, that is, the input is the list of instructions to be decoded, and the output is the signals that need to be decoded.
[0055] In a specific embodiment, as Figure 3 shown, the Inbuffer module includes a Packet Buffer module and a MetaBuffer module. Among them, the Packet Buffer module is used to store the cell data (packet cell information) of the packet. The Packet Buffer module supports the network acceleration instruction to extract the stored data by indexing in units of bits. The MetaBuffer module is used to store the Meta information (packet meta information) of the packet, and this module also supports extracting data by indexing in units of bits. For example, the Inbuffer module supports extracting packet data with lengths of 1 bit, 2 bits, 3 bits, 4 bits, etc.
[0056] In a specific embodiment, the second instruction processing module further includes a Fast RegFile module. The instruction pipeline logic processing module is configured to send the first decoded instruction to the Fast RegFile module when the first decoded instruction needs to access the Fast RegFile module. The Fast RegFile module is configured to receive the first decoded instruction and output a corresponding access address to the Inbuffer module in response to the first decoded instruction. The Inbuffer module is further configured to receive the access address output by the Fast RegFile module and output corresponding packet data to the instruction pipeline logic processing module.
[0057] In a specific embodiment, the Fast RegFile module is composed of registers built with hardware circuits and can receive instructions and output data in the same cycle.
[0058] In a specific embodiment, the second instruction processing module further includes a thread decoding module and an Outbuffer module. Specifically, the thread decoding module is configured to receive instructions sent by the pipeline logic processing module, decode the received instructions, and write the decoded packet data into the Outbuffer module. The Outbuffer module is configured to store the packet data written by the thread decoding module.
[0059] Specifically, as Figure 4 shown, the Outbuffer module includes a New Header Buffer module and a New MetaBuffer module. The New Header Buffer module is configured to store the Head information (packet header information) of the assembled packet, and the New Meta Buffer module is configured to store the Meta information of the assembled packet.
[0060] In a specific embodiment, the system further includes a state machine processing module. Specifically, the thread decoding module is further configured to receive instructions sent by the instruction pipeline logic processing module, decode the instructions, and send the decoded instructions to the state machine processing module. The state machine processing module is configured to receive and process the commands sent by the thread decoding module, and in response to the commands, read the corresponding packet data from the Outbuffer and send it to the corresponding target address.
[0061] Specifically, the state machine processing module includes multiple state machines. Each thread has its own dedicated state machine. Each state machine includes an s_idle state, an s_co_aw state, an s_wg_aw state, and an s_wg_b state. In the s_idle state, it waits to receive a new long-cycle instruction. Once there is a long-cycle instruction to be processed, the information prior to the instruction is first temporarily stored in the meta owned by each thread for subsequent process handling. After receiving a message in this state, it fixedly jumps to the s_co_aw state. In the s_co_aw state, the state machine sends a request message according to the meta information of each thread and then jumps to the s_wg_aw state. In this state, each thread monitors the process of data being written into the Inbuffer or the register file module. When it monitors that the data has been written into the Inbuffer or the register file module, it jumps to the s_wg_b state. In the s_wg_b state, it receives a response message. After receiving the response message, the state of the thread can be switched to the Run0 state.
[0062] In a specific embodiment, the Inbuffer module further includes a Result Buffer module, and the Outbuffer module further includes a Key buffer module. The Key buffer module is used to respond to the received search instruction and output the content in the Key buffer to the search and matching module. The search and matching module performs a search and match based on the received keyword content to determine whether there is a keyword identical to the content output from the Key Buffer and writes the result into the Result Buffer module. The Result Buffer module is used to receive and save the search result returned by the search and matching module. Preferably, the Result Buffer module supports indexing and extracting data in units of bits.
[0063] In a specific implementation, the Inbuffer module supports writing data to a 256-bit bus and reading data with a maximum width of 256 bits at any position. The Inbuffer module uses a multiple-thread sharing method, that is, multiple threads share one port to access the internal RAM. The Inbuffer module is implemented using a dual-port RAM with one read and one write. Meta Buffer, PacketBuffer, and Result Buffer are distinguished by different address spaces. Since Inbuffer supports reading data with a maximum width of 256 bits at any bit position, the total bit width of Inbuffer needs to be expanded to 512 bits. Preferably, starting from address 0 of the RAM, they are Result Buffer, Packet Buffer, and Meta Buffer, and each type of Buffer is further divided into the Buffer of each thread. Starting from the low address, the first is the storage address of thread 0, and the second is the storage address of thread 1, and they are arranged in sequence according to the thread id.
[0064] The following uses Packet Buffer as an example to illustrate how to extract data by index in bit units. To extract data from Packet Buffer, the instruction will give the corresponding offset information and size information. According to the offset provided by the instruction, the instruction bit addressing address in the Packet Buffer is addressed, and the offset is used as the base address. The bit stream of size is extracted from the base address, where the data corresponding to the address offset is placed in the high bit of the pipeline data, and the bit data corresponding to offset+size is placed in the low bit of the pipeline data.
[0065] Outbuffer includes Key Buffer, New Head Buffer, and New Meta Buffer. Outbuffer is implemented by multiple threads sharing RAM, and different types of buffers occupy different address spaces. Preferably, the bit width of Outbuffer is 512 bits, and it is implemented by 8 64-bit RAMs.
[0066] In a specific embodiment, the first instruction processing module and the second instruction processing module share a first instruction decoding module and an instruction pipeline logic processing module. The first instruction processing module further includes a register file module. Specifically, the first instruction decoding module is further configured to decode the general instruction to obtain a second decoded instruction, and send the second decoded instruction to the instruction pipeline logic processing module. When the instruction pipeline logic processing module determines that the second decoded instruction is an instruction for accessing the register file module, it sends the second decoded instruction to the register file module. The register file module outputs corresponding packet data to the instruction pipeline logic processing module according to the access address, and the instruction pipeline logic processing module processes the received packet data and outputs it to the corresponding target address.
[0067] Specifically, the register file module is composed of a random access memory (RAM). The register file module needs 3 clock cycles to output data after receiving an instruction.
[0068] In the system of the present application, the combination of the register file module and the Fast RegFile is adopted. On the one hand, it can meet the timing requirements of network acceleration instructions, and on the other hand, it can reduce the chip area.
[0069] Preferably, the first instruction processing module and the second instruction processing module share the instruction pipeline logic processing module.
[0070] Specifically, the instruction pipeline logic processing module adopts a 7-stage pipeline, and the 7-stage pipeline is respectively the RR0 pipeline stage, the RR1 pipeline stage, the RR2 pipeline stage, the EX pipeline stage, the M0 pipeline stage, the M1 pipeline stage, and the WB pipeline stage. The RR0 pipeline stage is used to cache the first decoded signal decoded by the first decoding module, and is also used to initiate read operations on the register file module and the FastRegFile module. In a specific embodiment, the instruction pipeline logic processing module has a feed-forward network (bypass network), and the main function of the bypass network is to send the latest data, register index, and TID (thread ID) information generated by the EALU and WB into the bypass network for subsequent instructions to reference. In the RR0 stage, if the source operand appears on the bypass network, the data on the bypass network needs to be preferentially used as the latest value of the source operand. That is, in the RR0 stage, the source operand is gated to this stage and latched into the RRI when the clock rising edge arrives. In the RR1 stage, if the source operand used by the instruction appears on the bypass network, regardless of whether the valid field of the source operand in the pipeline signal has been set to true, the data on the bypass network is gated to this stage of the pipeline and waits for the pipeline to the next stage EX, and at the same time, the valid field of the source operand is set to true. In the RR2 stage, if the source operand used by the instruction appears on the bypass network, regardless of whether the valid field of the source operand in the pipeline signal has been set to true, the data on the bypass network is gated to this stage of the pipeline and waits for the pipeline to the next stage EX.
[0071] In the EX stage, the main functions performed include: 1. Responsible for arithmetic and logical operations, memory access addresses, jump judgments, target address calculations for branch instructions, byte swap operations, and bit operations; 2. Receiving the packet data output by the InBuffer; 3. The thread decoding module (Agent Dec) is responsible for decoding the instructions in the EX for use as input to the state machine processing module, and also inputting the newly generated data to the state machine module; 4. Read and write access to the CSR (Control Status Register); 5. Sending the latest data read back by the instruction into the bypass network.
[0072] The M0 and M1 stages are the times for coordinating with the Data TCM (DTCM) memory access, and at the same time, sending the respective read data on the pipeline into the bypass channel, where the function of the DTCM is to support the storage part of the load / store instructions of the RISCV standard. This stage is mainly to coordinate with the 3-cycle read process of the DTCM, and at the same time, send the read data in M0 and M1 to the bypass network for subsequent instructions to use.
[0073] The WB stage is the last stage of single-cycle instruction execution. If there is data that needs to be written back to the register file module in this stage, it directly occupies the write port of the register file module with the highest priority.
[0074] The WB stage needs to handle: 1. Send the latest read data on the pipeline to bypass; 2. Write the register file module and Fast RegFile with the highest priority; 3. If the current instruction is an instruction that can be completed on the instruction pipeline without state machine control and is marked as the last instruction of the thread by the instruction fetch module, then it is necessary to send tid and Run0 to the instruction fetch module.
[0075] It should be noted that the pipeline stages in the instruction pipeline logic processing module may not be limited to the 7-stage pipeline introduced above. Those skilled in the art can select appropriate pipeline stages according to specific requirements.
[0076] When the instruction pipeline logic processing module determines that an instruction needs to be processed by the thread decoding module, in the EX stage of the pipeline logic processing module, the instruction is sent to the thread decoding module. The thread decoding module is used to receive the instruction sent by the pipeline logic processing module and perform decoding, and send the decoded instruction to the state machine processing module. The state machine processing module is used to receive the instruction decoded by the thread decoding module and process the instruction.
[0077] Specifically, the instructions processed by the state machine processing module include instructions that need to be queued but the processing cycle is uncertain, instructions that do not need to be queued and the processing cycle is uncertain. The instructions that do not need to be queued and the processing cycle is uncertain can be to read message data from the slave and write the message data to the Fast RegFile module or the register file module. The instructions that need to be queued and the processing cycle is uncertain can be to write the data in the Outbuffer back to the Inbuffer or the register file module, or to send the data in the Outbuffer to the message in-order module for in-order output of the message.
[0078] The second aspect of the present application also provides a chip, which includes the aforementioned message processing system.
[0079] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.
[0080] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims
1. A message processing system, characterized in that, it includes: An instruction acquisition module, configured to acquire a message instruction address, obtain an instruction packet according to the message instruction address, and determine a target message instruction from the instruction packet and send it to an instruction cache queue; the target message instruction is a general instruction or a network acceleration instruction, where the general instruction refers to a RISCV standard instruction and / or an extended instruction, and the network acceleration instruction refers to a custom instruction generated based on the general instruction; An instruction cache queue, configured to cache the target message instruction; A first instruction processing module, configured to receive and decode the general instruction sent by the instruction cache queue, and process the decoded general instruction through an instruction pipeline; A second instruction processing module, configured to receive and decode the network acceleration instruction sent by the instruction cache queue, and process the decoded network acceleration instruction through the instruction pipeline.
2. The system according to claim 1, characterized in that, the second instruction processing module includes: A first instruction decoding module, configured to decode the network acceleration instruction to obtain a first decoded instruction; An instruction pipeline logic processing module, configured to receive the first decoded instruction and send the first decoded instruction to the second instruction decoding module; A second instruction decoding module, configured to receive the first decoded instruction and decode the first decoded instruction to obtain a corresponding access address; An Inbuffer module, configured to store cell data and Meta information of a message, the Inbuffer module is configured to receive and in response to the corresponding access address, output corresponding message data to the instruction pipeline logic processing module, where the Inbuffer module supports the network acceleration instruction to extract data in units of bits; An instruction pipeline logic processing module, configured to receive the first decoded instruction and the data sent by the Inbuffer module, perform processing, and send the processing result to a corresponding target address.
3. The system according to claim 2, characterized in that, the Inbuffer module includes: A Packet Buffer module, configured to store cell data of a message, where the Packet Buffer module supports the network acceleration instruction to extract the stored data in units of bits; A Meta Buffer module, configured to store the Meta information of the message, the Meta Buffer module supports the network acceleration instruction to extract data in units of bits.
4. The system according to claim 2, characterized in that, the second instruction processing module further includes a FastRegFile module, the instruction pipeline logic processing module is further configured to receive the first decoded instruction and in response to the first decoded instruction, send the access address in the first decoded instruction to the Fast RegFile module; The Fast RegFile module is used to receive and respond to the access address output by the instruction pipeline logic processing module, and output the corresponding access address to the Inbuffer module; The Inbuffer module is further used to receive the access address output by the Fast RegFile module, and output the corresponding message data to the instruction pipeline logic processing module; The instruction pipeline logic processing module is used to receive and process the message data.
5. The system according to any one of claims 2-4, wherein, The second instruction processing module further includes a thread decoding module and an Outbuffer module: The thread decoding module is used to receive the instruction sent by the instruction pipeline logic processing module, decode it, and write the decoded message data into the Outbuffer module; The Outbuffer module is used to store the message data written by the thread decoding module.
6. The system according to claim 5, wherein, The system further includes a state machine processing module, wherein, The thread decoding module is used to receive the instruction sent by the instruction pipeline logic processing module, decode it, and send the decoded instruction to the state machine processing module; The state machine processing module is used to receive and process the instruction sent by the thread decoding module, and in response to this instruction, read the corresponding message data from the Outbuffer and send it to the corresponding target address.
7. The system according to claim 6, wherein, The Outbuffer module includes: a New HeaderBuffer module and a New Meta Buffer module, wherein The New Header Buffer module is used to store the head information of the assembled message, The New Meta Buffer module is used to store the Meta information of the assembled message.
8. The system according to claim 7, wherein, The Inbuffer module further includes a Result Buffer module, and the Outbuffer module further includes a Key Buffer module, The Key Buffer module is used to output the content in the Key Buffer to the search matching module for searching in response to the received search instruction; The Result Buffer module is used to receive and save the search matching result returned by the search matching module, wherein, the Result Buffer module supports indexing and extracting data in units of bits.
9. The system according to claim 8, wherein, The first instruction processing module and the second instruction processing module share the first instruction decoding module and the instruction pipeline logic processing module, and the first instruction processing module further includes a register file module; The first instruction decoding module is further used to decode the general instruction to obtain a second decoded instruction; The instruction pipeline logic processing module is further configured to receive the second decoded instruction, and in response to the second decoded instruction, send the access address in the second decoded instruction to the register file module; The register file module is configured to receive the access address sent by the pipeline logic processing module, and in response to the access address, send packet data to the instruction pipeline logic processing module; The instruction pipeline logic processing module is further configured to receive the packet data sent by the register file module, perform processing, and send the processing result to the corresponding target address.
10. A chip, characterized in that, it includes the system according to any one of claims 1-9.