In-pixel AD common circuit for two-stage AD quantization architecture image sensor

Abstract

The invention relates to an in-pixel AD common circuit for a two-stage AD quantization architecture image sensor, and belongs to the technical field of image sensors. The circuit comprises an integrating circuit, a comparator, a counter and a residual voltage output circuit, adjacent pixels share a comparator or a counter, or the comparator and the counter are added; in the integration time, the residual voltage output circuit is closed, the input current is continuously injected, and the whole circuit continuously repeats the circulation process of integration, comparator overturning, counter one adding, self-resetting and integration; when the integration time is over, the counter is locked, and a count value serves as a high-order AD quantization result; and meanwhile, the residual voltage output circuit is opened, and at the moment, the voltage output by the integrating circuit is output to a post-stage circuit to complete AD quantization as a low-order AD quantization result. According to the high-speed image sensor, the pixel size is reduced and the signal transmission time of the high-speed image sensor is shortened through the in-pixel AD common circuit structure of the adjacent pixels.

Description

Technical Field

[0001] The present invention belongs to the technical field of image sensors, and relates to an in-pixel circuit structure of an image sensor adopting a two-stage AD quantization architecture combining in-pixel AD and column-level AD. Background Art

[0002] The photosensitive units of a solid-state image sensor are integrated on a semiconductor substrate to form a pixel array for acquiring image information. According to the photoelectric conversion effect, the reflected light of an external object irradiates the pixel array, and the corresponding pixel units convert the optical signal into an electrical signal, which is processed and stored according to the positional relationship. The image sensor needs to perform AD (analog-to-digital) conversion to output a digital signal, converting the analog signal into a digital signal. In order to photograph a fast-moving target or record the subtle changes of a target within an extremely short time, the demand for ultra-high-speed image sensors is becoming more and more extensive.

[0003] Ultra-high-speed image sensors are positioned for high-speed motion sampling. Currently, there are two mainstream process routes: planar and stacked. The two-dimensional planar type generally uses multiple groups of column-parallel analog-to-digital conversion circuits, dual-slope column-level analog-to-digital conversion circuits, etc. to improve the overall conversion rate. The three-dimensional stacked image sensor structure uses pixel-level parallel analog-to-digital conversion, and all pixels are converted and read out simultaneously.

[0004] Based on the three-dimensional stacked image sensor structure, a two-stage AD quantization architecture combining pixel-level AD and column-level AD can further reduce the time required for AD conversion and increase the output image frame rate.

[0005] Since the exposure time of an ultra-high-speed image sensor is extremely short, pixel-level AD can reduce the overall AD conversion time, but the required circuit area is large, which will cause problems such as too large pixel size, too long charge transfer time, and too long signal transmission distance.

[0006] Aiming at the situation that the existing technology cannot meet or can only partially meet the target usage scenario, it is urgent to design a new in-pixel circuit structure. Summary of the Invention

[0007] In view of this, the purpose of the present invention is to provide an in-pixel AD sharing circuit for an image sensor with a two-stage AD quantization architecture, and solve the problem of the large circuit area of the in-pixel AD of the existing image sensor by sharing the two-stage AD circuit structure of the in-pixel AD by adjacent pixels.

[0008] To achieve the above purpose, the present invention provides the following technical solutions:

[0009] An in-pixel AD sharing circuit for an image sensor with a two-stage AD quantization architecture, comprising an integrating circuit, a comparator, a counter, and a residual voltage output circuit; adjacent pixels share the circuit, that is, share the comparator or the counter, or the comparator plus the counter;

[0010] The integrating circuit converts the continuously injected current into a voltage, and the voltage changes with the integration time;

[0011] The comparator compares the output voltage of the integrating circuit with a reference voltage, and the comparator flips when the output voltage and the reference voltage are the same; when the comparator flips, it outputs a pulse signal to increment the count value of the counter by one; at the same time, it resets the integrating circuit to start integrating again;

[0012] During the integration time, the residual voltage output circuit is turned off, the input current is continuously injected, and the overall circuit continuously repeats the cycle of integration - comparator flip - counter increment - self-reset - integration;

[0013] At the end or before the end of the integration time, the counter is locked, and the count value is used as the high-order AD quantization result; the residual voltage output circuit is turned on, and the output voltage of the integrating circuit at this moment is output to the subsequent circuit to complete AD quantization, serving as the low-order AD quantization result.

[0014] Further, the integrating circuit includes an integrating capacitor, a reset switch, etc.

[0015] Further, the high-order AD quantization result and the low-order AD quantization result are synthesized into a complete AD quantization result through a splicing circuit.

[0016] Further, n adjacent pixels are defined as P 1 、P 2 、…、P n ;The high-order AD quantization results of P 1 ~P n are shared, and the high-order AD quantization result of any one of the pixels P m can be selected as the high-order AD quantization result of P 1 ~P n .

[0017] Further, the self-reset pulses of P 1 ~P n share the self-reset pulse signal of P m .

[0018] Further, the low-order AD quantization results of P 1 ~P n are obtained by quantifying their respective residual voltages in the subsequent circuit.

[0019] Further, the AD quantization result of P m is equal to Pm The high - order AD quantization result of m and the low - order AD quantization result of P are concatenated to obtain.

[0020] The beneficial effects of the present invention are as follows: The present invention adopts a two - stage AD quantization structure including in - pixel AD and column - level AD, sharing the comparator circuit and the counter circuit. Since the difference between the AD quantization results of adjacent pixel signals is generally in the low - order bits, the layout area required by the circuit can be significantly reduced under the condition of sacrificing a small amount of quantization accuracy.

[0021] The present invention can adapt to application scenarios with different pixel sizes and different dynamic ranges by adjusting the number of pixels n, the high - order AD quantization bit number B1, and the low - order AD quantization bit number B2, and has a certain universality.

[0022] Other advantages, objectives, and features of the present invention will be described to some extent in the subsequent specification, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in detail preferably with reference to the accompanying drawings, where:

[0024] Figure 1 is a simplified structural diagram of the in - pixel AD sharing circuit applicable to the two - stage AD quantization architecture image sensor of the present invention;

[0025] Figure 2 is a circuit structure diagram shared by four adjacent pixels;

[0026] Figure 3 is the layout of a single pixel;

[0027] Figure 4 is the layout of the circuit shared by four adjacent pixels. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The following uses specific specific examples to illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention schematically, and the following embodiments and the features in the embodiments can be combined with each other without conflict.

[0029] Among them, the attached drawings are only for illustrative purposes, showing only schematic diagrams rather than physical diagrams, and should not be construed as a limitation on the present invention; for better illustration of the embodiments of the present invention, some components in the attached drawings will be omitted, enlarged or reduced, which does not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the attached drawings may be omitted.

[0030] In the attached drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, they are based on the orientation or positional relationship shown in the attached drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the attached drawings are only for illustrative purposes and should not be construed as a limitation on the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0031] Please refer to Figures 1 to 4 , the basic circuit structure of an in-pixel AD sharing circuit for an image sensor applicable to a two-stage AD quantization architecture provided by the present invention is as Figure 1 shown, including an integration circuit, a comparator, a counter, a residual voltage output circuit, etc., where the comparator and the counter can be shared. The integration circuit includes an integration capacitor, a reset switch, etc.

[0032] The integration circuit converts the continuously injected current into a voltage, and the voltage changes with the integration time.

[0033] The comparator compares the output voltage of the integration circuit with a reference voltage, and the comparator flips when the output voltage is the same as the reference voltage.

[0034] When the comparator flips, it outputs a pulse signal to increment the count value of the counter; at the same time, it resets the integration circuit to start integrating again.

[0035] During the integration time, the residual voltage output circuit is turned off, and the input current is continuously injected. The overall circuit continuously repeats the cycle process of integration - comparator flip - counter increment - self-reset - integration. When the integration time ends or before it ends, the counter is locked, and the count value is used as the high-order AD quantization result and output to the subsequent circuit; the residual voltage output circuit is turned on, and the output voltage of the integration circuit at this moment is output to the subsequent circuit to complete AD quantization and serves as the low-order AD quantization result.

[0036] The high-order AD quantization result and the low-order AD quantization result are synthesized into a complete AD quantization result through a splicing circuit.

[0037] Adjacent pixels can share a comparator circuit and a counter circuit. n adjacent pixels are respectively called P 1 、P 2 、…、P n ; The high-order AD quantization results of P 1 ~P n are shared, and the high-order AD quantization result of any one of the pixels P m can be selected as the high-order AD quantization result of P 1 ~P n . The self-reset pulses of P 1 ~P n share the self-reset pulse signal of P m . The low-order AD quantization results of P 1 ~P n are obtained by quantifying their respective residual voltages in the subsequent circuit. The AD quantization result of P m is equal to the concatenation of the high-order AD quantization result of P m and the low-order AD quantization result of P m .

[0038] Example:

[0039] In this example, the pixel size is 20μm×20μm, and the high-order AD quantization bit number B 1 is 4 bits, and the low-order AD quantization bit number B 2 is 10 bits. The layout area of the integration circuit is 10μm×10μm, the layout area of the comparator is 10μm×8μm, the layout area of the residual voltage output circuit is 8μm×6μm, and the layout area of the counter is 8μm×25μm, as Figure 3 shown.

[0040] The length of the counter in the Y direction has exceeded the length of the pixel in the Y direction. Considering the counter circuit structure and the overall routing of the pixel array, it can only be arranged in one direction. If the high-order AD quantization bit number increases, the length of the counter in the Y direction will further increase. The total area of the integration circuit, comparator, residual voltage output circuit, and counter is 428μm 2 , which is greater than the total pixel area of 400μm 2 , with a ratio of 107%. Considering the power supply and signal routing again, it is normally impossible to implement the circuit layout design, and the pixel size needs to be increased to at least 25μm×25μm or more.

[0041] Set N to 4 and m to 1. Four adjacent pixels are arranged in a 2×2 pattern, sharing the comparator circuit and the counter circuit. The circuit structure diagram is as Figure 2 shown, and the layout is as Figure 4 shown.

[0042] After the shared circuit, the length of the counter in the Y direction is 25μm, which is less than the length of 4 pixels in the Y direction, which is 40μm. The total area of the module circuit layout is equal to the area of the integration circuit × 4 + the area of the residual voltage output circuit × 4 + the area of the comparator × 1 + the area of the counter × 1, which is 872μm 2 , which is less than the total area of 4 pixels, 1600μm 2 , with a ratio of 54.5%, and sufficient space is left for power and signal traces.

[0043] It can be illustrated by this embodiment that by adopting the two-stage AD shared circuit structure proposed by the present invention, the pixel size required under the condition of the same AD quantization bits can be reduced, thereby shortening the signal transmission time of the high-speed image sensor.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the present technical solution, and they should all be covered by the scope of the claims of the present invention.

Claims

1. An intra-pixel AD sharing circuit for an image sensor with a two-stage AD quantization architecture, characterized in that: It includes an integration circuit, a comparator, a counter and a residual voltage output circuit; adjacent pixels share a comparator or a counter, or a comparator plus a counter; The integration circuit converts the continuously injected current into a voltage, and the voltage varies with the integration time; The comparator compares the output voltage of the integration circuit with the reference voltage. When the output voltage and the reference voltage are the same, the comparator flips. When the comparator flips, it outputs a pulse signal to increase the counter count by one. At the same time, the integration circuit is reset to restart integration. During the integration time, the residual voltage output circuit is closed, the input current is continuously injected, and the overall circuit continuously repeats the cycle of integration-comparator flip-counter addition-self-reset-integration; When the integration time ends or before it ends, the counter is locked and the count value is used as the high-bit AD quantization result; the residual voltage output circuit is turned on, and at this moment the output voltage of the integration circuit is output to the subsequent circuit to complete AD quantization as the low-bit AD quantization result.

2. The intra-pixel AD sharing circuit according to claim 1, characterized in that: The integration circuit includes an integration capacitor and a reset switch.

3. The intra-pixel AD sharing circuit according to claim 1, characterized in that: The high-bit AD quantization result and the low-bit AD quantization result are synthesized into a complete AD quantization result through a splicing circuit.

4. The intra-pixel AD sharing circuit according to claim 1, characterized in that: Define n adjacent pixels as P1, P2, ..., P n ; P1~P n The high-bit AD quantization results are shared, and any pixel P is selected m The high-bit AD quantization result is used as P1~P n The high-bit AD quantization result.

5. The intra-pixel AD sharing circuit according to claim 4, characterized in that: P1~P n The self-reset pulse shares P m Self-reset pulse signal.

6. The intra-pixel AD sharing circuit according to claim 4, characterized in that: P1~P n The low-bit AD quantization results are quantized in the subsequent circuit using their respective residual voltages.

7. The intra-pixel AD sharing circuit according to claim 6, characterized in that: P m The AD quantification result is equal to P m The high-order AD quantization results and P m The low-bit AD quantization results are spliced ​​together.

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