Formation method of semiconductor structure and storage structure

Abstract

A method for forming a semiconductor structure and a storage structure, the method comprising: forming a substrate comprising: first gate layers extending in a first direction, at least two first gate layers being arranged in a second direction; the dielectric layer is located on the first gate layer; forming a second gate material layer on the substrate; spin-coating a filling layer on the second gate material layer; patterning the filling layer to expose a part of the second gate material layer; and etching the exposed second gate material layer by taking the patterned filling layer as a mask to form a second gate layer which is located on the dielectric layer. The filling layer is formed in a spin coating mode, the filling layer has considerable fluidity, the filling capacity of the filling layer is higher, sufficient filling of the grooves between the adjacent first gate layers can be effectively guaranteed, the patterning precision of the filling layer can be effectively guaranteed, and the morphology and quality of the formed second gate layer can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure and a storage structure. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. For storage devices, people's requirements for storage density and read / write speed of storage devices are becoming higher and higher.

[0003] With the development of mainstream process technology, the storage structure with split gate has attracted more and more attention. However, the split gate structure is more complex and requires higher process difficulty. In the storage structure, the morphology and performance of the floating gate are often more prone to problems. Summary of the invention

[0004] The problem solved by the present invention is how to improve the morphology and quality of the second gate structure in the storage structure.

[0005] In order to solve the above problems, the present invention provides a method for forming a storage structure, comprising:

[0006] A substrate is formed, the substrate comprising: a first gate layer, the first gate layer extends along a first direction, and at least two first gate layers are arranged along a second direction; a dielectric layer, the dielectric layer is located on the first gate layer; a second gate material layer is formed on the substrate; a filling layer is spin-coated on the second gate material layer; the filling layer is patterned to expose a portion of the second gate material layer; the patterned filling layer is used as a mask to etch the exposed second gate material layer to form a second gate layer, the second gate layer is located on the dielectric layer.

[0007] Optionally, the step of spin-coating a filling layer on the second gate material layer includes: spin-coating a filling layer on the second gate material layer, wherein the filling layer fills the grooves between adjacent first gate layers and extends onto the dielectric layer.

[0008] Optionally, in the step of spin coating a filling layer on the second gate material layer, a depth of a groove between adjacent first gate layers is greater than 0.1 μm.

[0009] Optionally, in the step of spin coating a filling layer on the second gate material layer, a depth-to-width ratio of trenches between adjacent first gate layers is greater than 0.5.

[0010] Optionally, in the step of spin coating a filling layer on the second gate material layer, a thickness of the filling layer on the dielectric layer is in the range of 1500Å to 4000Å.

[0011] Optionally, in the step of spin coating a filling layer on the second gate material layer, the filling layer is a bottom anti-reflective coating.

[0012] Optionally, the method further includes: after spin-coating a filling layer on the second gate material layer and before patterning the filling layer, forming a low-temperature hard mask layer on the filling layer.

[0013] Optionally, the step of forming a low-temperature hard mask layer on the filling layer includes: forming the low-temperature hard mask layer on the filling layer at a process temperature lower than 250 degrees Celsius.

[0014] Optionally, in the step of forming a low-temperature hard mask layer on the filling layer, the low-temperature hard mask layer is a low-temperature oxide layer.

[0015] Optionally, in the step of forming a low-temperature hard mask layer on the filling layer, the thickness of the low-temperature hard mask layer is in the range of 50Å to 300Å.

[0016] Optionally, the step of patterning the filling layer includes: forming a patterned photoresist on the filling layer, wherein the patterned photoresist is located on a portion of the filling layer; and performing etching using the patterned photoresist as a mask to form a patterned filling layer.

[0017] Optionally, in the step of etching the exposed second gate material layer to form the second gate layer, the exposed second gate material layer is etched until the substrate is exposed.

[0018] Optionally, in the step of using the patterned filling layer as a mask to etch the exposed second gate material layer to form the second gate layer, there is a remaining filling layer on the second gate layer; the formation method also includes: removing the remaining filling layer.

[0019] Optionally, the step of removing the remaining filling layer includes: removing the remaining filling layer by ashing.

[0020] Correspondingly, the present invention also provides a storage structure, which is formed by the forming method of the present invention.

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0022] In the technical solution of the present invention, after forming the second gate material layer on the substrate, a filling layer is spin-coated on the second gate material layer; after patterning the filling layer, the second gate material layer is etched using the patterned filling layer as a mask to form a second gate layer. The filling layer is formed by spin coating, and the filling layer has considerable fluidity, and the filling ability of the filling layer is stronger, which can effectively ensure the full filling of the grooves between adjacent first gate layers, can effectively ensure the accuracy of the patterning of the filling layer, and can effectively improve the morphology and quality of the formed second gate layer.

[0023] In an optional solution of the present invention, after the filling layer is spin-coated and before the filling layer is patterned, a low-temperature hard mask layer is formed on the filling layer. The provision of the low-temperature hard mask layer can effectively improve the accuracy of pattern transfer, can effectively reduce the thickness of the filling layer and the photoresist to reduce the etching amount, and is conducive to improving process reliability and stability.

[0024] In an optional solution of the present invention, the filling layer is a bottom anti-reflection layer, and the low-temperature hard mask layer is a low-temperature oxide layer. The combination of the bottom anti-reflection layer and the low-temperature oxide layer is stable and reliable, and can effectively reduce process risks and improve process stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic cross-sectional structure diagram of an intermediate structure in a storage structure forming method;

[0026] Figures 2 to 13 It is a structural schematic diagram of each step in some embodiments of the storage structure forming method of the present invention. DETAILED DESCRIPTION

[0027] As can be seen from the background technology, the morphology and performance of the floating gate in the storage structure of the prior art are prone to problems. Now, the causes of the morphology and performance problems are analyzed in combination with an intermediate structure in the formation process of a floating gate structure:

[0028] like Figure 1 As shown, the formation process of the floating gate structure includes: forming a base, the base includes: a substrate 10; a selection gate layer 11 located on the substrate 10, the selection gate layer 11 extends along a first direction, and at least two selection gate layers 11 are arranged along a second direction; a dielectric layer 12 located on the selection gate layer 11; forming a floating gate material layer 14 on the base; forming a filling layer 15 on the floating gate material layer 14; and forming a hard mask layer 16 on the filling layer 15.

[0029] Then, the hard mask layer 16 and the filling layer 15 are patterned; the floating gate material layer 14 is etched using the patterned hard mask layer 16 and the filling layer 15 as masks, thereby forming a floating gate layer on the selection gate layer 11 .

[0030] In the process of forming the filling layer 15 on the floating gate material layer 14 , a filling layer of an amorphous carbon film (APF) is formed on the floating gate material layer 14 by deposition.

[0031] As device density increases, the depth of the trenches between adjacent select gate layers becomes larger (the depth of the trenches can reach more than 0.1 μm), and the aspect ratio becomes larger (the aspect ratio can reach more than 0.5). It is more difficult to fill trenches with large aspect ratios. Amorphous carbon-filled trenches formed by deposition are prone to hollow depressions (such as Figure 1 as shown in the dashed box 20).

[0032] The appearance of voids and depressions will affect the flatness of the subsequently formed photoresist layer, make the critical dimension (CD) of the formed photoresist larger, and affect the protection of the floating gate layer by the filling layer, affecting the etching effect; and during the photolithography rework process, the appearance of voids and depressions can easily cause rework anomalies caused by abnormal removal of the filling layer, thereby easily causing unnecessary wafer losses.

[0033] In order to solve the technical problem, the present invention provides a method for forming a storage structure, comprising:

[0034] A substrate is formed, the substrate comprising: a first gate layer, the first gate layer extends along a first direction, and at least two first gate layers are arranged along a second direction; a dielectric layer, the dielectric layer is located on the first gate layer; a second gate material layer is formed on the substrate; a filling layer is spin-coated on the second gate material layer; the filling layer is patterned to expose a portion of the second gate material layer; the patterned filling layer is used as a mask to etch the exposed second gate material layer to form a second gate layer, the second gate layer is located on the dielectric layer.

[0035] According to the technical solution of the present invention, the filling layer is formed by spin coating, the filling layer has considerable fluidity, and the filling ability of the filling layer is stronger, which can effectively ensure the full filling of the grooves between adjacent first gate layers, can effectively ensure the accuracy of the patterning of the filling layer, and can effectively improve the morphology and quality of the formed second gate layer.

[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] refer to Figures 2 to 13 , showing a schematic structural diagram of each step in some embodiments of the storage structure forming method of the present invention.

[0038] refer to Figure 2 , combined with reference Figure 3 and Figure 4 ,in Figure 3 yes Figure 2 The schematic diagram of the cross-section structure at the position of the dotted line A1A2, Figure 4 yes Figure 2 Schematic diagram of the cross-sectional structure at the position of the middle dotted line B1B2.

[0039] First, a substrate is formed, the substrate comprising: a first gate layer 111 extending along a first direction, at least two first gate layers 111 arranged along a second direction; and a dielectric layer 112 located on the first gate layer 111 .

[0040] The substrate is used to provide a process basis for subsequent processes. The first gate layer 111 is used to form a gate electrode of a selection gate.

[0041] Specifically, in a plane parallel to the surface of the substrate, the first gate layer 111 is in a strip shape, the first gate layer 111 extends along a first direction, and at least two first gate layers 111 are arranged along a second direction.

[0042] For example, Figure 2 As shown, in some embodiments, the first gate layer 111 is in the shape of a long strip extending along a first direction, and at least two first gate layers 111 are arranged in parallel along a second direction, wherein the second direction and the first direction are perpendicular to each other.

[0043] Specifically, the first gate layer 111 is used to form a gate electrode of a selection gate, and the material of the first gate layer 111 is a conductive material. For example, Figure 2 In some of the embodiments shown, the material of the first gate layer 111 is polysilicon.

[0044] The dielectric layer 112 is used to achieve electrical insulation between the first gate layer 111 and subsequent structures.

[0045] Specifically, in a plane parallel to the substrate surface, the dielectric layer 112 is in a strip shape, the dielectric layer 112 extends along a first direction, and the dielectric layer 112 and the first gate layer 111 are arranged in a one-to-one correspondence. The material of the dielectric layer 112 is an insulating material. For example, the material of the dielectric layer 112 is silicon oxide.

[0046] It should be noted that the base also includes: a substrate 101 (such as Figure 3 and Figure 4 As shown in ), the first gate layer 111 is located on the substrate 101; the active region (as Figure 2As shown in the red dashed box, the active region is located in the substrate 101 between the adjacent first gate layers 111 and the second gate layer ( Figure 2 The substrate 101 is formed in the substrate 101 below the photoresist PR.

[0047] In addition, if Figure 3 As shown, the substrate further includes: a sidewall 113, the sidewall 113 is located on the sidewalls of the first gate layer 111 and the dielectric layer 112; and a high temperature oxide layer 114, the high temperature oxide layer 114 is located on the sidewall 113 and the dielectric layer 112. In addition, the high temperature oxide layer 114 on the adjacent first gate layers 111 is extended and connected. Figure 1 As shown, the high temperature oxide layer 114 on the adjacent first gate layers 111 also extends onto and is connected to the substrate 101 between the adjacent first gate layers 111 .

[0048] The substrate 101 may be a silicon substrate, and the material of the substrate 101 is silicon. For example, the material of the substrate 101 may be selected from single crystal silicon, polycrystalline silicon or amorphous silicon. In other embodiments, the material of the substrate may also be selected from silicon, germanium, gallium arsenide or silicon germanium compound; the substrate may also be selected from a structure having an epitaxial layer or a silicon structure on an epitaxial layer; the substrate may also be other semiconductor materials.

[0049] The sidewall 113 may be a sidewall of a laminated structure; for example, the sidewall 113 may be a laminated structure, and the sidewall 113 may include: a nitride layer and an oxide layer; the sidewall 113 cooperates with the high temperature oxide layer 114 to form a sidewall of an oxide-nitride-oxide structure, that is, an ONO structure. In addition, the material of the high temperature oxide layer 114 may be high temperature silicon oxide.

[0050] By way of example, the steps of forming a substrate include: providing a substrate 101; forming a stack of a first gate layer 111 and a dielectric layer 112 on the substrate 101, wherein the stack of the first gate layer 111 and the dielectric layer 112 is in the shape of a long strip extending along a first direction in a plane parallel to the surface of the substrate 101, and at least two stacks of the first gate layer 111 and the dielectric layer 112 are arranged along a second direction; forming a sidewall 113 on the sidewall of the stack of the first gate layer 111 and the dielectric layer 112; and forming a high-temperature oxide layer 114 on the substrate, the sidewall 113 and the dielectric layer 112 exposed by the dielectric layer 112.

[0051] It should be noted that if Figure 4 As shown, the substrate further includes: an isolation structure 102, the isolation structure 102 is located in the substrate 101 below the first gate layer 111. The isolation structure 102 is configured to achieve electrical isolation between adjacent active regions. The isolation structure 102 is located in the active region (such as Figure 2The area outside the red dashed box.

[0052] Continue to refer Figures 2 to 4 After forming a substrate, a second gate material layer 120 is formed on the substrate.

[0053] The second gate material layer 120 is used to provide a basis for forming a second gate layer.

[0054] Specifically, the second gate material layer 120 is used to form a floating gate, and the second gate layer is a polysilicon layer. The material of the second gate material layer 120 is the same as that of the first gate layer 111 , both of which are polysilicon.

[0055] Specifically, the step of forming the second gate material layer 120 on the substrate includes: forming the second gate material layer 120 on the substrate by deposition, wherein the deposition method can be at least one of chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0056] The second gate material layer 120 covers the entire substrate. The second gate material layer 120 is located on the stack of the substrate 101, the first gate layer 111 and the dielectric layer 112. The substrate also has a substrate where the dielectric layer 112 is exposed, a sidewall 113 and a high temperature oxide layer 114 on the dielectric layer 112; the second gate material layer 120 is located on the high temperature oxide layer 114.

[0057] like Figures 2 to 4 As shown, next, a filling layer 130 is spin-coated on the second gate material layer 120 .

[0058] The filling layer 130 is used to fill the trenches between adjacent first gate layers 111 , thereby providing a highly flat process surface for subsequent processes.

[0059] The filling layer 130 is formed by spin coating, and has considerable fluidity. The filling layer 130 has a stronger filling ability, can effectively ensure the full filling of the grooves between adjacent first gate layers 111, can effectively improve the photolithography accuracy, can effectively ensure the accuracy of the patterning of the filling layer 130, and can effectively improve the morphology and quality of the formed second gate layer.

[0060] In some embodiments, in the step of spin coating the filling layer 130 on the second gate material layer 120, the depth d of the groove between adjacent first gate layers 111 is greater than 0.1 μm. Specifically, the depth d of the groove between adjacent first gate layers 111 is the distance between the surface of the second gate material layer 120 on the top of the dielectric layer 112 and the surface of the second gate material layer 120 on the substrate 101 between adjacent first gate layers 111 in the direction perpendicular to the substrate surface.

[0061] In some embodiments, in the step of spin coating the filling layer 130 on the second gate material layer 120, the aspect ratio of the grooves between adjacent first gate layers 111 is greater than 0.5. The depth-to-width ratio of the grooves between adjacent first gate layers 111 is large, and it is difficult to fill them; forming the filling layer 130 by spin coating can ensure that the filling layer 130 fully fills the grooves, avoids the occurrence of hollow depressions in the filling layer 130, and the filling layer 130 has a highly flat surface.

[0062] In some embodiments of the present invention, the step of spin coating a filling layer 130 on the second gate material layer 120 includes: spin coating a filling layer 130 on the second gate material layer 120 , wherein the filling layer 130 fills the grooves between adjacent first gate layers 111 and extends onto the dielectric layer 112 .

[0063] In addition to filling the grooves between adjacent first gate layers 111 to provide a highly flat process surface, the filling layer 130 can also serve as an etching mask in subsequent processes to protect the structure underneath; extending the filling layer 130 to the top of the dielectric layer 112 on the first gate layer 111 can effectively ensure the masking effect of the filling layer 130.

[0064] In some embodiments, in the step of spin coating the filling layer 130 on the second gate material layer 120, the thickness h of the filling layer 130 on the dielectric layer 112 (eg Figure 3 ) is in the range of 1500Å to 4000Å. The thickness of the filling layer 130 on the dielectric layer 112 is appropriate, which can control the process risk while ensuring the protection of the filling layer 130 to the underlying structure; and because the filling layer 130 is formed by spin coating, the filling layer 130 has a good filling ability, and the thickness of the filling layer 130 on the dielectric layer 112 is small, which can effectively reduce the etching amount in the subsequent process, which is conducive to improving the accuracy of pattern transfer.

[0065] In some embodiments of the present invention, in the step of spin coating the filling layer 130 on the second gate material layer 120, the filling layer 130 is a bottom anti-reflection coating (BARC). Specifically, the filling layer 130 is a bottom anti-reflection coating; the bottom anti-reflection coating can be formed by a fluid precursor, can be formed by spin coating, and has good filling ability.

[0066] Continue to refer Figures 2 to 4 In some embodiments of the present invention, the formation method further includes: after spin coating the filling layer 130 on the second gate material layer 120 and before patterning the filling layer 130 , forming a low-temperature hard mask layer 140 on the filling layer 130 .

[0067] The low temperature hard mask layer 140 is used to cooperate with the filling layer 130 and act as a mask in the subsequent etching process to protect the structure below it. The setting of the low temperature hard mask layer 140 can effectively improve the accuracy of pattern transfer, can effectively reduce the thickness of the filling layer 130 and the photoresist to reduce the etching amount, and is conducive to improving the process reliability and stability.

[0068] In some embodiments, the step of forming the low temperature hard mask layer 140 on the filling layer 130 includes: forming the low temperature hard mask layer 140 on the filling layer 130 at a process temperature lower than 250 degrees Celsius. Controlling the process temperature for forming the low temperature hard mask layer 140 can effectively reduce the impact of the process of forming the low temperature hard mask layer 140 on the filling layer 130, and can effectively prevent the filling layer 130 from being damaged.

[0069] In some embodiments, in the step of forming the low-temperature hard mask layer 140 on the filling layer 130, the low-temperature hard mask layer 140 is a low-temperature oxide layer. The low-temperature oxide layer is easy to obtain in the semiconductor manufacturing process, and the filling layer 130 is a bottom anti-reflection layer. The combination of the bottom anti-reflection layer and the low-temperature oxide layer is stable and reliable, which can effectively reduce process risks and improve process stability.

[0070] In some embodiments, in the step of forming the low temperature hard mask layer 140 on the filling layer 130, the thickness of the low temperature hard mask layer 140 is in the range of 50Å to 300Å. The thickness of the low temperature hard mask layer 140 is suitable to ensure its masking function while controlling the etching amount, saving materials, and ensuring process reliability and stability.

[0071] Combined with reference Figures 5 to 8 ,in Figure 5 and Figure 3 The cross-section position corresponds to Figure 6 and Figure 4 The cross-section position corresponds to, Figure 7 and Figure 3 The cross-section position corresponds to Figure 8 and Figure 4 The cross-section position corresponds.

[0072] After the filling layer 130 is spin-coated, the filling layer 130 is patterned to expose a portion of the second gate material layer 120 .

[0073] The filling layer 130 is patterned to define the position and size of the second gate layer to be formed. The patterned filling layer 130 is located on a portion of the second gate material layer 120, exposing the surface of the remaining second gate material layer 120.

[0074] In some embodiments of the present invention, the step of patterning the filling layer 130 includes: Figures 2 to 4 As shown, a patterned photoresist PR is formed on the filling layer 130, and the patterned photoresist PR is located on a portion of the filling layer 130; Figures 5 to 8 As shown, etching is performed using the patterned photoresist PR as a mask to form a patterned filling layer 130 .

[0075] Specifically, the step of forming a patterned photoresist PR on the filling layer 130 includes: spin coating the photoresist on the filling layer 130; and exposing and developing the photoresist to form the patterned photoresist PR.

[0076] Specifically, the step of etching using the patterned photoresist PR as a mask to form a patterned filling layer 130 includes: using the patterned photoresist PR as a mask, etching the low-temperature hard mask layer 140 and the filling layer 130 in sequence until the second gate material layer 120 is exposed, thereby forming a patterned filling layer 130.

[0077] In some embodiments, the thickness of the photoresist PR is appropriate to the thickness of the low-temperature hard mask layer 140, so that when etching is performed using the patterned photoresist PR as a mask to form a patterned filling layer 130, there is a remainder of the low-temperature hard mask layer 140 below the patterned photoresist PR, and when the patterned filling layer 130 is formed, there is also a remainder of the low-temperature hard mask layer 140 on the patterned filling layer 130.

[0078] Specifically, in the step of sequentially etching the low-temperature hard mask layer 140 and the filling layer 130 using the patterned photoresist PR as a mask, the low-temperature hard mask layer 140 and the filling layer 130 may be sequentially etched by dry etching.

[0079] For example, the step of sequentially etching the low-temperature hard mask layer 140 and the filling layer 130 includes: etching the low-temperature hard mask layer 140 using an etching gas including carbon tetrafluoride; and etching the filling layer 130 using an etching gas including oxygen.

[0080] It should be noted that Figure 2 Only the first gate layer 111 and the photoresist are shown, and other structures are hidden for clarity.

[0081] refer to Figures 9 to 13 ,in Fig. 9 and Figure 3 The cross-section position corresponds to Fig.10 and Figure 4 The cross-section position corresponds to, Fig.11 yes Figure 1 Schematic diagram of the top view structure in the corresponding direction, Fig.12 yes Fig.11 The cross-sectional structure diagram at the position of the dotted line C1C2, Fig.13 yes Fig.11 Schematic diagram of the cross-sectional structure at the position of the middle dotted line D1D2.

[0082] Next, the patterned filling layer 130 is used as a mask to etch the exposed second gate material layer 120 to form a second gate layer 121 . The second gate layer 121 is located on the dielectric layer 112 .

[0083] The step of etching the second gate material layer 120 is used to form a second gate layer 121 ; the second gate layer 121 is used to form a floating gate.

[0084] In some embodiments of the present invention, in the step of etching the exposed second gate material layer 120 to form the second gate layer 121, the exposed second gate material layer 120 is etched until the substrate is exposed. Figures 2 to 13 In some of the embodiments shown, the substrate comprises a substrate with a dielectric layer 112 exposed, a side wall 113, and a high temperature oxide layer 114 on the dielectric layer 112; in the step of etching the exposed second gate material layer 120 to form a second gate layer 121, the exposed second gate material layer 120 is etched until the high temperature oxide layer 114 is exposed.

[0085] In some embodiments, the patterned filling layer 130 is used as a mask to etch the exposed second gate material layer 120 to form the second gate layer 121. When the exposed second gate material layer 120 is etched until the substrate is exposed, the second gate layer 121 still has a remaining filling layer 130.

[0086] In some embodiments, when a patterned filling layer 130 is formed, a remaining low-temperature hard mask layer 140 is also present on the patterned filling layer 130; in the step of etching the exposed second gate material layer 120 to form a second gate layer 121, the remaining low-temperature hard mask layer 140 and the patterned filling layer 130 are used as masks to etch the exposed second gate material layer 120 to form a second gate layer 121.

[0087] In some embodiments, the remaining low-temperature hard mask layer 140 and the patterned filling layer 130 are used as masks to etch the exposed second gate material layer 120 to form the second gate layer 121, and the remaining low-temperature hard mask layer 140 is simultaneously etched to be removed; when the substrate is exposed and the second gate layer 121 is formed, the remaining low-temperature hard mask layer 140 on the formed second gate layer 121 is removed to expose the filling layer 130 on the formed second gate layer 121.

[0088] Specifically, in the step of etching the exposed second gate material layer 120 using the patterned filling layer 130 as a mask to form the second gate layer 121 , the exposed second gate material layer 120 may be etched by dry etching to form the second gate layer 121 .

[0089] For example, the step of etching the exposed second gate material layer 120 includes: using a process gas including carbon tetrafluoride to remove the natural oxide layer on the surface of the second gate material layer 120; using an etching gas including hydrogen bromide, chlorine, sulfur hexafluoride and oxygen to etch the exposed second gate material layer 120.

[0090] like Figures 11 to 13 As shown, in some embodiments of the present invention, the forming method further comprises: removing the remaining filling layer 130. The filling layer 130 is removed to expose the second gate layer 121, thereby providing a basis for subsequent processes.

[0091] In some embodiments, the step of removing the remaining filling layer 130 includes: removing the remaining filling layer 130 by ashing. The filling layer 130 is a bottom anti-reflection coating, and for example, the filling layer 130 is an organic bottom anti-reflection layer. Removing the remaining filling layer 130 by ashing can effectively reduce the impact of removing the remaining filling layer 130 on other structures, and can effectively improve process stability and reliability.

[0092] It should be noted that if Fig.11As shown, in some embodiments of the present invention, the first gate layer 111 is in the shape of an elongated strip extending along a first direction, and at least two first gate layers 111 are arranged in parallel along a second direction; the second gate layer 121 is in the shape of an elongated strip, and the second gate layer 121 extends along the second direction, spanning the at least two first gate layers 111, and at least two second gate layers 121 are arranged in parallel along the first direction.

[0093] Correspondingly, the present invention also provides a semiconductor structure, which is formed by the forming method of the present invention.

[0094] Specifically, the semiconductor structure includes: a substrate, the substrate includes: a first gate layer, the first gate layer extends along a first direction, and at least two first gate layers are arranged along a second direction; a dielectric layer, the dielectric layer is located on the first gate layer; a second gate layer, the second gate layer is located on the dielectric layer, the second gate layer extends along the second direction, spanning the at least two first gate layers, and at least two second gate layers are arranged in parallel along the first direction; a filling layer, the filling layer is located on the second gate layer, and the filling layer is formed by spin coating.

[0095] The semiconductor structure is formed by the forming method of the present invention, and the specific technical solution of the semiconductor structure can refer to the embodiments of the aforementioned forming method.

[0096] In summary, after forming the second gate material layer on the substrate, a filling layer is spin-coated on the second gate material layer; after patterning the filling layer, the second gate material layer is etched using the patterned filling layer as a mask to form the second gate layer. The filling layer is formed by spin coating, and the filling layer has considerable fluidity, and the filling ability of the filling layer is stronger, which can effectively ensure the full filling of the grooves between adjacent first gate layers, can effectively ensure the accuracy of the patterning of the filling layer, and can effectively improve the morphology and quality of the formed second gate layer.

[0097] Moreover, after the filling layer is spin-coated and before the filling layer is patterned, a low-temperature hard mask layer is formed on the filling layer. The provision of the low-temperature hard mask layer can effectively improve the accuracy of pattern transfer, can effectively reduce the thickness of the filling layer and the photoresist to reduce the etching amount, and is conducive to improving process reliability and stability.

[0098] In addition, the filling layer is a bottom anti-reflection layer, and the low-temperature hard mask layer is a low-temperature oxide layer. The combination of the bottom anti-reflection layer and the low-temperature oxide layer is stable and reliable, which can effectively reduce process risks and improve process stability.

[0099] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a storage structure, characterized in that: include: Forming a substrate, the substrate comprising: a first gate layer, the first gate layer extending along a first direction, at least two first gate layers arranged along a second direction; a dielectric layer, the dielectric layer being located on the first gate layer; forming a second gate material layer on the substrate; Spin coating a filling layer on the second gate material layer; Patterning the filling layer to expose a portion of the second gate material layer; The patterned filling layer is used as a mask to etch the exposed second gate material layer to form a second gate layer, wherein the second gate layer is located on the dielectric layer.

2. The forming method according to claim 1, characterized in that: The step of spin coating a filling layer on the second gate material layer includes: spin coating a filling layer on the second gate material layer, wherein the filling layer fills the grooves between adjacent first gate layers and extends onto the dielectric layer.

3. The forming method according to claim 2, characterized in that: In the step of spin coating a filling layer on the second gate material layer, the depth of the trenches between adjacent first gate layers is greater than 0.1 μm.

4. The forming method according to claim 2, characterized in that: In the step of spin coating a filling layer on the second gate material layer, the aspect ratio of the trenches between adjacent first gate layers is greater than 0.

5.

5. The forming method according to claim 2, characterized in that: In the step of spin coating a filling layer on the second gate material layer, the thickness of the filling layer on the dielectric layer is in the range of 1500Å to 4000Å.

6. The forming method according to claim 1, characterized in that: In the step of spin coating a filling layer on the second gate material layer, the filling layer is a bottom anti-reflection coating.

7. The forming method according to claim 1, characterized in that: Also includes: After the filling layer is spin-coated on the second gate material layer and before the filling layer is patterned, a low-temperature hard mask layer is formed on the filling layer.

8. The forming method according to claim 7, characterized in that: The step of forming a low-temperature hard mask layer on the filling layer includes: forming the low-temperature hard mask layer on the filling layer at a process temperature lower than 250 degrees Celsius.

9. The forming method according to claim 7, characterized in that: In the step of forming a low-temperature hard mask layer on the filling layer, the low-temperature hard mask layer is a low-temperature oxide layer.

10. The forming method according to claim 7, characterized in that: In the step of forming a low-temperature hard mask layer on the filling layer, the thickness of the low-temperature hard mask layer is in the range of 50Å to 300Å.

11. The forming method according to claim 1, characterized in that: The step of patterning the filling layer comprises: forming a patterned photoresist on the filling layer, wherein the patterned photoresist is located on a portion of the filling layer; Etching is performed using the patterned photoresist as a mask to form a patterned filling layer.

12. The forming method according to claim 1, characterized in that: The exposed second gate material layer is etched to form the second gate layer, and the exposed second gate material layer is etched until the substrate is exposed.

13. The forming method according to claim 1, characterized in that: In the step of etching the exposed second gate material layer using the patterned filling layer as a mask to form a second gate layer, the second gate layer also has a remaining filling layer; The forming method further includes: removing the remaining filling layer.

14. The forming method according to claim 13, characterized in that: The step of removing the remaining filling layer includes: removing the remaining filling layer by ashing.

15. A semiconductor structure, characterized in that: The storage structure is formed by the forming method according to any one of claims 1 to 14.

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