Flash memory device structure and simulation method thereof

Abstract

The invention discloses a flash memory device structure and a simulation method thereof, and relates to the technical field of semiconductor storage. The storage string comprises a top selection tube, a virtual storage unit, at least one storage unit, a virtual storage unit and a bottom selection tube which are vertically stacked in sequence; each of the top selection tube, the virtual storage unit, the storage unit and the bottom selection tube comprises a filling layer, a polycrystalline silicon channel layer, a tunneling layer, a charge trapping layer, a barrier layer, a ferroelectric layer and a metal gate which are sequentially arranged from inside to outside; a drain electrode close to the top selection tube and a source electrode close to the bottom selection tube are arranged at the two ends of the polycrystalline silicon channel layer respectively; and a non-conductive insulating layer is arranged between the adjacent metal gates. Based on the scheme, the reliability of the flash memory is improved by introducing the ferroelectric layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor storage technology, and in particular to a flash memory device and a simulation method thereof. Background Art

[0002] Flash memory devices are a type of storage medium widely used in electronic devices. However, as the requirements for storage capacity and speed of electronic devices continue to increase, traditional flash memory structures have gradually exposed limitations in programming efficiency, erasing efficiency and storage window due to the need for higher operating voltages and longer times during programming and erasing operations and a smaller storage window, resulting in lower flash memory reliability. Summary of the invention

[0003] The invention provides a flash memory device structure and a simulation method thereof, which are used to improve the technical problem of low reliability of a traditional flash memory structure.

[0004] A first aspect of the present invention provides a flash memory device structure, comprising: a storage string;

[0005] The storage string includes a top selection tube, a dummy storage unit, at least one storage unit, a dummy storage unit, and a bottom selection tube stacked vertically in sequence;

[0006] The top selection tube, the dummy storage unit, the storage unit and the bottom selection tube all include a filling layer, a polysilicon channel layer, a tunneling layer, a charge trapping layer, a blocking layer, a ferroelectric layer and a metal gate which are sequentially arranged from the inside to the outside;

[0007] The two ends of the polysilicon channel layer are respectively provided with a drain electrode close to the top selection tube and a source electrode close to the bottom selection tube;

[0008] A non-conductive insulating layer is disposed between adjacent metal gates.

[0009] Optionally, the thickness of the ferroelectric layer is 6 nm, the thickness of the blocking layer is 4 nm, the thickness of the charge trapping layer is 5 nm, the thickness of the tunneling layer is 5 nm, the thickness of the polysilicon channel is 10 nm, and the thickness of the filling layer is 15 nm;

[0010] The lateral gate length of the metal gate is 28 nm, the longitudinal gate length of the metal gate is 40 nm, and the gate spacing between adjacent metal gates is 28 nm;

[0011] The electron defect concentration and hole defect concentration of the charge trapping layer are both .

[0012] Optionally, there are multiple storage units, and the multiple storage units are stacked vertically in sequence.

[0013] Optionally, the source electrode and the drain electrode are provided with a concentration of N-type doping;

[0014] The polysilicon channel layer is provided with a concentration of N-type doping.

[0015] Optionally, there are multiple top selection tubes and / or multiple bottom selection tubes.

[0016] Optionally, the tunneling layer, the barrier layer and the filling layer are all made of silicon dioxide material;

[0017] The charge trapping layer is made of silicon nitride material;

[0018] The ferroelectric layer is made of silicon-doped hafnium oxide material.

[0019] A second aspect of the present invention provides a method for simulating a flash memory device structure, comprising:

[0020] Model the flash memory device structure through TCAD tools and determine the simulation model;

[0021] After selecting a physical model from the physical model repository preset by the TCAD tool, electrical performance simulation is performed based on the simulation model to determine simulation test data.

[0022] A third aspect of the present invention provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the simulation method of the flash memory device structure as described in any one of the above items.

[0023] A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed, implements the simulation method for the flash memory device structure as described in any one of the above items.

[0024] A fifth aspect of the present invention provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements a method for simulating a flash memory device structure as described in any one of the above.

[0025] It can be seen from the above technical solutions that the present invention has the following advantages:

[0026] A flash memory device structure provided in the first aspect of the present invention comprises: a storage string; the storage string comprises a top selection tube, a virtual storage unit, at least one storage unit, a virtual storage unit and a bottom selection tube which are vertically stacked in sequence; the top selection tube, the virtual storage unit, the storage unit and the bottom selection tube all comprise a filling layer, a polysilicon channel layer, a tunneling layer, a charge trapping layer, a blocking layer, a ferroelectric layer and a metal gate which are arranged in sequence from the inside to the outside; a drain electrode close to the top selection tube and a source electrode close to the bottom selection tube are respectively arranged at both ends of the polysilicon channel layer; a non-conductive insulating layer is arranged between adjacent metal gates. Based on the above scheme, the ferroelectric layer is used as the functional layer, and the ferroelectric material undergoes a polarization effect under an electric field. The polarization effect is consistent with the direction of the electric field generated by the programming / erase voltage. At this time, the electric dipoles in the ferroelectric layer remain in the same position after displacement, and the positive charges distributed at the interface of the ferroelectric layer attract electrons at the channel to pass through the tunneling layer and enter the charge trapping layer, thereby improving the programming efficiency. When performing an erase operation, the voltage bias on the metal electrode of the storage unit becomes a negative bias, and the attraction effect of the ferroelectric layer is reversed, which also improves the erase efficiency. At the same time, the polarization effect of the ferroelectric layer can achieve efficient charge control in programming / erase operations. Under the same operating voltage, the charge trapping layer can achieve a higher density of charge injection, making the gap between the programming state and the erased state more obvious, thereby expanding the effective storage window. Therefore, the overall reliability of the flash memory is improved.

[0027] The second aspect of the present invention provides a simulation method for a flash memory device structure, comprising: after selecting a physical model from a physical model repository preset by a TCAD tool, performing electrical performance simulation based on the simulation model to determine simulation test data. Based on the above scheme, the flash memory device structure is modeled and electrical characteristics are simulated according to the device behavior with different physical models. The flash memory performance of the flash memory device structure can be evaluated through simulation test data, so as to speed up the adjustment of structural parameters to optimize flash memory performance and help improve flash memory reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0029] Figure 1 A schematic structural diagram of a flash memory device structure provided by a first embodiment of the present invention;

[0030] Figure 2 A programming operation timing diagram of a flash memory device structure is provided for a first embodiment of the present invention;

[0031] Figure 3 A read operation timing diagram of a flash memory device structure is provided for the first embodiment of the present invention;

[0032] Figure 4 A flowchart of a method for simulating a flash memory device structure provided by a second embodiment of the present invention;

[0033] Figure 5 The second embodiment of the present invention provides a program / erase operation method of a CTF-NAND and MFONOS device. d -V g Characteristic curve;

[0034] Figure 6 A schematic diagram comparing the ISPP pulse programming performance of CTF-NAND and MFONOS devices provided by the second embodiment of the present invention;

[0035] Figure 7 A schematic diagram of programming voltages of CTF-NAND and MFONOS devices under different threshold voltage variations provided by a second embodiment of the present invention;

[0036] In the figure: 1. top selection tube; 2. non-conductive insulating layer; 3. storage unit; 4. virtual storage unit; 5. bottom selection tube; 6. metal gate; 7. ferroelectric layer; 8. blocking layer; 9. charge trapping layer; 10. tunneling layer; 11. polysilicon channel layer; 12. filling layer; 13. drain; 14. source. DETAILED DESCRIPTION

[0037] The embodiment of the present invention provides a flash memory device structure and a simulation method thereof, which are used to improve the technical problem of low reliability of a traditional flash memory structure.

[0038] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] See also Figure 1 , Figure 1 A schematic structural diagram of a flash memory device structure provided by the first embodiment of the present invention.

[0040] The present embodiment provides a flash memory device structure, including: a storage string;

[0041] The storage string includes a top selection tube 1, a dummy storage unit 4, at least one storage unit 3, a dummy storage unit 4 and a bottom selection tube 5 which are stacked vertically in sequence;

[0042] The top selection tube 1, the dummy storage unit 4, the storage unit 3 and the bottom selection tube 5 all include a filling layer 12, a polysilicon channel layer 11, a tunneling layer 10, a charge trapping layer 9, a blocking layer 8, a ferroelectric layer 7 and a metal gate 6 which are sequentially arranged from the inside to the outside;

[0043] The two ends of the polysilicon channel layer 11 are respectively provided with a drain 13 close to the top selection tube 1 and a source 14 close to the bottom selection tube 5;

[0044] A non-conductive insulating layer 2 is disposed between adjacent metal gates 6 .

[0045] It should be noted that a storage string (String) is a basic structure for realizing data storage and operation in a flash memory device. This embodiment proposes a new flash memory device structure (abbreviated as MFONOS structure) by optimizing the structural characteristics of the storage string. The storage string includes a top selection tube 1, a virtual storage unit 4 (Dummy), a storage unit 3 (Cell) and a bottom selection tube 5. The top selection tube 1, the virtual storage unit 4, the storage unit 3, the virtual storage unit 4 and the bottom selection tube 5 are stacked in sequence in a direction perpendicular to the substrate of the flash memory device. The number of storage units 3 in the storage string is 1 to n, that is, WL 1 ~WL nIt can be understood that the top selection tube 1, the dummy storage unit 4, the storage unit 3 and the bottom selection tube 5 have basically the same structure, but their threshold voltages are different, so the functions performed in the flash memory are designed differently. The selection tube is used to control the connection between the storage string and the bit line and the source line. The dummy storage unit 4 is usually not directly accessed during operation, that is, it does not store valid data, but the introduction of the dummy unit can slow down the channel potential change gradient at the edge of the string to optimize the electrical characteristics of the storage string and improve the reliability of reading and writing. The storage unit 3 realizes data reading, programming and erasing by applying different gate voltages. The basic structure of these components includes a filling layer 12, a polysilicon channel layer 11, a tunneling layer 10, a charge trapping layer 9, a blocking layer 8, a ferroelectric layer 7 and The metal gate 6 is provided with a source 14 and a drain 13 connected at both ends of the polysilicon channel layer 11, wherein the drain 13 is provided close to the top selection tube 1, and the source 14 is provided close to the bottom selection tube 5, thereby, a storage string is formed by stacking the connection relationship of the top selection tube 1 source 14-drain 13 of the virtual storage unit 4-source 14 of the virtual storage unit 4-drain 13 of the storage unit 3-source 14 of the storage unit 3-drain 13 of the storage unit 3-drain 13 of the bottom selection tube 5, at this time, the filling layer 12, the polysilicon channel layer 11, the tunneling layer 10, the charge trapping layer 9, the blocking layer 8 and the ferroelectric layer 7 are continuously shared among them, and the metal gate 6 is a structure in which each element independently controls the execution operation, therefore, a non-conductive insulating layer 2 is provided between adjacent metal gates 6 for insulation separation to ensure electrical isolation;

[0046] In order to illustrate the beneficial effects of the flash memory device structure, the present embodiment provides an operation process of a flash memory device structure for reference: after activating the top selection tube 1 and the bottom selection tube 5, when the voltage is applied to the metal gate 6 of each storage cell 3 (Cell), the charges flowing between the source 14 and the drain 13 in the polysilicon channel layer 11 corresponding to the metal gate 6 undergo a tunneling effect, and at the same time, the ferroelectric layer 7 is polarized, and the polarization direction is consistent with the programming electric field direction (vertical to the channel and downward) to promote the tunneling effect. The electrons undergoing the tunneling effect pass through the tunneling layer 10 and are captured by defects in the charge trapping layer 9, thereby changing the threshold voltage of the storage cell 3 to store information; when performing a programming operation, the metal gate 6 of the target storage cell 3 in the flash memory device structure, i.e., the storage cell 3 to be programmed, is first applied with a conduction voltage V pass After applying programming voltage V pgm (18~20V), the metal gate 6 of other storage cells 3 is applied with a conduction voltage V pass (6~8V) to prevent the non-target storage unit 3 from being accidentally programmed, the drain 13 and the metal gate 6 of the bottom selection tube 5 are grounded to GND, the source 14 is applied with 1V, and the metal gate 6 of the top selection tube 1 is applied with 8V voltage. The programming timing diagram of each electrode is as follows Figure 2When performing an erase operation, the metal gate 6 of the target memory cell 3 in the flash memory device structure, that is, the memory cell 3 to be erased, is controlled to apply an erase voltage V erase ( ), the source 14 and the drain 13 and the metal gate 6 of other storage cells 3 are all grounded GND; when performing a read operation, the metal gate 6 of the target storage cell 3 in the flash memory device structure, i.e., the storage cell 3 to be read, is controlled to apply a read voltage V read , the metal gate 6 of other storage cells 3 and top selection tube 1 and bottom selection tube 5 in the same storage string (String) is applied with a conduction voltage V pass (6~8V), the drain 13 applies a detection voltage V pre (0.5V) to detect whether the storage unit 3 to be read is turned on. At the same time, the source 14 is connected to the zero potential GND. The timing diagram of each electrode reading is as follows Figure 3 As shown;

[0047] Based on the above scheme, the ferroelectric layer 7 is used as the functional layer, and the ferroelectric material undergoes a polarization effect under an electric field, and the polarization effect is consistent with the direction of the electric field generated by the programming / erasing voltage. At this time, the electric dipoles in the ferroelectric layer 7 remain unchanged after displacement, and the positive charges distributed at the interface of the ferroelectric layer 7 attract the electrons at the channel to pass through the tunneling layer 10 and enter the charge trapping layer 9, thereby improving the programming efficiency; on the contrary, when performing an erasing operation, the voltage bias on the metal electrode of the storage unit 3 becomes a negative bias, and the attraction effect of the ferroelectric layer 7 will be opposite, which also improves the erasing efficiency; at the same time, the polarization effect of the ferroelectric layer can achieve efficient charge control in the programming / erasing operation. Therefore, compared with traditional flash memory devices such as CTF-NAND memory, under the same operating voltage, the charge trapping layer 9 can achieve a higher density of charge injection, making the gap between the programming state and the erased state more obvious, thereby expanding the effective storage window; therefore, the flash memory device structure provided in this embodiment has a faster operating speed, thereby improving the reliability of the flash memory, which is specifically manifested in faster programming speed and erase speed and an effectively expanded storage window, which helps to match the user's 3D NAND flash memory devices are facing increasing performance requirements.

[0048] In a specific implementation of this embodiment, the thickness of the ferroelectric layer 7 is 6 nm, the thickness of the barrier layer 8 is 4 nm, the thickness of the charge trapping layer 9 is 5 nm, the thickness of the tunneling layer 10 is 5 nm, the thickness of the polysilicon channel is 10 nm, and the thickness of the filling layer 12 is 15 nm;

[0049] The lateral gate length of the metal gate 6 is 28 nm, the longitudinal gate length of the metal gate 6 is 40 nm, and the gate spacing between adjacent metal gates 6 is 28 nm;

[0050] The electron defect concentration and hole defect concentration of the charge trapping layer 9 are both .

[0051] It should be noted that, based on the optimized structural composition, this embodiment provides optimized structural parameters, wherein the thickness of the ferroelectric layer 7 (T fe ) is 6 nm, the O / N / O structure composed of the blocking layer 8-charge trapping layer 9-tunneling layer 10 is used for charge trapping, and the thickness is 4 nm / 5 nm / 5 nm respectively. The thickness of the polysilicon channel layer 11 (T ch ) is 10 nm, the thickness of the filling layer 12 (T f ) is 15 nm; the lateral gate length (L g ) is 28 nm, and the vertical gate length (T g ) is 40 nm, and the gate spacing between adjacent metal gates 6, i.e., the distance between gates (L sp ) is set to 28 nm. The appropriate gate spacing can reduce electrical interference while facilitating high-density integration to improve storage density. The enhanced capacitive coupling between adjacent gates makes programming and erasing operations more efficient to improve read and write speeds. At the same time, for the defect configuration in the charge trapping layer 9, the electron type defect (n CTN ) and hole type defects (p CTN ) concentrations were set to .

[0052] It can be understood that the thickness of each layer refers to the distance between two surfaces of each layer that are relatively distributed along the surface direction parallel to the substrate of the flash memory device or along the direction perpendicular to the channel, the horizontal metal gate length refers to the length of the metal gate 6 along the channel direction, and the vertical metal gate length refers to the length of the metal gate 6 along the direction parallel to the substrate surface of the flash memory device or along the direction perpendicular to the channel. For details, please refer to Figure 1 shown.

[0053] In a more specific implementation of this embodiment, the source electrode 14 and the drain electrode 13 are provided with a concentration of N-type doping;

[0054] The polysilicon channel layer 11 is provided with a concentration of N-type doping.

[0055] It should be noted that the structures that need to be doped in the storage string include the source 14, the drain 13 and the area where the polysilicon channel layer 11 is located, and N-type doping or P-type doping can be used; in a preferred implementation, the source 14, the drain 13 and the polysilicon channel layer 11 are all doped with N-type or P-type, that is, the same doping type is used, which helps to form a continuous electronic conduction path to improve conductivity, reduce interface defects that are easily caused by different carrier types, and improve charge transfer characteristics; further, the source 14 and the drain 13 are both doped with a concentration of N-type doping and the channel region uses When the N-type doping concentration is high, under this structural parameter design, optimizing the doping concentration and distribution of the source 14 and the drain 13 helps to improve the current driving capability and thus speed up the reading speed. Optimizing the doping concentration of the polysilicon channel layer 11 can improve the charge injection efficiency to reduce the time and power consumption of the programming / erase operation, thereby improving the programming / erase efficiency.

[0056] In a more specific implementation of this embodiment, there are multiple storage units 3, and the multiple storage units 3 are stacked vertically in sequence.

[0057] It should be noted that when there are multiple storage units 3, Figure 1 Taking the three memory cells 3 shown as an example, multiple memory cells 3 are stacked in sequence between the virtual memory cells 4 along a direction perpendicular to the substrate of the flash memory device. At this time, the filling layer 12, the polysilicon channel layer 11, the tunneling layer 10, the charge trapping layer 9, the blocking layer 8 and the ferroelectric layer 7 are continuously shared between the memory cells 3, and the source 14 and the drain 13 of the adjacent memory cells 3 are connected to enable the current to pass through each memory cell 3 in the storage string in sequence.

[0058] Based on the aforementioned structural composition and parameter design, under the structural parameters, i.e., operating configuration, shown in Table 1, the flash memory device structure of this embodiment has better flash memory performance:

[0059] Table 1 Structural parameters and operation configuration

[0060]

[0061] In a specific implementation of this embodiment, there are multiple top selection tubes 1 and / or bottom selection tubes 5 .

[0062] It should be noted that, in this embodiment, Figure 1As shown, three top selection tubes 1 and three bottom selection tubes 5 are provided. By setting the number of top selection tubes 1 or / and bottom selection tubes 5 to be multiple to form a redundant design, the fault tolerance of the flash memory device during operation is improved. In one implementation, a parallel connection redundant distribution can be adopted, that is, multiple top selection tubes 1 or multiple bottom selection tubes 5 are connected in parallel and then connected to the virtual storage unit 4. The advantage of this parallel connection mode is that the current conduction capacity can be increased. In another implementation, a redundancy distribution combining parallel and series hybrid connection can also be considered, that is, multiple top selection tubes 1 are divided into multiple top tube groups, and the top selection tubes 1 in each top tube group are connected in parallel. The top tube groups can be connected in parallel or in series. Similarly, multiple bottom selection tubes 5 are divided into multiple bottom tube groups. After the bottom selection tubes 5 in the group are connected in parallel, the bottom tube groups can be connected in parallel or in series. This can not only achieve a certain redundancy backup and current expansion capability, but also achieve more flexible operation through group control.

[0063] In some implementations of this embodiment, the tunneling layer 10, the barrier layer 8 and the filling layer 12 are all made of silicon dioxide; the charge trapping layer 9 is made of silicon nitride; and the ferroelectric layer 7 is made of silicon-doped hafnium oxide.

[0064] In a more specific embodiment, the flash memory device structure includes a plurality of memory strings, and the plurality of memory strings are distributed in an array.

[0065] It should be noted that multiple storage strings can be provided in the flash memory device structure. The multiple storage strings are arranged in rows and columns to form a three-dimensional storage array. The multiple storage strings can be coordinated and controlled through shared control lines (such as word lines, bit lines and source lines). For details, please refer to the prior art and will not be repeated here.

[0066] See also Figure 4 , Figure 4 A flowchart of a method for simulating a flash memory device structure provided in accordance with a second embodiment of the present invention.

[0067] This embodiment provides a simulation method for a flash memory device structure, including:

[0068] Step 101: Model the flash memory device structure using a TCAD tool to determine a simulation model.

[0069] As a powerful tool, TCAD (Technology Computer-Aided Design) simulation technology is widely used in the design and optimization of semiconductor devices. By simulating the electrical performance and physical characteristics of the device, the performance of the flash memory device structure can be evaluated and optimized before actual manufacturing, thus saving time and cost.

[0070] It should be noted that this embodiment uses TCAD tools to simulate and test the designed flash memory device structure. Taking sentaurus TCAD as an example, the SDE (Sentaurus Structure Editor) module of sentaurus TCAD is a tool for building and optimizing semiconductor device structures. First, the flash memory device structure is modeled using SDE to determine the simulation model. The simulation model corresponds to Figure 1 The structure shown.

[0071] Step 102 : After selecting a physical model from a physical model repository preset by the TCAD tool, electrical performance simulation is performed based on the simulation model to determine simulation test data.

[0072] It should be noted that S-Device (Sentaurus Device) is a core module in sentaurus TCAD used to simulate and analyze the electrical characteristics, physical behavior and performance optimization of semiconductor devices. S-Device provides powerful device simulation capabilities and supports a variety of semiconductor device types and physical models.

[0073] After using SDE to build the simulation structure of the device and adding the necessary simulation grids, S-Device will be used to configure the simulation of electrical characteristics: For programming and erasing operations, the non-local tunneling model (Non-local Model) is selected. Since the tunneling effect mainly occurs at the interface between the channel and the tunnel oxide layer during operation, the non-local tunneling model grid is defined on this interface; considering the thickness of the charge trapping layer, the tunneling layer and the polysilicon channel layer, the tunneling distance can be set to be greater than or equal to the thickness of the tunneling layer and less than the sum of the thicknesses of the tunneling layer and the charge trapping layer. For example, according to the structural parameters shown in Table 1 in the first embodiment, the tunneling distance can be set to 8 nm; in the charge trapping layer, the carrier capture-emission model and the carrier drift-diffusion model are mainly considered; specifically, the defect densities of both donor and acceptor types are set to , the donor-type trap energy level is located 1.5 eV above the valence band, while the acceptor-type trap energy level is located 1.24 eV below the reversal band; through the coupling of the defect model and the non-local tunneling model, the dynamic process of electrons being trapped and subsequently detrapped after entering the charge trapping layer during the tunneling process can be effectively simulated; under the action of high electric field strength, the trap barrier in the charge trapping layer is reduced, resulting in the emission of trapped electrons. In order to simulate this phenomenon, the Poole-Frenkel model is introduced into the defect model, which can consider and predict the probability of electron emission under high electric field; for the erase operation, the Gate Induced Drain Leakage (GIDL) erase method is used. The GIDL phenomenon occurs because the source / drain electrodes of the selector tubes at both ends of the device have a large potential difference with the gate, resulting in the band-to-band tunneling effect (Band-to-Band The occurrence of GIDL erasure mechanism (BTB) will generate electron-hole pairs, which will generate a large number of holes in the channel. The holes are then injected into the charge trapping layer to complete the erasure process. Therefore, in order to accurately simulate the GIDL erasure mechanism, a band-to-band tunneling model is configured in the channel region of the device, and combined with a doping concentration-dependent migration model, Shockley-Read-Hall (SRH) model, high-field saturation model (High-Field Saturation Models) and mobility surface degradation model; among them, more detailed physical parameter configurations are shown in Table 2-4:

[0074] Table 2 Key parameter configuration of non-local tunneling model

[0075]

[0076] Table 3 Key parameter configuration of trap model for charge trapping layer

[0077]

[0078] Table 4 Key parameter configuration of ferroelectric layer polarization model

[0079]

[0080] According to the above configuration design, after selecting the non-local tunneling model, carrier capture-emission model, carrier drift-diffusion model, Poole-Frenkel model, band-to-band tunneling model, doping concentration-dependent migration model, Shockley-Read-Hall composite model, high field saturation model and mobility surface degradation model from the physical model repository preset in S-Device, complete the corresponding parameter configuration, carry out electrical performance simulation to determine the simulation test data, and by evaluating the simulation results of the programming, erasing and storage window performance of the flash memory device structure, the thickness of the barrier layer, the voltage of the metal gate and other parameters can be adjusted to further optimize the flash memory performance. Modeling and performance evaluation of the flash memory device structure using TCAD simulation technology helps to reduce R&D costs and development cycles, and improve the market competitiveness of flash memory devices.

[0081] In order to illustrate the effectiveness of the flash memory device structure of the first embodiment, the MFONOS structure memory and the charge trap flash NAND (CTF-NAND) memory of the traditional flash memory structure are simulated and verified by the TCAD tool:

[0082] 1) During the simulation, both devices used the same programming / erase voltage pulse amplitude and width, i.e. In this study, the constant current method was used to extract the threshold voltage (Vt) of the device, so the threshold voltage is defined as the drain current (I d )for The corresponding gate voltage value (V g ). For a memory device, the memory window (MW) is the threshold voltage difference between the programmed and erased states, i.e. ;according to Figure 5 The drain current-gate voltage (I d -V g ) characteristic curve, the experimental results show that the storage window of MFONOS device is 5.84 V, while the storage window of CTF-NAND is 3.78 V; therefore, under the same programming voltage (19 V), the storage window of MFONOS memory device is 2.06 V higher than that of CTF-NAND device, and the window width is increased by 54.50%. The reason for this performance improvement is that the ferroelectric layer in MFONOS device can attract more electrons into the charge trapping layer during programming;

[0083] 2) ISPP programming is a widely used programming algorithm in flash memory programming operations. In order to evaluate the difference in ISPP performance between MFONOS devices and CTF-NAND, a programming pulse amplitude of 15 V to 25 V and a pulse width of 100 µs were used to program the two devices simultaneously and record their threshold voltage change ΔVth ; Figure 6 The threshold voltage changes of MFONOS and CTF-NAND devices under different programming pulses are given. In the programming voltage range of 15 V to 22 V, MFONOS can obtain a higher threshold voltage change than CTF-NAND. However, when the programming voltage exceeds 23 V, the threshold voltage change of MFONOS begins to be lower than that of CTF-NAND. It is worth noting that in actual ISPP programming applications, programming voltages exceeding 23 V are not common, so the impact of this voltage range on ISPP performance can be ignored. Therefore, in the conventional ISPP programming voltage range, the threshold voltage change of MFONOS at 15 V is 5 times that of CTF-NAND, increases to 2 times that of CTF-NAND at 18 V, and is 40.88% higher than that of CTF-NAND at 20 V.

[0084] 3) Figure 7 The required programming voltages for CTF-NAND and MFONOS devices to achieve different threshold voltage changes are shown. From the perspective of power consumption, the required programming voltage for MFONOS is 15.87% lower than that for CTF-NAND devices to achieve the same threshold voltage change.

[0085] In summary, through multiple simulation verifications, it can be seen that MFONOS has lower power consumption and better ISPP programming performance, and this improvement comes from the ferroelectric layer introduced by MFONOS in the barrier layer. During the programming process, the high-k dielectric properties and polarization properties of the ferroelectric layer itself are coupled with the trapped charges of the charge trapping layer, which can improve the programming performance to a certain extent.

[0086] An embodiment of the present invention further provides a computer device, including a memory and a processor, wherein a computer program is stored in the memory; when the computer program is executed by the processor, the processor executes the steps of the simulation method of the flash memory device structure of any of the above embodiments.

[0087] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the simulation method of the flash memory device structure as in any of the above embodiments are implemented.

[0088] An embodiment of the present invention further provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the method for simulating the flash memory device structure of any of the above embodiments.

[0089] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A flash memory device structure, characterized in that: include: Storage string; The storage string includes a top selection tube, a dummy storage unit, at least one storage unit, a dummy storage unit, and a bottom selection tube stacked vertically in sequence; The top selection tube, the dummy storage unit, the storage unit and the bottom selection tube all include a filling layer, a polysilicon channel layer, a tunneling layer, a charge trapping layer, a blocking layer, a ferroelectric layer and a metal gate which are sequentially arranged from the inside to the outside; The two ends of the polysilicon channel layer are respectively provided with a drain electrode close to the top selection tube and a source electrode close to the bottom selection tube; A non-conductive insulating layer is disposed between adjacent metal gates.

2. The flash memory device structure according to claim 1, characterized in that: The thickness of the ferroelectric layer is 6 nm, the thickness of the blocking layer is 4 nm, the thickness of the charge trapping layer is 5 nm, the thickness of the tunneling layer is 5 nm, the thickness of the polysilicon channel is 10 nm, and the thickness of the filling layer is 15 nm; The lateral gate length of the metal gate is 28 nm, the longitudinal gate length of the metal gate is 40 nm, and the gate spacing between adjacent metal gates is 28 nm; The electron defect concentration and hole defect concentration of the charge trapping layer are both .

3. The flash memory device structure according to claim 1, characterized in that: There are a plurality of storage units, and the plurality of storage units are stacked vertically in sequence.

4. The flash memory device structure according to claim 2, characterized in that: The source electrode and the drain electrode are provided with a concentration of N-type doping; The polysilicon channel layer is provided with a concentration of N-type doping.

5. The flash memory device structure according to claim 1, characterized in that: There are multiple top selection tubes and / or multiple bottom selection tubes.

6. The flash memory device structure according to claim 1, characterized in that: The tunneling layer, the barrier layer and the filling layer are all made of silicon dioxide material; The charge trapping layer is made of silicon nitride material; The ferroelectric layer is made of silicon-doped hafnium oxide material.

7. A method for simulating a flash memory device structure, characterized in that: include: Model the flash memory device structure through TCAD tools and determine the simulation model; After selecting a physical model from the physical model repository preset by the TCAD tool, electrical performance simulation is performed based on the simulation model to determine simulation test data.

8. A computer device, characterized in that: It comprises a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor executes the steps of the simulation method of the flash memory device structure as claimed in claim 7.

9. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the steps of the method for simulating the flash memory device structure as claimed in claim 7 are implemented.

10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method for simulating the flash memory device structure as claimed in claim 7 are implemented.

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