Self-termination etching method of silicon-based dielectric layer and application of self-termination etching method

Abstract

The invention discloses a self-termination etching method of a silicon-based dielectric layer and application of the self-termination etching method. The self-termination etching method comprises the following steps: providing a substrate, and forming an aluminum oxide layer on the surface of the substrate as an etching stop layer; covering and growing a silicon-based dielectric layer on the surface of the etching stop layer; ion beam etching is carried out on the silicon-based dielectric layer by adopting a fluorine-based etching atmosphere, oxygen is doped in the fluorine-based etching atmosphere, so that the reaction activity of fluorine-based gas in the fluorine-based etching atmosphere to the etching stop layer is reduced, and etching is terminated at the etching stop layer. According to the invention, the etching selectivity ratio of the etching stop layer to the silicon-based dielectric layer is improved by utilizing the phenomenon that the etching reaction activity of the fluorine-based gas to silicon oxide is obviously reduced after oxygen is doped into the fluorine-based gas, so that an etching stop effect is achieved; the method has obvious help for improving depth uniformity and roughness of an etching bottom surface and avoiding etching damage to a semiconductor material, and is very suitable for constructing a high-quality * D1 + (07) device and other applications.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor electronic technologies, and particularly to a self-terminating etching method for a silicon-based dielectric layer and its application. Background Art

[0002] The new generation of wide-bandgap semiconductor material gallium nitride (GaN) has both high breakdown voltage (3.1 MV / cm) and high electron mobility (~1500 cm 2 / V·s), etc., and has broad application prospects in the fields of high frequency and high power electronics. Due to the existence of the polarization effect, the A1GaN / GaN heterostructure is the currently mainly applied planar structure GaN HEMT, which has significant advantages such as high current density, high breakdown voltage, and high frequency.

[0003] There are surface states caused by crystal defects on the surface of the A1GaN / GaN heterojunction material. Under high-frequency and high-power applications, current collapse phenomena occur in the device, greatly reducing the output current of the device. To avoid the above problems, in the prior art, a layer or multiple layers of SiN are often grown on the surface of the AlGaN / GaN HEMT device by methods such as chemical vapor deposition (CVD, such as plasma-enhanced PECVD, coupled plasma ICPCVD, low-pressure LPCVD), etc. x 、SiO 2 and other silicon-based dielectrics are used as passivation materials. Growing a passivation layer can effectively suppress the current collapse phenomenon, achieve effective isolation between electrodes, and can also reduce the influence of the environmental atmosphere on the electrical characteristics of the device.

[0004] Since the dielectric layer deposited by the CVD method is usually tiled on the surface of the wafer, during the device preparation process, processes such as window etching of some regions of the dielectric layer are often required, such as gate window opening, source-drain interconnection electrode window opening, etc. Currently, typical SiN x 、SiO 2 and other silicon-based dielectrics are etched using etching methods such as inductively coupled plasma (ICP), reactive ion etching (RIE), etc. The working gas in the etching usually includes one or more of CHF 3 、SF 6 、CF 4 This method generally controls the etching depth, perpendicularity, accuracy, etc. of the dielectric layer by controlling process parameters such as the power of the plasma radio frequency source and the etching time.

[0005] The passivation material can reduce the density of states at the AlGaN surface and the AlGaN / GaN interface, but during the subsequent gate dielectric window etching process, when using a conventional process scheme to etch SiN x 、SiO 2Media such as [specific media] cannot effectively avoid problems such as over-etching of AlGaN and etching surface damage, which will cause an increase in gate leakage current and a decrease in the output performance of the transistor. At the same time, due to the characteristics of the etching equipment and process, the uniformity, roughness, and etching selectivity of the medium window etching interface and depth have all been challenged to a certain extent. Summary of the Invention

[0006] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a self-terminating etching method for a silicon-based dielectric layer and its application.

[0007] To achieve the foregoing invention purpose, the technical solutions adopted by the present invention include:

[0008] In the first aspect, the present invention provides a self-terminating etching method for a silicon-based dielectric layer, which includes:

[0009] Providing a substrate and forming an alumina layer on the surface of the substrate as an etching stop layer;

[0010] Covering and growing a silicon-based dielectric layer on the surface of the etching stop layer;

[0011] Performing ion beam etching on the silicon-based dielectric layer using a fluorine-based etching atmosphere, and doping oxygen into the fluorine-based etching atmosphere to reduce the reaction activity of the fluorine-based gas in the fluorine-based etching atmosphere with the etching stop layer, and the etching terminates at the etching stop layer.

[0012] In the second aspect, the present invention also provides a manufacturing method for a GaN HEMT device, which includes:

[0013] Sequentially preparing and forming at least a channel layer and a barrier layer on a substrate to obtain a substrate;

[0014] Using the above self-terminating etching method to form a pattern structure on the surface of the substrate, the pattern structure includes an etching stop layer and a silicon-based dielectric layer formed in sequence, and in the gate region, the silicon-based dielectric layer is ion beam etched to expose the etching stop layer;

[0015] Forming a gate in the gate region, and forming a source electrode and a drain electrode on both sides of the gate region respectively; wherein the source electrode and the drain electrode form at least an ohmic contact with the barrier layer.

[0016] In the third aspect, the present invention also provides a GaN HEMT device prepared by the above manufacturing method, which includes a substrate and correspondingly arranged gate, source electrode, and drain electrode, and the substrate includes a channel layer, a barrier layer, an etching stop layer, and a silicon-based dielectric layer stacked along a specified direction;

[0017] In the gate region, an etching notch is formed in the silicon-based dielectric layer, and the etching notch penetrates through the silicon-based dielectric layer and extends to the etch stop layer, and at least part of the structure of the gate is filled in the etching notch;

[0018] The source electrode and the drain electrode are respectively arranged on both sides of the gate region, and the source electrode and the drain electrode form an ohmic contact with at least the barrier layer.

[0019] Based on the above technical solution, compared with the prior art, the beneficial effects of the present invention include:

[0020] In the technical solution provided by the present invention, a layer of aluminum oxide is inserted between the silicon-based dielectric layer and the substrate as an etch stop layer. By utilizing the phenomenon that the etching reaction activity of silicon oxide is significantly reduced after oxygen is doped into the fluorine-based gas, the etching selectivity between the etch stop layer and the silicon-based dielectric layer is improved, thereby playing an obvious etching stop role, which is significantly helpful for improving the depth uniformity, the roughness of the etched bottom surface, and avoiding etching damage to the semiconductor material, and is very suitable for constructing high-quality GaN HEMT devices and other applications.

[0021] The above description is only an overview of the technical solution of the present invention. In order to enable those skilled in the art to more clearly understand the technical means of the present application and implement it in accordance with the content of the specification, the following takes the preferred embodiments of the present invention and combines detailed drawings to illustrate as follows. Brief Description of the Drawings

[0022] Figure 1 is a schematic diagram of the overall structure of the GaN HEMT device provided by the present invention;

[0023] Figure 2 is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by a typical embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by a typical embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by a typical embodiment of the present invention;

[0026] Figure 5 is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by a typical embodiment of the present invention;

[0027] Figure 6 is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by a typical embodiment of the present invention;

[0028] Figure 7 It is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by a typical embodiment of the present invention;

[0029] Figure 8 It is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by a typical embodiment of the present invention;

[0030] Figure 9 It is an AFM structure diagram of the self-terminated etched surface in the manufacturing process of the GaN HEMT device provided by a typical embodiment of the present invention;

[0031] Figure 10 It is an AFM structure diagram of the self-terminated etched surface in the manufacturing process of the GaN HEMT device provided by a typical embodiment in the comparative example;

[0032] Figure 11 It is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by another typical embodiment of the present invention;

[0033] Figure 12 It is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by another typical embodiment of the present invention;

[0034] Figure 13 It is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by another typical embodiment of the present invention;

[0035] Figure 14 It is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by another typical embodiment of the present invention;

[0036] Figure 15 It is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by another typical embodiment of the present invention;

[0037] Figure 16 It is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by another typical embodiment of the present invention;

[0038] Figure 17 It is a schematic diagram of one of the process structures in the manufacturing process of the GaN HEMT device provided by another typical embodiment of the present invention.

[0039] Description of reference numerals:

[0040] 001. Substrate, 002. Transition layer, 003. High-resistance layer, 004. Channel layer, 005. Insertion layer, 006. Barrier layer, 007. Etch stop layer, 008. Silicon-based dielectric layer, 009. Gate, 010. Source electrode, 011. Drain electrode;

[0041] 101. Substrate, 102. AlN / AlGaN transition layer structure, 103. High-resistance layer, 104. GaN channel layer, 105. AlN insertion layer, 106. Barrier layer, 107. Al 2 O 3 etch stop layer, 108. Dielectric layer, 108A. First silicon-based dielectric layer, 108B. Second silicon-based dielectric layer, 109. Photoresist layer, 110. Gate contact metal, 111A. Source electrode contact metal, 111B. Drain electrode contact metal. Detailed implementation manners

[0042] In view of the deficiencies in the prior art, the inventors of this case have proposed the technical solution of the present invention through long-term research and a large number of practices. The following will further explain the technical solution, its implementation process, principle, etc.

[0043] In the following description, many specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention may be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below.

[0044] Moreover, relational terms such as "first" and "second" are only used to distinguish one component or method step with the same name from another, and do not necessarily require or imply any actual relationship or order between these components or method steps.

[0045] Smaller surface etching damage, and realizing self-terminating etching of the dielectric can be used to prepare high-performance and highly uniform AlGaN / GaN HEMTs, which plays a very important role. Aiming at the deficiencies of the above prior art, this patent aims to provide a self-terminating etching solution for dielectrics such as SiN x , SiO 2 etc. This solution can achieve automatic termination of silicon-based dielectric etching and prevent etching damage to the underlying materials during the etching process. At the same time, since this technical solution can well achieve etching termination and its etching depth depends on a more uniform coating technology, this solution can achieve very high intra-wafer and inter-wafer uniformity.

[0046] Based on the above technical concept, an embodiment of the present invention provides a self-terminating etching method for a silicon-based dielectric layer, which includes the following steps:

[0047] Provide a substrate and form an aluminum oxide layer on the surface of the substrate as an etch stop layer;

[0048] A silicon-based dielectric layer is grown and formed to cover the surface of the etching stop layer;

[0049] The silicon-based dielectric layer is subjected to ion beam etching using a fluorine-based etching atmosphere, and oxygen is doped in the fluorine-based etching atmosphere to reduce the reactivity of the fluorine-based gas in the fluorine-based etching atmosphere with respect to the etching stop layer, and the etching terminates at the etching stop layer.

[0050] It should be noted that in some typical examples, the self-terminating etching method provided by the present invention takes the GaN HEMT device as the main example, and can mainly overcome the problems of etching damage and difficult control of etching depth when opening a window in the semiconductor material in the GaN HEMT device; however, this does not mean that the self-terminating etching method provided by the present invention can only be applied to GaN HEMT devices. It is fully applicable to different epitaxial heterojunction structures and also applicable to different gate structures, such as depletion-type AlGaN / GaN heterojunction structures and enhancement-type p-GaN / AlGaN / GaN heterojunction structures, and is not limited thereto; in addition, the deposition method of the aluminum oxide etching stop layer is preferably atomic layer deposition. This deposition method is convenient for controlling the layer thickness for a relatively thin etching stop layer, but the feasible method is not limited thereto, and it is also applicable to Al grown by other thermal oxidation equipment 2 O 3 .

[0051] The basic principle of the technical solution provided by the present invention lies in: a relatively thin layer of Al x / SiO 2 is grown below dielectrics such as SiN 2 O 3 where precise etching stop is required by using techniques such as atomic layer deposition (ALD), and then a silicon-based dielectric layer with a required thickness is grown by methods such as PECVD. Then, a certain concentration of O x or SiO 2 is added to the fluorine-based etching atmosphere, and its concentration range is regulated. The silicon-based dielectric is etched at a relatively high chamber pressure. In the presence of oxygen, the etching rate of the fluorine-based etching atmosphere for the Al 2 O 2 material is significantly reduced, forming a large etching selectivity ratio, and the etching of dielectrics such as SiN 3 or SiO x or SiO 2 can be effectively stopped on Al 2 O 3 . At this time, the etching depth is everywhere equal to the thickness of the deposited dielectric within the wafer, and the uniformity of the dielectric window etching is high; in addition, A1 2 O 3It can effectively prevent the etching atmosphere from eroding the underlying semiconductor, metal, or other dielectric layers, thereby reducing etching damage.

[0052] The above technical solution proposes a method for self-terminating etching of dielectric window opening without damage, introducing a thin layer of Al 2 O 3 dielectric layer. By using an oxygen-containing fluorine-based gas, self-terminating etching of silicon-based dielectric passivation layers such as SiN x or SiO 2 can be achieved, realizing high uniformity of dielectric window opening etching. This technical solution can be applied to the window opening etching of the dielectric layer in the gate region to achieve non-destructive etching of the GaN material in the gate region, and can also be applied to the window opening etching of the dielectric layer in the metal interconnect process to achieve consistent control of the passivation layer thickness, and is not limited to this.

[0053] Regarding the specific process conditions, in some embodiments, the volume ratio of oxygen in the fluorine-based etching atmosphere is 1-40%.

[0054] The fluorine-based gas reacts with the silicon-based dielectric to form volatile etching products such as SiF 6 etc., while the fluorine-based gas reacts with the Al 2 O 3 layer to form AlF 3 which is difficult to volatilize, to prevent further etching and form a self-terminating etching effect. If the oxygen / fluorine-based gas ratio is too high, the formation of AlF 3 will be restricted, thus affecting the etching rate.

[0055] In some embodiments, the pressure of the fluorine-based etching atmosphere is 10-100 Pa. When the pressure in the etching chamber is relatively low, the etching rate is relatively fast, which is likely to lead to difficulty in accurately grasping the time of the etching stop layer.

[0056] In some embodiments, the temperature of the ion beam etching is 25 °C, for example, the RF power is about 200 W, for example, 100-400 W; the flow rate of the fluorine-based gas is 10-40 sccm, and the flow rate of the inert carrier gas is 10-40 sccm.

[0057] In some embodiments, the fluorine-based gas includes SF 6 , CHF 3 , CF 4 any one or a combination of two of them.

[0058] As a typical application example, in multiple embodiments of the present invention, the gas conditions that can be adopted are: the flow rate of SF 6 gas is 10 sccm, the flow rate of CHF 3 gas is 10 sccm, and the flow rate of Ar gas is 20 sccm.

[0059] In some embodiments, the thickness of the alumina layer is 5 - 30 nm.

[0060] In some embodiments, the number of cycles of atomic layer deposition is 60 - 300 times.

[0061] In some embodiments, the silicon-based dielectric layer includes SiN x and / or SiO 2 .

[0062] In some embodiments, the fluorine-based gas includes CHF 3 , SF 6 , CF 4 or any combination of two or more thereof.

[0063] In some embodiments, in order to achieve patterned etching, for example, to construct a gate region, the self-terminating etching method may further include the following steps:

[0064] Construct a patterned mask layer on the silicon-based dielectric layer, and use the patterned mask layer to perform patterned etching on the silicon-based dielectric layer.

[0065] As a further application of the above technical solution, an embodiment of the present invention further provides a manufacturing method of a GaN HEMT device, which includes the following steps:

[0066] At least a channel layer and a barrier layer are sequentially formed on a substrate to obtain a substrate;

[0067] A graphic structure is formed on the surface of the substrate by using the self-terminating etching method provided in any of the above embodiments. The graphic structure includes an etching stop layer and a silicon-based dielectric layer formed in sequence, and in the gate region, the silicon-based dielectric layer is etched by an ion beam to expose the etching stop layer;

[0068] A gate is formed in the gate region, and a source electrode and a drain electrode are respectively formed on both sides of the gate region; wherein the source electrode and the drain electrode form an ohmic contact with at least the barrier layer.

[0069] Regarding specific implementation details, in some embodiments, the substrate includes a substrate, a transition layer, a high-resistance layer, the channel layer, an insertion layer, and the barrier layer stacked in sequence along a specified direction.

[0070] In some embodiments, the formation process of the source electrode and / or the drain electrode specifically includes the following process flow:

[0071] The corresponding position in the non-gate region is etched by ICP etching and / or RIE etching, and the etching depth extends into the channel layer to form an electrode region;

[0072] Deposit a laminated metal in the electrode region and perform overall annealing to form an ohmic contact between the laminated metal and the sidewalls of the barrier layer and the channel layer.

[0073] In addition, an embodiment of the present invention further provides a GaN HEMT device fabricated by the manufacturing method provided in any of the above embodiments, which includes a substrate and a gate, a source, and a drain correspondingly arranged. The substrate includes a channel layer, a barrier layer, an etch stop layer, and a silicon-based dielectric layer laminated along a specified direction;

[0074] In the gate region, an etch notch is formed in the silicon-based dielectric layer, and the etch notch penetrates through the silicon-based dielectric layer and extends to the etch stop layer, and at least part of the structure of the gate is filled in the etch notch;

[0075] The source and the drain are respectively arranged on both sides of the gate region, and the source and the drain penetrate through the silicon-based dielectric layer and the etch stop layer and form an ohmic contact with at least the barrier layer.

[0076] As a specific example, reference can be made to Figure 1 As shown, the overall structure of a GaN HEMT device provided by an embodiment of the present invention is a substrate 001, a transition layer 002, a high-resistance layer 003, a channel layer 004, an insertion layer 005, a barrier layer 006, an etch stop layer 007, a silicon-based dielectric layer 008, a gate 009, a source 010, and a drain 011 laminated in sequence; an etch notch area (or called a window area) is etched in the silicon-based dielectric layer 008 above the etch stop layer 007, and the etch notch area penetrates through the silicon-based dielectric layer 008 until the etch stop layer 007, and part or all of the structure of the gate 009 is filled in the notch; in addition, on both sides of the gate, the source 010 and the drain 011 are constructed, and they generally penetrate at least the etch stop layer 007 and the silicon-based dielectric layer 008 and form an ohmic contact with the barrier layer 006. More specifically, they can continue to penetrate and directly enter the channel layer 004. Although the source 010 and the drain 011 are partially necessary components for constructing the device, the specific detailed structures of the source 010 and the drain 011 are not specifically limited in the present invention, as long as the corresponding functions can be achieved; the substrate 001 of the GaN HEMT device can include materials such as silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride, etc., and is not limited thereto.

[0077] The technical solution of the present invention will be further described in detail below through several embodiments in combination with the drawings. However, the selected embodiments are only used to illustrate the present invention and do not limit the scope of the present invention.

[0078] Embodiment 1

[0079] This embodiment provides a preparation process for a GaN HEMT device with a single-layer silicon-based dielectric layer. The specific process is as follows for referenceFigure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 as shown.

[0080] Using the method of metalorganic chemical vapor deposition (MOCVD), a 600-nm AlN / AlGaN transition layer structure 102 is deposited on a Si<111> substrate 101, and then a 4-μm C-doped Al 0.07 Ga 0.93 N high-resistance layer 103, a 300-nm high-quality unintentionally doped GaN channel layer 104 with low electron concentration, a 1-2-nm AlN insertion layer 105, and a 20-nm Al 0.20 Ga 0.80 N barrier layer 106 are epitaxially grown, obtaining a 2DEG sheet resistance of 350 Ω / □ and a concentration of ~1.0×10 13 cm -3 , and a mobility of ~1800 cm 2 V -1 s -1 of the A1GaN / GaN heterostructure D-HEMT epitaxial wafer is used as the substrate.

[0081] After cleaning the epitaxial wafer with an inorganic solution, the epitaxial wafer is transferred into an ALD device. Using TMA and high-purity water as reaction precursors, the growth temperature is 300 °C, the carrier gas flow rate is 60 sccm, the number of cycles is 240, and an A1 2 O 3 etch stop layer 107 with a thickness of 15 - 20 nm is grown. On the above sample, a SiN× dielectric layer 108 with a thickness of about 100 nm is grown using a plasma-enhanced chemical vapor deposition equipment (PECVD). The process parameters for depositing the dielectric layer are: the gas flow ratio of SiH 4 : NH 3 = 2:1, the pressure is 600 mTorr, the temperature is 280 °C, and the power is 22 W.

[0082] Using a photoresist layer 109 as a mask, the photoresist is used for exposure to pattern the gate region on the above wafer. The developed wafer is placed in an ion beam etcher (IBE) to etch away the silicon-based dielectric SiN x . The etching process is carried out at a relatively high chamber pressure (60 Pa), and the atmosphere used is CHF 3 , SF 6 , CF 4 , O 2A mixed gas, in which the ratio of each fluorine-based gas is 1:1:1, the oxygen concentration range is 20%, the reaction chamber pressure is 13.3 Pa, and in an oxygen-containing atmosphere, the F-based gas cannot etch Al 2 O 3 , has an extremely high etching selectivity for silicon-based dielectrics and Al 2 O 3 and can achieve automatic stop of etching, preventing damage to the underlying material of the dielectric during the etching process.

[0083] Use methods such as organic cleaning with acetone to remove the photoresist layer 109. After using piranha solution to remove residual organic matter, deposit a stack of gate contact metals 110 of Ti / Al / Ti = 20 / 200 / 20 nm in the gate region using electron beam evaporation technology. Use photoresist development to define the source-drain electrode contact regions, and use ICP etching process or RIE etching process for etching. Etch the dielectric layer, barrier layer, and part of the channel layer under the source-drain contact regions, and deposit a stack of metals of Ti / Al / Ti / TiN = 20 / 130 / 50 / 50 nm, N 2 After rapid annealing at 890 °C for 180 s in an N atmosphere, form ohmic contact source contact metal 111A and drain contact metal 111B.

[0084] In this embodiment, by using the above oxygen-containing etching process, the uniformity of gate dielectric window etching can be achieved, avoiding over-etching of the barrier layer and surface damage during the etching process, and reducing the damage to device performance caused by interface etching.

[0085] Comparative Example 1

[0086] This comparative example is generally the same as Example 1, and the main difference is that:

[0087] Omit the process of preparing the A1 2 O 3 etch stop layer 107, and directly deposit the dielectric layer 108 on the barrier layer 106 and then perform etching windowing under the same etching conditions.

[0088] Comparative Example 2

[0089] When performing ion beam etching windowing, do not introduce O 2 , and keep other conditions such as the ratio of fluorine-based gases, pressure, ion beam voltage, power, temperature, etc. unchanged.

[0090] When performing ion beam etching windowing, introduce O 2 , change the volume ratio of oxygen / fluorine-based gas, and keep other conditions such as the ratio of fluorine-based gases, pressure, ion beam voltage, power, temperature, etc. unchanged.

[0091] The etching rate and etching uniformity under different etching conditions are shown in Table 1 for reference.

[0092] Table 1:

[0093]

[0094] Specifically, reference can be made to Figure 9 and Figure 10 , Figure 9 which is the surface topography map after etching in Example 1, Figure 10 and which is the surface topography map after etching in Comparative Example 1. Figure 9 After etching with an oxygen-containing fluorine-based gas in, the etching self-terminates on the Al2O3 surface, and the surface roughness is about 0.7 nm. Figure 10 is a typical silicon-based dielectric etching scheme, and the surface roughness is about 3 nm.

[0095] Example 2

[0096] This example is generally the same as Example 1, and the main differences are as follows:

[0097] Adjust the growth time of the Al 2 O 3 etching stop layer 107 to make its thickness 5 nm; adjust the material of the dielectric layer 108 to SiO 2 , with a thickness of 200 nm; adjust the chamber pressure of the fluorine-based etching atmosphere to 100 Pa and the oxygen concentration to 40%.

[0098] Example 3

[0099] This example is generally the same as Example 1, and the main differences are as follows:

[0100] Adjust the growth time of the A1 2 O 3 etching stop layer 107 to make its thickness 30 nm; adjust the material of the dielectric layer 108 to SiO 2 , with a thickness of 200 nm; adjust the chamber pressure of the fluorine-based etching atmosphere to 10 Pa and the oxygen concentration to 5%.

[0101] The above Examples 2 - 3 are similar to Example 1, and devices with obvious etching stop effects can be prepared, which is significantly helpful for solving the problems of etching damage and etching uniformity.

[0102] Example 4

[0103] This example provides a preparation process for a GaN HEMT device with a double-layer silicon-based dielectric layer. The specific process is referred to Figure 2 , Figure 11 , Figure 12 , Figure 13 , Figure 14 ,Figure 15 , Figure 16 , Figure 17 as shown in:

[0104] Using the method of metal organic chemical vapor deposition (MOCVD), deposit a 600 nm AlN / AlGaN transition layer structure 102 on the Si<111> substrate 101, and then epitaxially grow a 4 μm C-doped Al 0.07 Ga 0.93 N high-resistance layer 103, a 300 nm high-quality unintentionally doped GaN channel layer 104 with low electron concentration, a 1-2 nm AlN insertion layer 105, and a 20 nm Al 0.20 Ga 0.80 N barrier layer 106, obtaining a 2DEG sheet resistance of 350 Ω / □ and a concentration of ~1.0×10 13 cm -3 , and a mobility of ~1800 cm 2 V -1 s -1 D-HEMT epitaxial wafer of AlGaN / GaN heterostructure.

[0105] After cleaning the epitaxial wafer with an inorganic solution, transfer the epitaxial wafer into a plasma enhanced chemical vapor deposition (PECVD) equipment to grow a 20 nm thick SiN x first silicon-based dielectric layer 108A. The process parameters for depositing the dielectric layer are: the gas flow ratio of SiH 4 : NH 3 = 2:1, the pressure is 600 mTorr, the temperature is 280 °C, and the power is 22 W.

[0106] Transfer the above sample into an ALD equipment, use TMA and high-purity water as reaction precursors, the growth temperature is 300 °C, the carrier gas flow rate is 60 sccm, the number of cycles is 240, and grow a 15-20 nm thick Al 2 O 3 etch stop layer 107. On the above sample, use a plasma enhanced chemical vapor deposition equipment (PECVD) to grow a SiN x second silicon-based dielectric layer 108B with a thickness of 100-200 nm as a passivation layer. The conditions for dielectric deposition are the same as those for depositing the first silicon-based dielectric layer 108A.

[0107] Use the photoresist layer 109 as a mask, expose using the photoresist, pattern the gate region on the above wafer, and place the developed wafer in an ion beam etcher (IBE) to etch away the second silicon-based dielectric layer 108B. The etching process is carried out at a relatively high chamber pressure (100 Pa), and the atmosphere used is CHF 3 , SF 6 , CF 4 , O2 A mixed gas with equal proportions, the pressure in the reaction chamber is 13.3 Pa. In an oxygen-containing atmosphere, the F-based gas cannot etch Al. 2 O 3 The etch stop layer 107 can achieve automatic etch stop and prevent damage to the underlying dielectric material during the etching process.

[0108] Use an organic cleaning method such as acetone to remove the photoresist layer 109. After using the piranha solution to remove the residual organic matter, deposit a stack gate contact metal 110 of Ti / Al / Ti = 20 / 200 / 20 nm in the gate region using electron beam evaporation technology. Use photoresist development to define the source-drain electrode contact area, and use the ICP etching process or the RIE etching process for etching. Etch the dielectric layer, barrier layer, and part of the channel layer under the source-drain contact area, and deposit a stack metal of Ti / Al / Ti / TiN = 20 / 130 / 50 / 50 nm. 2 After rapid annealing at 890 °C for 180 s in an N atmosphere, the source contact metal 111A and drain contact metal 111B of ohmic contact are prepared.

[0109] By using the above oxygen-containing etching process, the uniformity of the gate dielectric window etching can be achieved, avoiding over-etching of the barrier layer and surface damage during the etching process, and reducing the damage of the interface etching to the device performance.

[0110] The device structure and the corresponding preparation method provided in this embodiment belong to another type of typical GaN HEMT device, using an insulating layer and a metal gate, a gallium nitride device similar to the MOSFET structure. 2 O 3 Al can act as an etch stop layer while retaining the silicon-based dielectric insulating layer in the area under the gate. This composite dielectric layer can further improve the gate breakdown voltage and reduce gate leakage. This embodiment can illustrate that the self-stop etching technical solution provided by the present invention can be used for GaN HEMTs with various structures and has general applicability to the manufacture of depletion-mode HEMTs.

[0111] Based on the above embodiments and comparative examples, it can be clear that the technical solution provided by the embodiments of the present invention inserts a layer of alumina between the silicon-based dielectric layer and the substrate as an etch stop layer, and uses the phenomenon that the etching reaction activity of silicon oxide is significantly reduced after oxygen is incorporated into the fluorine-based gas to improve the etching selectivity between the etch stop layer and the silicon-based dielectric layer, thereby playing an obvious etch stop role, which is significantly helpful for improving the depth uniformity, the roughness of the etched bottom surface, and avoiding etching damage to the semiconductor material, and is very suitable for constructing high-quality GaN HEMT devices and other applications.

[0112] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. It is not intended to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims

1. A self-termination etching method for a silicon-based dielectric layer, characterized in that: include: Providing a substrate, and forming an aluminum oxide layer on the surface of the substrate as an etching stop layer; Growing and covering the surface of the etching stop layer to form a silicon-based dielectric layer; The silicon-based dielectric layer is ion-beam etched using a fluorine-based etching atmosphere, and oxygen is doped into the fluorine-based etching atmosphere to reduce the reactivity of the fluorine-based gas in the fluorine-based etching atmosphere to the etching stop layer, and the etching is terminated at the etching stop layer.

2. The self-termination etching method according to claim 1, characterized in that: The volume ratio of oxygen in the fluorine-based etching atmosphere is 1-40%; And / or, the pressure of the fluorine-based etching atmosphere is 10-100 Pa.

3. The self-termination etching method according to claim 1, characterized in that: The temperature of the ion beam etching is 15-35° C., the radio frequency power is 100-400 W, the fluorine-based gas flow rate is 10-40 sccm, and the inert carrier gas flow rate is 10-40 sccm; And / or, the fluorine-based gas includes any one of SF6, CHF3, CF4 or a combination of two thereof.

4. The self-termination etching method according to claim 1, characterized in that: The thickness of the aluminum oxide layer is 5-30 nm; And / or, the number of cycles of the atomic layer deposition is 60-300 times.

5. The self-termination etching method according to claim 1, characterized in that: The silicon-based dielectric layer includes SiN x and / or SiO2; And / or, the fluorine-based gas includes any one of CHF3, SF6, CF4 or a combination of two or more thereof.

6. The self-termination etching method according to claim 1, characterized in that: Also includes: A patterned mask layer is constructed above the silicon-based dielectric layer, and the silicon-based dielectric layer is patterned etched using the patterned mask layer.

7. A method for manufacturing a GaN HEMT device, characterized in that: include: Forming at least a channel layer and a barrier layer in sequence on a substrate to obtain a base; Using the self-termination etching method according to any one of claims 1 to 6 to form a graphic structure on the surface of the substrate, the graphic structure includes an etch stop layer and a silicon-based dielectric layer formed in sequence, and in the gate region, the silicon-based dielectric layer is ion beam etched to expose the etch stop layer; forming a gate in the gate region, and forming a source and a drain on both sides of the gate region respectively; The source electrode and the drain electrode at least form an ohmic contact with the barrier layer.

8. The method according to claim 7, characterized in that: The base comprises a substrate, a transition layer, a high resistance layer, the channel layer, an insertion layer and the barrier layer which are sequentially stacked along a specified direction.

9. The manufacturing method according to claim 7, characterized in that: The process of forming the source and / or drain specifically includes: Etching the corresponding position of the non-gate region by ICP etching and / or RIE etching, and the etching depth extends to the channel layer to form an electrode region; A stacked metal is deposited in the electrode region and annealed as a whole, so that the stacked metal forms an ohmic contact with the side wall of the barrier layer and the channel layer.

10. The GaN HEMT device manufactured by the manufacturing method according to any one of claims 7 to 9, characterized in that: It comprises a substrate and a gate, a source and a drain arranged accordingly, wherein the substrate comprises a channel layer, a barrier layer, an etching stop layer and a silicon-based dielectric layer stacked along a specified direction; In the gate region, the silicon-based dielectric layer forms an etching gap, the etching gap penetrates the silicon-based dielectric layer and extends to the etching stop layer, and at least a part of the structure of the gate is filled in the etching gap; The source electrode and the drain electrode are respectively arranged on both sides of the gate region, and the source electrode and the drain electrode penetrate the silicon-based dielectric layer and the etching stop layer to at least form an ohmic contact with the barrier layer.

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