Semiconductor structure and preparation method thereof
By etching into grooves in the test area of the substrate and preparing test devices, the problem that the existing technology cannot monitor the internal loss of the substrate is solved, and effective monitoring of the impact on product performance and improvement of yield is achieved.
Patent Information
- Application Number
- CN202510218610.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2025-05-27
AI Technical Summary
The existing test structure cannot effectively monitor the internal loss defects of the substrate, resulting in the inability to judge the impact of the internal loss of the substrate on product performance.
The internal loss of the substrate is monitored by etching the grooves in the test area of the substrate and forming a test device at the bottom of the grooves and within the substrate.
Effectively monitor the impact of the internal loss of the substrate on product performance to avoid yield loss caused by omission defects.
Smart Images
Figure CN120050966A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art
[0002] WAT (wafer acceptance test) refers to the electrical testing of various test structures (test keys) on a wafer after the entire wafer fabrication is completed but before packaging. By analyzing the WAT data, problems in the semiconductor manufacturing process can be discovered to assist in adjusting the manufacturing process.
[0003] However, internal damage defects of the substrate (such as dislocations, etc.) are difficult to detect during incoming inspection because they are not surface damages and have small sizes. Current test structures also have difficulty monitoring the internal damage of the substrate, so it is impossible to determine the impact of the internal damage of the substrate on product performance. Summary of the Invention
[0004] The purpose of this application is to provide a semiconductor structure, a method for manufacturing the same, and a semiconductor structure to solve the problem that existing test structures cannot monitor the impact of internal damage of the substrate on product performance.
[0005] To achieve the above purpose, this application provides a method for manufacturing a semiconductor structure, including:
[0006] Providing a substrate, where the substrate has a test region;
[0007] Etching the substrate to form a groove in the test region, where the groove extends from the surface of the substrate into the substrate;
[0008] Forming a test device in the test region, where a part of the test device is located on the substrate at the bottom of the groove and another part is located inside the substrate.
[0009] Optionally, the substrate further has a normal cell region, and the step of etching the substrate to form the groove includes:
[0010] Etching the substrate to form the groove in the test region and form isolation grooves in the normal cell region;
[0011] Filling isolation materials in the groove and the isolation grooves to form an isolation structure in the isolation grooves; and,
[0012] Removing the isolation materials in the groove.
[0013] Optionally, the substrate further has a normal cell region. When forming the test device in the test region, a normal device is also formed synchronously in the normal cell region, and the normal device has the same structure as the test device.
[0014] Optionally, the lateral width of the test device is greater than the lateral width of the normal device.
[0015] Optionally, the test device and the normal device are at least one of a MOS transistor, a capacitor, a triode, and a diode.
[0016] Optionally, the test device is a MOS transistor. The MOS transistor includes a first source / drain region and a first gate structure. The first gate structure is located on the substrate within the groove, and the first source / drain region is located within the substrate on both sides of the first gate structure, and the first source / drain region extends along the sidewall of the groove to the surface of the substrate.
[0017] The present application also provides a semiconductor structure, including:
[0018] A substrate having a test region;
[0019] A groove located within the test region and extending from the surface of the substrate into the substrate;
[0020] A test device located within the test region, with a part located on the substrate at the bottom of the groove and another part located within the substrate.
[0021] Optionally, the test device includes at least one of a MOS transistor, a capacitor, a triode, and a diode.
[0022] Optionally, the test device is a MOS transistor. The MOS transistor includes a first source / drain region and a first gate structure. The first gate structure is located on the substrate within the groove, and the first source / drain region is located within the substrate on both sides of the first gate structure, and the first source / drain region extends along the sidewall of the groove to the surface of the substrate.
[0023] Optionally, the substrate further has a normal cell region, and the semiconductor structure further includes a normal device. The normal device is located within the normal cell region and has the same structure as the test device.
[0024] In the semiconductor structure and its manufacturing method provided by the present invention, a substrate is provided, and the substrate has a test region; the substrate is etched to form a groove in the test region, and the groove extends from the surface of the substrate into the substrate; a test device is formed in the test region, and a part of the test device is located on the substrate at the bottom of the groove, and the other part is located in the substrate. In this application, the substrate is first etched to form the groove. After etching the substrate, the internal damage defects of the substrate are amplified. At the same time, the groove can expose the internal region of the substrate. By fabricating the test device on the substrate at the bottom of the groove and in the substrate, testing the test device can effectively monitor the impact of the internal damage of the substrate on the product performance, and avoid the problem of yield loss caused by missed defects. Description of the Drawings
[0025] Figure 1 is a manufacturing method of the semiconductor structure provided in the first embodiment of the present application;
[0026] Figures 2 to 7 is a schematic structural diagram corresponding to the corresponding steps of the manufacturing method of the semiconductor structure provided in the first embodiment of the present application, where Figure 7 is a schematic structural diagram of the semiconductor structure provided in the second embodiment of the present application;
[0027] Figure 8 is a schematic structural diagram of the semiconductor structure provided in the second embodiment of the present application;
[0028] Among them, the reference numerals are:
[0029] 100 - Substrate; 100a - Test region; 100b - Normal unit region; 201 - Buffer dielectric layer; 202 - Mask layer; 200a - Groove; 200b - Isolation groove; 300 - Isolation material layer; 400 - Photoresist layer; Well1 - First well region; Well2 - Second well region; 501 - First gate structure; 502 - First source / drain region; 503 - First metal silicide layer; 601 - Second gate structure; 602 - Second source / drain region; 603 - Second metal silicide layer; 504 - First dielectric layer; 505 - First upper plate layer; 604 - Second dielectric layer; 605 - Second upper plate layer. Detailed Embodiments
[0030] The following will describe the detailed embodiments of the present application in more detail with reference to the schematic diagrams. According to the following description, the advantages and features of the present application will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present application.
[0031] Embodiment 1
[0032] Figure 1 The manufacturing method of the semiconductor structure provided in this embodiment. As Figure 1 shown, the manufacturing method of the semiconductor structure includes:
[0033] Step S100: Provide a substrate, the substrate having a test region;
[0034] Step S200: Etch the substrate to form a groove within the test region, the groove extending from the surface of the substrate into the substrate;
[0035] Step S300: Form a test device within the test region, a part of the test device being located on the substrate at the bottom of the groove and another part being located within the substrate.
[0036] Figures 2 to 7 The structural schematic diagram corresponding to the corresponding steps of the manufacturing method of the semiconductor structure provided in this embodiment. Next, it will be described in detail in conjunction with Figures 2 to 7 the manufacturing method of the semiconductor structure provided in this embodiment.
[0037] As Figure 2 shown, perform Step S100 to provide the substrate 100. The substrate 100 can be, for example, at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductor materials, and also includes multi-layer structures composed of these semiconductor materials, etc., or is silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. In this embodiment, the substrate 100 has a test region 100a and a normal unit region 100b. The test region 100a is a region for forming various test devices (such as WAT test devices), and the normal unit region 100b is a region for forming normal devices (forming the final product). Generally speaking, the substrate 100 can be a wafer at this time. The test region 100a can be the dicing region (the region where the dicing lane is located) of the substrate 100, and the normal unit region 100b is the region of the substrate 100 other than the test region 100a, but it should not be limited thereto.
[0038] Please continue to refer to Figure 2, Step S200 is performed to sequentially form a buffer dielectric layer 201 and a mask layer 202 on the substrate 100. The buffer dielectric layer 201 covers the top surface of the substrate 100, and the mask layer 202 covers the top surface of the buffer dielectric layer 201. The material of the buffer dielectric layer 201 can be an oxidation material, such as silicon oxide, silicon oxynitride, or silicon carbonitride, etc. The buffer dielectric layer 201 can be an oxide layer naturally formed on the surface of the substrate 100 or intentionally formed by a deposition process, and this application does not limit it. The material of the mask layer 202 can be a nitride material, such as silicon nitride, etc.
[0039] Next, a part of the depth of the mask layer 202, the buffer dielectric layer 201, and the substrate 100 is etched to form a groove 200a in the test area 100a, and at the same time, an isolation groove 200b is formed in the normal cell area 100b. Both the groove 200a and the isolation groove 200b penetrate downward from the top surface of the mask layer 202 through the mask layer 202 and the buffer dielectric layer 201 and then extend into the substrate 100. After etching the substrate 100, the internal damage defects of the substrate 100 can be magnified, and at the same time, the groove 200a can expose the internal area of the substrate 100.
[0040] As Figure 3 shown, an isolation material is filled in the groove 200a and the isolation groove 200b. At the same time, the isolation material also covers the mask layer 202, and all the isolation materials form an isolation material layer 300. The isolation material layer 300 covers the mask layer 202 on the front side and fills the groove 200a and the isolation groove 200b, so as to form an isolation structure in the isolation groove 200b. The isolation structure is a trench isolation structure and is located in the normal cell area 100b.
[0041] From Figure 3 it can be seen that the area of the isolation material layer 300 corresponding to the groove 200a and the isolation groove 200b is sunken downward, so the surface of the isolation material layer 300 is not flat.
[0042] As Figure 4 shown, a photoresist layer 400 is formed on the isolation material layer 300, and the photoresist layer 400 is patterned to remove the photoresist layer 400 in the test area 100a and retain a part of the photoresist layer 400 in the normal cell area 100b. After patterning, the remaining photoresist layer 400 covers a part of the isolation material layer 300 in the normal cell area 100b, exposing the isolation material layer 300 in the test area 100a and a part of the isolation material layer 300 in the normal cell area 100b.
[0043] Please continue to refer to Figure 4 Figure 4 , using the remaining photoresist layer 400 as a mask, etch to remove all of the isolation material layer 300 within the test region 100a and a portion of the isolation material layer 300 within the normal cell region 100b, but a portion of the isolation material layer 300 within the normal cell region 100b is retained, and the isolation structure is not damaged.
[0044] As Figure 5 shown, use a photoresist stripping process to remove the remaining photoresist layer 400, and perform a polishing process to remove the excess isolation material layer 300 on the top surface of the mask layer 202, so that the top surface of the entire mask layer 202 is exposed. Then use an etching process to remove the mask layer 202 and the buffer dielectric layer 201 until the top surface of the substrate 100 is exposed.
[0045] Next, perform step S300 to form test devices within the test region 100a and simultaneously form normal devices within the normal cell region 100b. Since the normal devices and the test devices are prepared synchronously, the structures of the normal devices and the test devices are the same.
[0046] Optionally, the test devices and the normal devices can be at least one of MOS transistors, capacitors, bipolar transistors, and diodes. Next, taking the test devices and the normal devices as MOS transistors as an example, the steps of forming test devices within the test region 100a and simultaneously forming the normal devices within the normal cell region 100b will be described in detail.
[0047] As Figure 6 shown, perform ion implantation on the substrate 100 through an ion implantation process to form a first well region Well1 within the substrate 100 within the test region 100a, and simultaneously form a second well region Well2 within the substrate 100 within the normal cell region 100b. Both the first well region Well1 and the second well region Well2 extend from the surface of the substrate 100 into the substrate 100. The types of ions implanted into the first well region Well1 and the second well region Well2 are the same. For example, N-type ions can be implanted into both or P-type ions can be implanted into both. As can be seen from Figure 6 it, the first well region Well1 straddles the groove 200a.
[0048] Please continue to refer to Figure 6, a first gate structure 501 is formed on the substrate 100 within the test region 100a, and at the same time, a second gate structure 601 is formed on the substrate 100 within the normal cell region 100b. The first gate structure 501 is located on the substrate 100 at the bottom of the groove 200a. Therefore, the first gate structure 501 is also located above the first well region Well1, and the second gate structure 601 is located above the second well region Well2. The first gate structure 501 and the second gate structure 601 have the same structure. For example, both the first gate structure 501 and the second gate structure 601 may include a gate oxide layer, a gate electrode layer, and gate sidewalls. The gate oxide layer and the gate electrode layer are stacked in sequence from bottom to top, and the gate sidewalls cover the sidewalls of the gate oxide layer and the gate electrode layer.
[0049] As Figure 7 shown, ion implantation is performed on the first well region Well1 and the second well region Well2 to form a first source / drain region 502 on both sides of the first gate structure 501 and a second source / drain region 602 on both sides of the second gate structure 601. The first source / drain region 502 extends from the top surface of the first well region Well1 into the first well region Well1, and the second source / drain region 602 extends from the top surface of the second well region Well2 into the second well region Well2. The ion types implanted in the first source / drain region 502 and the second source / drain region 602 are the same. For example, N-type ions or P-type ions can be implanted uniformly.
[0050] It should be noted that the first source / drain region 502 is located within the substrate 100 on both sides of the first gate structure 501, and the first source / drain region 502 extends along the sidewall of the groove 200a to the surface of the substrate 100; while the second source / drain region 602 is located within the substrate 100 on both sides of the second gate structure 601, and the second source / drain region 602 is located on the surface of the substrate 100.
[0051] Please continue to refer to Figure 7, a first metal silicide layer 503 is formed on top of the gate electrode layer of the first source-drain region 502 and the first gate structure 501. At the same time, a second metal silicide layer 603 is formed on top of the gate electrode layer of the second source-drain region 602 and the second gate structure 601. The first metal silicide layer 503 and the second metal silicide layer 603 are used to reduce the contact resistance. In this way, the test device can be formed in the test region 100a, and at the same time, the normal device can be formed synchronously in the normal cell region 100b. Among them, the test device includes a first gate structure 501, a first source-drain region 502 and a first metal silicide layer 503. The first gate structure 501 and the first metal silicide layer 503 are located on the substrate 100, and the first source-drain region 502 is located in the substrate 100; the normal device includes a second gate structure 601, a second source-drain region 602 and a second metal silicide layer 603. The second gate structure 601 and the second metal silicide layer 603 are located on the substrate 100, and the second source-drain region 602 is located in the substrate 100.
[0052] Next, a plurality of interconnect structures can be formed on the substrate 100. Each interconnect structure is correspondingly interconnected with the gate electrode layer of the first gate structure 501, the first metal silicide layer 503, the gate electrode layer of the second gate structure 601, and the second metal silicide layer 603, so as to lead out the first gate structure 501, the first source-drain region 502, the second gate structure 601, and the second source-drain region 602.
[0053] The interconnect structure generally includes a plug and a metal layer. Since the first source-drain region 502 extends along the sidewall of the groove 200a to the surface of the substrate 100, the plug structure for leading out the first source-drain region 502 can only extend to the surface of the substrate 100 without extending into the groove 200a, thereby reducing the height difference between the plug structure for leading out the first source-drain region 502 and the plug structure for leading out the second source-drain region 602, and further reducing the manufacturing difficulty of the device.
[0054] After that, a voltage can be applied to the first gate structure 501 and the first source-drain region 502 by using the interconnection structure, so as to perform an electrical test on the test device. For example, parameters such as the threshold voltage of the test device can be tested. Since a part of the test device is located on the substrate 100 at the bottom of the groove 200a and another part is located within the substrate 100, performing an electrical test on the test device can effectively monitor the influence of the internal damage of the substrate 100 on the product performance (for example, monitoring whether the threshold voltage of the test device drifts to confirm the influence of the internal damage of the substrate 100 on the product performance), and avoid the problem of yield loss caused by missed defects. At the same time, the groove 200a in the test region 100a and the trench isolation structure in the normal cell region 100b are fabricated together, and the test device is fabricated together with the normal device. Therefore, the semiconductor structure can be formed in the present application without changing the process flow.
[0055] Figure 7 It is a schematic structural diagram of the semiconductor structure provided in this embodiment. As Figure 7 shown, the semiconductor structure includes the substrate 100, the groove 200a, and the test device.
[0056] Among them, the substrate 100 has a test region 100a, and the test region 100a is a region for forming various test devices (such as WAT test devices). Generally speaking, the substrate 100 can be a wafer at this time, and the test region 100a can be the dicing region (the region where the dicing lane is located) of the substrate 100.
[0057] There is a groove 200a in the substrate 100. The groove 200a is located in the test region 100a and extends from the surface of the substrate 100 into the substrate 100. The test device is located in the test region 100a, and a part of the test device is located on the substrate 100 at the bottom of the groove 200a, and another part is located within the substrate 100.
[0058] Specifically, the test device can be at least one of a MOS transistor, a capacitor, a triode, and a diode. In this embodiment, the test device is a MOS transistor, which includes a first gate structure 501, a first source / drain region 502, and a first metal silicide layer 503. The first gate structure 501 and the first metal silicide layer 503 are located on the substrate 100, specifically on the substrate 100 at the bottom of the groove 200a. The first source / drain region 502 is located within the substrate 100, specifically within the first well region Well1 within the test region 100a of the substrate 100. The first gate structure 501 can include a gate oxide layer, a gate electrode layer, and a gate sidewall. The gate oxide layer and the gate electrode layer are stacked in sequence from bottom to top, and the gate sidewall covers the sidewalls of the gate oxide layer and the gate electrode layer. The first source / drain region 502 extends from the top surface of the first well region Well1 into the first well region Well1, and the first source / drain region 502 is located on both sides of the first gate structure 501. The first metal silicide layer 503 is located on the top of the first source / drain region 502 and the gate electrode layer of the first gate structure 501.
[0059] Further, the first source / drain region 502 is located within the substrate 100 on both sides of the first gate structure 501, and the first source / drain region 502 extends along the sidewall of the groove 200a to the surface of the substrate 100.
[0060] Perform an electrical test on the test device. For example, parameters such as the threshold voltage of the test device can be tested. Since a part of the test device is located on the substrate 100 at the bottom of the groove 200a (the first gate structure 501 and the first metal silicide layer 503), and another part is located within the substrate 100 (the first source / drain region 502), performing an electrical test on the test device can effectively monitor the impact of internal damage of the substrate 100 on product performance (for example, monitoring whether the threshold voltage of the test device has drifted to confirm the impact of internal damage of the substrate 100 on product performance), and avoid the problem of yield loss caused by missing defects.
[0061] Further, the semiconductor structure further includes a normal device. The normal device is located within the normal unit region 100b of the substrate, and the structure of the normal device is the same as that of the test device. Specifically, the normal device can also be at least one of a MOS transistor, a capacitor, a triode, and a diode.
[0062] When both the test device and the normal device are MOS transistors, the normal device includes a second gate structure 601, second source / drain regions 602, and a second metal silicide layer 603. The second gate structure 601 and the second metal silicide layer 603 are located on the substrate 100, specifically on the substrate 100 within the normal cell region 100b. The second source / drain regions 602 are located within the substrate 100, specifically within the second well region Well2 within the substrate 100 within the normal cell region 100b. The second gate structure 601 may include a gate oxide layer, a gate electrode layer, and gate sidewalls. The gate oxide layer and the gate electrode layer are stacked in sequence from bottom to top, and the gate sidewalls cover the sidewalls of the gate oxide layer and the gate electrode layer. The second source / drain regions 602 extend from the top surface of the second well region Well2 into the second well region Well2, and the second source / drain regions 602 are located on both sides of the second gate structure 601. The second metal silicide layer 603 is located on top of the second source / drain regions 602 and the gate electrode layer of the second gate structure 601.
[0063] Further, the second source / drain regions 602 are located within the substrate 100 on both sides of the second gate structure 601, and the second source / drain regions 602 are located on the surface of the substrate 100.
[0064] Further, the lateral width of the test device is also greater than the lateral width of the normal device, so as to further magnify the internal damage defects of the substrate 100 and improve the monitoring effect.
[0065] Embodiment 2
[0066] Figure 8 The structural schematic diagram of the semiconductor structure provided in this embodiment is as follows. As Figure 8 shown, the difference from Embodiment 1 is that in this embodiment, the test device in the semiconductor structure is a capacitor. Specifically, the test device includes a first dielectric layer 504 and a first upper electrode layer 505. The first dielectric layer 504 is located on the substrate 100 at the bottom of the groove 200a, and the first upper electrode layer 505 is located on the first dielectric layer 504. More particularly, the substrate 100 is also part of the test device, specifically serving as the first lower electrode layer of the test device.
[0067] Perform an electrical test on the test device. For example, parameters such as the capacitance value of the test device can be tested. Since a part of the test device is located on the substrate 100 at the bottom of the groove 200a (the first dielectric layer 504 and the first upper electrode layer 505), and another part is located within the substrate 100 (the substrate 100 serves as the first lower electrode layer), performing an electrical test on the test device can effectively monitor the impact of the internal loss of the substrate 100 on the product performance (for example, monitoring whether the capacitance value of the test device has drifted to confirm the impact of the internal loss of the substrate 100 on the product performance), and avoid the problem of yield loss caused by missed defects.
[0068] When fabricating the semiconductor structure in this embodiment, the difference from the first embodiment is that after removing the mask layer 202 and the buffer dielectric layer 201 in the first embodiment (see Figure 5 ), as Figure 8 shown, a dielectric material layer and an upper electrode material layer are sequentially formed on the substrate 100 ( Figure 8 not shown in the figure). The dielectric material layer covers the substrate 100, and the upper electrode material layer covers the dielectric material layer. Then, the upper electrode material layer and the dielectric material layer are etched, and a part of the upper electrode material layer and the dielectric material layer at the bottom of the groove 200a are retained as the first upper electrode layer 505 and the first dielectric layer 504 of the test device, and a part of the upper electrode material layer and the dielectric material layer in the normal cell region 100b are retained as the second upper electrode layer 605 and the second dielectric layer 604 of the normal device. The substrate 100 also serves as the second lower electrode of the normal device.
[0069] It can be understood that in this embodiment, the groove 200a in the test region 100a and the trench isolation structure in the normal cell region 100b are fabricated together, and the test device and the normal device are fabricated together. Therefore, the semiconductor structure can be formed without changing the process flow in this application.
[0070] In summary, in the semiconductor structure and its manufacturing method provided by the embodiments of the present application, a substrate 100 is provided, and the substrate 100 has a test region 100a; the substrate 100 is etched to form a groove 200a in the test region 100a, and the groove 200a extends from the surface of the substrate 100 into the substrate 100; a test device is formed in the test region 100a, and a part of the test device is located on the substrate 100 at the bottom of the groove 200a, and the other part is located in the substrate 100. In the present application, the substrate 100 is first etched to form the groove 200a. After the substrate 100 is etched, the internal damage defects of the substrate 100 are amplified. At the same time, the groove 200a can expose the internal region of the substrate 100. By fabricating the test device on the substrate 100 at the bottom of the groove 200a and within the substrate 100, testing the test device can effectively monitor the impact of the internal damage of the substrate 100 on the product performance, and avoid the problem of yield loss caused by missed defects.
[0071] It should be noted that the embodiments in this specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the system disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.
[0072] It should also be noted that although the present application has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present application. For any person skilled in the art, without departing from the scope of the technical solution of the present application, many possible changes and modifications can be made to the technical solution of the present application by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still belong to the scope of protection of the technical solution of the present application.
[0073] It should also be understood that unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequential relationship, etc. between each component, element, step.
[0074] It should also be recognized that the terminology described herein is only used to describe specific embodiments and is not intended to limit the scope of the present application. It must be noted that the singular forms "a" and "an" used herein and in the appended claims include plural referents unless the context clearly dictates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices and may include sub-steps and sub-devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" definition unless the context clearly dictates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the present application may include performing selected tasks manually, automatically, or in combination.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate having a test area; Etching the substrate to form a groove in the test area, wherein the groove extends from the surface of the substrate into the substrate; A test device is formed in the test area, a portion of the test device is located on the substrate at the bottom of the groove, and another portion of the test device is located in the substrate.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The substrate also has a normal cell region, and the step of etching the substrate to form the groove comprises: Etching the substrate to form the groove in the test area and to form an isolation groove in the normal cell area; Filling the groove and the isolation trench with an isolation material to form an isolation structure in the isolation trench; and, The isolation material in the groove is removed.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The substrate further has a normal cell region. When the test device is formed in the test region, a normal device is also formed in the normal cell region simultaneously. The normal device has the same structure as the test device.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The lateral width of the test device is greater than the lateral width of the normal device.
5. The method for preparing a semiconductor structure according to claim 3, characterized in that: The test device and the normal device are at least one of a MOS tube, a capacitor, a triode and a diode.
6. The method for preparing a semiconductor structure according to claim 1, wherein: The test device is a MOS tube, which includes a first source and drain region and a first gate structure. The first gate structure is located on the substrate in the groove, the first source and drain region is located in the substrate on both sides of the first gate structure, and the first source and drain region extends along the side wall of the groove to the surface of the substrate.
7. A semiconductor structure, characterized in that: include: a substrate having a test area; a groove located in the test area and extending from the surface of the substrate into the substrate; A test device is located in the test area, with a portion thereof being located on the substrate at the bottom of the groove and another portion thereof being located in the substrate.
8. The semiconductor structure according to claim 7, wherein: The test device includes at least one of a MOS tube, a capacitor, a triode and a diode.
9. The semiconductor structure according to claim 7, wherein: The test device is a MOS tube, which includes a first source and drain region and a first gate structure. The first gate structure is located on the substrate in the groove, the first source and drain region is located in the substrate on both sides of the first gate structure, and the first source and drain region extends along the side wall of the groove to the surface of the substrate.
10. The semiconductor structure according to any one of claims 7 to 9, characterized in that: The substrate further comprises a normal cell region, and the semiconductor structure further comprises a normal device, wherein the normal device is located in the normal cell region and has the same structure as the test device.