Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: forming an initial first dielectric layer on an isolation structure after a dummy gate is formed, the initial first dielectric layer is located on the side wall of a fin part, and the initial first dielectric layer exposes the top of the fin part; the exposed fin part and the initial first dielectric layer are etched, a first dielectric layer is formed on the isolation structure, a groove is formed in the fin part, the first dielectric layer is formed by the initial first dielectric layer, and the bottom surface of the groove is lower than the top surface of the first dielectric layer; forming a source drain layer in the groove; a second dielectric layer is formed on the first dielectric layer, the second dielectric layer is located on the side wall of the dummy gate, an opening is formed in the second dielectric layer, and the opening exposes the surface of the source-drain layer and the surface of the first dielectric layer; the conductive layer is formed in the opening, so that the size of the source-drain layer is controlled, good contact between the conductive layer and the source-drain layer is obtained, contact resistance is reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] In the existing semiconductor field, a fin field-effect transistor (FinFET) is a new type of multi-gate device. Compared with a planar metal-oxide-semiconductor field-effect transistor (MOSFET), the fin field-effect transistor has stronger short-channel suppression ability and stronger operating current, and has now been widely used in various semiconductor devices.

[0003] However, the performance of the fin field-effect transistor formed by the existing technology still needs to be further improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of the formed semiconductor structure.

[0005] To solve the above technical problem, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a base, a fin portion located on the base, and an isolation structure, the isolation structure is located on the sidewall of the fin portion, and the top surface of the isolation structure is lower than the top surface of the fin portion; a gate located on the surface of the substrate and spanning the fin portion, the gate is located on the sidewall and the top surface of a part of the fin portion; a first dielectric layer located on the isolation structure, the first dielectric layer is located on the sidewall of the fin portion, a groove is formed in the fin portion, and the bottom surface of the groove is lower than the top surface of the first dielectric layer; a source-drain layer located in the groove; a second dielectric layer located on the first dielectric layer, the second dielectric layer is located on the sidewall of the gate, and an opening is formed in the second dielectric layer, the opening exposes the surface of the source-drain layer and the first dielectric layer; and a conductive layer located in the opening.

[0006] Optionally, the surface of the first dielectric layer is flat.

[0007] Optionally, the lowest point of the bottom surface of the groove is at a second preset distance from the top surface of the first dielectric layer, and the range of the second preset distance is 5 nm to 20 nm.

[0008] Optionally, it further includes: a sidewall located on the sidewall of the gate, and the sidewall is also located between the sidewall of the fin portion and the first dielectric layer.

[0009] Optionally, the thickness range of the first dielectric layer is 5 nm to 30 nm.

[0010] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a base, fin portions located on the base, and isolation structures, the isolation structures are located on the sidewalls of the fin portions, and the top surface of the isolation structures is lower than the top surface of the fin portions; forming a dummy gate across the fin portions on the surface of the substrate, the dummy gate is located on partial sidewalls and the top surface of the fin portions; after forming the dummy gate, forming an initial first dielectric layer on the isolation structures, the initial first dielectric layer is located on the sidewalls of the fin portions, and the initial first dielectric layer exposes the top of the fin portions; etching the exposed fin portions and the initial first dielectric layer to form a first dielectric layer on the isolation structures and form a groove in the fin portions, using the initial first dielectric layer to form the first dielectric layer, the bottom surface of the groove is lower than the top surface of the first dielectric layer; forming source-drain layers in the grooves; forming a second dielectric layer on the first dielectric layer, the second dielectric layer is located on the sidewalls of the dummy gate, and there is an opening in the second dielectric layer, the opening exposes the surface of the source-drain layers and the first dielectric layer; forming a conductive layer in the opening.

[0011] Optionally, the etching selectivity of the etching process for the fin portions and the initial first dielectric layer ranges from 10:1 to 100:1.

[0012] Optionally, it includes: there is a first preset distance between the top surface of the initial first dielectric layer and the top surface of the fin portions, and the range of the first preset distance is from 10 nm to 50 nm; the lowest point of the bottom surface of the groove has a second preset distance from the top surface of the first dielectric layer, and the range of the second preset distance is from 5 nm to 20 nm.

[0013] Optionally, the surface of the initial first dielectric layer is flat.

[0014] Optionally, after forming the dummy gate and before forming the initial first dielectric layer, it further includes: forming sidewalls on the sidewalls of the dummy gate and the fin portions.

[0015] Optionally, when etching the exposed fin portions and the initial first dielectric layer, the sidewalls are also etched; the etching selectivity of the etching process for the fin portions and the sidewalls ranges from 5:1 to 50:1.

[0016] Optionally, after forming the source-drain layers and before forming the second dielectric layer, it further includes: forming an etch stop layer on the surface of the first dielectric layer and the surface of the source-drain layers, the material of the etch stop layer is different from the material of the first dielectric layer and different from the material of the second dielectric layer.

[0017] Optionally, the method for forming the second dielectric layer and the opening includes: forming a second dielectric material layer on the substrate, the second dielectric material layer being higher than the top surface of the dummy gate; planarizing the second dielectric material layer until the dummy gate is exposed; forming a hard mask layer on the second dielectric material layer, the hard mask layer exposing a part of the second dielectric material layer; using the hard mask layer as a mask to etch the second dielectric material layer until the source / drain layer and the surface of the first dielectric layer are exposed, thereby forming the second dielectric layer and the opening.

[0018] Optionally, after the planarization process and before forming the hard mask layer, it further includes: replacing the dummy gate with a gate.

[0019] Optionally, the process for forming the source / drain layer includes a selective epitaxial growth process.

[0020] Optionally, the method for forming the initial first dielectric layer includes: forming a first dielectric material layer on the substrate, the top surface of the first dielectric material layer being higher than the top surface of the fin; planarizing the first dielectric material layer; after the planarization process, etching back the first dielectric material layer until a part of the sidewall of the fin is exposed, thereby forming the initial first dielectric layer.

[0021] Optionally, the material of the first dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0022] Optionally, the thickness range of the first dielectric layer is 5 nm to 30 nm.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In the method for forming the semiconductor structure provided by the technical solution of the present invention, an initial first dielectric layer is formed on the isolation structure, the exposed fin and the initial first dielectric layer are etched, and a groove is formed in the fin. Since the size of the initial first dielectric layer is large, during the etching process of forming the groove, by selecting an appropriate etching selectivity between the fin and the initial first dielectric layer, it is beneficial to precisely control the distance between the bottom surface of the groove and the top surface of the first dielectric layer. The epitaxial growth of the source / drain layer is restricted by the first dielectric layer, which is beneficial to controlling the size of the source / drain layer; in addition, when etching the second dielectric material layer to form an opening exposing the surface of the source / drain layer, the opening exposes the first dielectric layer without exposing the isolation structure at the bottom of the first dielectric layer, reducing the etching time, thereby reducing the etching damage to the source / drain layer, being beneficial to obtaining a good contact between the conductive layer and the source / drain layer, reducing the contact resistance, and thus improving the performance of the device.

[0025] Further, after forming the source / drain layer and before forming the second dielectric layer, an etch stop layer is also formed on the surface of the first dielectric layer and the surface of the source / drain layer. The material of the etch stop layer is different from that of the first dielectric layer and different from that of the second dielectric layer. When forming an opening exposing the surface of the source / drain layer, the etch stop layer can prevent further etching of the first dielectric layer, so the etching time can be reduced, thereby reducing the etching damage to the source / drain layer, facilitating obtaining a good contact between the conductive layer and the source / drain layer, reducing the contact resistance, and thus improving the performance of the device. Description of the Drawings

[0026] Figures 1 to 8 is a schematic structural diagram of each step of a method for forming a semiconductor structure;

[0027] Figures 9 to 21 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention. Detailed Embodiments

[0028] It should be noted that the "surface" and "on" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0029] As described in the background art, the performance of the fin field-effect transistor formed by the prior art still needs to be further improved. Now, a method for forming a semiconductor structure is used for illustration and analysis.

[0030] Figures 1 to 8 is a schematic structural diagram of each step of a method for forming a semiconductor structure.

[0031] Please refer to Figure 1 and Figure 2 , Figure 1 is a top view structural diagram, Figure 2 is Figure 1 a cross-sectional structural diagram along the EE1 direction in

[0032] Please refer to Figure 3 , etch the fin portions 101 on both sides of the dummy gate 103 and the sidewalls 104 of the fin portions 101 to form grooves 105 in the fin portions 101.

[0033] It should be noted that Figures 3 to 8 has the same view direction as Figure 2 .

[0034] Please refer to Figures 4 to 6 , and a source-drain layer 106 is formed in the groove 105.

[0035] It should be noted that Figures 4 to 6 are respectively used to schematically show the structures of the source-drain layer 106 formed under different morphologies of the groove 105.

[0036] Please continue to refer to Figure 5 on the basis of Figure 7 , and an interlayer dielectric layer 107 is formed on the substrate and the source-drain layer 106; a mask layer 108 is formed on the interlayer dielectric layer 107, and the mask layer 108 exposes a part of the interlayer dielectric layer 107; using the mask layer 108 as a mask, the interlayer dielectric layer 107 is etched until the source-drain layer 106 is exposed, and an opening 109 is formed in the interlayer dielectric layer 107.

[0037] Please continue to refer to Figure 7 on the basis of Figure 8 , and a zero-th metal layer 110 is formed in the opening 109.

[0038] In the method for forming the above fin field-effect transistor device, during the formation of the groove 105, due to the relatively thin sidewall 104 of the fin 101 sidewall and the etching selectivity difference between the sidewall 104 and the fin 101, etc., after the etching process, it is not easy to control the height of the sidewall 104 retained on the fin 101 sidewall. Since the sidewall 104 will limit the growth of the source-drain layer 106, when the height difference between the bottom of the groove 105 and the sidewall 104 is h2 (as shown in Figure 5 ), the morphology of the formed source-drain layer 106 is better. When the height difference h1 is too small (as shown in Figure 4 ), it is easy to cause the merging between adjacent source-drain layers 106. When the height difference h3 is too large (as shown in Figure 6 ), it is easy to cause the lateral dimension of the source-drain layer 106 to be smaller, and then it is difficult to form an ideal contact between the zero-th metal layer 110 and the source-drain layer 106, resulting in too large contact resistance and affecting the device performance. In addition, during the formation of the opening 109, it is easy to cause etching damage to the source-drain layer 106 (as shown by the dashed line in Figure 7 ), which will also cause the contact resistance between the zero-th metal layer 110 and the source-drain layer 106 to be too large and affect the device performance.

[0039] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same. An initial first dielectric layer is formed on the isolation structure, and the exposed fin portion and the initial first dielectric layer are etched to form a groove in the fin portion. Since the size of the initial first dielectric layer is relatively large, during the etching process of forming the groove, by selecting an appropriate etching selectivity between the fin portion and the initial first dielectric layer, it is beneficial to precisely control the distance between the bottom surface of the groove and the top surface of the first dielectric layer. The epitaxial growth of the source / drain layer is restricted by the first dielectric layer, which is beneficial to controlling the size of the source / drain layer. Additionally, when etching the second dielectric material layer to form an opening exposing the surface of the source / drain layer, the opening exposes the first dielectric layer but does not expose the isolation structure at the bottom of the first dielectric layer, reducing the etching time, thereby reducing the etching damage to the source / drain layer, facilitating obtaining a good contact between the conductive layer and the source / drain layer, reducing the contact resistance, and thus improving the performance of the device.

[0040] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of specific embodiments of the present invention is provided with reference to the accompanying drawings.

[0041] Figures 9 to 21 It is a schematic structural diagram of each step of the method for forming the semiconductor structure in the embodiment of the present invention.

[0042] Please refer to Figures 9 to 11 , Figure 9 which is a top view structural diagram omitting the sidewall material layer, Figure 10 and Figure 9 is a cross-sectional structural diagram along the MM1 direction in Figure 11 and Figure 9 is a cross-sectional structural diagram along the FF1 direction in . A substrate is provided, and the substrate includes a base 200, fin portions 201 located on the base 200, and an isolation structure 202. The isolation structure 202 is located on the sidewalls of the fin portions 201, and the top surface of the isolation structure 202 is lower than the top surface of the fin portions 201. A dummy gate 203 spanning the fin portions 201 is formed on the surface of the substrate, and the dummy gate 203 is located on the sidewalls and the top surface of some of the fin portions 201.

[0043] In this embodiment, the material of the base 200 is silicon. In other embodiments, the material of the base includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0044] In this embodiment, the material of the fin 201 is silicon. In other embodiments, the material of the fin 201 may also be germanium, germanium-silicon, or other materials.

[0045] In this embodiment, the material of the dummy gate 203 is polysilicon.

[0046] Subsequently, after forming the dummy gate 203, an initial first dielectric layer is formed on the isolation structure 202.

[0047] In this embodiment, after forming the dummy gate 203 and before forming the initial first dielectric layer, a spacer 204 is further formed on the sidewalls of the dummy gate 203 and the fin 201.

[0048] In this embodiment, the method for forming the spacer 204 includes: forming a spacer material layer (not shown in the figure) on the surface of the substrate and the dummy gate 203, and using the spacer material layer on the sidewalls of the dummy gate 203 and the fin 201 as the spacer 204.

[0049] Please refer to Figure 12 , Figure 12 The view direction of Figure 11 is the same as that of

[0050] After forming the dummy gate 203, an initial first dielectric layer 205 is formed on the isolation structure 202. The initial first dielectric layer 205 is located on the sidewall of the fin 201, and the top of the fin 201 is exposed by the initial first dielectric layer 205.

[0051] Specifically, the top of the fin 201 is exposed by the initial first dielectric layer 205 through the spacer material layer.

[0052] In this embodiment, there is a first preset distance d1 between the top surface of the initial first dielectric layer 205 and the top surface of the fin 201. The range of the first preset distance d1 is from 10 nm to 50 nm.

[0053] In this embodiment, the method for forming the initial first dielectric layer 205 includes: forming a first dielectric material layer (not shown in the figure) on the substrate, with the top surface of the first dielectric material layer being higher than the top surface of the fin 201; planarizing the first dielectric material layer; after the planarization process, etching back the first dielectric material layer until a part of the sidewall of the fin 201 is exposed, thereby forming the initial first dielectric layer 205.

[0054] The material of the initial first dielectric layer 205 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the initial first dielectric layer 205 is silicon oxide.

[0055] Please refer to Figure 13 , Figure 13 The view direction of Figure 12 is the same as that of Figure 12 . Etch the exposed fin 201 and the initial first dielectric layer 205 (as shown in Figure 12 ), form a first dielectric layer 206 on the isolation structure 202, and form a groove 207 in the fin 201. Use the initial first dielectric layer 205 to form the first dielectric layer 206, with the bottom surface of the groove 207 being lower than the top surface of the first dielectric layer 205.

[0056] Here, since the size of the initial first dielectric layer 205 is relatively large, during the etching process of forming the groove 207, selecting an appropriate etching selectivity between the fin 201 and the initial first dielectric layer 205 is beneficial for precisely controlling the distance between the bottom surface of the groove 207 and the top surface of the first dielectric layer 206. By using the first dielectric layer 206 to limit the epitaxial growth of the source-drain layer, it is beneficial for controlling the size of the source-drain layer.

[0057] In this embodiment, before etching the exposed fin 201 and the initial first dielectric layer 205, the sidewall material layer is also etched until the top surface of the fin 201 is exposed.

[0058] In this embodiment, the lowest point of the bottom surface of the groove 207 has a second preset distance d2 from the top surface of the first dielectric layer 206, and the range of the second preset distance d2 is 5 nm to 20 nm.

[0059] In this embodiment, while etching the exposed fin 201 and the initial first dielectric layer 205, the sidewall 204 is also etched.

[0060] In this embodiment, the etching selectivity of the etching process for the fin 201 and the sidewall 204 ranges from 5:1 to 50:1; since the sidewall of the sidewall 204 is protected by the initial first dielectric layer 205, the thickness of the sidewall 204 will not be too thin to cause uncontrollable etching. Selecting an appropriate etching selectivity for the fin 201 and the sidewall 204 is conducive to controlling the height of the sidewall 204 after etching.

[0061] In this embodiment, the etching selectivity of the etching process for the fin 201 and the initial first dielectric layer 205 ranges from 10:1 to 100:1.

[0062] The material of the first dielectric layer 206 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the first dielectric layer 206 is silicon oxide.

[0063] In this embodiment, the thickness range of the first dielectric layer 206 is 5 nm to 30 nm. The thickness refers to the dimension perpendicular to the surface of the substrate.

[0064] Please refer to Figure 14 , Figure 14 The view direction of Figure 13 is the same as that of Figure 13 . A source / drain layer 208 is formed in the groove 207 (as shown in

[0065] In this embodiment, the formation process of the source / drain layer 208 includes a selective epitaxial growth process.

[0066] Subsequently, a second dielectric layer is formed on the first dielectric layer 206. The second dielectric layer is located on the sidewalls of the pseudo-gate 203 and has an opening therein that exposes the surfaces of the source / drain layer 208 and the first dielectric layer 206.

[0067] In this embodiment, after forming the source / drain layer 208 and before forming the second dielectric layer, an etch stop layer 209 is further formed on the surfaces of the first dielectric layer 206 and the source / drain layer 208. The material of the etch stop layer 209 is different from that of the first dielectric layer 206 and different from that of the second dielectric layer.

[0068] In this embodiment, for the formation method of the second dielectric layer and the opening, please refer to Figures 15 to 18 .

[0069] Please refer to Figure 15 and Figure 16 . Figure 15 is a top view structural schematic diagram, Figure 16 is Figure 15Schematic cross-sectional structure diagram along the FF1 direction. A second dielectric material layer 210 is formed on the substrate, and the second dielectric material layer 210 is higher than the top surface of the dummy gate 203 (as Figure 10 shown); planarize the second dielectric material layer 210 until the dummy gate 203 is exposed.

[0070] The material of the second dielectric material layer 210 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride. The second dielectric material layer 210 is used to form a second dielectric layer. The material of the second dielectric layer may be the same as or different from the material of the first dielectric layer. In this embodiment, the material of the second dielectric layer is the same as the material of the first dielectric layer, and the material of the second dielectric material layer 210 is silicon oxide.

[0071] In this embodiment, after the planarization process, the dummy gate 203 is replaced with a gate 211.

[0072] The material of the gate 211 includes metal.

[0073] Please refer to Figure 17 and Figure 18 , Figure 17 which is a top view structure diagram, Figure 18 and Figure 17 is a schematic cross-sectional structure diagram along the FF1 direction in Figure 16 shown. A hard mask layer 212 is formed on the second dielectric material layer 210, and the hard mask layer 212 exposes a part of the second dielectric material layer 210 (as

[0074] shown); using the hard mask layer 212 as a mask, etch the second dielectric material layer 210 until the source / drain layer 209 and the surface of the first dielectric layer 206 are exposed, forming the second dielectric layer 213 and the opening 214.

[0075] In this embodiment, the materials of the first dielectric layer 206 and the second dielectric layer 213 are the same, and the etch stop layer 209 serves as an etch stop when forming the opening 214. When forming the opening 214 that exposes the surface of the source / drain layer 209, the etch stop layer 209 can prevent further etching of the first dielectric layer 206, so the etch time can be reduced, thereby reducing the etch damage to the source / drain layer 209, facilitating obtaining good contact between the conductive layer and the source / drain layer 209, reducing the contact resistance, and thus improving the performance of the device.

[0076] In another embodiment, when the materials of the first dielectric layer and the second dielectric layer are different, the etch stop layer may not be formed, and in the etching process of forming the opening, an etching process with a larger etching selectivity of the second dielectric layer to the first dielectric layer is selected.

[0077] Specifically, after forming the gate 211, the hard mask layer 212 is formed, and the hard mask layer 212 also lies on the surface of the gate 211.

[0078] Please refer to Figures 19 to 21 , Figure 19 for the top view structural schematic diagram, Figure 20 which is Figure 19 the cross-sectional structural schematic diagram along the MM1 direction in Figure 21 and Figure 19 the cross-sectional structural schematic diagram along the FF1 direction in , and a conductive layer 215 is formed in the opening 214.

[0079] In this embodiment, the material of the conductive layer 215 is metal.

[0080] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to Figures 19 to 21 , which includes: a substrate, the substrate includes a base 200, fins 201 located on the base 200, and isolation structures 202, the isolation structures 202 are located on the sidewalls of the fins 201, and the top surface of the isolation structures 202 is lower than the top surface of the fins 201; a gate 211 located on the surface of the substrate and spanning the fins 201, the gate 211 is located on the sidewalls and the top surface of part of the fins 201; a first dielectric layer 206 located on the isolation structures 202, the first dielectric layer 206 is located on the sidewalls of the fins 201, and the fins 201 have grooves 207 (such as Figure 13As shown, the bottom surface of the groove 207 is lower than the top surface of the first dielectric layer 206; a source / drain layer 208 located within the groove 207; a second dielectric layer 213 located on the first dielectric layer 206, the second dielectric layer 213 being located on the sidewalls of the gate 211, and an opening 214 being formed in the second dielectric layer 213 (as Figure 18 shown), the opening 214 exposing the surfaces of the source / drain layer 208 and the first dielectric layer 206; and a conductive layer 215 located within the opening 214.

[0081] In this embodiment, the surface of the first dielectric layer 206 is flat.

[0082] In this embodiment, the lowest point of the bottom surface of the groove 207 is at a second predetermined distance d2 from the top surface of the first dielectric layer 206, and the range of the second predetermined distance d2 is 5 nm to 20 nm.

[0083] In this embodiment, the semiconductor structure further includes: a spacer 204 located on the sidewalls of the gate 211 (as Figure 15 shown), and the spacer 204 is also located between the sidewalls of the fin 201 and the first dielectric layer 206.

[0084] In this embodiment, the thickness range of the first dielectric layer 206 is 5 nm to 30 nm.

[0085] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, comprising: a substrate including a base, fins located on the base, and isolation structures, the isolation structures being located on sidewalls of the fins, and a top surface of the isolation structures being lower than a top surface of the fins; a gate located on the substrate surface and spanning the fins, the gate being located on partial sidewalls and the top surface of the fins; a first dielectric layer located on the isolation structures, the first dielectric layer being located on sidewalls of the fins, a groove being formed in the fins, and a bottom surface of the groove being lower than a top surface of the first dielectric layer; a source-drain layer located in the groove; a second dielectric layer located on the first dielectric layer, the second dielectric layer being located on sidewalls of the gate, an opening being formed in the second dielectric layer, and the opening exposing surfaces of the source-drain layer and the first dielectric layer; a conductive layer located in the opening.

2. The semiconductor structure according to claim 1, characterized in that, the surface of the first dielectric layer is flat.

3. The semiconductor structure according to claim 1, characterized in that, a second preset distance is provided between a lowest point of the bottom surface of the groove and the top surface of the first dielectric layer, and the range of the second preset distance is from 5 nm to 20 nm.

4. The semiconductor structure according to claim 1, characterized in that, further comprising: a spacer located on sidewalls of the gate, and the spacer is further located between sidewalls of the fins and the first dielectric layer.

5. The semiconductor structure according to claim 1, characterized in that, the thickness range of the first dielectric layer is from 5 nm to 30 nm.

6. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate including a base, fins located on the base, and isolation structures, the isolation structures being located on sidewalls of the fins, and a top surface of the isolation structures being lower than a top surface of the fins; forming a dummy gate spanning the fins on the substrate surface, the dummy gate being located on partial sidewalls and the top surface of the fins; after forming the dummy gate, forming an initial first dielectric layer on the isolation structures, the initial first dielectric layer being located on sidewalls of the fins, and the initial first dielectric layer exposing the top of the fins; etching the exposed fins and the initial first dielectric layer to form a first dielectric layer on the isolation structures and form a groove in the fins, and using the initial first dielectric layer to form the first dielectric layer, and a bottom surface of the groove being lower than a top surface of the first dielectric layer; forming a source-drain layer in the groove; forming a second dielectric layer on the first dielectric layer, the second dielectric layer being located on sidewalls of the dummy gate, an opening being formed in the second dielectric layer, and the opening exposing surfaces of the source-drain layer and the first dielectric layer; forming a conductive layer in the opening.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, the etching selectivity ratio of the etching process for the fins and the initial first dielectric layer ranges from 10:1 to 100:

1.

8. The method for forming a semiconductor structure according to claim 6, characterized in that, comprising: There is a first preset distance between the top surface of the initial first dielectric layer and the top surface of the fin, and the range of the first preset distance is from 10 nm to 50 nm; The lowest point of the bottom surface of the groove is at a second preset distance from the top surface of the first dielectric layer, and the range of the second preset distance is from 5 nm to 20 nm.

9. The method for forming a semiconductor structure according to claim 6, characterized in that, The surface of the initial first dielectric layer is flat.

10. The method for forming a semiconductor structure according to claim 6, characterized in that, After forming the dummy gate and before forming the initial first dielectric layer, it further includes: forming sidewalls on the dummy gate and the sidewalls of the fin.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, While etching the exposed fin and the initial first dielectric layer, the sidewalls are also etched; the etching selectivity ratio of the etching process for the fin and the sidewalls ranges from 5:1 to 50:

1.

12. The method for forming a semiconductor structure according to claim 6, characterized in that, After forming the source / drain layer and before forming the second dielectric layer, it further includes: forming an etch stop layer on the surface of the first dielectric layer and the surface of the source / drain layer, and the material of the etch stop layer is different from the material of the first dielectric layer and different from the material of the second dielectric layer.

13. The method for forming a semiconductor structure according to claim 6, characterized in that, The method for forming the second dielectric layer and the opening includes: forming a second dielectric material layer on the substrate, and the second dielectric material layer is higher than the top surface of the dummy gate; planarizing the second dielectric material layer until the dummy gate is exposed; forming a hard mask layer on the second dielectric material layer, and the hard mask layer exposes a part of the second dielectric material layer; using the hard mask layer as a mask to etch the second dielectric material layer until the source / drain layer and the surface of the first dielectric layer are exposed, so as to form the second dielectric layer and the opening.

14. The method for forming a semiconductor structure according to claim 13, characterized in that, After the planarization process and before forming the hard mask layer, it further includes: replacing the dummy gate with a gate.

15. The method for forming a semiconductor structure according to claim 6, characterized in that, The formation process of the source / drain layer includes a selective epitaxial growth process.

16. The method for forming a semiconductor structure according to claim 6, characterized in that, The method for forming the initial first dielectric layer includes: forming a first dielectric material layer on the substrate, and the top surface of the first dielectric material layer is higher than the top surface of the fin; planarizing the first dielectric material layer; after the planarization process, back-etching the first dielectric material layer until a part of the sidewall of the fin is exposed, so as to form the initial first dielectric layer.

17. The method for forming a semiconductor structure according to claim 6, characterized in that, The material of the first dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride.

18. The method for forming a semiconductor structure according to claim 6, wherein, the thickness range of the first dielectric layer is from 5 nm to 30 nm.

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