Vertical ring gate transistor based on two-dimensional semiconductor material and preparation method

Abstract

The invention discloses a vertical ring gate transistor based on a two-dimensional semiconductor material and a preparation method, and belongs to the technical field of nano electronics. The vertical gate-all-around transistor comprises an insulating substrate arranged at a bottom layer, a bottom electrode arranged in the insulating substrate, a metal nano-column source electrode arranged at one end of the bottom electrode, an insulating dielectric layer arranged above the bottom electrode and the metal nano-column source electrode (the top end of the metal nano-column source electrode is partially exposed), and a gate electrode arranged on the insulating dielectric layer, the two-dimensional semiconductor material is arranged above the insulating dielectric layer, the drain electrode is arranged on the insulating dielectric layer covering the side of the metal nano-column source electrode, the insulating dielectric layer is arranged on the surfaces of the two-dimensional semiconductor material and the drain electrode, and the ring gate electrode is arranged on the outer ring of the insulating dielectric layer wrapping the whole metal nano-column source electrode. According to the vertical ring gate transistor, the gate regulation and control capability of the field effect transistor on the premise of a short channel can be effectively improved, the leakage current and the power consumption are effectively reduced, and the device performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of nanoelectronic technology, and in particular to a vertical ring-gate transistor based on two-dimensional semiconductor materials and a preparation method thereof. Background Art

[0002] As chip integration increases, the semiconductor industry has higher and higher requirements for the size of individual transistors. At the 22nm process node, the emergence of fin transistors continued Moore's Law and has been the mainstream structure of semiconductor devices for the past decade. However, at the 5nm technology node, the structural design of fin transistors is difficult to meet the needs of transistor electrostatic control, and leakage is difficult to control.

[0003] Due to their natural atomic-level thickness, two-dimensional semiconductor materials have excellent gate control effects. The mobility is relatively stable near the limit size (below 5nm), and low subthreshold swing and leakage current can be maintained. At present, the research on two-dimensional ring-gate structure is mainly focused on the planar ring-gate structure represented by multi-bridge channel transistors. Although it effectively improves the gate control effect of the material, there is still a lot of room for improvement in area efficiency, and the two-dimensional vertical ring-gate structure still needs to be further developed. Summary of the invention

[0004] The purpose of the present invention is to provide a vertical ring-gate transistor based on two-dimensional semiconductor materials and a preparation method to solve the problems existing in the above-mentioned prior art.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] One of the technical solutions of the present invention: a vertical gate-all-around transistor based on two-dimensional semiconductor materials, comprising:

[0007] Insulating substrate;

[0008] A bottom electrode, embedded on the surface of the insulating substrate;

[0009] A metal nanocolumn source electrode, disposed on the bottom electrode;

[0010] An insulating dielectric layer 1, covering the insulating substrate, the bottom electrode and surrounding the metal nanocolumn source electrode (the insulating dielectric layer 1 is wrapped around the surface of the metal nanocolumn source electrode, covers the bottom electrode and the insulating substrate, and reserves a position on the top of the metal nanocolumn source electrode to contact the two-dimensional semiconductor material layer);

[0011] A two-dimensional semiconductor material layer, covering the insulating dielectric layer 1 and the top surface of the metal nanocolumn source electrode;

[0012] An insulating dielectric layer 2 is arranged on the surface of the two-dimensional semiconductor material layer;

[0013] A drain electrode is arranged inside the insulating dielectric layer 2 and in contact with the two-dimensional semiconductor material layer (the drain electrode is arranged at a position where the two-dimensional semiconductor material layer covers the bottom of the metal nanocolumn source electrode);

[0014] A ring electrode wrapped around the side of the insulating dielectric layer 2 (the gate electrode wraps around the outer circle of the insulating dielectric layer 2 of the entire metal nanocolumn source electrode);

[0015] The total thickness of the insulating dielectric layer 1, the two-dimensional semiconductor material layer and the insulating dielectric layer 2 is less than the height of the metal nanocolumn source electrode.

[0016] The metal nanocolumns deposited inside the vertical ring-gate transistor of the present invention serve as the source electrode, forming a vertical structure with the drain electrode deposited at the bottom (the vertical structure can improve the area efficiency). The metal nanocolumns have a certain gate control effect on the two-dimensional semiconductor material, and combined with the ring-gate electrode, the subthreshold swing of the transistor is successfully reduced.

[0017] Furthermore, the insulating substrate is a silicon oxide substrate with a thickness of 90 to 300 nm;

[0018] The thickness of the bottom electrode and the drain electrode are independently 10 to 100 nm; the thickness of the bottom electrode is less than the thickness of the insulating substrate;

[0019] The metal nanocolumn source electrode has a diameter of 500nm to 6μm and a height of 10nm to 1μm;

[0020] The metal nanocolumn source electrode, bottom electrode and drain electrode are made of pure gold, or chromium metal and pure gold.

[0021] Further, the bottom electrode is arranged in a region pre-etched on the insulating substrate;

[0022] The metal nanocolumn source electrode is arranged at one end of the bottom electrode.

[0023] Furthermore, the thickness of the insulating dielectric layer 1 and the insulating dielectric layer 2 are independently 15 to 100 nm;

[0024] The thickness of the two-dimensional semiconductor material layer is 0.6-10 nm.

[0025] Furthermore, the materials of the insulating dielectric layer 1 and the insulating dielectric layer 2 are independently selected from hafnium oxide, zirconium oxide, aluminum oxide or silicon oxide;

[0026] The two-dimensional semiconductor material layer is a transition metal chalcogenide.

[0027] Furthermore, the two-dimensional semiconductor material layer is molybdenum disulfide, tellurene or black scale.

[0028] Furthermore, the ring gate electrode is made of pure gold, or chromium metal and pure gold;

[0029] The height of the ring gate electrode is the same as that of the metal nanocolumn source electrode.

[0030] Technical solution 2 of the present invention: A method for preparing the vertical gate-all-around transistor, comprising the following steps:

[0031] Performing patterned etching on the insulating substrate and depositing a bottom electrode in the etched area;

[0032] depositing a metal nanocolumn source electrode at one end of the bottom electrode;

[0033] An insulating dielectric layer 1 is deposited on the insulating substrate, the bottom electrode and the surface of the metal nanocolumn source electrode, and a position for contacting the two-dimensional semiconductor material layer is reserved on the top of the metal nanocolumn source electrode;

[0034] Transferring the two-dimensional semiconductor material layer to a position reserved for contact with the two-dimensional semiconductor material layer on the top of the metal nanocolumn source electrode and above the insulating dielectric layer 1;

[0035] Depositing a drain electrode at a position at the bottom of the metal nanocolumn source electrode covering the two-dimensional semiconductor material layer;

[0036] Depositing an insulating dielectric layer 2 on the surface of the two-dimensional semiconductor material layer and the drain electrode to form a nanocolumn structure;

[0037] A gate electrode is deposited on the outer circle of the nanocolumn structure to wrap the outer circle of the nanocolumn structure (the size and thickness of the circular ring structure of the cross-section of the gate electrode are matched with the size of the internal nanocolumn structure to ensure good contact) to obtain the vertical ring gate transistor.

[0038] Furthermore, the patterned etching method includes patterning by electron beam exposure and then performing SF 6 Plasma etching.

[0039] Furthermore, the SF 6 The gas flow rate of plasma etching is 10-50 sccm, the power is 25-100 W, and the etching time is 5-20 min.

[0040] Further, the method of depositing the bottom electrode, the metal nanocolumn source electrode, the drain electrode and the gate electrode comprises thermal evaporation or electron beam deposition;

[0041] The method of depositing the insulating dielectric layer 1 and the method of depositing the insulating dielectric layer 2 include atomic layer deposition;

[0042] The method for transferring a two-dimensional semiconductor material layer comprises: transferring the two-dimensional semiconductor material layer onto a thin film, then covering the position reserved for contact with the two-dimensional semiconductor material layer on the top of the metal nanocolumn source electrode and above the insulating dielectric layer 1, and finally dissolving the thin film.

[0043] Furthermore, the method of transferring the two-dimensional semiconductor material layer onto the film is selected from any one of the following methods:

[0044] Method 1: If a mechanically exfoliated sample is used, firstly, the two-dimensional semiconductor material layer is exfoliated onto a sacrificial substrate, and then a layer of PPC film is spin-coated on the surface of the sacrificial substrate. Deionized water is slowly injected on one side of the sacrificial substrate so that the two-dimensional semiconductor material layer on the sacrificial substrate is transferred along with the PPC film.

[0045] Method 2: If a single-layer two-dimensional semiconductor material is grown by CVD, a layer of PMMA is spin-coated on a sacrificial substrate of the grown material, and a 5% HF solution is used to etch away the oxide layer on the surface of the sacrificial substrate, so that the single-layer two-dimensional semiconductor material is transferred along with the PMMA film.

[0046] Furthermore, the method for dissolving the film includes: soaking in an acetone solution at a temperature of 50 to 70°C for 15 minutes, and then using a critical point dryer to replace the acetone in the structure with liquid carbon dioxide to complete the drying of the acetone, thereby preventing the acetone from damaging the two-dimensional semiconductor material during the volatilization process.

[0047] Compared with the fin structure, the ring-gate transistor structure prepared by the present invention increases the relative contact area between the gate and the material, thereby effectively enhancing the electrostatic control effect of the transistor. In addition, the vertical ring-gate transistor retains the advantages brought by the ring-gate structure and has a higher degree of freedom in vertical integration.

[0048] Technical solution three of the present invention: an application of the vertical ring-gate transistor in the preparation of electronic devices.

[0049] The present invention discloses the following technical effects:

[0050] (1) The vertical gate-all-around transistor based on two-dimensional semiconductor materials of the present invention can effectively improve the gate control capability of field effect transistors under the premise of shorter channels, effectively reduce leakage current and subthreshold swing, and improve device performance. Through the test of the transfer curve of the transistor and the parameter extraction, it is found that the subthreshold swing of the vertical gate-all-around transistor is reduced to one-third of that of the horizontal structure transistor, and a lower leakage current is obtained, which can reach the picoampere level.

[0051] (2) The present invention realizes the construction of a vertical ring-gate transistor based on two-dimensional semiconductor materials through a unique structural design, constructs a ring-gate structure with a width at the nanometer level, realizes the enhancement of the transistor gate control effect, and obtains a lower subthreshold swing. In addition, the design of the vertical ring-gate transistor retains the advantages brought by the ring-gate structure and has a higher degree of freedom in vertical integration, which has far-reaching significance for the research of high-area efficiency and low-power electronic devices of two-dimensional materials.

[0052] Moreover, the method of the present invention has a certain universality and is not limited to the materials used. Any material that can construct a similar structure can be studied by this method, which broadens the research scope of vertical ring-gate transistors based on two-dimensional semiconductor materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 Schematic diagram of the structure of a vertical ring-gate transistor, wherein 1 is an insulating substrate, 2 is a bottom electrode, 3 is a metal nanocolumn source electrode, 4-1 and 4-2 are insulating dielectric layers, 5 is a two-dimensional semiconductor material layer, 6 is a drain electrode, and 7 is a ring-gate electrode;

[0055] Figure 2 is the height and morphology of the metal nanopillar source electrode;

[0056] Figure 3 A scanning electron microscope image of the vertical gate-all-around transistor prepared in Example 1;

[0057] Figure 4 The transfer curves of the vertical gate-all-around transistor and the ordinary transistor (horizontal structure transistor) prepared in Example 1 are compared;

[0058] Figure 5 Schematic diagram of the structure of a horizontal structure transistor, where 8 is a conductive substrate, 9 is an insulating dielectric layer, and 10 is a two-dimensional MoS 2 Layer 11 is a metal source and drain electrode with a symmetrical structure;

[0059] Figure 6 The transfer curves of the vertical gate-all-around transistor prepared in Example 2 and a common transistor (horizontal structure transistor) are compared. DETAILED DESCRIPTION

[0060] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as limiting the present invention, but should be understood as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0061] It should be understood that the terms described in the present invention are only for describing special embodiments and are not intended to limit the present invention. In addition, for the numerical range in the present invention, it should be understood that each intermediate value between the upper and lower limits of the scope is also specifically disclosed. Each smaller range between the intermediate value in any stated value or stated range and any other stated value or intermediate value in the described range is also included in the present invention. The upper and lower limits of these smaller ranges can be independently included or excluded in the scope.

[0062] Unless otherwise indicated, all technical and scientific terms used herein have the same meanings as those generally understood by those skilled in the art. Although the present invention describes only preferred methods and materials, any methods and materials similar or equivalent to those described herein may also be used in the implementation or testing of the present invention. All documents mentioned in this specification are incorporated by reference to disclose and describe the methods and / or materials associated with the documents. In the event of a conflict with any incorporated document, the content of this specification shall prevail.

[0063] It will be apparent to those skilled in the art that various modifications and variations may be made to the specific embodiments of the present invention description without departing from the scope or spirit of the present invention. Other embodiments derived from the present invention description will be apparent to those skilled in the art. The present invention description and examples are exemplary only.

[0064] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0065] It should be pointed out that the matters not described in detail in the present invention are conventional operating means in the art and are not the focus of the present invention.

[0066] The “parts” described in the following examples are all “parts by weight”.

[0067] Example 1

[0068] A method for preparing a vertical gate-all-around transistor based on two-dimensional semiconductor materials:

[0069] Using a single layer of molybdenum disulfide as a two-dimensional semiconductor material layer, a vertical ring-gate transistor based on a single layer of molybdenum disulfide is constructed. Its structural composition is as follows Figure 1 As shown, it is composed of an insulating substrate 1, a bottom electrode 2, a metal nanocolumn source electrode 3, an insulating dielectric layer 4-1, a two-dimensional semiconductor material layer 5, a drain electrode 6, an insulating dielectric layer 4-2, and a ring gate electrode 7.

[0070] The preparation method is:

[0071] (1) A layer of polymethyl methacrylate is spin-coated on the surface of an insulating substrate 1 (silicon oxide substrate) with a thickness of 300 nm, and a position for depositing the bottom electrode is patterned by electron beam exposure. 6 Plasma etching is performed (gas flow rate is 20sccm, power is 25W, etching time is 5min) to reserve a position for the embedded bottom electrode, and a bottom electrode 2 (chromium / gold bottom electrode, in which 5nm of chromium metal is deposited and 10nm of pure gold is deposited thereon) with a thickness of 15nm is deposited at the reserved position by thermal evaporation (evaporation rate is 0.05nm / s) to fill the reserved position.

[0072] (2) By electron beam exposure (exposure voltage 30 kV, exposure dose 360) and thermal evaporation (evaporation rate 0.05 nm / s), a pure gold metal nanocolumn with a diameter of 4 μm and a height of 32 nm is deposited on one end of the bottom electrode 2 to form a metal nanocolumn source electrode 3, whose height and morphology are as shown in FIG. Figure 2 shown.

[0073] (3) An insulating dielectric layer 4-1 (hafnium dioxide dielectric layer) with a thickness of 20 nm is deposited on the surface of the metal nanocolumn source electrode 3, above the bottom electrode 2, and above the insulating substrate 1 by electron beam exposure (exposure voltage 30 kV, exposure dose 360) and atomic layer deposition (deposition temperature 140°C, purging time 35 s, deposition 180 cycles), and a position for contact with the two-dimensional semiconductor material layer is reserved on the top of the metal nanocolumn source electrode 3.

[0074] (4) Using a non-destructive and precise transfer method, the two-dimensional semiconductor material layer 5 (single layer of molybdenum disulfide, with a thickness of 0.6 nm) is transferred to the top of the insulating dielectric layer 4-1, wrapping the metal nanocolumn source electrode 3, and the insulating dielectric layer at the bottom of the metal nanocolumn source electrode 3 is also covered.

[0075] Specifically, a single-layer MoS2 material is grown by CVD, a layer of PMMA is spin-coated on a sacrificial substrate of the grown single-layer MoS2 material, and a 5% HF solution is used to immerse the substrate for about 5 minutes to etch away the oxide layer on the surface of the sacrificial substrate, thereby transferring the single-layer two-dimensional semiconductor material layer along with the PMMA film;

[0076] Using a precise transfer platform, the PMMA film with a single layer of molybdenum disulfide material is bonded to the metal nanocolumn source electrode 3, so that the single layer of molybdenum disulfide material precisely covers the top of the metal nanocolumn source electrode 3 and the surface of the insulating dielectric layer 4-1;

[0077] The substrate after the material transfer was immersed in an acetone solution at a temperature of 70° C. for 15 minutes to dissolve the PMMA. Subsequently, a critical point dryer was used to replace the acetone in the structure with liquid carbon dioxide to complete the drying of the acetone.

[0078] (5) Using electron beam exposure (exposure voltage 30 kV, exposure dose 360) and thermal evaporation (evaporation rate 0.05 nm / s), a drain electrode 6 (pure gold drain electrode) with a thickness of 18 nm is deposited at the position where the two-dimensional semiconductor material layer 5 covers the bottom of the metal nanocolumn source electrode 3.

[0079] (6) An insulating dielectric layer 4-2 (hafnium dioxide dielectric layer) with a thickness of 30 nm is deposited on the surface of the two-dimensional semiconductor material layer 5 by electron beam exposure (exposure voltage 30 kV, exposure dose 360) and atomic layer deposition (deposition temperature 140°C, purge time 35 s, deposition 360 cycles) to ensure that the insulating dielectric layer covers the entire coverage area of ​​the two-dimensional semiconductor material layer 5 and above the drain electrode to form a nanocolumn structure.

[0080] (7) Electron beam exposure (exposure voltage 30 kV, exposure dose 360) and thermal evaporation (evaporation rate 0.05 nm / s) are used to deposit a gate electrode with a height of 32 nm (chromium / gold gate electrode, wherein 10 nm of chromium metal is deposited and then 20 nm of pure gold is deposited on top) on the outer ring of the nanocolumn structure formed by wrapping the secondary deposited insulating dielectric layer 4-2. The size and thickness of the circular ring structure of the gate electrode cross-section are matched with the size of the internal nanocolumn structure, and are in close contact to ensure good contact to form a ring gate electrode 7, thereby obtaining a vertical ring gate transistor.

[0081] The scanning electron microscope image of the vertical gate-all-around transistor prepared in this embodiment is shown in Figure 3 The transfer curves of the vertical gate-all-around transistor prepared in this embodiment and the ordinary transistor are compared. Figure 4 .

[0082] from Figure 3 It can be seen that the material of the prepared vertical ring-gate transistor is intact and is hardly damaged during the processing, which is beneficial to the performance of the transistor.

[0083] from Figure 4 It can be seen that the subthreshold swing of ordinary transistors (horizontal structure transistors) is significantly higher than that of vertical ring-gate transistors, which also confirms that vertical ring-gate transistors have stronger gate control capabilities. Subthreshold swing (SS) is a key performance indicator for measuring transistor switching speed, representing the control ability of gate voltage over source-drain channel current, that is, the gate voltage change required for the source-drain current to change tenfold. The method for calculating the subthreshold swing based on the transfer curve of the transistor is expressed as follows:

[0084]

[0085] Among them, V gs is the gate voltage of the device, I ds is the source-drain current of the device.

[0086] pass Figure 4 The parameters of the two transfer curves in the figure are extracted, and it is calculated that when the source-drain current changes by two orders of magnitude, the subthreshold swing of the vertical gate-all-around transistor is 126.7mV / dec, while the subthreshold swing of the horizontal structure transistor is 359.7mV / dec. This fully confirms that the vertical gate-all-around transistor has better switching characteristics.

[0087] Among them, the horizontal structure transistor uses the same single-layer MoS 2 The structure of the horizontal transistor is shown in Figure 5 , consisting of a conductive substrate 8, an insulating dielectric layer 9, and a two-dimensional MoS 2 The layer 10 is composed of a metal source-drain electrode 11 with a symmetrical structure, and the preparation method thereof is as follows:

[0088] A. Atomic layer deposition is performed on a conductive substrate 8 (the substrate is heavily doped Si), with a deposition temperature of 140°C, a purge time of 35 seconds, and about 240 deposition cycles, to finally obtain an insulating dielectric layer 9 (hafnium dioxide dielectric layer) with a thickness of 30 nm.

[0089] B. Transferring two-dimensional MoS onto the deposited insulating dielectric layer 9 2 Layer 10: A single-layer molybdenum disulfide material grown by CVD is used to spin-coat a layer of PMMA on the sacrificial substrate of the grown single-layer molybdenum disulfide material. The substrate is soaked in a 5% HF solution for about 5 minutes. The solution etches away the oxide layer on the surface of the sacrificial substrate, thereby transferring the single-layer two-dimensional semiconductor material layer along with the PMMA film. Using a precise transfer platform, the PMMA film with a single-layer molybdenum disulfide material is bonded to the deposited insulating dielectric layer. The substrate after the material is transferred is soaked in an acetone solution at a temperature of 70°C for 15 minutes to dissolve the PMMA. Then, after soaking in an isopropanol solution to dissolve the acetone, take it out and blow dry it with an air gun.

[0090] C. Deposition of metal electrodes: After the material is transferred, a layer of PMMA is spin-coated on the substrate surface, and patterning is performed using an electron beam exposure process, that is, a voltage of 30 kV is used and an exposure dose is set to 360. The contact electrode area is set to a rectangle with a length of 10 μm and a width of 5 μm, and a channel length of 5 μm. After the exposed substrate is developed, a pure gold electrode with a thickness of 30 nm is deposited by thermal evaporation as a metal source and drain electrode 11, and the evaporation rate is 0.05 nm / s. Finally, a MoS 2 A horizontal structure transistor with a channel material. Its performance is shown in Figure 4 The dashed part in the transfer curve.

[0091] Example 2

[0092] Same as Example 1, except that the vertical gate-all-around structure transistor and the horizontal structure transistor are both prepared by using mechanically peeled multilayer molybdenum disulfide as the two-dimensional semiconductor material layer 5;

[0093] When preparing a vertical gate-all-around transistor, specifically:

[0094] First, the multilayer MoS2 is peeled off to the sacrificial substrate SiO 2 After that, a layer of PPC film is spin-coated on the surface of the sacrificial substrate. Deionized water is slowly injected on one side so that the multilayer molybdenum disulfide on the sacrificial substrate is transferred along with the PPC film. Using a precise transfer platform, the PPC film with multilayer molybdenum disulfide is bonded to the metal nanocolumn source electrode 3 so that the multilayer molybdenum disulfide material is precisely covered on the top of the metal nanocolumn source electrode 3 and the surface of the insulating dielectric layer 4-1. The substrate after the material is transferred is soaked in an acetone solution at a temperature of 70°C for 15 minutes to dissolve the PPC. Subsequently, a critical point dryer is used to replace the acetone in the structure with liquid carbon dioxide to complete the drying of the acetone.

[0095] When preparing a horizontal structure transistor, the following steps are performed: first, the multilayer MoS2 is peeled off to the sacrificial substrate SiO 2 After that, a layer of PPC film is spin-coated on the surface of the sacrificial substrate. Deionized water is slowly injected on one side so that the multi-layer molybdenum disulfide on the sacrificial substrate is transferred along with the PPC film. Using a precise transfer platform, the PPC film with multi-layer molybdenum disulfide is bonded to the insulating dielectric layer 9. The substrate after the material is transferred is soaked in an acetone solution at a temperature of 70°C for 15 minutes to dissolve the PPC. Subsequently, a critical point dryer is used to replace the acetone in the structure with liquid carbon dioxide to complete the drying of the acetone.

[0096] The transfer curves of the vertical gate-all-around transistor prepared in this embodiment and the ordinary horizontal structure transistor are compared as shown in FIG. Figure 6 .

[0097] pass Figure 6 The parameters of the two transfer curves in the figure are extracted, and it is calculated that when the source-drain current changes by two orders of magnitude, the subthreshold swing of the vertical gate-all-around transistor is 86.4mV / dec, while the subthreshold swing of the horizontal structure transistor is 273.2mV / dec. This fully proves that when the material used is mechanically peeled MoS2, the vertical gate-all-around transistor has better switching characteristics than the traditional horizontal structure transistor.

[0098] The embodiments described above are only descriptions of the preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A vertical gate-all-around transistor based on two-dimensional semiconductor materials, characterized in that: include: Insulating substrate; A bottom electrode, embedded on the surface of the insulating substrate; A metal nanocolumn source electrode, disposed on the bottom electrode; An insulating dielectric layer 1, covering the insulating substrate, the bottom electrode and surrounding the metal nanocolumn source electrode; A two-dimensional semiconductor material layer, covering the insulating dielectric layer 1 and the top surface of the metal nanocolumn source electrode; An insulating dielectric layer 2 is arranged on the surface of the two-dimensional semiconductor material layer; A drain electrode, disposed inside the insulating dielectric layer 2 and in contact with the two-dimensional semiconductor material layer; A ring electrode wrapped around the side of the insulating dielectric layer 2; The total thickness of the insulating dielectric layer 1, the two-dimensional semiconductor material layer and the insulating dielectric layer 2 is less than the height of the metal nanocolumn source electrode.

2. The vertical gate-all-around transistor according to claim 1, characterized in that: The insulating substrate is a silicon oxide substrate with a thickness of 90 to 300 nm; And / or, the thickness of the bottom electrode and the drain electrode are independently 10-100 nm; the thickness of the bottom electrode is less than the thickness of the insulating substrate; And / or, the diameter of the metal nanocolumn source electrode is 500nm-6μm, and the height is 10nm-1μm; And / or, the metal nanocolumn source electrode, bottom electrode and drain electrode are made of pure gold, or chromium metal and pure gold.

3. The vertical gate-all-around transistor according to claim 1, characterized in that: The bottom electrode is arranged in a region pre-etched on the insulating substrate; And / or, the metal nanocolumn source electrode is arranged at one end of the bottom electrode.

4. The vertical gate-all-around transistor according to claim 1, wherein: The thickness of the insulating dielectric layer 1 and the insulating dielectric layer 2 are independently 15 to 100 nm; And / or, the thickness of the two-dimensional semiconductor material layer is 0.6-10 nm.

5. The vertical gate-all-around transistor according to claim 1, wherein: The materials of the insulating dielectric layer 1 and the insulating dielectric layer 2 are independently selected from hafnium oxide, zirconium oxide, aluminum oxide or silicon oxide; And / or, the two-dimensional semiconductor material layer is a transition metal chalcogenide.

6. The vertical gate-all-around transistor according to claim 1, characterized in that: The ring gate electrode is made of pure gold, or chromium metal and pure gold; And / or, the height of the ring gate electrode is the same as the height of the metal nanocolumn source electrode.

7. A method for preparing a vertical gate-all-around transistor according to any one of claims 1 to 6, characterized in that: The following steps are involved: Performing patterned etching on the insulating substrate and depositing a bottom electrode in the etched area; depositing a metal nanocolumn source electrode at one end of the bottom electrode; An insulating dielectric layer 1 is deposited on the insulating substrate, the bottom electrode and the surface of the metal nanocolumn source electrode, and a position for contacting the two-dimensional semiconductor material layer is reserved on the top of the metal nanocolumn source electrode; Transferring the two-dimensional semiconductor material layer to a position reserved for contact with the two-dimensional semiconductor material layer on the top of the metal nanocolumn source electrode and above the insulating dielectric layer 1; Depositing a drain electrode at a position at the bottom of the metal nanocolumn source electrode covering the two-dimensional semiconductor material layer; Depositing an insulating dielectric layer 2 on the surface of the two-dimensional semiconductor material layer and the drain electrode to form a nanocolumn structure; A gate electrode is deposited on the outer circle of the nano-pillar structure to wrap the outer circle of the nano-pillar structure, so as to obtain the vertical ring-gate transistor.

8. The preparation method according to claim 7, characterized in that: The patterned etching method includes patterning by electron beam exposure and then performing SF6 plasma etching.

9. The preparation method according to claim 7, characterized in that: The method of depositing the bottom electrode, the metal nanocolumn source electrode, the drain electrode and the gate electrode comprises thermal evaporation or electron beam deposition; The method of depositing the insulating dielectric layer 1 and the method of depositing the insulating dielectric layer 2 include atomic layer deposition; The method for transferring a two-dimensional semiconductor material layer comprises: transferring the two-dimensional semiconductor material layer onto a film, then covering the position reserved for contact with the two-dimensional semiconductor material layer on the top of the metal nanocolumn source electrode and above the insulating dielectric layer 1, and finally dissolving the film.

10. Use of the vertical gate-all-around transistor according to any one of claims 1 to 6 in the preparation of electronic devices.

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