Manufacturing method of semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device, which comprises the following steps of: adjusting a step of opening a second hard mask layer of an NMOS (N-channel Metal Oxide Semiconductor) region after forming a germanium-silicon source drain of a PMOS (P-channel Metal Oxide Semiconductor) region in the prior art to a step of opening a second hard mask layer of an NMOS region before a photoetching process for forming the germanium-silicon source drain of the PMOS region, and removing the second hard mask layer on the top of a grid of the NMOS region and the top of a grid of the PMOS region by adopting a chemical mechanical polishing (CMP) method. According to the technical scheme, a photomask and a wet etching process which are needed when the second hard mask layer of the NMOS region is opened in the prior art can be omitted, the technological process is simplified, the photomask cost is saved, the problem that the surface of the substrate of the NMOS region is sunken due to the wet etching process is avoided, and the device performance is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and particularly to a manufacturing method of a semiconductor device. Background Art

[0002] In the field of semiconductor technology, with the rapid development of nano-processing technology, the process node of transistors has advanced to below 28 nanometers. Among them, SiGe (referred to as germanium silicon or silicon germanide) is introduced into the source and drain of PMOS transistors due to its excellent performance to improve the hole carrier mobility of PMOS transistors.

[0003] However, the existing CMOS process for introducing SiGe source and drain into PMOS transistors has problems of high mask cost and easy generation of substrate surface damage or surface depression. Summary of the Invention

[0004] The purpose of the present invention is to provide a manufacturing method of a semiconductor device, which can introduce SiGe source and drain into PMOS transistors, save masks, and improve the problems of substrate surface damage or surface depression.

[0005] To achieve the above purpose, the present invention provides a manufacturing method of a semiconductor device, which includes the following steps:

[0006] Provide a substrate with a PMOS region and an NMOS region, form an oxide layer, a gate layer, and a first hard mask layer on the surface of the substrate, and etch the first hard mask layer and the gate layer to form gates on the PMOS region and the NMOS region;

[0007] Form gate sidewalls on the sidewalls of each gate, and conformally deposit a contact etch stop layer and a second hard mask layer on the oxide layer, the gate sidewalls, and the first hard mask layer in sequence;

[0008] Deposit a sacrificial dielectric layer on the second hard mask layer, and perform chemical mechanical polishing on the sacrificial dielectric layer to remove the second hard mask layer on the top of the first hard mask layer;

[0009] Use a first wet process to remove the sacrificial dielectric layer;

[0010] Form a patterned photoresist layer to protect the NMOS region, and use the patterned photoresist layer as a mask to etch the second hard mask layer, the contact etch stop layer, and the substrate on the PMOS region to form source and drain trenches in the substrate on both sides of the gate in the PMOS region;

[0011] Remove the patterned photoresist layer and use a germanium silicon epitaxial growth process to form germanium silicon source and drain in the source and drain trenches;

[0012] The second wet process is adopted to remove the first hard mask layer and the second hard mask layer.

[0013] Optionally, both the contact etch stop layer and the sacrificial dielectric layer are oxides, and the etchant for the first wet process includes hydrofluoric acid.

[0014] Optionally, the contact etch stop layer on the top of the first hard mask layer is removed synchronously by the chemical mechanical polishing or the first wet process.

[0015] Optionally, the etchant for the second wet process includes phosphoric acid.

[0016] Optionally, the first hard mask layer and the second hard mask layer are made of the same material.

[0017] Optionally, both the contact etch stop layer and the second hard mask layer are formed by atomic layer deposition.

[0018] Optionally, in the manufacturing method, before removing the first hard mask layer and the second hard mask layer, a protective layer is formed on the top surface of the germanium-silicon source / drain; and / or, after removing the first hard mask layer and the second hard mask layer, metal is further deposited and rapid thermal annealing is performed to form metal silicide on the top surfaces of the germanium-silicon source / drain and the gate.

[0019] Optionally, in the manufacturing method, after removing the first hard mask layer and the second hard mask layer and before depositing metal, or after forming the gate and before depositing the contact etch stop layer, the following is further included: N-type ion implantation is performed on the substrate on both sides of the gate in the NMOS region to form an N-type ion-doped source / drain region.

[0020] Optionally, before depositing the metal, the oxide layer on the N-type ion-doped source / drain region is removed by wet etching to expose the surface of the N-type ion-doped source / drain region.

[0021] Optionally, during the process of forming the germanium-silicon source / drain in the source / drain trench by germanium-silicon epitaxial growth process, P-type ions are in-situ doped into the germanium-silicon source / drain to form a P-type ion-doped source / drain region; or, after removing the first hard mask layer and the second hard mask layer, the NMOS region is masked, and P-type ion implantation is performed on the germanium-silicon source / drain on both sides of the gate in the PMOS region to form a P-type ion-doped source / drain region.

[0022] Compared with the prior art, in the technical solution of the present invention, before forming a patterned photoresist layer to mask the NMOS region and defining a region for forming source / drain trenches in the PMOS region, the second hard mask layer on the top of the gate is first removed by depositing and chemical mechanical polishing (CMP) a sacrificial dielectric layer. On the one hand, when removing the sacrificial dielectric layer by using a first wet process, since the second hard mask layer, the contact etch stop layer and the oxide layer still cover the substrate surfaces on the outer sides of the gates in both the PMOS region and the NMOS region, the etching solution of this first wet process will not cause problems such as damage or even depression on the substrate surface, thereby improving the device performance. On the other hand, since the second hard mask layer on the top of the gates in both the PMOS region and the NMOS region is opened by chemical mechanical grinding before epitaxial growth of germanium-silicon source / drain in the source / drain trenches, one photomask used to separately remove the second hard mask layer on the top of the gates in the NMOS region can be saved, thus saving costs. Description of the Drawings

[0023] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0024] Figure 1 is a schematic diagram of the device cross-sectional structure in the manufacturing method of the existing semiconductor device.

[0025] Figure 2 is a flowchart of the manufacturing method of the semiconductor device according to a specific embodiment of the present invention.

[0026] Figure 3 is a schematic diagram of the device cross-sectional structure in the manufacturing method of the semiconductor device according to a specific embodiment of the present invention. Detailed Embodiments

[0027] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention. It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "comprises" is used to specify the presence of the stated features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0028] The technical solutions proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be more clearly understood. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0029] The process of the existing CMOS process for introducing SiGe source / drain into PMOS transistors includes the following steps:

[0030] Please refer to Figure 1 in (A). After forming the oxide layer 102, the gate 103, the first hard mask layer 104 and the double-layer gate sidewall (not labeled) of the PMOS region and the NMOS region, a contact etch stop layer 105, a second hard mask layer 106 and a bottom anti-reflection layer 107 are deposited, and a photoresist layer 108 is coated.

[0031] Please refer to Figure 1In (B), the photoresist layer 108 is lithographed through a corresponding photomask, and the photoresist layer 108 in the PMOS region is removed, while the NMOS region is masked by the remaining photoresist layer 108. Using the lithographed photoresist layer 108 as a mask, the bottom anti-reflection layer 107 is first etched, and then the second hard mask layer 106 and the contact etch stop layer 105 in the PMOS region are etched to expose the substrate 100 region in the PMOS region for manufacturing the SiGe source / drain. After that, the photoresist layer 108 and the bottom anti-reflection layer 107 are removed, and under the masking effect of the second hard mask layer 106, the exposed region of the substrate 100 in the PMOS region is further etched downward to form the source / drain trench 109. At this time, a part of the second hard mask layer 106 still remains on the sidewall of the gate sidewall in the PMOS region.

[0032] Please refer to Figure 1 In (C), SiGe is epitaxially grown in the source / drain trench 109 to form the germanium-silicon source / drain 110.

[0033] Please refer to Figure 1 In (D), in order to remove the first hard mask layer 104 on the top of the gates of both NMOS and PMOS simultaneously after the formation of the germanium-silicon source / drain 110 to expose the gate 103 for growing metal silicide, after the formation of the germanium-silicon source / drain 110 in the PMOS region, it is necessary to further remove the second hard mask layer 106 on the top of the gate 103 in the NMOS region. This process generally involves depositing the bottom anti-reflection layer 111, coating the photoresist layer 112, and lithographing the photoresist layer 112 through another photomask to remove the photoresist layer 112 in the NMOS region, while the PMOS region is masked by the remaining photoresist layer 112. Using the lithographed photoresist layer 112 as a mask, the bottom anti-reflection layer 111 exposed in the NMOS region is first etched, and then the second hard mask layer 106 on the top of the gate in the NMOS region and on the substrate 100 is dry-etched away. At this time, a part of the second hard mask layer 106 still remains on the sidewall of the gate sidewall in the NMOS region.

[0034] Please refer to Figure 1 In (E), the photoresist layer 112 and the bottom anti-reflection layer 111 are removed, the contact etch stop layer 105 on the top of the gate is opened by hydrofluoric acid, and then the first hard mask layer 104 on the top of the gate 103 and the second hard mask layer 106 on the sidewall of the gate sidewall are removed using phosphoric acid.

[0035] In the above process, two photomasks are required, resulting in high costs. Moreover, before removing the first hard mask layer 104 on the top of the gate 103 and the second hard mask layer 106 on the sidewalls of the gate spacers using phosphoric acid, it is necessary to first open the contact etch stop layer 105 on the top of the gate using hydrofluoric acid. Additionally, due to the different sizes of the gaps between the gate spacers and the line width on the top of the gate, the thickness of the contact etch stop layer 105 on the substrate and on the top of the gate may vary. Therefore, in order to completely remove the contact etch stop layer 105 on the top of the gate, an excessive amount of hydrofluoric acid must be used to etch the contact etch stop layer 105 on the top of the gate (i.e., over-etching occurs). This process easily consumes the oxide layer 102 on the exposed substrate surface in the NMOS region and may even expose the surface of the substrate 100, causing the hydrofluoric acid to directly contact the substrate and resulting in substrate surface damage or the formation of a substrate surface depression 113 (with a depth up to ). When removing the first hard mask layer 104 and the second hard mask layer 106 using phosphoric acid, it will further consume the oxide layer 102 on the exposed substrate surface in the NMOS region, exacerbating the formation of substrate surface damage or the substrate surface depression 113. This substrate surface depression 113 will affect the source-drain distance from the channel in the NMOS region and cause losses to the previously implanted ions, thereby affecting the performance of the CMOS device.

[0036] Furthermore, even if the thickness of the contact etch stop layer 105 on the substrate and on the top of the gate is the same, after the above-mentioned multiple wet etching processes (i.e., acid treatment), the oxide layer 102 on the exposed substrate surface in the NMOS region may still be consumed until the exposed substrate surface is revealed, causing these acids to directly contact the substrate and resulting in substrate surface damage or the formation of a substrate surface depression 113.

[0037] If the pattern of the other photomask is changed, although it is possible to retain a portion of the bottom anti-reflection layer 111 on the active region in the NMOS region when etching the bottom anti-reflection layer 111 and the second hard mask layer 106 in the NMOS region, a severe loading effect will occur when subsequently removing the second hard mask layer 106 on the top of the gate 103 in the NMOS region using dry etching. Moreover, this method has strict requirements for the modified photomask pattern, making it difficult to be widely implemented.

[0038] Based on this, please refer to Figure 2 , an embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps:

[0039] S1, providing a substrate having a PMOS region and an NMOS region, forming an oxide layer, a gate layer, and a first hard mask layer on the surface of the substrate, and etching the first hard mask layer and the gate layer to form gates on the PMOS region and the NMOS region;

[0040] S2. Form gate sidewalls on the sidewalls of each of the gates, and conformally deposit a contact etch stop layer and a second hard mask layer in sequence on the oxide layer, the gate sidewalls, and the first hard mask layer;

[0041] S3. Deposit a sacrificial dielectric layer on the second hard mask layer, and perform chemical mechanical polishing on the sacrificial dielectric layer to remove the second hard mask layer on the top of the first hard mask layer;

[0042] S4. Remove the sacrificial dielectric layer by using a first wet process;

[0043] S5. Form a patterned photoresist layer to protect the NMOS region, and use the patterned photoresist layer as a mask to etch the second hard mask layer, the contact etch stop layer, and the substrate on the PMOS region to form source / drain trenches in the substrate on both sides of the gate in the PMOS region;

[0044] S6. Remove the patterned photoresist layer and use a germanium-silicon epitaxial growth process to form germanium-silicon source / drains in the source / drain trenches;

[0045] S7. Remove the first hard mask layer and the second hard mask layer by using a second wet process.

[0046] In this embodiment, the process of providing the substrate 200 and forming the gates in step S1 includes:

[0047] First, please refer to Figure 3 (A) in. Reasonably select a substrate material according to the device usage requirements to provide the substrate 200, such as single-crystal silicon (Si), silicon-on-insulator (SOI), single-crystal germanium (Ge), germanium-on-insulator (GeOI), silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), etc. Further, form a shallow trench isolation structure 201 in the substrate 200 through a shallow trench isolation process (including shallow trench lithography, etching, and filling). The material of the shallow trench isolation structure 201 can be a conventional insulating material such as an oxide, a nitride, a nitrogen oxide, etc. The shallow trench isolation structure 201 is used to define a PMOS region and an NMOS region in the substrate 200, where Figure 3 the left region in corresponds to the PMOS region, and the right region corresponds to the NMOS region. Figure 3 Although only one NMOS region and one PMOS region are shown in, actually, according to the layout design requirements, multiple PMOS regions and multiple NMOS regions can be formed in the substrate. An N-type well region (not shown) can also be formed in the substrate 200 of the PMOS region, and a P-type well region (not shown) can also be formed in the substrate 200 of the NMOS region.

[0048] Next, please refer to Figure 3In (A) thereof, an oxide layer 202 is sequentially covered on the entire surface of the substrate 200 including the shallow trench isolation structure 201, and a gate layer and a first hard mask layer 204 are deposited. Among them, the oxide layer 202 can be formed by a thermal oxidation process or a chemical vapor deposition process, and it can be silicon dioxide, silicon oxynitride, silicon nitride, or a high-K material (such as hafnium-based oxide, etc.) with a dielectric constant K higher than that of silicon dioxide and their combinations. The material of the gate layer can be polysilicon, amorphous silicon, microcrystalline silicon, amorphous germanium, and their combinations. The first hard mask layer 204 can be silicon nitride, silicon oxynitride, and their combinations, etc. The oxide layer 202 can be a gate oxide layer with a uniform thickness, or it can be composed of a gate oxide layer with a uniform thickness and a native oxide layer located between the bottom of the gate oxide layer and the substrate 200.

[0049] Then, please refer to Figure 3 In (A) thereof, photolithography is performed by means of a photomask (not shown) for manufacturing the gate. This photolithography process can include depositing an amorphous carbon layer (not shown) and a bottom anti-reflection coating BARC (not shown), coating a photoresist PR (not shown), etc., and performing exposure, development, etching the bottom anti-reflection coating BARC and the amorphous carbon layer, etc., and using the remaining film layers such as the photoresist after photolithography as a mask to further etch the first hard mask layer 204. Then, after removing the remaining film layers such as the photoresist after photolithography, using the remaining first hard mask layer 204 after etching as a mask to etch the gate layer, so as to form a gate 203 on the substrates in both the PMOS region and the NMOS region. At this time, there is a remaining first hard mask layer 204 on the top of the gate 203. In this embodiment, the gates 203 on the PMOS region and the NMOS region are formed simultaneously, but in other embodiments, the gates 203 on the PMOS region and the NMOS region can also be formed separately and successively. The oxide layer sandwiched between the bottom of the gate 203 and the substrate 200 is the gate oxide layer.

[0050] In this embodiment, the process of forming the gate sidewall, the contact etch stop layer 205, and the second hard mask layer 206 in step S2 includes:

[0051] First, please refer to Figure 3 In (A) thereof, any suitable deposition process such as an atomic layer deposition process or a chemical vapor deposition process can be used to conformally deposit a sidewall material on the oxide layer 202, the sidewalls of each gate 203, and the top surface and sidewalls of the first hard mask layer 204, and through each sidewall etching process, a gate sidewall is formed on the sidewalls of each gate 203. The gate sidewall can be a single-layer film structure or a multi-layer film structure formed by different sidewall materials. For example, the gate sidewall includes an inner sidewall 203a and an outer sidewall 203b formed by two different sidewall materials. The inner sidewall 203a can be a material such as silicon dioxide, and the outer sidewall 203b can be a material such as silicon nitride.

[0052] Next, please refer to Figure 3 In (A) of Figure 3 , any suitable deposition process such as atomic layer deposition can be used to conformally deposit a contact etch stop layer 205 and a second hard mask layer 206 on the sidewalls of the surfaces of the oxide layer 202 and the gate sidewall, as well as on the top surface and sidewalls of the first hard mask layer 204 in sequence. Among them, the material of the contact etch stop layer 205 is different from that of the second hard mask layer 206 and the outer surface of the gate sidewall. On the one hand, the contact etch stop layer 205 can be used as an etch stop layer when etching or removing the first hard mask layer 204 and the second hard mask layer 206 subsequently. On the other hand, as a barrier protection layer, it can protect film layers such as the gate 203 from the loss of subsequent etching. As an example, the contact etch stop layer 205 is silicon oxide, and the second hard mask layer 206 is silicon nitride.

[0053] Optionally, after forming the gate 203 and before depositing the contact etch stop layer 205, or after forming the gate sidewall and before depositing the contact etch stop layer 205, without using an additional mask layer to mask the PMOS region, N-type ions such as phosphorus P, arsenic As, and antimony Sb can be used to perform ion implantation on the substrates on both sides of the gates of the PMOS region and the NMOS region together. Alternatively, a corresponding patterned mask layer can be formed first to mask the PMOS region and expose the NMOS region, and N-type ions are used to perform ion implantation on the substrates on both sides of the gate of the NMOS region, thereby forming an N-type ion-doped source / drain region (not shown) of the NMOS region.

[0054] In other embodiments of the present invention, after performing the above step S7, a patterned mask layer can also be formed to mask the PMOS region and expose the NMOS region, and N-type ions are used to perform ion implantation on the substrates on both sides of the gate of the NMOS region, thereby forming an N-type ion-doped source / drain region (not shown) of the NMOS region.

[0055] In step S3 of this embodiment, please refer to Figure 3 In (A) of Figure 3 , a sacrificial dielectric layer 207 can be deposited on the second hard mask layer 206 by using a process such as chemical vapor deposition to deposit materials such as oxides. The deposited sacrificial dielectric layer 207 can fill the gap between the gate sidewalls. Then, please refer to Figure 3 In (B) of Figure 3 , chemical mechanical polishing (CMP) is performed on the sacrificial dielectric layer, and the polishing is terminated on the surface of the first hard mask layer 204 above the top of the gate 203 (this CMP process can allow a non-negligible height consumption of the first hard mask layer 204, or can also allow a negligible height consumption of the first hard mask layer 204), thereby removing the second hard mask layer 206 and the contact etch stop layer 205 on the top of the first hard mask layer 204.

[0056] In other embodiments of the present invention, in step S3, the CMP process may also stop on the surface of the contact etch stop layer 205 above the top of the gate 203. The contact etch stop layer 205 may be removed together during the subsequent wet etching process for removing the sacrificial dielectric layer 207, so as to expose the top surface of the first hard mask layer 204. Thus, before forming the SiGe source / drain required for the PMOS region, one wet etching process for removing the contact etch stop layer 205 on the top of the gate can be reduced, thereby avoiding the consumption of the oxide layer 202 on the substrate in the prior art wet etching process and the unnecessary consumption of the substrate silicon before the metal silicidation process.

[0057] Among them, removing the second hard mask layer 206 and the contact etch stop layer 205 on the top of the gate 203 in this step S3 can reduce the loading effect of the NMOS region and the PMOS region in the subsequent process and avoid the problem of surface depression caused by the subsequent corresponding process on the substrate of the NMOS region.

[0058] In step S4 of this embodiment, please refer to Figure 3 (C) therein. Any suitable first wet process can be selected according to the material characteristics of the sacrificial dielectric layer 207 to remove the sacrificial dielectric layer 207. For example, if the sacrificial dielectric layer 207 is an oxide, an etching solution such as hydrofluoric acid is used to wet-etch and remove the sacrificial dielectric layer 207. Moreover, since the etching selectivity between the sacrificial dielectric layer 207 and the contact etch stop layer 205 is not high, the contact etch stop layer 205 on the top of the gate 203 is also removed simultaneously during the wet etching for removing the sacrificial dielectric layer 207. And since the second mask layer 206 and the contact etch stop layer 205 remain on the oxide layer 202 outside the gate 203 in the PMOS region and the NMOS region during this process, the etching solution will not penetrate through the second mask layer 206, the contact etch stop layer 205, and the oxide layer 202 to consume the silicon in the substrate 200.

[0059] In step S5 of this embodiment, please refer to Figure 3In (D), first, at least one of amorphous carbon, organic materials, and anti-reflection materials may be deposited to form a filling layer 208 that fills the gap between the gate sidewalls and has a flat top surface. Further, a photoresist is coated on the top surface of the filling layer 208, and then a corresponding photomask is used to perform photolithography (including processes such as exposure and development) on the photoresist to form a patterned photoresist layer 209. The patterned photoresist layer 209 masks the surface of the filling layer 208 in the NMOS region and exposes the surface of the filling layer 208 in the PMOS region. Then, using the patterned photoresist layer 209 as a mask, a corresponding dry etching process is used to sequentially etch the filling layer 208, the second hard mask layer 206, the contact etch stop layer 205, and the oxide layer 202, thereby exposing the substrate surface in the regions on both sides of the gate 203 in the PMOS region. The exposed substrate in the PMOS region is continuously etched to form source / drain trenches 210 in the substrate 200 on both sides of the gate 203 in the PMOS region.

[0060] It should be understood that since the dry etching process is anisotropic and its vertical etching rate is greater than the lateral etching rate, after the source / drain trenches 210 are formed, there are still excess sidewalls formed by the second hard mask layer 206 and the contact etch stop layer 205 remaining on the outer sidewalls of the gate sidewalls, which need to be removed subsequently.

[0061] In addition, Figure 3 The patterned photoresist layer 209 shown in (D) exposes the global surface of the PMOS region, but the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, when the photomask accuracy and photolithography accuracy permit, the patterned photoresist layer 209 may only expose the surface of the region in the PMOS region where the source / drain trenches 210 are to be formed. After etching the filling layer 208, the second hard mask layer 206, the contact etch stop layer 205, and the oxide layer 202 using the patterned photoresist layer 209 as a mask, the substrate surface in the PMOS region where the source / drain trenches 210 are to be formed is exposed, and the global surface of the NMOS region and the surfaces of other regions in the PMOS region except for the source / drain trenches 210 are masked and protected by the patterned photoresist layer 209 and the filling layer 208, the second hard mask layer 206, the contact etch stop layer 205, and the oxide layer 202 thereunder.

[0062] In step S6 of this embodiment, please refer to Figure 3In (E), first, the patterned photoresist layer 209 and the filling layer 208 are removed by any suitable process such as a wet stripping process. Then, any suitable germanium-silicon epitaxial growth process is adopted to grow germanium-silicon in the source-drain trenches 210 to form the germanium-silicon source / drain 211 required for the PMOS region. During this process, since the substrate surfaces of the NMOS region and other regions of the PMOS region are masked by films such as the remaining second hard mask layer 206, the tops of the respective gates 203 are masked by the first hard mask layer 204, and the sidewalls of the respective gates 203 are masked by the gate sidewalls, germanium-silicon will not grow on them.

[0063] Optionally, the top of the germanium-silicon source / drain 211 grown in the source-drain trenches 210 is higher than the top of the surrounding substrate 200.

[0064] Optionally, during the epitaxial growth of germanium-silicon in the source-drain trenches 210 in step S5, in-situ doping of P-type ions such as boron B, aluminum Al, gallium Ga, indium In, etc. is performed, so that the formed germanium-silicon source / drain 211 serves as the P-type ion-doped source / drain region required for the PMOS region. In other embodiments of the present invention, P-type ion implantation can also be performed on the germanium-silicon source / drain 211 after the epitaxial growth of the germanium-silicon source / drain 211 or after performing step S7 to form the P-type ion-doped source / drain region required for the PMOS region (not shown). This P-type ion-doped source / drain region can effectively reduce the source-drain contact resistance of the PMOS region and at the same time apply stress to the channel of the PMOS region to increase the hole carrier mobility.

[0065] In step S7 of this embodiment, please refer to Figure 3 In (F), after the germanium-silicon source / drain 211 is formed, the top surface of the germanium-silicon source / drain 211 can be thermally oxidized and other treatments are performed in an ozone environment to form a protective layer (not shown) to prevent the germanium-silicon source / drain 211 from being damaged in the subsequent processes of removing the first hard mask layer 204 and the second hard mask layer 206. Then, any suitable etching solution such as phosphoric acid is used for the second wet process to wet-etch and remove the first hard mask layer 204 on the top of the gate 203 and the second hard mask layer 206 on the outer wall of the gate sidewall. During this process, since there is a relatively thick oxide layer 202 on the substrate surface of the NMOS region, the problem of substrate surface depression will not occur.

[0066] After step S7 is completed in this embodiment and the source / drain regions of P-type ion doping in the PMOS region (not shown) and the source / drain regions of N-type ion doping in the NMOS region (not shown) are formed, the corresponding oxide layer 202 on the top surface of the contact region of the N-type ion-doped source / drain region and the protective layer on the top surface of the contact region of the P-type ion-doped source / drain region can be further removed, so as to expose the top surfaces of the contact regions of the N-type ion-doped source / drain region and the P-type ion-doped source / drain region; then, deposit a metal or alloy such as Co, Ni, Ti, etc., and perform rapid heat treatment processes such as the first rapid thermal annealing with a relatively low temperature. After removing the unreacted metal, perform rapid heat treatment processes such as the second rapid thermal annealing with a relatively high temperature, so as to form the required metal silicide. In this embodiment, the metal silicide (not shown) is formed on the top of the source / drain regions of P-type ion doping in the PMOS region, the source / drain regions of N-type ion doping in the NMOS region, and each gate 203 at the same time.

[0067] Optionally, before removing the corresponding oxide layer 202 on the top surface of the contact region of the N-type ion-doped source / drain region and the protective layer on the top surface of the contact region of the P-type ion-doped source / drain region, the contact etch stop layer (not shown) can be conformally deposited again, and a low-k material with a dielectric constant k lower than that of silicon dioxide can be further deposited to form an interlayer dielectric layer (ILD, not shown) with a flat top surface. Then, etch the interlayer dielectric layer, the contact etch stop layer, the corresponding oxide layer 202 on the top surface of the contact region of the N-type ion-doped source / drain region, and the protective layer (not shown) on the top surface of the contact region of the P-type ion-doped source / drain region to form source / drain contact holes exposing the top surfaces of the contact regions of the P-type ion-doped source / drain region in the PMOS region and source / drain contact holes exposing the top surfaces of the contact regions of the N-type ion-doped source / drain region in the NMOS region. After that, through metal deposition, the first rapid heat treatment, removal of the unreacted metal, and the second rapid heat treatment, metal silicide can be formed in each source / drain contact hole.

[0068] In summary, in the manufacturing method of the semiconductor device of the present invention, the step of opening the second hard mask layer in the NMOS region after forming the germanium-silicon source / drain in the PMOS region in the prior art is adjusted to before the photolithography process for forming the germanium-silicon source / drain in the PMOS region, and the second hard mask layer on the top of the gates in the NMOS region and the PMOS region is removed together by using the chemical mechanical polishing (CMP) method, which can eliminate the photomask and wet etching processes required in the prior art when opening the second hard mask layer in the NMOS region, simplify the process flow, save the photomask cost, and avoid the problem of the substrate surface depression in the NMOS region caused by this wet etching process, thereby improving the device performance. The manufacturing method of the semiconductor device of the present invention can be applied to the manufacture of devices with a process node of 28 nm and smaller.

[0069] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, comprising the following steps: Providing a substrate having a PMOS region and an NMOS region, forming an oxide layer, a gate layer and a first hard mask layer on the surface of the substrate, and etching the first hard mask layer and the gate layer to form gates on the PMOS region and the NMOS region; Forming gate sidewalls on the sidewalls of each of the gates, and conformally depositing a contact etch stop layer and a second hard mask layer in sequence on the oxide layer, the gate sidewalls and the first hard mask layer; Depositing a sacrificial dielectric layer on the second hard mask layer, and performing chemical mechanical polishing on the sacrificial dielectric layer to remove the second hard mask layer on top of the first hard mask layer; Removing the sacrificial dielectric layer by using a first wet process; Forming a patterned photoresist layer to protect the NMOS region, and using the patterned photoresist layer as a mask to etch the second hard mask layer, the contact etch stop layer and the substrate on the PMOS region to form source / drain trenches in the substrate on both sides of the gate in the PMOS region; Removing the patterned photoresist layer, and forming germanium-silicon source / drains in the source / drain trenches by using a germanium-silicon epitaxial growth process; Removing the first hard mask layer and the second hard mask layer by using a second wet process.

2. The manufacturing method according to claim 1, characterized in that, both the contact etch stop layer and the sacrificial dielectric layer are oxides, and the etching solution of the first wet process includes hydrofluoric acid.

3. The manufacturing method according to claim 1, characterized in that, the contact etch stop layer on top of the first hard mask layer is removed synchronously by the chemical mechanical polishing or the first wet process.

4. The manufacturing method according to claim 1, characterized in that, the etching solution of the second wet process includes phosphoric acid.

5. The manufacturing method according to claim 1, characterized in that, the first hard mask layer and the second hard mask layer are made of the same material.

6. The manufacturing method according to claim 1, characterized in that, both the contact etch stop layer and the second hard mask layer are formed by using an atomic layer deposition process.

7. The manufacturing method according to claim 1, characterized in that, before removing the first hard mask layer and the second hard mask layer, a protective layer is formed on the top surface of the germanium-silicon source / drains; and / or, after removing the first hard mask layer and the second hard mask layer, metal is further deposited and rapid thermal treatment is performed to form metal silicides on the top surfaces of the germanium-silicon source / drains and the gates.

8. The manufacturing method according to claim 7, characterized in that, after removing the first hard mask layer and the second hard mask layer and before depositing metal, or, after forming the gates and before depositing the contact etch stop layer, further comprising: performing N-type ion implantation on the substrate on both sides of the gate in the NMOS region to form an N-type ion-doped source / drain region.

9. The manufacturing method according to claim 8, characterized in that, before depositing the metal, the oxide layer on the N-type ion-doped source / drain region is removed by wet etching to expose the surface of the N-type ion-doped source / drain region.

10. The manufacturing method according to any one of claims 1-9, characterized in that, during the process of forming a germanium-silicon source / drain in the source / drain trench by using a germanium-silicon epitaxial growth process, P-type ions are in-situ doped into the germanium-silicon source / drain to form a P-type ion-doped source / drain region; or, after removing the first hard mask layer and the second hard mask layer, the NMOS region is masked, and P-type ion implantation is performed on the germanium-silicon source / drain on both sides of the gate of the PMOS region to form a P-type ion-doped source / drain region.

Images