Semiconductor structure and manufacturing method thereof
By using a high-voltage device light doping source and drain mask to form a doped region in the intrinsic device area of the semiconductor structure, high-voltage LDD implantation and ion implantation, the intrinsic device leakage problem is solved, and more efficient doping control is achieved, avoiding adverse effects on devices in other regions.
Patent Information
- Application Number
- CN202311573623.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-23
- Publication Date
- 2025-05-27
AI Technical Summary
The existing semiconductor structures with intrinsic devices are prone to leakage problems, and the traditional blanket P-type ion implantation method will have a negative impact on the performance of devices in other regions.
A window is added to the intrinsic device area using a first conductivity type light doped source and drain mask of a high voltage device to form a first conductivity type doped region, including a light doped source and drain region of a high voltage device area and a light doped adjustment region of an intrinsic device area. Through high voltage LDD implantation and first conductivity type ion implantation, the doping concentration of the P-type semiconductor layer or its conductivity type is increased or its conductivity type is changed.
Without increasing production costs, the leakage problem of intrinsic devices will be reduced without adversely affecting the performance and isolation effect of devices in other areas.
Smart Images
Figure CN120050988A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors and relates to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] As a ZVT (Zero or low threshold voltage) device, the native device is widely used in analog and digital circuits due to its high switching speed and low saturation voltage.
[0003] Traditional intrinsic devices are made directly on P-type substrates. Due to the low doping concentration of the substrate, they are prone to device punch-through, high leakage current, and the inability to measure the threshold voltage Vt. To solve this problem, the traditional approach is to increase the implantation of P-type ions (such as boron ions) to increase the P-type substrate concentration, suppress the punch-through phenomenon, and reduce the leakage current.
[0004] In order to save masks / reduce costs, blanket doping is usually selected. However, blanket doping will cause ions to be implanted into other areas, which will have other effects on device performance / well resistance Rs / isolation effect.
[0005] Therefore, how to improve the manufacturing process of semiconductor structures with intrinsic devices to reduce the leakage of intrinsic devices without increasing production costs and without causing additional adverse effects on devices in other regions has become an important technical problem that technical personnel in this field need to solve urgently.
[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, so as to solve the problem that the existing semiconductor structure with intrinsic devices is prone to leakage.
[0008] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:
[0009] Providing a P-type semiconductor layer, the P-type semiconductor layer comprising a core device region, an intrinsic device region and a high-voltage device region distributed according to a preset rule along a plane where the P-type semiconductor layer is located;
[0010] Provide a light-doped source / drain mask of the first conductivity type for high-voltage devices, and form a doped region of the first conductivity type in the P-type semiconductor layer based on the light-doped source / drain mask of the first conductivity type for high-voltage devices. Wherein, the light-doped source / drain mask of the first conductivity type for high-voltage devices is provided with a window in the intrinsic device region, and the doped region of the first conductivity type includes a light-doped source / drain region of the first conductivity type located in the high-voltage device region and a light-doped adjustment region of the first conductivity type located in the intrinsic device region;
[0011] Form a core PMOS transistor and a core NMOS transistor in the core device region, and form an intrinsic MOS transistor in the intrinsic device region. The intrinsic MOS transistor includes a lightly doped source / drain region of the second conductivity type and a heavily doped source / drain region of the second conductivity type located in the lightly doped adjustment region of the first conductivity type.
[0012] Optionally, before forming a doped region of the first conductivity type in the P-type semiconductor layer based on the light-doped source / drain mask of the first conductivity type for high-voltage devices, the following steps are further included: forming a deep N-well in the P-type semiconductor layer, the deep N-well is located in the core device region and in the region where the core NMOS transistor is to be formed.
[0013] Optionally, forming a doped region of the first conductivity type in the P-type semiconductor layer based on the light-doped source / drain mask of the first conductivity type for high-voltage devices includes the following steps:
[0014] Form a first photoresist layer on the P-type semiconductor layer;
[0015] Pattern the first photoresist layer based on the light-doped source / drain mask of the first conductivity type for high-voltage devices;
[0016] Perform ion implantation of the first conductivity type on the P-type semiconductor layer based on the patterned first photoresist layer.
[0017] Optionally, forming a core PMOS transistor and a core NMOS transistor in the core device region includes the following steps:
[0018] Form a second photoresist layer on the P-type semiconductor layer;
[0019] Pattern the second photoresist layer to obtain an N-well implantation window in the second photoresist layer;
[0020] Perform N-type ion implantation on the P-type semiconductor layer based on the patterned second photoresist layer to obtain an N-well in the P-type semiconductor layer, the N-well is located in the core device region and in the region where the core PMOS transistor is to be formed;
[0021] Form a third photoresist layer on the P-type semiconductor layer;
[0022] Pattern the third photoresist layer to obtain P-well implantation windows in the third photoresist layer;
[0023] Perform P-type ion implantation on the P-type semiconductor layer based on the patterned third photoresist layer to obtain P-wells in the P-type semiconductor layer, where the P-wells are located in the core device region and in the region where the core NMOS transistors are to be formed.
[0024] Optionally, the first conduction type is P-type, the second conduction type is N-type, and the intrinsic MOS transistor is an intrinsic NMOS transistor.
[0025] Optionally, the method for forming the first conduction type doped region includes ion implantation. The energy range of ion implantation is 40 keV - 180 keV, the dose range of ion implantation is 1E12 atoms per square centimeter - 1E13 atoms per square centimeter, and it is implanted in one or multiple times. The ion implantation angle range is 0° - 40°.
[0026] Optionally, the formation of the N-type lightly doped source / drain regions of the intrinsic NMOS transistor and the formation of the N-type lightly doped source / drain regions of the core NMOS transistor adopt the same process conditions; the formation of the N-type heavily doped source / drain regions of the intrinsic NMOS transistor and the formation of the N-type heavily doped source / drain regions of the core NMOS transistor adopt the same process conditions.
[0027] Optionally, the doping concentration of the N-type lightly doped source / drain regions of the core NMOS transistor enables the threshold voltage of the core NMOS transistor to meet one of the standard threshold voltage, low threshold voltage, and high threshold voltage.
[0028] Optionally, the first conduction type is N-type, the second conduction type is P-type, and the intrinsic MOS transistor is an intrinsic PMOS transistor.
[0029] Optionally, the method for forming the first conduction type doped region includes ion implantation. The energy range of ion implantation is 100 keV - 500 keV, the dose range of ion implantation is 2E12 atoms per square centimeter - 1E13 atoms per square centimeter, and it is implanted in one or multiple times. The ion implantation angle range is 0° - 40°.
[0030] Optionally, the formation of the P-type lightly doped source / drain regions of the intrinsic PMOS transistor and the formation of the P-type lightly doped source / drain regions of the core PMOS transistor adopt the same process conditions; the formation of the P-type heavily doped source / drain regions of the intrinsic PMOS transistor and the formation of the P-type heavily doped source / drain regions of the core PMOS transistor adopt the same process conditions.
[0031] Optionally, the doping concentration of the P-type lightly doped source / drain regions of the core PMOS transistor enables the threshold voltage of the core PMOS transistor to meet one of a standard threshold voltage, a low threshold voltage, and a high threshold voltage.
[0032] The present invention also provides a semiconductor structure, comprising:
[0033] A P-type semiconductor layer, including a core device region, an intrinsic device region, and a high-voltage device region distributed according to a preset rule in the plane where the P-type semiconductor layer is located;
[0034] A first-conductivity-type doping region, located in the P-type semiconductor layer, the first-conductivity-type doping region including a first-conductivity-type lightly doped source / drain region located in the high-voltage device region and a first-conductivity-type lightly doped adjustment region located in the intrinsic device region;
[0035] A core PMOS transistor and a core NMOS transistor, located in the core device region;
[0036] An intrinsic MOS transistor, located in the intrinsic device region, the intrinsic MOS transistor including a second-conductivity-type lightly doped source / drain region and a second-conductivity-type heavily doped source / drain region located in the first-conductivity-type lightly doped adjustment region.
[0037] Optionally, the first conductivity type is P-type, the second conductivity type is N-type, and the intrinsic MOS transistor is an intrinsic NMOS transistor.
[0038] Optionally, the first conductivity type is N-type, the second conductivity type is P-type, and the intrinsic MOS transistor is an intrinsic PMOS transistor.
[0039] As described above, the method for manufacturing a semiconductor structure according to the present invention forms a doped region of a first conductivity type in a P-type semiconductor layer based on a light-doped source / drain mask of a high-voltage (HV) device of the first conductivity type. Among them, the light-doped source / drain mask of the high-voltage device of the first conductivity type is provided with a window in the intrinsic device region. The formed doped region of the first conductivity type includes a light-doped source / drain region of the first conductivity type located in the high-voltage device region and a light-doped adjustment region of the first conductivity type located in the intrinsic device region. The light-doped source / drain region and the heavily doped source / drain region of the second conductivity type of the intrinsic MOS transistor are formed in the light-doped adjustment region of the first conductivity type. Based on the high-voltage process, without additionally increasing a mask, by using a light-doped source / drain (LDD) mask of a high-voltage device of the first conductivity type provided with a window in the intrinsic device region, and performing ion implantation of the first conductivity type in the intrinsic device region simultaneously by high-voltage LDD implantation, the doping concentration of the P-type semiconductor layer in the corresponding region can be increased or the P-type semiconductor layer in the corresponding region can be inverted into an N-type, thereby solving the leakage problem of the intrinsic MOS transistor. Compared with blanket P-type ion implantation, on the one hand, the present invention reduces an additional ion implantation process, and on the other hand, since only P-type ion implantation or a change in conductivity type is added in the intrinsic device region, the ion doping in other regions will not be changed, so there will be no other adverse effects on device performance / trap resistance Rs / isolation effect. Description of the Drawings
[0040] Figure 1 It shows a schematic diagram presented after forming a first photoresist layer on a P-type semiconductor layer in a method for manufacturing a semiconductor structure.
[0041] Figure 2 It shows a schematic diagram of the obtained structure after patterning the first photoresist layer and performing ion implantation to obtain an N-well in a method for manufacturing a semiconductor structure.
[0042] Figure 3 It shows a schematic diagram presented after forming a second photoresist layer on a P-type semiconductor layer, patterning the second photoresist layer and performing ion implantation to obtain a P-well in a method for manufacturing a semiconductor structure.
[0043] Figure 4 It shows a schematic diagram of the obtained structure after forming a core PMOS transistor, a core NMOS transistor, and an intrinsic NMOS transistor in a method for manufacturing a semiconductor structure.
[0044] Figure 5 It shows a schematic diagram of the obtained structure after first adding a blanket ion implantation to form a P-type doped layer in the P-type semiconductor layer after forming an N-well and a P-well, and then forming a core PMOS transistor, a core NMOS transistor, and an intrinsic NMOS transistor in another method for manufacturing a semiconductor structure.
[0045] Figure 6 It shows a process flow chart of the manufacturing method of the semiconductor structure of the present invention.
[0046] Figure 7 It shows a schematic structural diagram of the P-type semiconductor layer provided by the manufacturing method of the semiconductor structure of the present invention.
[0047] Figure 8 It shows a schematic diagram of the structure obtained after forming a P-type doped region in the P-type semiconductor layer based on the high-voltage device P-type lightly doped source / drain photomask in an embodiment of the manufacturing method of the semiconductor structure of the present invention.
[0048] Figure 9 It shows a schematic diagram of the structure obtained after forming an N-well in the P-type semiconductor layer in an embodiment of the manufacturing method of the semiconductor structure of the present invention.
[0049] Figure 10 It shows a schematic diagram of the structure obtained after forming a P-well in the P-type semiconductor layer in an embodiment of the manufacturing method of the semiconductor structure of the present invention.
[0050] Figure 11 It shows a schematic diagram of the structure obtained after forming the gate structures, sidewalls, lightly doped source / drain regions, and heavily doped source / drain regions of the core PMOS transistor, core NMOS transistor, and intrinsic NMOS transistor in an embodiment of the manufacturing method of the semiconductor structure of the present invention.
[0051] Figure 12 It shows a schematic diagram of the structure obtained after forming an N-type doped region in the P-type semiconductor layer based on the high-voltage device N-type lightly doped source / drain photomask in another embodiment of the manufacturing method of the semiconductor structure with an intrinsic PMOS transistor of the present invention.
[0052] Figure 13 It shows a schematic diagram of the structure obtained after forming an N-well in the P-type semiconductor layer in another embodiment of the manufacturing method of the semiconductor structure with an intrinsic PMOS transistor of the present invention.
[0053] Figure 14 It shows a schematic diagram of the structure obtained after forming a P-well in the P-type semiconductor layer in another embodiment of the manufacturing method of the semiconductor structure with an intrinsic PMOS transistor of the present invention.
[0054] Figure 15 It shows a schematic diagram of the structure obtained after forming the gate structures, sidewalls, lightly doped source / drain regions, and heavily doped source / drain regions of the core PMOS transistor, core NMOS transistor, and intrinsic PMOS transistor in another embodiment of the manufacturing method of the semiconductor structure with an intrinsic PMOS transistor of the present invention.
[0055] Element number description
[0056] 101 P-type semiconductor layer
[0057] 102 First photoresist layer
[0058] 103 Isolation structure
[0059] 104 Deep N-well
[0060] 105 N-well
[0061] 106 Second photoresist layer
[0062] 107 P-well
[0063] 108 Core PMOS transistor
[0064] 109 Core NMOS transistor
[0065] 110 Intrinsic NMOS transistor
[0066] 111 P-type doped layer
[0067] A Core device region
[0068] B Intrinsic device region
[0069] 201 P-type semiconductor layer
[0070] 202 Isolation structure
[0071] 203 Deep N-well
[0072] 204 P-type lightly doped adjustment region
[0073] 205 First photoresist layer
[0074] 206 Core PMOS transistor
[0075] 2061 Gate dielectric layer
[0076] 2062 Gate polysilicon
[0077] 2063 Gate sidewall
[0078] 2064 P-type lightly doped source / drain region
[0079] 2065 P-type heavily doped source / drain region
[0080] 2066 N-type pocket doped region
[0081] 207 Core NMOS transistor
[0082] 2071 Gate dielectric layer
[0083] 2072 Gate polysilicon
[0084] 2073 Gate sidewall
[0085] 2074 N-type lightly doped source / drain region
[0086] 2075 N-type heavily doped source / drain region
[0087] 2076 P-type pocket doping region
[0088] 208 Intrinsic NMOS transistor
[0089] 2081 Gate dielectric layer
[0090] 2082 Gate polysilicon
[0091] 2083 Gate sidewall
[0092] 2084 N-type lightly doped source / drain region
[0093] 2085 N-type heavily doped source / drain region
[0094] 2086 P-type pocket doping region
[0095] 209 Second photoresist layer
[0096] 210 N-well
[0097] 211 Third photoresist layer
[0098] 212 P-well
[0099] 213 N-type lightly doped adjustment region
[0100] 214 Intrinsic PMOS transistor
[0101] 2141 Gate dielectric layer
[0102] 2142 Gate polysilicon
[0103] 2143 Gate sidewall
[0104] 2144 P-type lightly doped source / drain region
[0105] 2145 P-type heavily doped source / drain region
[0106] 2146 N-type pocket doping region
[0107] C Core device region
[0108] D Intrinsic device region
[0109] S1 - S3 Steps Detailed implementation mode
[0110] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0111] Please refer to Figures 1 to 15 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0112] Please refer to Figure 1 - to Figure 4 , which shows a schematic diagram of the structure obtained in each step of a method for fabricating a semiconductor structure.
[0113] Specifically, as Figure 1 shown, it shows a schematic diagram of the structure obtained after forming a first photoresist layer 102 on a P-type semiconductor layer 101. Among them, the P-type semiconductor layer 101 includes a core device region A and an intrinsic device region B. An isolation structure 103 and a deep N-well 104 are pre-formed in the P-type semiconductor layer 101. The isolation structure 103 can be a shallow trench isolation structure, and different regions are isolated from each other through the isolation structure 103.
[0114] As Figure 2 shown, it shows a schematic diagram of the structure obtained after patterning the first photoresist layer 102 and performing ion implantation to form an N-well 105 in the P-type semiconductor layer 101.
[0115] As Figure 3 shown, it shows a schematic diagram presented after forming a second photoresist layer 106 on the P-type semiconductor layer 101, patterning the second photoresist layer 106, and performing ion implantation to form a P-well 107 in the deep N-well 104 of the P-type semiconductor layer 101.
[0116] As Figure 4As shown, it is a schematic diagram of the structure obtained after forming the core PMOS transistor 108, the core NMOS transistor 109, and the intrinsic NMOS transistor 110. Among them, both the core PMOS transistor 108 and the core NMOS transistor 109 are located in the core device region A and are isolated by an isolation structure. The source / drain regions of the core PMOS transistor 108 are formed in the N-well 105, the source / drain regions of the core NMOS transistor 109 are formed in the P-well 107, the intrinsic NMOS transistor 110 is located in the intrinsic device region B, and the source / drain regions of the intrinsic NMOS transistor 110 are directly formed in the P-type semiconductor layer 101.
[0117] In Figure 4 In the semiconductor structure shown, due to the low doping concentration of the P-type semiconductor layer 101, the intrinsic NMOS transistor 110 is prone to punch-through, generating a high leakage current, resulting in the inability to measure the threshold voltage Vt.
[0118] In one solution, by increasing the implantation of P-type ions (such as boron ions) to increase the concentration of the P-type semiconductor layer 101, the punch-through phenomenon of the intrinsic NMOS transistor 110 can be suppressed, the leakage current can be reduced, and at the same time, the photomask can be saved and the cost can be reduced. Please refer to Figure 5 , which shows a schematic diagram of the structure obtained after forming a blanket ion implantation to form a P-type doped layer 111 (the region above the horizontal dotted line) in the P-type semiconductor layer 101 after forming the N-well and the P-well in the manufacturing method of another semiconductor structure, and then forming the core PMOS transistor 108, the core NMOS transistor 108, and the intrinsic NMOS transistor 110. Among them, the P-type doped layer 111 is formed not only in the intrinsic device region B but also in the core device region A. That is to say, although the blanket ion implantation improves the leakage of the intrinsic NMOS transistor 110, at the same time, due to the ion implantation into other regions, it will bring other impacts on the device performance / well resistance Rs / isolation effect.
[0119] Through a large amount of research, the inventors of the present application have improved the manufacturing process of the semiconductor structure with intrinsic devices, which can reduce the leakage of the intrinsic devices without adding a photomask and have no additional adverse effects on the devices in other regions. The improved solution is described in detail below.
[0120] The present invention provides a manufacturing method of a semiconductor structure. Please refer to Figure 6 , which shows a process flow chart of the method, including the following steps:
[0121] S1: Provide a P-type semiconductor layer, where the P-type semiconductor layer includes a core device region, an intrinsic device region, and a high-voltage device region that are distributed according to a preset rule in the plane where the P-type semiconductor layer is located;
[0122] S2: Provide a light-doped source / drain mask of the first conductivity type for high-voltage devices, and form a doping region of the first conductivity type in the P-type semiconductor layer based on the light-doped source / drain mask of the first conductivity type for high-voltage devices. Among them, the light-doped source / drain mask of the first conductivity type for high-voltage devices is provided with a window in the intrinsic device region, and the doping region of the first conductivity type includes a light-doped source / drain region of the first conductivity type located in the high-voltage device region and a light-doped adjustment region of the first conductivity type located in the intrinsic device region;
[0123] S3: Form a core PMOS transistor and a core NMOS transistor in the core device region, and form an intrinsic MOS transistor in the intrinsic device region. The intrinsic MOS transistor includes a light-doped source / drain region of the second conductivity type and a heavily-doped source / drain region of the second conductivity type located in the light-doped adjustment region of the first conductivity type.
[0124] The above steps are described in detail below in conjunction with the structural drawings.
[0125] First, please refer to Figure 7 , and execute the step S1: Provide a P-type semiconductor layer 201. The P-type semiconductor layer 201 includes a core device region C, an intrinsic device region D, and a high-voltage device region (not shown) that are distributed according to a preset rule in the plane where the P-type semiconductor layer 201 is located.
[0126] As an example, the core device region C is used to manufacture low-voltage devices, the high-voltage device region is used to manufacture high-voltage devices, and the core device region C, the intrinsic device region D, and the high-voltage device region (not shown) are isolated by an isolation structure. The specific distribution positions of each region can be set according to actual needs and are not particularly limited here.
[0127] It should be noted that the "low voltage" and "high voltage" mentioned here and in other places are relative concepts. Among them, the power supply voltage of the low-voltage device is lower than that of the high-voltage device, and the specific voltage value is not particularly limited. For example, in one embodiment, the power supply voltage of the low-voltage device is 1.1V, and the power supply voltage of the high-voltage device is 5V. In another embodiment, the power supply voltage of the low-voltage device is 1.1V, and the power supply voltage of the high-voltage device is 32V, and a device with a power supply voltage of 5V or 8V is regarded as a medium-voltage device.
[0128] As an example, in a manufacturing process of a semiconductor structure having both high-voltage devices and low-voltage devices according to the present invention, the sequence of important steps includes: high-voltage N-well (HVNW) → deep N-well (DNW) → high-voltage P-well (HVPW) → active area photolithography (AAPH) → high-voltage N-type lightly doped source / drain (HV NLDD) → high-voltage P-type lightly doped source / drain (HV PLDD) → high-voltage gate oxide layer (HVGOX) → low-voltage N-well (LVNW) → low-voltage P-well (LVPW) → low-voltage gate oxide layer (LVGOX) → polysilicon (Poly) → spacer → low-voltage lightly doped source / drain (LV LDD) → source / drain region ion implantation (SD IMP), and some of these steps will be described in detail in the following paragraphs.
[0129] As an example, the material of the P-type semiconductor layer 201 can be selected from silicon, germanium, silicon germanium, silicon carbide, group III-V compounds, or other suitable semiconductor materials.
[0130] As an example, the P-type semiconductor layer 201 can be a separate P-type substrate or a P-type epitaxial layer grown on a substrate.
[0131] As an example, an isolation structure 202 is pre-formed in the P-type semiconductor layer 101. The isolation structure 202 can be a shallow trench isolation (STI) structure or other suitable isolation structures, and different device regions or different transistors in the same device region are isolated from each other through the isolation structure 202.
[0132] As an example, a deep N-well 203 is also pre-formed in the P-type semiconductor layer 101. The deep N-well 203 is located in the region of the core device area C for forming a core NMOS transistor, and the bottom surface of the deep N-well 203 is lower than the bottom surface of the isolation structure 202.
[0133] Please refer to Figure 8 , perform the step S2: Provide a high-voltage device first-conductivity-type lightly doped source / drain mask, and form a first-conductivity-type doped region in the P-type semiconductor layer 201 based on the high-voltage device first-conductivity-type lightly doped source / drain mask. Among them, the high-voltage device first-conductivity-type lightly doped source / drain mask is provided with a window in the intrinsic device area D, and the first-conductivity-type doped region includes a first-conductivity-type lightly doped source / drain region in the high-voltage device area and a first-conductivity-type lightly doped adjustment region in the intrinsic device area D.
[0134] It should be noted that the "lightly doped source / drain region" mentioned herein and in the rest of the text refers to the LDD (Lightly Doped Drain), which is a lightly doped source / drain region set near the heavily doped source / drain region in the MOS transistor channel, allowing the lightly doped source / drain region to also bear part of the voltage, which helps to prevent the hot electron degradation effect.
[0135] As an example, the first-conductivity-type lightly doped source / drain photomask of the high-voltage device is obtained by modifying the design based on the existing photomask without the window. That is to say, no additional photomask is required in the present invention.
[0136] In one embodiment, before producing the photomask, first modify the formula of the logic operation tool (LOTA) of the original first-conductivity-type lightly doped source / drain photomask of the high-voltage device, and produce the first-conductivity-type lightly doped source / drain photomask of the high-voltage device with a window added in the intrinsic device region D.
[0137] In other embodiments, it is also possible to modify the layout design of the original first-conductivity-type lightly doped source / drain photomask of the high-voltage device before producing the photomask, and produce the first-conductivity-type lightly doped source / drain photomask of the high-voltage device with a window added in the intrinsic device region D.
[0138] Hereinafter, taking the first conductivity type as P type as an example, the first-conductivity-type lightly doped source / drain photomask of the high-voltage device corresponds to the P-type lightly doped source / drain photomask of the high-voltage device, the first-conductivity-type doping region corresponds to the P-type doping region, the first-conductivity-type lightly doped source / drain region corresponds to the P-type lightly doped source / drain region, the first-conductivity-type lightly doped adjustment region corresponds to the P-type lightly doped adjustment region 204, and subsequently the second conductivity type corresponds to N type.
[0139] As an example, as Figure 8 shown, forming a P-type doping region in the P-type semiconductor layer 201 based on the P-type lightly doped source / drain photomask of the high-voltage device includes the following steps:
[0140] S2-1: Form a first photoresist layer 205 on the P-type semiconductor layer 201 by spin coating or other suitable methods;
[0141] S2-2: Pattern the first photoresist layer 205 based on the P-type lightly doped source / drain photomask of the high-voltage device and using photolithography processes such as exposure and development. The patterned first photoresist layer 205 has an opening in the intrinsic device region D;
[0142] S2-3: Based on the patterned first photoresist layer 205, perform P-type ion implantation on the P-type semiconductor layer 201, thereby obtaining a P-type lightly doped source / drain region of a high-voltage device in the high-voltage device region, and obtaining the P-type lightly doped adjustment region 204 in the intrinsic device region D.
[0143] As an example, the energy range of ion implantation is 40 keV - 180 keV, the dose range of ion implantation is 1E12 atoms per square centimeter - 1E13 atoms per square centimeter, and it is divided into one or multiple implantations. The ion implantation angle range is 0° - 40°, where Figure 8 the arrow in the figure indicates ion implantation.
[0144] Since the formation of the P-type lightly doped adjustment region 204 uses the P-type lightly doped source / drain mask that is originally required for high-voltage devices and does not add extra masks and extra ion implantation process steps, the production cost will not be increased. And since the P-type ion implantation of the P-type lightly doped adjustment region 204 is only in the intrinsic device region and will not change the ion doping in other regions, it will not have other adverse effects on device performance / well resistance Rs / isolation effect.
[0145] Please refer to Figures 9 to 11 again, and perform the step S3: form a core PMOS transistor 206 and a core NMOS transistor 207 in the core device region C, and form an intrinsic MOS transistor in the intrinsic device region D. The intrinsic MOS transistor includes a second-conductivity-type lightly doped source / drain region and a second-conductivity-type heavily doped source / drain region located in the first-conductivity-type lightly doped adjustment region.
[0146] Specifically, when the first conductivity type is P-type and the second conductivity type is N-type, the intrinsic MOS transistor is an intrinsic NMOS transistor 208, and the intrinsic NMOS transistor 208 includes an N-type lightly doped source / drain region and an N-type heavily doped source / drain region located in the P lightly doped adjustment region 204.
[0147] Specifically, as Figure 9 shown, first form a second photoresist layer 209 on the P-type semiconductor layer 201, and use photolithography processes such as exposure and development to pattern the second photoresist layer 209 to obtain an N-well implantation window in the second photoresist layer 209. Then, based on the patterned second photoresist layer 209, perform N-type ion implantation on the P-type semiconductor layer 201 to obtain an N-well 210 in the P-type semiconductor layer 201. The N-well 210 is located in the core device region C and in the region where the core PMOS transistor 206 is to be formed. After that, the second photoresist layer 209 can be removed.
[0148] As an example, the bottom surface of the N-well 210 is lower than the bottom surface of the isolation structure 202 and higher than the bottom surface of the deep N-well 203.
[0149] Specifically, as Figure 10 shown, a third photoresist layer 211 is further formed on the P-type semiconductor layer 201, and the third photoresist layer 211 is patterned by photolithography processes such as exposure and development to obtain a P-well implantation window in the third photoresist layer 211. Then, based on the patterned third photoresist layer 211, P-type ion implantation is performed on the P-type semiconductor layer 201 to obtain a P-well 212 in the P-type semiconductor layer 201. The P-well 212 is located in the core device region C and in the region where the core NMOS transistor 207 is to be formed. Thereafter, the third photoresist layer 211 can be removed.
[0150] As an example, the bottom surface of the P-well 212 is lower than the bottom surface of the isolation structure 202 and higher than the bottom surface of the deep N-well 203.
[0151] Specifically, then the gate structures, sidewalls, lightly doped source / drain regions, and heavily doped source / drain regions of the core PMOS transistor 206, the core NMOS transistor 207, and the intrinsic NMOS transistor 208 are formed. Among them, Figure 11 shows the gate dielectric layer 2061, gate polysilicon 2062, gate sidewall 2063, P-type lightly doped source / drain region 2064, and P-type heavily doped source / drain region 2065 of the core PMOS transistor 206, the gate dielectric layer 2071, gate polysilicon 2072, gate sidewall 2073, N-type lightly doped source / drain region 2074, and N-type heavily doped source / drain region 2075 of the core NMOS transistor 207, and the gate dielectric layer 2081, gate polysilicon 2082, gate sidewall 2083, N-type lightly doped source / drain region 2084, and N-type heavily doped source / drain region 2085 of the intrinsic NMOS transistor 208.
[0152] In this embodiment, an N-type pocket doping region 2066 of the core PMOS transistor 206, a P-type pocket doping region 2076 of the core NMOS transistor 207, and a P-type pocket doping region 2086 of the intrinsic NMOS transistor 208 are further formed by inclined angle ion implantation. Among them, the pocket (PKT) doping region helps to improve the short channel effect.
[0153] As an example, the N-type lightly doped source / drain regions 2084 of the intrinsic NMOS transistor 208 are formed under the same process conditions as the N-type lightly doped source / drain regions 2074 of the core NMOS transistor 207; the N-type heavily doped source / drain regions 2085 of the intrinsic NMOS transistor 208 are formed under the same process conditions as the N-type heavily doped source / drain regions 2075 of the core NMOS transistor 207, and the P-type pocket doping regions 2086 of the intrinsic NMOS transistor 208 are formed under the same process conditions as the P-type pocket doping regions 2076 of the core NMOS transistor 207.
[0154] As an example, the doping concentration of the N-type lightly doped source / drain regions of the core NMOS transistor 207 enables the threshold voltage of the core NMOS transistor 207 to meet one of the standard threshold voltage (SVT), low threshold voltage (LVT), and high threshold voltage (HVT), and can be selected according to specific device performance requirements.
[0155] Thus far, a semiconductor structure is fabricated, such as Figure 11As shown, the semiconductor structure includes a P-type semiconductor layer 201, a P-type doped region, a core PMOS transistor 206, a core NMOS transistor 207, and an intrinsic NMOS transistor 208. Among them, the P-type semiconductor layer 201 includes a core device region C, an intrinsic device region D, and a high-voltage device region (not shown) distributed according to a preset rule in the plane where the P-type semiconductor layer 201 is located. The P-type doped region is located in the P-type semiconductor layer 201 and includes a P-type lightly doped source / drain region in the high-voltage device region and a P-type lightly doped adjustment region 204 in the intrinsic device region D. The core PMOS transistor 206 and the core NMOS transistor 207 are located in the core device region C, and the intrinsic NMOS transistor 208 is located in the intrinsic device region D. The intrinsic NMOS transistor 208 includes an N-type lightly doped source / drain region 2084 and an N-type heavily doped source / drain region 2085 in the P-type lightly doped adjustment region 204. Due to the presence of the P-type lightly doped adjustment region 204 in the intrinsic device region D, the doping concentration of the P-type semiconductor layer 201 at the corresponding position is increased, effectively solving the leakage problem of the intrinsic NMOS transistor 208. At the same time, the P-type lightly doped adjustment region 204 is only formed in the intrinsic device region D, and the core device region and other regions are not affected, and the performance of the device will not deteriorate. In addition, the P-type lightly doped adjustment region 204 can be formed synchronously with the P-type lightly doped source / drain region in the high-voltage device region, without adding additional photomasks and ion implantation steps, and without increasing the production cost.
[0156] It should be noted that in Figures 8 - 11In the illustrated embodiment, the first conductivity type is P-type, the second conductivity type is N-type, the high-voltage device first conductivity type lightly doped source / drain mask correspondingly is the high-voltage device P-type lightly doped source / drain mask, the first conductivity type doped region correspondingly is the P-type doped region, the first conductivity type lightly doped source / drain region correspondingly is the P-type lightly doped source / drain region, the first conductivity type lightly doped adjustment region correspondingly is the P-type lightly doped adjustment region 204, the intrinsic MOS transistor correspondingly is the intrinsic NMOS transistor 208, and the intrinsic NMOS transistor 208 includes an N-type lightly doped source / drain region and an N-type heavily doped source / drain region located in the P lightly doped adjustment region 204. However, in another embodiment, the first conductivity type may also be N-type, the second conductivity type correspondingly is P-type, the high-voltage device first conductivity type lightly doped source / drain mask correspondingly is the high-voltage device N-type lightly doped source / drain mask, the first conductivity type doped region correspondingly is the N-type doped region, the first conductivity type lightly doped source / drain region correspondingly is the N-type lightly doped source / drain region, the first conductivity type lightly doped adjustment region correspondingly is the N-type lightly doped adjustment region, the intrinsic MOS transistor correspondingly is the intrinsic PMOS transistor, and the intrinsic PMOS transistor includes a P-type lightly doped source / drain region and a P-type heavily doped source / drain region located in the N lightly doped adjustment region.
[0157] As an example, please refer to Figures 12 - 15 , which shows a schematic structural diagram presented after some key process nodes of the steps S2 - S3 in this another embodiment.
[0158] Specifically, as Figure 12 shown, it is a schematic diagram of the structure obtained after forming an N-type doped region in the P-type semiconductor layer 201 based on the high-voltage device N-type lightly doped source / drain mask in step S2. Among them, the high-voltage device N-type lightly doped drain mask has a window added in the intrinsic device region D, and the N-type doped region includes an N-type lightly doped source / drain region located in the high-voltage device region and an N-type lightly doped adjustment region 213 located in the intrinsic device region D.
[0159] As an example, N-type ion implantation is performed on the P-type semiconductor layer 201 based on the patterned first photoresist layer 205, so as to obtain an N-type lightly doped source / drain region of the high-voltage device in the high-voltage device region and obtain the N-type lightly doped adjustment region 213 in the intrinsic device region D. The energy range of the ion implantation is 100 keV - 500 keV, the dose range of the ion implantation is 2E12 atoms per square centimeter - 1E13 atoms per square centimeter, and it is implanted in one or multiple times. The ion implantation angle range is 0° - 40°. Among them, the arrow in 12 indicates the ion implantation.
[0160] As Figure 13As shown, it is a schematic diagram of the structure obtained after forming the N-well 210 in the P-type semiconductor layer 201 in the step S3. Among them, the N-well 210 is located in the core device region C and in the region where the core PMOS transistor 206 is to be formed.
[0161] As Figure 14 shown, it is a schematic diagram of the structure obtained after forming the P-well 212 in the P-type semiconductor layer 201 in the step S3. Among them, the P-well 212 is located in the core device region C and in the region where the core NMOS transistor 207 is to be formed.
[0162] As Figure 15 shown, it is a schematic diagram of the structure obtained after forming the gate structures, spacers, lightly doped source / drain regions, and heavily doped source / drain regions of the core PMOS transistor 206, the core NMOS transistor 207, and the intrinsic PMOS transistor 214 in the step S3. Among them, Figure 15 the gate dielectric layer 2061, the gate polysilicon 2062, the gate spacer 2063, the P-type lightly doped source / drain region 2064, and the P-type heavily doped source / drain region 2065 of the core PMOS transistor 206 are shown, the gate dielectric layer 2071, the gate polysilicon 2072, the gate spacer 2073, the N-type lightly doped source / drain region 2074, and the N-type heavily doped source / drain region 2075 of the core NMOS transistor 207 are shown, and the gate dielectric layer 2141, the gate polysilicon 2142, the gate spacer 2143, the P-type lightly doped source / drain region 2144, and the P-type heavily doped source / drain region 2145 of the intrinsic PMOS transistor 214 are shown.
[0163] As an example, an angled ion implantation is further used to form the N-type pocket doping region 2066 of the core PMOS transistor 206, the P-type pocket doping region 2076 of the core NMOS transistor 207, and the N-type pocket doping region 2146 of the intrinsic PMOS transistor 214.
[0164] As an example, the P-type lightly doped source / drain region 2144 of the intrinsic PMOS transistor 214 is formed under the same process conditions as the P-type lightly doped source / drain region 2064 of the core PMOS transistor 206; the P-type heavily doped source / drain region 2145 of the intrinsic PMOS transistor 214 is formed under the same process conditions as the P-type heavily doped source / drain region 2065 of the core PMOS transistor 206, and the N-type pocket doping region 2146 of the intrinsic PMOS transistor 214 is formed under the same process conditions as the N-type pocket doping region 2066 of the core PMOS transistor 206.
[0165] As an example, the doping concentration of the N-type lightly doped source / drain regions of the core PMOS transistor 206 enables the threshold voltage of the core PMOS transistor 206 to meet one of the standard threshold voltage (SVT), low threshold voltage (LVT), and high threshold voltage (HVT), and can be selected according to specific device performance requirements.
[0166] Specifically, relative to Figures 8 - 11 the illustrated embodiment increases the doping concentration of the P-type semiconductor layer in the corresponding region to increase the threshold voltage of the intrinsic NMOS transistor. Figures 12 - 15 In the illustrated embodiment, by adding the N-type lightly doped adjustment region 213 in the intrinsic device region D, the substrate type of the corresponding region of the intrinsic device region D is changed (adjusted from P-type to N-type). During the subsequent manufacturing process, the intrinsic NMOS transistor in the semiconductor structure is adjusted to an intrinsic PMOS transistor. Since the N-type light doping concentration of the N-type lightly doped adjustment region 213 is relatively high, the probability of punch-through between the source and drain of the obtained intrinsic PMOS transistor is lower than that of the original intrinsic NMOS transistor (when the doping concentration of the P-type semiconductor layer is not increased), thereby improving device leakage. And since the N-type lightly doped adjustment region 213 is only formed in the intrinsic device region D, the core device region and other regions are not affected, and the performance of the device will not deteriorate. At the same time, the formation of this intrinsic PMOS transistor does not add additional photomasks and ion implantation steps, and does not increase the production cost.
[0167] In summary, the manufacturing method of the semiconductor structure of the present invention forms a doping region of the first conductivity type in the P-type semiconductor layer based on the light mask of the lightly doped source / drain of the high-voltage (HV) device of the first conductivity type. Among them, the light mask of the lightly doped source / drain of the high-voltage device of the first conductivity type is provided with a window in the intrinsic device region. The formed doping region of the first conductivity type includes the lightly doped source / drain region of the first conductivity type in the high-voltage device region and the lightly doped adjustment region of the first conductivity type in the intrinsic device region. The lightly doped source / drain region of the second conductivity type and the heavily doped source / drain region of the second conductivity type of the intrinsic MOS transistor are formed in the lightly doped adjustment region of the first conductivity type. Based on the high-voltage process, without additionally increasing the light mask, by using the light mask of the lightly doped source / drain (LDD) of the high-voltage device of the first conductivity type with a window provided in the intrinsic device region, and performing the ion implantation of the first conductivity type in the intrinsic device region simultaneously by high-voltage LDD implantation, the doping concentration of the P-type semiconductor layer in the corresponding region can be increased or the P-type semiconductor layer in the corresponding region can be inverted into the N-type, thereby solving the leakage problem of the intrinsic MOS transistor. Compared with the blanket P-type ion implantation, on the one hand, the present invention reduces an additional ion implantation process, and on the other hand, since only the P-type ion implantation or the change of the conductivity type is increased in the intrinsic device region, the ion doping in other regions will not be changed, so there will be no other adverse effects on the device performance / well resistance Rs / isolation effect. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0168] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, it includes the following steps: Provide a P-type semiconductor layer, and the P-type semiconductor layer includes a core device region, an intrinsic device region, and a high-voltage device region that are distributed according to a preset rule in the plane where the P-type semiconductor layer is located; Provide a first-conductivity-type lightly doped source / drain mask for high-voltage devices, and form a first-conductivity-type doped region in the P-type semiconductor layer based on the first-conductivity-type lightly doped source / drain mask for high-voltage devices. Among them, the first-conductivity-type lightly doped source / drain mask for high-voltage devices is provided with a window in the intrinsic device region, and the first-conductivity-type doped region includes a first-conductivity-type lightly doped source / drain region located in the high-voltage device region and a first-conductivity-type lightly doped adjustment region located in the intrinsic device region; Form a core PMOS transistor and a core NMOS transistor in the core device region, and form an intrinsic MOS transistor in the intrinsic device region. The intrinsic MOS transistor includes a second-conductivity-type lightly doped source / drain region and a second-conductivity-type heavily doped source / drain region located in the first-conductivity-type lightly doped adjustment region.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Before forming a first-conductivity-type doped region in the P-type semiconductor layer based on the first-conductivity-type lightly doped source / drain mask for high-voltage devices, it further includes the following steps: form a deep N-well in the P-type semiconductor layer, and the deep N-well is located in the core device region and in the region where the core NMOS transistor is to be formed.
3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Forming a first-conductivity-type doped region in the P-type semiconductor layer based on the first-conductivity-type lightly doped source / drain mask for high-voltage devices includes the following steps: Form a first photoresist layer on the P-type semiconductor layer; Pattern the first photoresist layer based on the first-conductivity-type lightly doped source / drain mask for high-voltage devices; Perform first-conductivity-type ion implantation on the P-type semiconductor layer based on the patterned first photoresist layer.
4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Forming a core PMOS transistor and a core NMOS transistor in the core device region includes the following steps: Form a second photoresist layer on the P-type semiconductor layer; Pattern the second photoresist layer to obtain an N-well implantation window in the second photoresist layer; Perform N-type ion implantation on the P-type semiconductor layer based on the patterned second photoresist layer to obtain an N-well in the P-type semiconductor layer. The N-well is located in the core device region and in the region where the core PMOS transistor is to be formed; Form a third photoresist layer on the P-type semiconductor layer; Pattern the third photoresist layer to obtain a P-well implantation window in the third photoresist layer; Perform P-type ion implantation on the P-type semiconductor layer based on the patterned third photoresist layer to obtain a P-well in the P-type semiconductor layer. The P-well is located in the core device region and in the region where the core NMOS transistor is to be formed.
5. The method for fabricating a semiconductor structure according to claim 1, It is characterized in that: The first conduction type is P-type, the second conduction type is N-type, and the intrinsic MOS transistor is an intrinsic NMOS transistor.
6. The manufacturing method of the semiconductor structure according to claim 5, It is characterized in that: The method for forming the first conduction type doped region includes ion implantation. The energy range of ion implantation is 40 keV - 180 keV, the dose range of ion implantation is 1E12 atoms per square centimeter - 1E13 atoms per square centimeter, and it is implanted in one or multiple times. The ion implantation angle range is 0° - 40°.
7. The manufacturing method of the semiconductor structure according to claim 5, It is characterized in that: The formation of the N-type lightly doped source / drain region of the intrinsic NMOS transistor and the formation of the N-type lightly doped source / drain region of the core NMOS transistor adopt the same process conditions; the formation of the N-type heavily doped source / drain region of the intrinsic NMOS transistor and the formation of the N-type heavily doped source / drain region of the core NMOS transistor adopt the same process conditions.
8. The manufacturing method of the semiconductor structure according to claim 7, It is characterized in that: The doping concentration of the N-type lightly doped source / drain region of the core NMOS transistor makes the threshold voltage of the core NMOS transistor meet one of the standard threshold voltage, low threshold voltage, and high threshold voltage.
9. The manufacturing method of the semiconductor structure according to claim 1, It is characterized in that: The first conduction type is N-type, the second conduction type is P-type, and the intrinsic MOS transistor is an intrinsic PMOS transistor.
10. The manufacturing method of the semiconductor structure according to claim 9, It is characterized in that: The method for forming the first conduction type doped region includes ion implantation. The energy range of ion implantation is 100 keV - 500 keV, the dose range of ion implantation is 2E12 atoms per square centimeter - 1E13 atoms per square centimeter, and it is implanted in one or multiple times. The ion implantation angle range is 0° - 40°.
11. The manufacturing method of the semiconductor structure according to claim 9, It is characterized in that: The formation of the P-type lightly doped source / drain region of the intrinsic PMOS transistor and the formation of the P-type lightly doped source / drain region of the core PMOS transistor adopt the same process conditions; the formation of the P-type heavily doped source / drain region of the intrinsic PMOS transistor and the formation of the P-type heavily doped source / drain region of the core PMOS transistor adopt the same process conditions.
12. The manufacturing method of the semiconductor structure according to claim 11, It is characterized in that: The doping concentration of the P-type lightly doped source / drain region of the core PMOS transistor makes the threshold voltage of the core PMOS transistor meet one of the standard threshold voltage, low threshold voltage, and high threshold voltage.
13. A semiconductor structure, It is characterized in that, Including: A P-type semiconductor layer, including a core device region, an intrinsic device region, and a high-voltage device region distributed according to a preset rule in the plane where the P-type semiconductor layer is located; A first conductivity type doped region, located in the P-type semiconductor layer, the first conductivity type doped region includes a first conductivity type lightly doped source / drain region located in the high-voltage device region and a first conductivity type lightly doped adjustment region located in the intrinsic device region; A core PMOS transistor and a core NMOS transistor, located in the core device region; An intrinsic MOS transistor, located in the intrinsic device region, the intrinsic MOS transistor includes a second conductivity type lightly doped source / drain region and a second conductivity type heavily doped source / drain region located in the first conductivity type lightly doped adjustment region.
14. The semiconductor structure according to claim 13, wherein: The first conductivity type is P-type, the second conductivity type is N-type, and the intrinsic MOS transistor is an intrinsic NMOS transistor.
15. The semiconductor structure according to claim 13, wherein: The first conductivity type is N-type, the second conductivity type is P-type, and the intrinsic MOS transistor is an intrinsic PMOS transistor.