Semiconductor structure and forming method of semiconductor structure
By injecting the fin structure on the isolation region in the FinFET process to form a non-diffusion layer, the problem of insufficient process and performance of cutting off the single diffusion region in the prior art is solved, and higher device density and semiconductor structure stability are achieved.
Patent Information
- Application Number
- CN202311577133.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-23
- Publication Date
- 2025-05-27
AI Technical Summary
In the existing FinFET process, the process and performance of single diffusion zone cutting to form shallow trench isolation need to be improved, and it is difficult to effectively improve the device density and the stability of the semiconductor structure.
By removing the dielectric structure and gate structure on the isolation region, the fin structure on the isolation region is ion implanted by reverse ions to form a non-diffusion layer to achieve electrical isolation of the fin structure.
This method simplifies the process flow, reduces the stress influence on the fin structure, and improves the stability and integration of the semiconductor structure.
Smart Images
Figure CN120050989A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Art
[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously reducing the size of integrated circuit devices to increase their speed. Currently, due to the requirements of high device density, high performance, and low cost, the semiconductor industry has advanced to nanotechnology process nodes, and the preparation of semiconductor devices is restricted by various physical limits.
[0003] As the size of CMOS devices continues to shrink, challenges from manufacturing and design aspects have promoted the development of three-dimensional designs such as fin field-effect transistors (FinFETs). Compared with existing planar transistors, FinFETs are advanced semiconductor devices for process nodes of 20 nm and below. They can effectively control the difficult-to-overcome short-channel effect caused by device scaling, and can also effectively increase the density of transistor arrays formed on the substrate. At the same time, the gate in the FinFET surrounds the fin (fin-shaped channel), so it can control the static electricity from three sides, and its performance in static electricity control is also more prominent.
[0004] In order to prevent the source and drain doping regions of different transistors from being connected to each other, it is necessary to form an isolation layer in the fin, and at the same time, in order to reduce the area of the isolation layer and improve the integration degree of the formed semiconductor structure. The prior art has introduced SDB (Single Diffusion Break) and DDB (Double Diffusion Break) technologies.
[0005] In order to further increase the density of devices in the FinFET process, many single diffusion breaks can be designed to form more and narrower shallow trench isolations to save the area of the gate array.
[0006] However, the existing processes and performances of designing single diffusion breaks to form shallow trench isolations still need to be improved. Summary of the Invention
[0007] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, which can improve the performance of the semiconductor structure.
[0008] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate and a fin structure located on the substrate, the substrate including a device region and an isolation region arranged along the extending direction of the fin structure, and the fin structure having a first ion therein; forming a gate structure spanning the fin structure and a dielectric structure located on the substrate, the gate structure being located on the isolation region and the device region, and the gate structure being located within the dielectric structure; removing the dielectric structure on the isolation region and the gate structure on the isolation region, forming an opening in the dielectric structure on the isolation region, the opening exposing the top surface and the sidewall surface of the fin structure; performing ion implantation of a second ion on the fin structure exposed by the opening, the conductivity type of the second ion being opposite to that of the first ion, so that the fin structure on the isolation region is formed into a diffusion prevention layer, and the material of the diffusion prevention layer is the intrinsic semiconductor material of the fin structure.
[0009] Optionally, the material of the fin structure includes silicon or silicon germanium.
[0010] Optionally, the first ion includes a P-type ion or an N-type ion; the second ion includes an N-type ion or a P-type ion; the N-type ion includes a phosphorus ion, an arsenic ion or an antimony ion; the P-type ion includes a boron ion, a boron fluoride ion or an indium ion.
[0011] Optionally, in the process of forming the gate structure and the dielectric structure spanning the fin structure, it further includes: forming source / drain doping regions in the fin structures on both sides of the gate structure.
[0012] Optionally, the forming methods of the gate structure, the source / drain doping regions and the dielectric structure include: forming a plurality of gate structures spanning the fin structure on the isolation region and the device region, the gate structures being located on the isolation structure, and the plurality of gate structures being perpendicular to the extending direction of the fin structure; forming source / drain doping regions in the fin structures on both sides of the gate structure; forming a dielectric structure on the substrate, the dielectric structure covering the top surface and the sidewall surface of the fin structure, covering the top surface and the sidewall surface of the gate structure.
[0013] Optionally, the forming methods of the gate structure, the source / drain doping regions and the dielectric structure include: forming a plurality of dummy gate structures spanning the fin structure on the isolation region and the device region; forming source / drain doping regions in the fin structures on both sides of the dummy gate structures; forming a first dielectric layer on the substrate, the fin structure and the dummy gate structures being located within the first dielectric layer, and the first dielectric layer exposing the top surface of the dummy gate structures; removing the dummy gate structures, and forming a plurality of gate structures in the first dielectric layer; forming a second dielectric layer on the first dielectric layer and on the gate structures, and the dielectric structure including the first dielectric layer and the second dielectric layer.
[0014] Optionally, before forming the gate structure and the dielectric structure across the fin structure, it further includes: forming an isolation structure on the substrate, the isolation structure is located on the sidewalls of the fin structure, and the top surface of the isolation structure is lower than the top surface of the fin structure, the gate structure is located on the isolation structure, and the opening further exposes the top surface of the isolation structure.
[0015] Optionally, it further includes: forming a filling layer in the opening.
[0016] Correspondingly, the technical solution of the present invention further provides a semiconductor structure, including: a substrate, the substrate includes a device region and an isolation region; a fin structure located on the device region, the device region and the isolation region are arranged along the extending direction of the fin structure, and the fin structure has a first ion; a diffusion barrier layer located on the isolation region, the material of the diffusion barrier layer is the intrinsic semiconductor material of the fin structure, and the diffusion barrier layer is located between adjacent fin structures; a gate structure across the fin structure, the gate structure is located on the device region; a dielectric structure located on the substrate, and the gate structure is located in the dielectric structure.
[0017] Optionally, the material of the fin structure includes silicon or silicon germanium.
[0018] Optionally, the first ion includes a P-type ion or an N-type ion; the N-type ion includes a phosphorus ion, an arsenic ion or an antimony ion; the P-type ion includes a boron ion, a boron fluoride ion or an indium ion.
[0019] Optionally, it further includes: source-drain doping regions located in the fin structures on both sides of the gate structure.
[0020] Optionally, it further includes: an isolation structure located on the substrate, the isolation structure is located on the sidewalls of the fin structure, and the top surface of the isolation structure is lower than the top surface of the fin structure, and the gate structure is located on the isolation structure.
[0021] Optionally, it further includes: a filling layer located on the diffusion barrier layer, and the filling layer is located in the dielectric structure.
[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0023] The technical solution of the present invention is to remove the dielectric structure and the gate structure on the isolation region, and perform ion implantation of inversion ions on the fin structure exposed on the isolation region, so that the fin structure on the isolation region is formed into a diffusion prevention layer, and the material of the diffusion prevention layer is the intrinsic semiconductor material of the fin structure, so as to electrically isolate the fin structure. The method does not need to add a process flow for removing the fin structure on the isolation region, thereby simplifying the process flow, having less stress impact on the fin structure, making the stress of the semiconductor structure balanced, and improving the stability of the semiconductor structure. Description of the Drawings
[0024] Figure 1 and Figure 2 are schematic structural diagrams of the formation process of a semiconductor structure in an embodiment;
[0025] Figures 3 to 13 are schematic structural diagrams of the formation process of a semiconductor structure in an embodiment of the present invention. Detailed Embodiments
[0026] As described in the background art, the process and performance of designing a single diffusion region cut-off to form shallow trench isolation still need to be improved. Now, specific embodiments will be analyzed and described.
[0027] Figure 1 and Figure 2 are schematic structural diagrams of the formation process of a semiconductor structure in an embodiment.
[0028] Please refer to Figure 1 , a substrate 100 and a fin structure 101 located on the substrate 100 are provided. The substrate 100 includes a device region and an isolation region arranged along the extending direction of the fin structure 101; a gate structure 102 spanning the fin structure 101, source / drain doping regions 103 in the fin structure 101 on both sides of the gate structure 102, and a dielectric structure 104 located on the substrate 100 are formed. The gate structure 102 is located on the isolation region and the device region, and the gate structure 102 is located in the dielectric structure 104.
[0029] Please refer to Figure 2 , the gate structure 102 on the isolation region and the fin structure 101 at the bottom of the gate structure 102 on the isolation region are removed, and an opening 105 located in the dielectric structure 104 and the fin structure 101 is formed on the isolation region. The bottom of the opening 105 is lower than or flush with the bottom of the fin structure 101.
[0030] The opening 105 is used to form an anti-diffusion structure in the opening 105 subsequently to isolate the fin structures 101 on both sides of the opening 105. When forming the opening 105, a part of the dielectric structure 104 on the top of the gate structure 102 needs to be removed, the gate structure 102 on the isolation region needs to be removed, and the fin structure 101 at the bottom of the gate structure 102 on the isolation region needs to be removed. Since source / drain doping regions 103 are formed in the fin structures 101 on both sides of the gate structure 102, and the source / drain doping regions 103 provide compressive stress or tensile stress to the channel according to the type of the semiconductor structure. Before removing the gate structure 102 and the fin structure 101 at the bottom of the gate structure 102, the overall stress of the semiconductor structure reaches equilibrium. After removing the gate structure 102 and the fin structure 101 at the bottom of the gate structure 102, the opening 105 will be subjected to the extrusion stress F( Figure 2 as shown), and the overall stress balance in the fin structure 101 will be damaged. Even if an anti-diffusion structure is formed in the opening 105 subsequently, the stress imbalance in the fin structure 101 has been caused, that is, the original stress tendency of the source / drain doping regions 103 is damaged, thereby affecting the performance of the semiconductor structure.
[0031] To solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure. By removing the dielectric structure on the isolation region and the gate structure on the isolation region, ion implantation of inversion ions is performed on the fin structure exposed on the isolation region, so that the fin structure on the isolation region is formed into an anti-diffusion layer, and the material of the anti-diffusion layer is the intrinsic semiconductor material of the fin structure to electrically isolate the fin structure. The method does not need to add a process flow for removing the fin structure on the isolation region, thereby simplifying the process flow, having less stress impact on the fin structure, making the stress of the semiconductor structure balanced, and improving the stability of the semiconductor structure.
[0032] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention in detail with reference to the drawings.
[0033] Figures 3 to 13 It is a schematic structural diagram of the process of forming a semiconductor structure in an embodiment of the present invention.
[0034] Please refer to Figure 3 and Figure 4 , Figure 3 is Figure 4 a top view of Figure 4 is Figure 3 a schematic structural diagram in the direction of the section line AA1 in , providing a substrate 200 and fin structures 201 located on the substrate 200. The substrate 200 includes a device region II and an isolation region I arranged along the extending direction of the fin structures 201, and the fin structures 201 have first ions.
[0035] The number of the fin structures 201 is multiple, and the extending directions of the multiple fin structures 201 are parallel to the first direction X, and the first direction X is parallel to the surface of the substrate 200.
[0036] In this embodiment, the material of the fin structure 201 includes silicon, germanium or silicon germanium.
[0037] The first ions include P-type ions or N-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions or indium ions.
[0038] When the first ions include P-type ions, the material of the fin structure 201 includes silicon, germanium or silicon germanium; when the first ions include N-type ions, the material of the fin structure 201 includes silicon.
[0039] In this embodiment, the material of the substrate 200 is silicon.
[0040] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
[0041] Please refer to Figures 5 to 7 , Figure 5 is Figure 6 and Figure 7 a top view of the dielectric structure 204 omitted, Figure 6 is Figure 5 a schematic structural diagram in the direction of the section line AA1 in Figure 7 is Figure 5 a schematic structural diagram in the direction of the section line BB1 in . An isolation structure 205 is formed on the substrate 200. The isolation structure 205 is located on the sidewalls of the fin structures 201, and the top surface of the isolation structure 205 is lower than the top surface of the fin structures 201; a plurality of gate structures 202 spanning the fin structures 201 are formed on the isolation region I and the device region II. The gate structures 202 are located on the isolation structure 205, and the plurality of gate structures 202 are perpendicular to the extending direction of the fin structures 201; source-drain doping regions 203 are formed in the fin structures 201 on both sides of the gate structures 202; a dielectric structure 204 is formed on the substrate 200. The dielectric structure 204 covers the top surface and the sidewall surfaces of the fin structures 201, covers the top surface and the sidewall surfaces of the gate structures, and the gate structures 202 are located in the dielectric structure 204.
[0042] The material of the isolation structure 205 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.
[0043] In this embodiment, the material of the isolation structure 205 includes silicon oxide.
[0044] The gate structure 202 includes a gate dielectric layer (not shown) and a gate layer (not labeled) located on the gate dielectric layer.
[0045] In this embodiment, the material of the gate dielectric layer includes silicon oxide or a low-k (k less than 3.9) material; the material of the gate layer includes polysilicon.
[0046] In another embodiment, the material of the gate dielectric layer includes a high-k dielectric material, the dielectric constant of the high-k dielectric material is greater than 3.9, the material of the gate dielectric layer is a high-k (k greater than 3.9) dielectric material, and the material of the gate dielectric layer includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, or aluminum oxide; the material of the gate layer includes a metal, and the metal includes tungsten.
[0047] In another embodiment, the method for forming the gate structure, source / drain doping regions, and dielectric structure includes: forming a plurality of dummy gate structures on the isolation region and the device region, the dummy gate structures straddling the fin structures; forming source / drain doping regions in the fin structures on both sides of the dummy gate structures; forming a first dielectric layer on the substrate, the fin structures and the dummy gate structures being located in the first dielectric layer, the first dielectric layer exposing the top surface of the dummy gate structures; removing the dummy gate structures to form a plurality of gate structures in the first dielectric layer; forming a second dielectric layer on the first dielectric layer and on the gate structures, and the dielectric structure includes the first dielectric layer and the second dielectric layer.
[0048] The material of the dielectric structure 204 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.
[0049] In this embodiment, the material of the dielectric structure 204 includes silicon oxide.
[0050] Please refer to Figure 8 and Figure 9 , Figure 8 is a schematic diagram based on Figure 6 and Figure 9 is in Figure 7Schematic diagram based on this, removing the dielectric structure 204 on the isolation region I and the gate structure 202 on the isolation region I, forming an opening 206 in the dielectric structure 204 on the isolation region I, the opening 206 exposing the top surface and sidewall surface of the fin structure 201, and the opening 206 also exposing the top surface of the isolation structure 205.
[0051] The method for removing the dielectric structure 204 on the isolation region I and the gate structure 202 on the isolation region I includes: forming a patterned mask layer (not shown) on the dielectric structure 204, the patterned mask layer exposing the surface of the dielectric structure 204 on the isolation region I; etching the dielectric structure 204 using the patterned mask layer as a mask until the surface of the gate structure 202 on the isolation region I is exposed; continuing to remove the exposed gate structure 202 until the top surface and sidewall surface of the fin structure 201 are exposed, and the top surface of the isolation structure 205 is exposed, and forming an opening 206 in the dielectric structure 204 on the isolation region I.
[0052] The process for etching the dielectric structure 204 includes a dry etching process; the process for removing the exposed gate structure 202 includes a dry etching process.
[0053] Please refer to Figure 10 and Figure 11 , Figure 10 is a schematic diagram based on Figure 8 this, Figure 11 is a schematic diagram based on Figure 9 this, performing ion implantation of a second ion on the fin structure 201 exposed by the opening 206, the conduction type of the second ion being opposite to the conduction type of the first ion, so that the fin structure 201 on the isolation region I is formed into a diffusion prevention layer 207, and the material of the diffusion prevention layer 207 is the intrinsic semiconductor material of the fin structure 201.
[0054] The fin structure 201 has a first ion. After performing ion implantation of a second ion on the fin structure 201 exposed by the opening 206, the conduction type of the second ion is opposite to the conduction type of the first ion, so that the electric charges of the second ion and the first ion can neutralize each other, and the fin structure 201 on the isolation region I is formed into a diffusion prevention layer 207 without conductive performance. Then the material of the diffusion prevention layer 207 is the intrinsic semiconductor material of the fin structure 201, so that the diffusion prevention layer 207 electrically isolates the fin structure 201, without the need to add a process flow for removing the fin structure 201 on the isolation region I, thus simplifying the process flow, having a smaller stress impact on the fin structure 201, making the stress of the semiconductor structure balanced, and improving the stability of the semiconductor structure.
[0055] The second ions include N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions or indium ions.
[0056] Please refer to Figure 12 and Figure 13 , Figure 12 For the schematic diagram based on Figure 10 On the basis of, Figure 13 For the schematic diagram based on Figure 11 On the basis of, a filling layer 208 is formed within the opening 206, the filling layer 208 is located within the dielectric structure 204, and the filling layer 208 covers the top surface and the sidewall surface of the anti-diffusion layer 207.
[0057] The material of the filling layer 208 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride and silicon carbon oxynitride.
[0058] Correspondingly, an embodiment of the present invention further provides a semiconductor structure. Please continue to refer to Figure 12 , including:
[0059] A substrate 200, the substrate 200 includes a device region II and an isolation region I;
[0060] A fin structure 201 located on the device region II, the device region II and the isolation region I are arranged along the extending direction of the fin structure 201, and the fin structure 201 has first ions therein;
[0061] An anti-diffusion layer 207 located on the isolation region I, the material of the anti-diffusion layer 207 is the intrinsic semiconductor material of the fin structure 201, and the anti-diffusion layer 207 is located between adjacent fin structures 201;
[0062] A gate structure 202 spanning the fin structure 201, the gate structure 202 is located on the device region II;
[0063] A dielectric structure 204 located on the substrate 200, the gate structure 202 is located within the dielectric structure 204.
[0064] In this embodiment, the material of the fin structure 201 includes silicon or silicon germanium.
[0065] In this embodiment, the first ions include P-type ions or N-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions or indium ions.
[0066] In this embodiment, it further includes: source-drain doping regions 203 located in the fin structures 201 on both sides of the gate structure 202.
[0067] In this embodiment, it further includes: an isolation structure 205 located on the substrate 200, the isolation structure 205 is located on the sidewalls of the fin structures 201, and the top surface of the isolation structure 205 is lower than the top surface of the fin structures 201, and the gate structure 202 is located on the isolation structure 205.
[0068] In this embodiment, it further includes: a filling layer 208 located on the anti-diffusion layer 207, the filling layer 208 is located in the dielectric structure 204, and the filling layer 208 covers the top surface and the sidewall surface of the anti-diffusion layer 207.
[0069] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate and a fin structure located on the substrate, the substrate including a device region and an isolation region arranged along the extending direction of the fin structure, and a first ion is present in the fin structure; forming a gate structure spanning the fin structure and a dielectric structure located on the substrate, the gate structure being located on the isolation region and the device region, and the gate structure being located within the dielectric structure; removing the dielectric structure on the isolation region and the gate structure on the isolation region, forming an opening in the dielectric structure on the isolation region, the opening exposing the top surface and sidewall surfaces of the fin structure; performing ion implantation of a second ion on the fin structure exposed by the opening, the conduction type of the second ion being opposite to that of the first ion, so that the fin structure on the isolation region is formed into a diffusion barrier layer, and the material of the diffusion barrier layer is the intrinsic semiconductor material of the fin structure.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, the material of the fin structure includes silicon or silicon germanium.
3. The method for forming a semiconductor structure according to claim 1, characterized in that, the first ion includes a P-type ion or an N-type ion; the second ion includes an N-type ion or a P-type ion; the N-type ion includes a phosphorus ion, an arsenic ion or an antimony ion; the P-type ion includes a boron ion, a boron fluoride ion or an indium ion.
4. The method for forming a semiconductor structure according to claim 1, characterized in that, during the process of forming the gate structure and the dielectric structure spanning the fin structure, it further includes: forming source / drain doping regions in the fin structures on both sides of the gate structure.
5. The method for forming a semiconductor structure according to claim 4, characterized in that, the forming methods of the gate structure, the source / drain doping regions and the dielectric structure include: forming a plurality of gate structures spanning the fin structure on the isolation region and the device region, the gate structures being located on the isolation structure, and the plurality of gate structures being perpendicular to the extending direction of the fin structure; forming source / drain doping regions in the fin structures on both sides of the gate structure; forming a dielectric structure on the substrate, the dielectric structure covering the top surface and sidewall surfaces of the fin structure, covering the top surface and sidewall surfaces of the gate structure.
6. The method for forming a semiconductor structure according to claim 4, characterized in that, the forming methods of the gate structure, the source / drain doping regions and the dielectric structure include: forming a plurality of dummy gate structures spanning the fin structure on the isolation region and the device region; forming source / drain doping regions in the fin structures on both sides of the dummy gate structures; forming a first dielectric layer on the substrate, the fin structure and the dummy gate structures being located within the first dielectric layer, and the first dielectric layer exposing the top surface of the dummy gate structures; removing the dummy gate structures, and forming a plurality of gate structures in the first dielectric layer; forming a second dielectric layer on the first dielectric layer and on the gate structures, and the dielectric structure includes the first dielectric layer and the second dielectric layer.
7. The method for forming a semiconductor structure according to claim 1, characterized in that, Before forming a gate structure and a dielectric structure across the fin structure, it further includes: forming an isolation structure on the substrate, the isolation structure being located on the sidewalls of the fin structure, and a top surface of the isolation structure being lower than a top surface of the fin structure, the gate structure being located on the isolation structure, and the opening further exposing the top surface of the isolation structure.
8. The method for forming a semiconductor structure according to claim 1, wherein, it further includes: forming a filling layer in the opening.
9. A semiconductor structure, wherein, it includes: a substrate including a device region and an isolation region; a fin structure located on the device region, the device region and the isolation region being arranged along an extending direction of the fin structure, and a first ion being present in the fin structure; a diffusion barrier layer located on the isolation region, the material of the diffusion barrier layer being an intrinsic semiconductor material of the fin structure, the diffusion barrier layer being located between adjacent fin structures; a gate structure across the fin structure, the gate structure being located on the device region; a dielectric structure located on the substrate, the gate structure being located within the dielectric structure.
10. The semiconductor structure according to claim 9, wherein, the material of the fin structure includes silicon or silicon germanium.
11. The semiconductor structure according to claim 9, wherein, the first ion includes a P-type ion or an N-type ion; the N-type ion includes a phosphorus ion, an arsenic ion or an antimony ion; the P-type ion includes a boron ion, a boron fluoride ion or an indium ion.
12. The semiconductor structure according to claim 9, wherein, it further includes: source / drain doping regions within the fin structures on both sides of the gate structure.
13. The semiconductor structure according to claim 9, wherein, it further includes: an isolation structure located on the substrate, the isolation structure being located on the sidewalls of the fin structure, and a top surface of the isolation structure being lower than a top surface of the fin structure, the gate structure being located on the isolation structure.
14. The semiconductor structure according to claim 9, wherein, it further includes: a filling layer located on the diffusion barrier layer, the filling layer being located within the dielectric structure.