Array substrate and preparation method thereof, display panel and display device

Abstract

The invention provides an array substrate and a preparation method thereof, a display panel and a display device. The array substrate comprises: a substrate; the barrier layer and the thin film transistor are arranged on the substrate, the thin film transistor comprises an active layer and a first gate layer located on the side, close to the substrate, of the active layer, and the first gate layer is located on the side, away from the substrate, of the barrier layer; the dielectric protection layer is arranged on the side, close to the substrate, of the first gate layer in a stacked mode and located on the side, away from the substrate, of the barrier layer, and the orthographic projection of the dielectric protection layer on the substrate covers the orthographic projection of the first gate layer on the substrate. The bottom gate structure of the thin film transistor can be reliably protected, bottom gate partial deletion caused by electrochemical corrosion due to interaction of water vapor and charges at the bottom of the bottom gate is avoided, interference on the thin film transistor is reduced, stable work of the thin film transistor is guaranteed, and then it is guaranteed that the display panel has a good display effect; therefore, the product yield and the product competitiveness are improved.

Description

Technical Field

[0001] The present invention generally relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel and a display device. Background Art

[0002] In the driving circuit of the display panel, the thin film transistor (TFT) is generally located on the flexible substrate PI. For the thin film transistor including the bottom gate, the charge adsorption effect causes the charge to be adsorbed on the interface near the bottom gate and the barrier layer (Barrier). Due to the hygroscopic property of the PI material, water vapor gathers at the interface between the PI and the barrier layer. The interaction between water vapor and electronic charge causes electrochemical corrosion of the bottom gate water vapor, resulting in failure of the thin film transistor and failure of the GOA level transfer, causing abnormal display of the display panel and affecting the quality of the display panel. Summary of the invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide an array substrate and a preparation method thereof, a display panel and a display device, which can reliably protect the bottom gate structure of the thin film transistor, avoid partial loss of the bottom gate caused by electrochemical corrosion due to the interaction between water vapor and charge at the bottom of the bottom gate, thereby reducing interference with the thin film transistor, ensuring stable operation of the thin film transistor, and further ensuring that the display panel has a good display effect, so as to improve the product yield and product competitiveness.

[0004] In a first aspect, the present invention provides an array substrate, comprising:

[0005] substrate;

[0006] A barrier layer and a thin film transistor are arranged on the substrate, wherein the thin film transistor comprises an active layer and a first gate layer located on a side of the active layer close to the substrate, and the first gate layer is located on a side of the barrier layer away from the substrate;

[0007] The dielectric protection layer is stacked and arranged on a side of the first gate layer close to the substrate and on a side of the barrier layer away from the substrate, and the orthographic projection of the dielectric protection layer on the substrate covers the orthographic projection of the first gate layer on the substrate.

[0008] As an optional solution, the orthographic projection of the first gate layer on the substrate is located within the orthographic projection region of the dielectric protection layer on the substrate.

[0009] As an optional solution, the dielectric protection layer is a semiconductor material, preferably, the dielectric protection layer is amorphous silicon.

[0010] As an optional solution, when the thin film transistor is turned off to maintain the driving voltage, a shielding electric field is formed between the interface between the dielectric protection layer and the blocking layer and the interface between the blocking layer and the first gate layer.

[0011] As an alternative, the thin film transistor further includes a second gate layer. A first gate insulating layer is stacked on the side of the active layer facing away from the substrate, and the second gate layer is located on the side of the first gate insulating layer facing away from the substrate.

[0012] As an alternative, the active layer includes one of polysilicon, oxide semiconductor, and a stacked structure of oxide semiconductor and polysilicon.

[0013] As an alternative, the thin film transistor further includes a second gate insulating layer, a first interlayer dielectric layer, a buffer layer, a third gate insulating layer, a source-drain layer, a second interlayer dielectric layer, and a planarization layer, which are stacked on the second gate layer in a direction away from the substrate.

[0014] As an alternative, the source-drain layer is connected to the first gate layer and the second gate layer respectively.

[0015] In a second aspect, the present invention provides a method for manufacturing an array substrate, specifically including:

[0016] Providing a substrate;

[0017] Forming a barrier layer and a dielectric protection layer on the substrate in sequence, and the dielectric protection layer is stacked on the side of the barrier layer facing away from the substrate;

[0018] Forming a thin film transistor, which includes an active layer and a first gate layer located on the side of the active layer close to the substrate. The first gate layer is located on the side of the dielectric protection layer facing away from the substrate, and the orthographic projection of the dielectric protection layer on the substrate covers the orthographic projection of the first gate layer on the substrate.

[0019] In a third aspect, the present invention provides a display panel, including the array substrate of the first aspect.

[0020] In a fourth aspect, the present invention provides a display device, including the array substrate of the first aspect or the display panel of the second aspect.

[0021] In the display panel of the present invention, by providing a dielectric protection layer, the dielectric protection layer is stacked on the side of the first gate layer close to the substrate and is located on the side of the barrier layer facing away from the substrate. The orthographic projection of the dielectric protection layer on the substrate covers the orthographic projection of the first gate layer on the substrate. The dielectric protection layer in the present invention can isolate water vapor, and at the same time, a shielding electric field can be formed between the interface of the dielectric protection layer and the barrier layer and the interface of the dielectric protection layer and the first gate layer, so as to effectively shield the transfer of electronic charges, avoid the partial loss of the first gate due to the interaction between water vapor and charges at the bottom of the first gate layer, thereby reducing the interference to the thin film transistor, ensuring the stable operation of the thin film transistor, and further ensuring that the display panel has a good display effect, so as to improve the product yield and product competitiveness. Description of the Drawings

[0022] Other features, objectives, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings:

[0023] Figure 1 Surface display mirror picture of a thin-film transistor in the prior art;

[0024] Figure 2 is Figure 1 Cross-sectional view taken along line A-A in

[0025] Figure 3 is Figure 1 Cross-sectional view taken along line B-B in

[0026] Figure 4 Schematic diagram showing charge adsorption in a double-gate thin-film transistor in the prior art;

[0027] Figure 5 Schematic diagram showing the absence of bottom-gate electrochemical corrosion in a double-gate thin-film transistor in the prior art;

[0028] Figure 6 OLED abnormal display diagram of a double-gate thin-film transistor in the prior art;

[0029] Figure 7 Schematic structural diagram of an array substrate according to an embodiment of the present application;

[0030] Figure 8 Schematic structural diagram of another array substrate according to an embodiment of the present application;

[0031] Figure 9 Schematic diagram of dielectric protection in an array substrate according to an embodiment of the present application.

[0032] In the figure,

[0033] 100. Array substrate;

[0034] 10. Substrate; 20. Barrier layer; 30. Thin-film transistor, 31. Active layer, 32. First gate layer, 33. Buffer layer, 34. First gate insulating layer, 35. Second gate layer, 36. Second gate insulating layer, 37. First interlayer dielectric layer, 38. Third gate insulating layer, 39. Source-drain layer, 40. Second interlayer dielectric layer, 41. Planarization layer;

[0035] 50. Dielectric protection layer; Detailed implementation manners

[0036] The present application will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention and do not limit the invention. Additionally, it should be noted that for the sake of convenience of description, only the parts related to the invention are shown in the drawings.

[0037] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0038] LTPO (Low Temperature Polycrystalline Oxide) OLED has a relatively long holding time in the low-frequency state for GOA (Gate on Array Substrate). The single-gate TFT structure has a risk of insufficient holding potential at low frequencies due to relatively large leakage current. The double-gate TFT structure can reduce the leakage problem of the single-gate TFT and effectively improve the switching efficiency of the device. As Figures 1-3 shown, the OLED is composed of several organic materials PI (substrate 10), inorganic materials SiN x and SiO x (barrier layer 20), metal film layer BSM (first gate layer 32), active layer 31, Gate (second gate layer 35) and its SD film layer (source-drain layer 39); Figure 3 In the double-gate structure of Gate1 and BSM, they are connected through SD and maintain the same potential during the operation of the TFT, improving the working efficiency of the TFT, that is, reducing the leakage current of the TFT and enhancing the switching effect of the TFT. As Figure 4 shown, when the TFT is turned off to maintain the GOA voltage, both Gate1 (second gate layer 35) and BSM (first gate layer 32) are at positive potentials. Due to the charge adsorption effect, electrons are adsorbed at the interface near the bottom barrier layer 20 (Barrier2) of the BSM. The PI organic material at the bottom of the BSM has a moisture absorption effect, and water vapor accumulates at the interface between the PI at the bottom of the BSM and Barrier2. The interaction between water vapor and electron charges leads to the loss of BSM due to water vapor electrochemical corrosion (as Figure 5 shown), that is, the metal undergoes an oxidation reaction (M → Mn + + ne - ), and the electrochemical corrosion of BSM (M → Mn + + ne - ) causes abnormalities in the Multi-Buffer film layer (buffer layer) of the TFT device, resulting in the failure of the TFT device and thus the failure of the GOA level transmission, forming an abnormal display of the OLED (as Figure 6 ). This problem seriously affects the product reliability and the product development progress. There are major potential risks at the product terminal, affecting the product competitiveness.

[0039] Based on the above problems, as Figures 7-9 shown, the embodiment of the present application provides an array substrate 100, including:

[0040] Substrate 10;

[0041] A barrier layer 20 and a thin film transistor 30 are disposed on a substrate 10. The thin film transistor 30 includes an active layer 31 and a first gate layer 32 located on a side of the active layer 31 close to the substrate 10. The first gate layer 32 is located on a side of the barrier layer 20 away from the substrate 10.

[0042] A dielectric protection layer 50 is stacked on a side of the first gate layer 32 close to the substrate 10 and is located on a side of the barrier layer 20 away from the substrate 10. A positive projection of the dielectric protection layer 50 on the substrate 10 covers a positive projection of the first gate layer 32 on the substrate 10.

[0043] It can be understood that the substrate 10 may include a flexible material or a rigid material. Exemplarily, when the display panel has requirements for foldability or bendability, the substrate 10 may be made of a flexible material, such as but not limited to PET (Polyethyleneterephthalate), PEN (Polyethylene naphthalatetwoformic acid glycol ester), or PI (Polyimide), etc.; when the display panel has rigid requirements, the substrate 10 may be made of a rigid material, such as but not limited to glass or PMMA (Polymethyl methacrylate), etc.

[0044] Among them, the barrier layer 20 is disposed on the substrate 10, and the barrier layer 20 may be but not limited to SiO x ;

[0045] The thin film transistor 30 may be but not limited to an oxide thin film transistor 30 (Oxide TFT), a low temperature polysilicon thin film transistor 30 (LTPS TFT), or a low temperature polysilicon oxide thin film transistor 30 (LTPO TFT); the thin film transistor 30 in the embodiments of the present application may be a bottom gate structure. Exemplarily, the thin film transistor 30 may sequentially include a gate layer, a gate insulating layer, an active layer, an interlayer dielectric layer, a source electrode, and a drain electrode, etc.; of course, the thin film transistor 30 may also be a double gate structure. Exemplarily, the thin film transistor 30 may include a bottom gate layer, a bottom gate insulating layer, an active layer, a top gate insulating layer, a top gate layer, an interlayer dielectric layer, a source electrode, and a drain electrode, etc. arranged in sequence.

[0046] It can also be understood that for a thin-film transistor with a bottom-gate structure, since the barrier layer 20 close to the substrate 10 usually has a relatively thin thickness, and due to the moisture-absorbing property of the organic material of the substrate 10, the bottom gate in the thin-film transistor with the bottom-gate structure is more likely to undergo electrochemical corrosion due to the interaction between water vapor and electronic charges, resulting in partial loss of the bottom gate. Therefore, in the embodiments of the present application, a dielectric protection layer 50 is provided. The dielectric protection layer 50 is disposed on the side of the first gate layer 32 (bottom gate layer) close to the substrate 10. On the one hand, the dielectric protection layer 50 can act as the barrier layer 20, increasing the thickness to further block water and oxygen, and at the same time having a good insulation effect. On the other hand, after the thin-film transistor 30 is turned off and the driving voltage is maintained, due to charge migration, opposite charges are respectively accumulated at the interface between the first gate layer 32 and the dielectric protection layer 50 and at the interface between the dielectric protection layer 50 and the barrier layer 20, forming a dielectric protection layer 50 which is beneficial to forming a shielding electric field, and can effectively shield the migration of electronic charges, thereby avoiding the electrochemical corrosion reaction of the first gate layer 32.

[0047] Among them, the dielectric protection layer 50 can be made of semiconductor materials, such as but not limited to silicon, silicon oxide, etc.; the orthographic projection of the dielectric protection layer 50 on the substrate 10 covers the orthographic projection of the first gate layer 32 on the substrate 10. Specifically, the orthographic projection of the dielectric protection layer 50 on the substrate 10 can completely coincide with the orthographic projection of the first gate layer 32 on the substrate 10, or the orthographic projection of the first gate layer 32 on the substrate 10 is located within the orthographic projection area of the dielectric protection layer 50 on the substrate 10, that is, the orthographic projection of the dielectric protection layer 50 is greater than or equal to the orthographic projection of the first gate layer 32, indicating that in the direction parallel to the substrate 10, the size of the dielectric protection layer 50 is greater than or equal to the size of the first gate layer 32. In this way, the first gate layer 32 can be reliably protected, water vapor can be isolated, and the transfer of electronic charges can be shielded, thereby preventing the problem of partial loss of the first gate layer 32 caused by electrochemical corrosion.

[0048] The array substrate of the embodiments of the present application solves the problem that in the existing array substrate with a bottom-gate structure, the bottom gate of the thin-film transistor 30 is prone to electrochemical corrosion, resulting in partial loss, thereby affecting the stability of the thin-film transistor 30. The array substrate of the embodiments of the present application, by providing the dielectric protection layer 50, the dielectric protection layer 50 can isolate water vapor, and at the same time, a shielding electric field can be formed between the interface of the dielectric protection layer 50 and the barrier layer 20 and the interface of the dielectric protection layer 50 and the first gate layer 32, thereby effectively shielding the transfer of electronic charges, avoiding partial loss of the first gate layer 32 caused by the interaction between water vapor and charges at the bottom of the first gate layer 32, thereby reducing the interference to the thin-film transistor 30, ensuring the stable operation of the thin-film transistor 30, and further ensuring that the display panel has a good display effect, so as to improve the product yield and product competitiveness.

[0049] In a preferred embodiment, the orthographic projection of the first gate layer 32 on the substrate 10 is located within the orthographic projection area of the dielectric protection layer 50 on the substrate 10. In this embodiment, the size of the dielectric protection layer 50 in the direction parallel to the substrate 10 is larger than that of the first gate layer 32, which is beneficial to reliably protect the first gate layer 32 and prevent the first gate layer 32 from undergoing electrochemical corrosion.

[0050] In a preferred embodiment, the dielectric protection layer 50 is a semiconductor material. Preferably, the dielectric protection layer 50 is amorphous silicon.

[0051] In this embodiment, the dielectric protection layer 50 is a semiconductor material. After being energized, the dielectric protection layer 50 has the properties of a conductor, and after being powered off, it has the properties of an insulating layer. While reliably protecting the first gate layer 32, it protects the normal function of the first gate layer 32.

[0052] As an implementable manner, when the thin-film transistor 30 turns off and maintains the driving voltage, a shielding electric field is formed between the interface of the dielectric protection layer 50 and the barrier layer 20 and the interface of the barrier layer 20 and the first gate layer 32.

[0053] In this embodiment, since the first gate layer 32 has a positive potential after the thin-film transistor 30 turns off and maintains the driving voltage, according to the principle of charge adsorption, negative charges accumulate at the interface between the first gate layer 32 and the dielectric protection layer 50, and positive charges are adsorbed at the interface between the dielectric protection layer 50 and the barrier layer 20. Therefore, the dielectric protection layer 50 can form a shielding electric field, which can effectively shield the migration of electron charges, thereby preventing the first gate layer 32 from undergoing an electrochemical corrosion reaction.

[0054] As an implementable manner, the thin-film transistor 30 further includes a second gate layer 35. A first gate insulating layer 34 is laminated on the side of the active layer 31 facing away from the substrate 10, and the second gate layer 35 is located on the side of the first gate insulating layer 34 facing away from the substrate 10.

[0055] In this embodiment, the second gate layer 35 is located on the side of the active layer 31 facing away from the substrate 10. The second gate layer 35 serves as the top gate, and the first gate layer 32 serves as the bottom gate. The first gate layer 32 and the second gate layer 35 serve as the dual gates of the thin-film transistor 30. The structure of the dual-gate thin-film transistor 30 is beneficial to reducing the leakage current, improving the stability and reliability of the device. The switching speed of the dual-gate thin-film transistor 30 is relatively fast, and it can achieve a higher operating frequency, making it suitable for fields such as high-speed circuits and display technologies, thereby effectively improving the operating efficiency and applicable fields of the thin-film transistor 30.

[0056] In some embodiments, the active layer 31 includes one of polysilicon, an oxide semiconductor, and a stacked oxide semiconductor and polysilicon.

[0057] Among them, the oxide semiconductor can be, but is not limited to, indium tin oxide (ITO), indium gallium zinc oxide (IGZO), etc.

[0058] In some embodiments, the thin film transistor 30 further includes a second gate insulating layer 36, a first interlayer dielectric layer 37, a buffer layer 33, a third gate insulating layer 38, a source-drain layer 39, a second interlayer dielectric layer 40, and a planarization layer 41 that are stacked on the second gate layer 35 along a direction away from the substrate 10.

[0059] Among them, the second gate insulating layer 36, the first interlayer dielectric layer 37, the buffer layer 33, the third gate insulating layer 38, and the second interlayer dielectric layer 40 can each be, but are not limited to, SiO x , SiN x , silicon oxynitride, etc.; the source-drain layer 39 is a metal film layer, and the planarization layer 41 can be an organic material layer, such as, but not limited to, PI.

[0060] It can be understood that the interlayer dielectric layer has good isolation and insulation effects; the buffer layer 33 can be used to prevent metal ions from diffusing into the active layer 31, preventing effects on characteristics such as threshold voltage and leakage current, and a suitable buffer layer 33 can improve the quality of the interface of the active layer 31 and prevent leakage current from occurring at the interface of the active layer 31.

[0061] In some embodiments, the first gate insulating layer 34, the second gate insulating layer 36, and the third gate insulating layer 38 can also be organic materials with a relatively low dielectric constant, such as PI.

[0062] In some embodiments, the source-drain layer 39 is respectively connected to the first gate layer 32 and the second gate layer 35.

[0063] In this embodiment, when the thin film transistor 30 is operating, the first gate layer 32 and the second gate layer 35 maintain the same potential, which is beneficial to reducing the leakage current of the thin film transistor 30 and improving the switching effect of the thin film transistor 30, thereby improving the operating efficiency of the thin film transistor 30.

[0064] In summary, for the array substrate according to the embodiments of the present application, by providing the dielectric protection layer 50, the dielectric protection layer 50 is stacked on the side of the first gate layer 32 close to the substrate 10 and located on the side of the barrier layer 20 facing away from the substrate 10, and the orthographic projection of the dielectric protection layer 50 on the substrate 10 covers the orthographic projection of the first gate layer 32 on the substrate 10. The dielectric protection layer 50 in the present invention can isolate water vapor, and at the same time, a shielding electric field can be formed between the interface of the dielectric protection layer 50 and the barrier layer 20 and the interface of the dielectric protection layer 50 and the first gate layer 32, so as to effectively shield the electron charge transfer, avoid the electrochemical corrosion caused by the interaction between the water vapor and the charge at the bottom of the first gate layer 32, resulting in the missing part of the first gate, thereby reducing the interference to the thin film transistor 30, ensuring the stable operation of the thin film transistor 30, and further ensuring that the display panel has a good display effect, so as to improve the product yield and product competitiveness;

[0065] Moreover, a shielding electric field is formed between the interface of the dielectric protection layer 50 and the first gate layer 32 and the interface of the dielectric protection layer 50 and the barrier layer 20, which can effectively shield the electron charge transfer, and further avoid the electrochemical corrosion of the first gate layer 32.

[0066] In a second aspect, the embodiments of the present application provide a method for manufacturing an array substrate, which specifically includes:

[0067] Step S10: Provide the substrate 10;

[0068] Step S20: Sequentially form the barrier layer 20 and the dielectric protection layer 50 on the substrate 10, and the dielectric protection layer 50 is stacked on the side of the barrier layer 20 facing away from the substrate 10;

[0069] Among them, the barrier layer 20 can be, but is not limited to, a silicon oxide layer, and can be formed by chemical vapor deposition; the dielectric protection layer 50 can be, but is not limited to, a semiconductor layer, specifically an amorphous silicon layer, a silicon oxide layer, etc., and can be formed by chemical vapor deposition or the like. The embodiments of the present application do not make specific limitations on this.

[0070] Step S30: Form the thin film transistor 30. The thin film transistor 30 includes an active layer 31 and a first gate layer 32 located on the side of the active layer 31 close to the substrate 10. The first gate layer 32 is located on the side of the dielectric protection layer 50 facing away from the substrate 10, and the orthographic projection of the dielectric protection layer 50 on the substrate 10 covers the orthographic projection of the first gate layer 32 on the substrate 10.

[0071] Among them, forming the thin film transistor 30 includes forming the thin film transistor 30 on the side of the dielectric protection layer 50 facing away from the substrate 10, specifically including: sequentially forming a first gate layer 32, an insulating layer, and an active layer 31 on the side of the dielectric protection layer 50 facing away from the substrate 10; among them, the insulating layer can adopt a multi-layer stacked structure, for example, but not limited to, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked along the direction away from the substrate 10.

[0072] In the method for manufacturing an array substrate according to an embodiment of the present application, by forming a dielectric protection layer 50 on the side of the barrier layer 20 facing away from the substrate 10, the operation is simple and easy to implement. At the same time, the prepared dielectric protection layer 50 can isolate water vapor, and a shielding electric field can be formed between the interface of the dielectric protection layer 50 and the barrier layer 20 and the interface of the dielectric protection layer 50 and the first gate layer 32, thereby effectively shielding the transfer of electronic charges, avoiding partial loss of the first gate layer 32 caused by the interaction between water vapor and charges at the bottom of the first gate layer 32, reducing interference with the thin film transistor 30, ensuring the stable operation of the thin film transistor 30, and further ensuring that the display panel has a good display effect, so as to improve the product yield and product competitiveness.

[0073] In a third aspect, an embodiment of the present application provides a display panel, including the array substrate 100 of the first aspect. It can be understood that the display panel has all the features and advantages of the above-mentioned array substrate 100, which will not be elaborated here. In short, the display panel has a good display effect, and the display panel has a high product yield and product competitiveness.

[0074] It can also be understood that the display panel further includes an anode layer provided on the side of the planarization layer of the array substrate 100 facing away from the substrate. A pixel definition layer is provided on the side of the anode layer facing away from the substrate. The pixel definition layer defines pixel opening areas arranged in an array. A light-emitting layer is provided in the pixel opening areas. A cathode layer is provided on the side of the light-emitting layer facing away from the substrate. A packaging layer is provided on the side of the cathode layer facing away from the substrate. A color filter layer, a touch layer, a cover plate, etc. are provided on the side of the packaging layer facing away from the substrate.

[0075] Among them, the array substrate includes a plurality of pixel driving circuits distributed in an array. The pixel driving circuit can include a plurality of electronic components such as thin film transistors and capacitors. For example, each pixel driving circuit can include three thin film transistors and one capacitor, constituting 3T1C (that is, one driving transistor, two switching transistors, and one capacitor). It can also include more than three transistors and at least one capacitor, such as 4T1C (that is, one driving transistor, three switching transistors, and one capacitor), 5T1C (that is, one driving transistor, four switching transistors, and one capacitor), or 7T1C (that is, one driving transistor, six switching transistors, and one capacitor), etc.

[0076] Among them, the anode layer, pixel definition layer, light-emitting layer, cathode layer, and encapsulation layer can form a display layer. The pixel definition layer has a plurality of pixel openings, and one pixel opening defines the position of a light-emitting device. For example, the light-emitting device can be an OLED light-emitting device or a QLED light-emitting device, etc. Taking the OLED light-emitting device as an example, in the direction away from the substrate, the light-emitting device can include an anode layer, a light-emitting layer, and a cathode layer that are sequentially stacked. Of course, the light-emitting device can also include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer disposed between the anode layer and the light-emitting layer, and at least one of an electron injection layer, an electron transport layer, and a hole blocking layer disposed between the cathode layer and the light-emitting layer; in some embodiments, the structure of the anode layer can be a composite structure formed by sequentially stacking a transparent conductive oxide thin film / metal thin film / transparent conductive oxide thin film. Among them, the material of the above transparent conductive oxide thin film is, for example, any one of ITO (Indium tin oxide) and IZO (Indium zinc oxide), and the material of the above metal thin film is, for example, any one of gold (Au), silver (Ag), nickel (Ni), and platinum (Pt). Also, for example, the structure of the anode layer can also be a single-layer structure, and the material of the single-layer structure can be any one of ITO, IZO, Au, Ag, Ni, Pt. Each pixel opening exposes a part of the anode of the corresponding light-emitting device, and at least a part of the light-emitting layer is located within the corresponding pixel opening and forms an electrical connection with the corresponding anode layer. For example, the cathode layers of the light-emitting layers can be electrically connected to each other and form an integral structure. For example, the material of the cathode can be any one of aluminum (Al), silver (Ag), and magnesium (Mg), or any one of a magnesium-silver alloy and an aluminum-lithium alloy.

[0077] The encapsulation layer is disposed on the side of the cathode layer away from the substrate to protect the light-emitting layer. The encapsulation layer can include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. For example, the first inorganic encapsulation layer and the second inorganic encapsulation layer can be made of an inorganic material such as a nitride, an oxide, a nitride oxide, a nitrate, a carbide, or any combination thereof, and the preparation process can use a Chemical Vapor Deposition (CVD) process, such as a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. For example, the organic insulating layer can be made of materials such as acrylic fiber, hexamethyldisiloxane, polyacrylate, polycarbonate, polystyrene, etc., and the preparation process can use an Ink Jet Printing (IJP) process.

[0078] In some embodiments, the color filter layer may include a first color filter unit, a second color filter unit, and a third color filter unit. The first color filter unit, the second color filter unit, and the third color filter unit are color filter units of different colors. The first color filter unit, the second color filter unit, and the third color filter unit may have different thicknesses or the same thickness, or two of them may have the same thickness and the other may have a different thickness;

[0079] In some other embodiments, the adjacent color filter units of the color filter layer do not overlap with each other, and the color filter layer further includes a black matrix disposed between the adjacent color filter units to absorb ambient light, reduce the ambient light reflection of the display panel, and achieve a dark state when the screen is turned off. Of course, in other embodiments, there may be a first overlapping area between the first color filter unit and the second color filter unit, a second overlapping area between the second color filter unit and the third color filter unit, and a third overlapping area between the third color filter unit and the first color filter unit. When two color filter units of different colors overlap, the light transmittance of the overlapping area is relatively low, so it can be used as a black matrix. In this way, the first overlapping area, the second overlapping area, and the third overlapping area of the display panel can all be used as black matrices to achieve a light-shielding effect, and there is no need to additionally provide a black matrix.

[0080] The touch control layer is used to implement the touch control function. The touch control layer may be disposed between the encapsulation layer and the color filter layer to implement an in-screen touch control structure, which is beneficial to reducing the thickness of the display panel. Of course, in other embodiments, the touch control layer may also be disposed at other positions of the display panel, and the embodiments of the present application do not limit this.

[0081] The cover plate is mainly used to protect the entire display panel. The cover plate may be, but is not limited to, glass, transparent resin material, PET, etc., as long as it has good light transmittance. The embodiments of the present application do not make specific limitations on this.

[0082] Taking glass as an example, when applied to a curved display product, at least one side of the cover plate is bent, and the layers of the display module are adhered through a 3D adhesion process.

[0083] Fourthly, the present invention provides a display device, including the display panel of the third aspect. It can be understood that the display device has all the features and advantages of the above display panel, and will not be elaborated here. In short, the display device has high quality and yield rate, and high display resolution.

[0084] The display device is a product with an image display function. For example, the display device can be any one of the following: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a portable video camera, a viewfinder, a navigator, a vehicle, a large-area wall, a household appliance, an information query device (such as a business query device in departments such as e-government, banks, hospitals, and power), a monitor, etc. The display device can also be a microdisplay or a product containing a microdisplay. The product containing a microdisplay can be any one of a smart watch, a smart bracelet, a head-mounted display, a stereoscopic display mirror, and an AR device (such as AR glasses), a VR device (such as VR glasses), etc. For example, the microdisplay can be a display with a display size ranging from about 0.2 inches to about 2.5 inches, but is not limited thereto. It can be understood that the microdisplay can also be a display with a smaller display size, such as a display size less than or equal to 0.2 inches.

[0085] It should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. in the above description is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the panel or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more.

[0086] The above description is only a preferred embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A barrier layer and a thin film transistor disposed on the substrate, wherein the thin film transistor comprises an active layer and a first gate layer located on a side of the active layer close to the substrate, and the first gate layer is located on a side of the barrier layer away from the substrate; A dielectric protection layer is stacked and arranged on a side of the first gate layer close to the substrate and on a side of the barrier layer away from the substrate, and an orthographic projection of the dielectric protection layer on the substrate covers an orthographic projection of the first gate layer on the substrate.

2. The array substrate according to claim 1, characterized in that: The orthographic projection of the first gate layer on the substrate is located within the orthographic projection region of the dielectric protection layer on the substrate.

3. The array substrate according to claim 1, characterized in that: The dielectric protection layer is made of semiconductor material, and preferably, the dielectric protection layer is made of amorphous silicon.

4. The array substrate according to claim 1, characterized in that: When the thin film transistor is turned off to maintain the driving voltage, a shielding electric field is formed between the interface between the dielectric protection layer and the blocking layer and the interface between the blocking layer and the first gate layer.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The thin film transistor further includes a second gate layer. A first gate insulating layer is stacked on a side of the active layer facing away from the substrate. The second gate layer is located on a side of the first gate insulating layer facing away from the substrate.

6. The array substrate according to claim 5, characterized in that: The active layer includes one of polycrystalline silicon, oxide semiconductor, and a stacked oxide semiconductor and polycrystalline silicon.

7. The array substrate according to claim 5, characterized in that: The thin film transistor further includes a second gate insulating layer, a first interlayer dielectric layer, a buffer layer, a third gate insulating layer, a source-drain electrode layer, a second interlayer dielectric layer and a planar layer stacked on the second gate layer in a direction away from the substrate.

8. The array substrate according to claim 5, characterized in that: The source and drain layers are connected to the first gate layer and the second gate layer respectively.

9. A method for preparing an array substrate according to any one of claims 1 to 8, characterized in that: Specifically include: providing the substrate; The barrier layer and the dielectric protection layer are sequentially formed on the substrate, wherein the dielectric protection layer is stacked and arranged on a side of the barrier layer away from the substrate; The thin film transistor is formed, and the thin film transistor includes the active layer and a first gate layer located on a side of the active layer close to the substrate, the first gate layer is located on a side of the dielectric protection layer away from the substrate, and the orthographic projection of the dielectric protection layer on the substrate covers the orthographic projection of the first gate layer on the substrate.

10. A display panel, characterized in that The invention comprises the array substrate according to any one of claims 1 to 8.

11. A display device, characterized in that It comprises the array substrate according to any one of claims 1 to 8 or the display panel according to claim 10.

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