Semiconductor structure and preparation process thereof, and light-emitting array and preparation process thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a preparation process thereof, and a light-emitting array and a preparation process thereof, a plurality of grooves and bulges are arranged on a substrate, the grooves are used for accommodating at least part of layers of light-emitting units, the side walls of the bulges are used for at least covering the side walls of light-emitting layers in the light-emitting units, and when the light-emitting units epitaxially grow in the grooves, the side walls of the light-emitting layers in the light-emitting units are separated from each other. The side wall of the light-emitting unit can form a stable structure with the side wall of the bulge or other structural layers on the side wall of the bulge, so that the damage or defects of the light-emitting layer can be reduced, a non-radiative recombination center and a current leakage path are further reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor optoelectronic devices, and particularly to a semiconductor structure and its manufacturing process, a light-emitting array and its manufacturing process. Background Art

[0002] Micro-sized light-emitting diodes (Micro-LEDs) are regarded as the next-generation display devices due to their advantages such as high responsiveness, high brightness, high contrast, ultra-high resolution, and low power consumption, and have been rapidly developed in recent years.

[0003] In the existing Micro-LEDs, mesa etching technology is required during both pixelation and electrode preparation processes, resulting in damage to the sidewalls of Micro-LEDs and affecting device performance.

[0004] Therefore, how to reduce the sidewall damage of Micro-LEDs has become an urgent problem to be solved. Summary of the Invention

[0005] The present invention provides a semiconductor structure and its manufacturing process, a light-emitting array and its manufacturing process to solve the problem of reducing the sidewall damage of Micro-LEDs and improving device performance.

[0006] According to one aspect of the present invention, a semiconductor structure is provided, including:

[0007] A substrate;

[0008] A plurality of grooves and protrusions, the grooves are located on the substrate, the protrusions are located between adjacent grooves, and the top surface of the protrusion and the bottom surface of the groove are connected by the sidewall of the protrusion; the grooves are used to accommodate at least part of the layers of the light-emitting unit, and the light-emitting unit includes a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer stacked; the sidewall of the protrusion is used to at least cover the sidewall of the light-emitting layer;

[0009] A growth limiting layer, located on the top surface of the protrusion, and the growth limiting layer is used to limit the growth of the light-emitting unit in the groove.

[0010] According to another aspect of the present invention, a light-emitting array is provided, including:

[0011] A light-emitting unit layer, the light-emitting unit layer includes light-emitting units arranged in an array, and the light-emitting unit includes a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer stacked in sequence;

[0012] A graphic structure layer, the graphic structure layer includes protrusions and a plurality of grooves, the protrusions are located between adjacent grooves, at least part of the layers of the light-emitting unit are located in the grooves, and the sidewall of the protrusion at least covers the sidewall of the light-emitting layer of the light-emitting unit.

[0013] According to another aspect of the present invention, another light-emitting array is provided, including:

[0014] A graphic structure layer, the graphic structure layer includes a protrusion and a plurality of grooves, and the protrusion is located between adjacent grooves;

[0015] A plurality of light-emitting units, at least part of the layers of the light-emitting units are located in the grooves, and the light-emitting units include a first type semiconductor layer, a light-emitting layer, and a second type semiconductor layer stacked in sequence;

[0016] The passivation layer is at least located on the side wall of the protrusion and at least covers the side wall of the light-emitting layer.

[0017] According to another aspect of the present invention, there is provided another light emitting array, comprising:

[0018] A light-emitting unit layer, the light-emitting unit layer includes light-emitting units arranged in an array, and the light-emitting units include a first type semiconductor layer, a light-emitting layer, and a second type semiconductor layer stacked in sequence;

[0019] A graphic structure layer, wherein the graphic structure layer comprises a plurality of defining units, adjacent defining units are spaced apart from each other, the defining units are formed with grooves, at least a portion of the light-emitting unit is located in the grooves, and the sidewalls of the defining units at least cover the sidewalls of the light-emitting layer of the light-emitting unit;

[0020] A connecting layer, located on a side of the first type semiconductor layer away from the light emitting layer;

[0021] A common first electrode and a plurality of discrete second electrodes, the common first electrode and the first type semiconductor layer are located on the same side of the connecting layer, the common first electrode is arranged between the limiting units, and the common first electrode is electrically connected to the first type semiconductor layer through the connecting layer; the second electrode is located on the side of the second type semiconductor layer away from the light emitting layer and is electrically connected to the second type semiconductor layer.

[0022] According to another aspect of the present invention, there is provided a process for preparing a semiconductor structure, comprising:

[0023] forming a substrate, the substrate comprising a substrate and a transition layer located on the substrate;

[0024] forming a pattern layer, wherein the pattern layer is located on a side of the transition layer away from the substrate; the pattern layer is a single crystal layer;

[0025] forming a growth restriction layer, wherein the growth restriction layer is located on a side of the pattern layer facing away from the substrate;

[0026] The growth restriction layer and the pattern layer are etched to form a groove, and the transition layer is exposed at the bottom of the groove.

[0027] According to another aspect of the present invention, another process for preparing a semiconductor structure is provided, comprising:

[0028] providing a substrate;

[0029] A groove is formed on a substrate, and a protrusion is included between adjacent grooves;

[0030] A passivation layer is formed, and the passivation layer is at least located on the sidewall of the protrusion; the passivation layer is a single crystal layer;

[0031] A growth limiting layer is formed on the side of the protrusion facing away from the substrate.

[0032] Optionally, the passivation layer is at least located on the sidewall of the protrusion and the bottom surface of the groove.

[0033] According to another aspect of the present invention, a preparation process of a light emitting array is provided, which includes first forming a protrusion or a passivation layer for at least covering the sidewall of the light emitting layer of the light emitting unit, and then forming the light emitting unit, and the light emitting unit includes a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer stacked in sequence.

[0034] The technical solution of the embodiment of the present invention, by providing a plurality of grooves and protrusions on the substrate, the grooves are used to accommodate at least part of the layers of the light emitting unit, and the sidewalls of the protrusions are used to at least cover the sidewalls of the light emitting layer in the light emitting unit. When the light emitting unit grows epitaxially in the groove, the sidewalls of the light emitting unit can form a stable structure with the sidewalls of the protrusions or other structural layers on the sidewalls of the protrusions, which helps to reduce the damage or defects of the light emitting layer, and further reduces the non-radiative recombination centers and current leakage paths, and improves the device performance.

[0035] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0037] Figure 1 is a top view of a partial area of a semiconductor structure provided by an embodiment of the present invention;

[0038] Figure 2 is a cross-sectional view of a partial area of a semiconductor structure provided by an embodiment of the present invention;

[0039] Figure 3 is another cross-sectional view of a partial area of a semiconductor structure provided by an embodiment of the present invention;

[0040] Figure 4It is a cross-sectional view of a partial area of another semiconductor structure provided by an embodiment of the present invention;

[0041] Figure 5 It is a cross-sectional view of a partial area of another semiconductor structure provided by an embodiment of the present invention;

[0042] Figure 6 It is a cross-sectional view of a partial area of another semiconductor structure provided by an embodiment of the present invention;

[0043] Figure 7 It is a cross-sectional view of a partial area of another semiconductor structure provided by an embodiment of the present invention;

[0044] Figure 8 It is a schematic structural diagram of a light-emitting array provided by an embodiment of the present invention;

[0045] Figure 9 It is a schematic structural diagram of another light-emitting array provided by an embodiment of the present invention;

[0046] Figure 10 It is a schematic structural diagram of another light-emitting array provided by an embodiment of the present invention;

[0047] Figure 11 It is a schematic structural diagram of another light-emitting array provided by an embodiment of the present invention;

[0048] Figure 12 It is a schematic structural diagram of another light-emitting array provided by an embodiment of the present invention;

[0049] Figure 13 It is a top view of a light-emitting array provided by an embodiment of the present invention;

[0050] Figure 14 It is a structural diagram after each step is completed in the preparation process flow of a semiconductor structure provided by an embodiment of the present invention;

[0051] Figure 15 It is a structural diagram after each step is completed in the preparation process flow of another semiconductor structure provided by an embodiment of the present invention;

[0052] Figure 16 It is a process flow chart for preparing a light-emitting array provided by an embodiment of the present invention;

[0053] Figure 17 It is a process flow chart for preparing another light-emitting array provided by an embodiment of the present invention. Detailed implementation manners

[0054] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solution in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0055] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0056] Figure 1 is a top view of a partial area of a semiconductor structure provided by an embodiment of the present invention, Figure 2 is a cross-sectional view of a partial area of a semiconductor structure provided by an embodiment of the present invention. Referring to Figure 1 and Figure 2 , the semiconductor structure includes: a substrate 10; a plurality of grooves 20 and protrusions 30, the grooves 20 are located on the substrate 10, the protrusions 30 are located between adjacent grooves 20, and the top surface 32 of the protrusion 30 and the bottom surface 21 of the groove 20 are connected through the side wall 31 of the protrusion 30; the groove 20 is used to accommodate at least part of the layers of the light-emitting unit, and the light-emitting unit includes a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer stacked; the side wall 31 of the protrusion 30 is used to at least cover the side wall of the light-emitting layer; a growth confinement layer 40, located on the top surface 32 of the protrusion 30, and the growth confinement layer 40 is used to confine the growth of the light-emitting unit in the groove 20.

[0057] Among them, the substrate 10 includes a substrate. In some alternative embodiments, the substrate 10 further includes other structural layers on the substrate. The groove 20 is located on the substrate 10. In some embodiments, the groove 20 can be formed by patterning the surface of the substrate 10, that is, the surface of the substrate 10 includes the groove 20 and the protrusion 30. In other embodiments, other structural layers can be formed on the substrate 10, and then the other structural layers are patterned to form the groove 20 and the protrusion 30. That is, the groove 20 and the protrusion 30 can be structures of the substrate 10 itself or structures of other structural layers outside the substrate 10.

[0058] The groove 20 of the semiconductor structure is used to accommodate the light-emitting unit. For example, at least part of the layers of the light-emitting unit can be formed in the groove 20 by epitaxial growth. In some embodiments, the light-emitting layer and the second-type semiconductor layer of the light-emitting unit are located in the groove 20, and the first-type semiconductor layer is located outside the groove 20. In other embodiments, part of the first-type semiconductor layer, the light-emitting layer and the second-type semiconductor layer of the light-emitting unit are located in the groove 20. In other embodiments, the first-type semiconductor layer, the light-emitting layer and the second-type semiconductor layer of the light-emitting unit are all located in the groove 20. In some embodiments, the semiconductor structure may include the light-emitting unit or part of the layers of the light-emitting unit. During the preparation process of the semiconductor structure, first, the structure of the groove 20 and the protrusion 30 is formed on the substrate 10, and then the light-emitting unit or part of the layers of the light-emitting unit is grown in the groove 20. For example, the first-type semiconductor layer, the light-emitting layer and the second-type semiconductor layer are sequentially grown in the groove 20 to form the light-emitting unit. Among them, the first-type semiconductor layer is an N-type semiconductor layer, and the second-type semiconductor layer is a P-type semiconductor layer; or the first-type semiconductor layer is a P-type semiconductor layer, and the second-type semiconductor layer is an N-type semiconductor layer. The light-emitting layer can be a quantum well layer, optionally a multi-quantum well layer, such as an InGaN / GaN multi-quantum well layer. In this embodiment, the top surface 32 of the protrusion 30 includes a growth limiting layer 40. The growth limiting layer 40 serves as a mask layer for growing the light-emitting unit. The growth limiting layer 40 is different from the material of the protrusion 30. The growth limiting layer 40 can be used to limit the growth of the light-emitting unit in the groove 20 and prevent the light-emitting unit from growing on the top surface 32 of the protrusion 30, so that the light-emitting unit is restricted in the groove 20.

[0059] In the related art, since the light-emitting layer needs to be etched, or the sidewall of the light-emitting layer is exposed, or the sidewall of the light-emitting layer is covered by other inappropriate materials, damage or defects are likely to occur on the sidewall of the light-emitting layer. The damage or defects on the sidewall of the light-emitting layer provide non-radiative recombination centers and current leakage paths, thus seriously deteriorating the device performance. In this embodiment, by forming a light-emitting unit in the groove 20 of the semiconductor structure, there is no need to etch the light-emitting layer. The sidewall 31 of the protrusion 30 covers at least the sidewall of the light-emitting layer in the light-emitting unit, that is, in the horizontal direction, the positive projection of the protrusion 30 on the sidewall of the light-emitting unit covers at least the sidewall of the light-emitting layer, where the horizontal direction is perpendicular to the thickness direction of the semiconductor structure. In some alternative embodiments, the sidewall 31 of the protrusion 30 covers the sidewall of the light-emitting unit. In some embodiments, the sidewall 31 of the protrusion 30 contacts the sidewall of the light-emitting layer in the light-emitting unit. In other embodiments, other structural layers may be included between the sidewall 31 of the protrusion 30 and the sidewall of the light-emitting unit. In this case, other structural layers (such as a passivation layer) on the sidewall 31 of the protrusion 30 contact the sidewall of the light-emitting layer in the light-emitting unit. In this embodiment, by arranging the light-emitting unit in the groove 20 and the sidewall 31 of the protrusion 30 covering at least the sidewall of the light-emitting layer, the sidewall of the light-emitting layer can be protected. When the light-emitting unit grows epitaxially in the groove, the sidewall of the light-emitting unit can form a stable structure with the sidewall of the protrusion or other structural layers on the sidewall of the protrusion, which helps to reduce the damage or defects of the light-emitting layer, and further reduces non-radiative recombination centers and current leakage paths, improving the device performance.

[0060] Figure 3 is a cross-sectional view of a partial area of another semiconductor structure provided by an embodiment of the present invention, Figure 4 is a cross-sectional view of a partial area of yet another semiconductor structure provided by an embodiment of the present invention. Refer to Figure 3 and Figure 4 , optionally, the substrate 10 includes a substrate 11 and a transition layer 12. The transition layer 12 is located on the side of the substrate 11 close to the light-emitting unit 50, and the transition layer 12 is used to reduce the lattice mismatch and / or thermal mismatch between the substrate 11 and the light-emitting unit 50. Refer to Figure 4 , in some embodiments, the semiconductor structure further includes a light-emitting unit 50. Optionally, the light-emitting units 50 are arranged in the grooves 20 in a one-to-one correspondence.

[0061] Optionally, the material of the substrate 11 is sapphire, silicon, silicon carbide or gallium arsenide. In some embodiments, the transition layer 12 is at least one of a low-temperature gallium nitride layer (the growth temperature of gallium nitride is 500 to 600 °C), an AlN layer, an AlGaN layer, an undoped gallium nitride layer or an N-type doped gallium nitride layer. Optionally, the transition layer 12 may include a superlattice structure, that is, the transition layer 12 includes alternately grown different material layers, so as to reduce the lattice mismatch degree between the substrate 11 and the light-emitting unit 50.

[0062] In some embodiments, the surface of the transition layer 12 facing away from the substrate 11 and the surface of the light-emitting unit 50 facing the substrate 11 have semiconductor layers of the same type. Exemplarily, if the surface of the light-emitting unit 50 facing the substrate 11 is a first-type semiconductor layer, then the surface of the transition layer 12 facing away from the substrate 11 is a first-type semiconductor layer; if the surface of the light-emitting unit 50 facing the substrate 11 is a second-type semiconductor layer, then the surface of the transition layer 12 facing away from the substrate 11 is a second-type semiconductor layer. In this way, when forming the light-emitting unit 50 on the substrate 10 (such as by epitaxial growth), since the contact interface is a semiconductor layer of the same type, the light-emitting unit 50 can be formed better and more easily on the top surface of the transition layer 12, reducing the defects generated at the contact interface and making it easier to switch to the process of forming the light-emitting unit 50 (such as the process switch before and at the start of epitaxial growth).

[0063] Optionally, the surface of the transition layer 12 facing away from the substrate 10 is an N-type semiconductor layer. Correspondingly, the surface of the light-emitting unit 50 facing the substrate 11 is an N-type semiconductor layer.

[0064] In this embodiment, both the surface of the transition layer 12 away from the substrate 11 and the surface of the light-emitting unit 50 facing the substrate 11 are N-type semiconductor layers. In the light-emitting unit 50 or the substrate 10 including the substrate 11 and the transition layer 12, since the thickness of the N-type semiconductor layer (generally greater than 1 μm) is thicker than that of the P-type semiconductor layer (generally less than 1 μm), the formation time is longer, and the process window is larger. This allows for a sufficient process window when forming the light-emitting unit 50 on the transition layer 12. For example, the thicker thickness can annihilate the defects generated in the transition layer 12 or at the contact interface, improving the crystal quality of the light-emitting unit 50; after forming the light-emitting unit 50, the substrate 11 needs to be peeled off. Processes such as thinning and polishing can be performed on the surface of the transition layer 12 facing the substrate 11. The N-type semiconductor layer can be used as a common electrode layer to form a separate electrode connected to the P-type semiconductor layer of the light-emitting unit 50 on the surface of the light-emitting unit 50 facing away from the substrate 11, thereby independently controlling the independent light emission of each light-emitting unit 50 located in the groove 20.

[0065] Continue to refer to Figures 2 - 4 , optionally, the protrusion 30 is a single-crystal layer. In some embodiments, the sidewall of the single-crystal layer covers the entire sidewall of the light-emitting unit 50 and is in contact with the sidewall of the light-emitting unit 50, that is, the sidewall of the single-crystal layer covers the sidewalls of the first-type semiconductor layer, the light-emitting layer, and the second-type semiconductor layer.

[0066] Specifically, the sidewall damage, defect states, and surface states of the light-emitting unit 50 in the related art include surface dangling bonds. By setting the protrusion 30 as a single-crystal layer, the single-crystal layer can at least contact the sidewalls of the light-emitting layer in the light-emitting unit 50, enabling the epitaxial growth of the sidewalls of the light-emitting layer and the single-crystal layer with similar lattice parameters and structures, forming stable and single-oriented chemical bonds. That is, the sidewalls 31 of the protrusion 30 form covalent bonds with the sidewalls of the light-emitting layer, effectively suppressing the surface dangling bonds of the light-emitting unit 50, being able to remove surface states to the greatest extent, achieving better sidewall quality, greatly improving the light-emitting efficiency and reducing device leakage, and avoiding sidewall damage in step etching during Micro-LED pixelation at the current stage. In some embodiments, the sidewalls of the single-crystal layer cover the sidewalls of the light-emitting unit 50 and contact the sidewalls of the first-type semiconductor layer, the sidewalls of the light-emitting layer, and the sidewalls of the second-type semiconductor layer in the light-emitting unit 50. In this solution, the structure of the protrusion 30 and the groove 20 is first formed, and the protrusion 30 is a single-crystal layer. Then, the light-emitting unit 50 is grown in the groove 20, and the growth of the light-emitting unit 50 can be carried out under high-temperature conditions, enabling the light-emitting unit 50 to form stable chemical bonds with the single-crystal layer. This solution is different from the traditional technology of first pixelating to form the light-emitting unit 50 and then performing sidewall passivation. The traditional sidewall passivation technology not only has a low growth temperature, the density of the passivation layer is not high, and some surface states cannot be effectively passivated, but also its passivation interface is still amorphous or polycrystalline domains, with many defect states. In addition, although the selective epitaxy and nanowires in the non-pixelated solution can effectively avoid sidewall damage to a certain extent, there are still some edge surface states and defect states formed by epitaxy on the sidewalls of the light-emitting unit 50, and these surface states or defect states will also reduce the light efficiency. This solution also makes up for the inherent deficiencies of such solutions.

[0067] Optionally, the first-type semiconductor layer, the light-emitting layer, and the second-type semiconductor layer each include gallium nitride. In some embodiments, the single-crystal layer is at least one of an aluminum nitride layer, a silicon carbide layer, or a zinc oxide layer. Optionally, the crystal structure of the single-crystal layer is a wurtzite structure.

[0068] Aluminum nitride, silicon carbide, or zinc oxide are all single-crystal materials with good insulation properties, and their lattice constants are close to the lattice constant of gallium nitride in the light-emitting unit 50. On the one hand, it cuts off the connection between adjacent light-emitting units 50, and on the other hand, it ensures that the single-crystal layer forms covalent bonds with the sidewalls of the light-emitting unit 50, improving the sidewall damage, surface states, and defect states of the light-emitting unit 50.

[0069] Moreover, aluminum nitride, silicon carbide, or zinc oxide are high heat dissipation and high refractive index materials. The sidewalls of the light-emitting unit 50 are attached to a single-crystal layer of aluminum nitride, silicon carbide, or zinc oxide material, such that the sidewalls of the light-emitting layer and the sidewalls of the single-crystal layer protrusions 30 form a high-quality single-crystal cross-section. The interfacial thermal resistance is very small, enabling higher heat conduction to be formed and increasing the heat dissipation of the light-emitting layer. When the sidewalls 31 of the protrusions 30 cover the sidewalls of the light-emitting unit 50, the heat dissipation of the entire sidewalls of the light-emitting unit 50 can be increased, avoiding the influence of the excessive temperature of the light-emitting unit 50 on the performance of the light-emitting device, and further improving the light-emitting efficiency and device performance. In some embodiments, heat dissipation or heat conduction structures may also be respectively provided on the top and bottom surfaces of the light-emitting unit 50, thereby achieving efficient heat dissipation of the entire structure of the light-emitting unit.

[0070] Optionally, the lattice mismatch degree between the crystal structure of the single-crystal layer and the crystal structure of the light-emitting layer is less than or equal to 5%. In this way, the lattice parameters of the protrusions 30 of the single-crystal layer can be closer to those of the light-emitting layer. When the light-emitting unit 50 is grown in the groove 20, the sidewalls of the light-emitting layer can form more stable covalent bonds with the sidewalls 31 of the single-crystal layer protrusions 30, better suppressing the dangling bonds on the sidewalls of the light-emitting layer, and removing the defect states and surface states on the sidewalls of the light-emitting layer to a greater extent, thereby improving the sidewall quality of the light-emitting layer.

[0071] In some embodiments, the sidewalls 31 of the protrusions 30 cover the sidewalls of the light-emitting unit 50, and the lattice mismatch degree between the crystal structure of the single-crystal layer and the crystal structure of the light-emitting unit 50 is less than or equal to 5%. In this way, the lattice parameters of the protrusions 30 of the single-crystal layer can be closer to those of the entire light-emitting unit 50. When the light-emitting unit 50 is grown in the groove 20, the sidewalls of the light-emitting unit 50 can form more stable covalent bonds with the sidewalls 31 of the single-crystal layer protrusions 30, better suppressing the dangling bonds on the sidewalls of the light-emitting unit 50, and removing the defect states and surface states on the sidewalls of the light-emitting unit 50 to a greater extent, thereby improving the sidewall quality of the light-emitting unit 50.

[0072] In the related art, no other structural layer is provided on the sidewalls of the light-emitting layer or a material with a lower refractive index (refractive index less than 1) is provided. That is, the outside of the sidewalls of the light-emitting layer is air or other low refractive index materials. Since there is a large difference between the refractive index of gallium nitride and the refractive index of air or other low refractive index materials (the refractive index of GaN is n = 2.47, and the refractive index of air is 1.00), according to the total reflection law, photons within a certain angular range are totally reflected back into the semiconductor at the sidewall interface with air, which limits the improvement of the light extraction efficiency of GaN-based Micro-LEDs. Optionally, in this embodiment, the refractive index of the protrusions 30 is greater than 1. Among them, the refractive indices of aluminum nitride, silicon carbide, or zinc oxide are all greater than 2, which are similar to the refractive index of GaN in the light-emitting unit. Therefore, the light escape angle is very large, which helps to increase the light extraction efficiency.

[0073] Figure 5It is a cross-sectional view of a partial region of another semiconductor structure provided by an embodiment of the present invention. Figure 6 It is a cross-sectional view of a partial region of yet another semiconductor structure provided by an embodiment of the present invention. Refer to Figure 5 and Figure 6 , optionally, the material of the substrate 10 is sapphire, silicon, silicon carbide or gallium arsenide, and the surface of the substrate 10 includes grooves 20 and protrusions 30. In this embodiment, the grooves 20 and protrusions 30 can be formed by patterning the surface of the substrate 10. Refer to Figure 6 , in some embodiments, the semiconductor structure further includes a light-emitting unit 50. Optionally, the light-emitting units 50 are arranged in one-to-one correspondence in the grooves 20.

[0074] Continue to refer to Figure 5 and Figure 6 , optionally, the semiconductor structure further includes a passivation layer 60, and the passivation layer 60 is at least located on the sidewall 31 of the protrusion 30 and at least covers the sidewall of the light-emitting layer.

[0075] Among them, the passivation layer 60 can be formed after the protrusions 30 and grooves 20 of the substrate 10. After forming the passivation layer 60, the light-emitting unit 50 can be formed in the groove 20. For example, the light-emitting unit 50 is formed in the groove 20 by epitaxial growth. The passivation layer 60 can be in contact with the sidewall of the light-emitting layer. By providing that the passivation layer 60 at least covers the sidewall of the light-emitting layer, the sidewall of the light-emitting layer is protected, which helps to reduce the damage or defects of the light-emitting layer, and further reduces the non-radiative recombination centers and current leakage paths, thereby improving the device performance.

[0076] Figure 7 It is a cross-sectional view of a partial region of another semiconductor structure provided by an embodiment of the present invention. Refer to Figure 7 , in some embodiments, the passivation layer 60 is at least located on the sidewall 31 of the protrusion 30 and the bottom surface 21 of the groove 20. Among them, Figure 7 exemplarily shows the case where the passivation layer 60 is located on the sidewall 31 and the top surface 32 of the protrusion 30, and the bottom surface 21 of the groove 20. In this embodiment, the passivation layer 60 at least covers the sidewall 31 of the protrusion 30 and the bottom surface 21 of the groove 20. The passivation layer 60 located on the sidewall 31 of the protrusion 30 covers the sidewall of the light-emitting layer of the light-emitting unit 50. Since the passivation layer 60 covers the sidewall 31 of the protrusion 30 and the bottom surface 21 of the groove 20, during the formation of the light-emitting unit 50, the bottom and sidewalls of the light-emitting unit 50 are respectively in contact with the passivation layer 60, which can reduce the contact interface defects or contamination caused by different materials of the bottom surface 21 of the groove 20 and the sidewall 31 of the protrusion 30, and improve the crystal quality consistency of the bottom and sidewalls of the light-emitting unit 50, especially the crystal quality of the contact interface between the bottom and sidewalls of the light-emitting unit 50.

[0077] In some embodiments, the passivation layer 60 is a single crystal layer.

[0078] In this way, the sidewall of the light-emitting layer epitaxially grows with a single-crystalline layer having similar lattice parameters and structure, forming stable and single-oriented chemical bonds. That is, the sidewall 31 of the protrusion 30 forms a covalent bond with the sidewall of the light-emitting unit 50, sufficiently suppressing the dangling bonds on the surface of the light-emitting unit 50, being able to remove surface states to the greatest extent, achieving better sidewall quality, greatly improving the light-emitting efficiency and reducing device leakage, and avoiding sidewall damage in step etching in current Micro-LED pixelation. This solution first forms the structure of the protrusion 30 and the groove 20 on the substrate 10, then forms a passivation layer 60 at least on the sidewall 31 of the protrusion 30, and then grows the light-emitting unit 50 in the groove 20. The growth of the light-emitting unit 50 can be carried out under high-temperature conditions, enabling the light-emitting unit 50 to form stable chemical bonds with the single-crystalline layer, forming a high-quality single-crystalline interface, improving the sidewall quality of the light-emitting layer, and enhancing the heat dissipation performance.

[0079] Optionally, the material of the single-crystalline layer is at least one of an aluminum nitride layer, a silicon carbide layer, or a zinc oxide layer. Optionally, the crystal structure of the single-crystalline layer is a wurtzite structure.

[0080] Optionally, the refractive index of the passivation layer 60 is greater than 1, which can increase the light escape angle and thus increase the light extraction efficiency.

[0081] Continue to refer to Figures 1 - 7 , optionally, the distance between the side of the light-emitting unit 50 facing away from the substrate 10 and the bottom surface 21 of the groove 20 is less than or equal to the distance between the side of the growth-limiting layer 40 facing away from the substrate 10 and the bottom surface 21 of the groove 20.

[0082] In this way, it is ensured that the sidewall of the light-emitting unit 50 is covered by the sidewall 31 of the protrusion 30 or the sidewall of the growth-limiting layer 40, so that the sidewall of the light-emitting unit 50 is not exposed to the air, and the protrusion 30 or the growth-limiting layer 40 provides protection for the sidewall of the light-emitting unit 50, which helps to reduce sidewall damage, surface states or defect states of the light-emitting unit 50 and improve the device performance of the light-emitting unit 50.

[0083] In some embodiments, the distance between the side of the light-emitting unit 50 facing away from the substrate 10 and the bottom surface 21 of the groove 20 is less than or equal to the distance between the top surface 32 of the protrusion 30 and the bottom surface 21 of the groove 20. In this way, it can be ensured that the sidewalls of the light-emitting unit 50 are all covered by the sidewall 31 of the protrusion 30, so that the sidewall 31 of the protrusion 30 can provide protection for the sidewalls of the light-emitting unit 50. In addition, when the protrusion 30 is a single-crystalline layer or a single-crystalline layer is provided on the sidewall 31 of the protrusion 30, during the epitaxial growth process of the light-emitting unit 50, the sidewalls of the light-emitting unit 50 can form stable covalent bonds with the sidewalls of the single-crystalline layer, and the sidewalls of the light-emitting unit 50 form a high-quality interface with the single-crystalline layer, reducing sidewall damage, surface states and defect states of the light-emitting unit 50 and improving the device performance of the light-emitting unit 50.

[0084] In addition, by setting the distance between the side of the light-emitting unit 50 facing away from the substrate 10 and the bottom surface 21 of the groove 20 to be less than or equal to the distance between the top surface 32 of the protrusion 30 and the bottom surface 21 of the groove 20, the growth thickness of the light-emitting unit 50 is small and will not exceed the height of the protrusion 30. When the light-emitting array is formed and the substrate 11 is peeled off later, the structural layer of the light-emitting unit 50 does not need to be peeled off, reducing material waste, lowering the manufacturing cost, and at the same time reducing the process difficulty.

[0085] Continuing to refer to Figures 1 - 7 , optionally, the side wall 31 of the protrusion 30 is perpendicular to the bottom surface 21 of the groove 20.

[0086] Optionally, the bottom surface 21 of the groove 20 is parallel to the horizontal plane. Specifically, in this embodiment, the structures of the groove 20 and the protrusion 30 are formed, and then the light-emitting unit 50 is formed in the groove 20. When the side wall 31 of the protrusion 30 includes the passivation layer 60, the passivation layer 60 can also be perpendicular to the bottom surface of the groove 20 and is uniformly distributed on the side wall 31 of the protrusion 30. In this way, the thickness of the passivation layer 60 on the side wall of the light-emitting unit 50 is uniform, which is beneficial to improving the light-emitting uniformity and heat dissipation uniformity of the light-emitting unit 50, and thus improving the device performance of the light-emitting unit 50.

[0087] When the passivation layer 60 is formed after the light-emitting unit 50 is formed, when the side wall of the light-emitting unit 50 is perpendicular or inclined to the horizontal plane, since the light-emitting unit 50 layer is generally placed horizontally under various process conditions, it is difficult for the obtained passivation layer 60 to be perpendicular to the horizontal plane, or it is difficult for the passivation layer 60 to be uniformly formed on the side wall of the light-emitting unit 50. For example, along the side wall of the light-emitting unit 50, the thickness of the passivation layer 60 is thicker or thinner at positions farther away from the substrate 11.

[0088] In some embodiments, the included angle between the side wall 31 of the protrusion 30 and the bottom surface 21 of the groove 20 is greater than or less than 90 degrees. In this way, the areas of the side of the light-emitting unit 50 facing the substrate 10 and the side facing away from the substrate 10 located in the groove 20 are different. By setting the side with the larger area as the light-emitting surface, a light mask structure can be formed, increasing the light extraction efficiency.

[0089] In some embodiments, the growth limiting layer 40 is a polycrystalline layer or an amorphous layer. Due to the random orientation of polycrystals or amorphous materials, when the light-emitting unit 50 is epitaxially grown in the groove 20, the light-emitting unit 50 will not grow on the surface of the growth limiting layer 40, thereby limiting the light-emitting unit 50 in the groove 20.

[0090] Optionally, the growth limiting layer 40 can be a transparent oxide layer. In some embodiments, the growth limiting layer 40 is at least one of a silicon dioxide layer, a tantalum pentoxide layer, and a titanium-tungsten alloy layer.

[0091] Optionally, the refractive index of the growth limiting layer 40 is greater than 1. In this way, the light condensing effect of the light emitting unit 50 can be increased and stray light can be reduced.

[0092] An embodiment of the present invention also provides a light emitting array. Figure 8 It is a schematic structural diagram of a light emitting array provided by an embodiment of the present invention. Refer to Figure 8 , the light emitting array includes: a light emitting unit layer, the light emitting unit layer includes light emitting units 50 arranged in an array, and the light emitting unit 50 includes a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer stacked in sequence; a graphic structure layer, the graphic structure layer includes protrusions 30 and a plurality of grooves 20, the protrusions 30 are located between adjacent grooves 20, at least part of the layers of the light emitting unit 50 are located in the grooves 20, and the side walls 31 of the protrusions 30 at least cover the side walls of the light emitting layer of the light emitting unit 50.

[0093] Among them, Figure 8 The shown light emitting array can be obtained by removing the substrate 11 from the Figure 4 shown semiconductor structure. This light emitting array has the beneficial effects of the semiconductor structure in the above embodiments of the present invention, which will not be elaborated here.

[0094] Figure 9 It is a schematic structural diagram of another light emitting array provided by an embodiment of the present invention. Refer to Figure 9 , in this light emitting array, a whole layer of the first type semiconductor layer 51 is included under the protrusion 30, and each light emitting unit shares this whole layer of the first type semiconductor layer 51. In some embodiments, the light emitting layer and the second type semiconductor layer may be included in the groove 20; in other embodiments, the first type semiconductor layer, the light emitting layer, and the second type semiconductor layer are included in the groove 20, and the first type semiconductor layer in the groove 20 is electrically connected to the whole layer of the first type semiconductor layer 51 under the protrusion 30.

[0095] In some embodiments, the side wall 31 of the protrusion 30 is in contact with the side wall of the light emitting layer. In this way, during the growth process of the light emitting unit 50, a high-quality interface structure can be formed between the side wall of the light emitting layer and the side wall 31 of the protrusion 30. In some embodiments, the top surface 32 of the protrusion 30 further includes a growth limiting layer.

[0096] Optionally, the graphic structure layer is formed before the light emitting unit 50. In this way, the side wall damage caused during the pixelization process in the related art when pixelization is performed first and then the graphic structure layer is formed can be eliminated. In some embodiments, the graphic structure layer is a single crystal layer. In this way, when the light emitting unit 50 grows epitaxially in the groove 20 of the graphic structure layer, a covalent bond can be formed between the side wall of the light emitting unit 50 and the side wall of the single crystal layer, improving the surface state and defect state of the side wall of the light emitting unit 50, and further improving the device performance of the light emitting unit 50.

[0097] The embodiment of the present invention also provides another light-emitting array. Figure 10 It is a schematic structural diagram of another light-emitting array provided by the embodiment of the present invention. Figure 11 It is a schematic structural diagram of yet another light-emitting array provided by the embodiment of the present invention. Refer to Figure 10 and Figure 11 , the light-emitting array includes: a graphic structure layer, the graphic structure layer includes protrusions 30 and a plurality of grooves 20, and the protrusions 30 are located between adjacent grooves 20; a plurality of light-emitting units 50, at least part of the light-emitting units 50 are located in the grooves 20, and the light-emitting units 50 include a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer stacked in sequence; a passivation layer 60, the passivation layer 60 is at least located on the side wall 31 of the protrusion 30 and at least covers the side wall of the light-emitting layer.

[0098] Among them, Figure 10 The shown light-emitting array can be obtained by forming light-emitting units in the grooves 20 and thinning the substrate on the basis of the semiconductor structure shown in Figure 7 . The shown light-emitting array can be obtained by forming light-emitting units in the grooves 20 and thinning the substrate on the basis of the semiconductor structure shown in Figure 11 . The light-emitting array has the beneficial effects of the semiconductor structure in the above embodiments of the present invention, which will not be elaborated here. Figure 6 The shown light-emitting array can be obtained by forming light-emitting units in the grooves 20 and thinning the substrate on the basis of the semiconductor structure shown in

[0099] In some embodiments, the passivation layer 60 is at least located on the side wall 31 of the protrusion 30 and the bottom surface 21 of the groove 20.

[0100] Optionally, the passivation layer 60 is integrally formed. Correspondingly, the passivation layer 60 is also located on the top surface 32 of the protrusion 30. In this way, the formation step of the passivation layer 60 is simple, and the manufacturing process is simplified.

[0101] Optionally, the passivation layer 60 is formed before the light-emitting unit 50. In some embodiments, the passivation layer 60 is a single crystal layer. In some embodiments, the top surface 32 of the protrusion 30 further includes a growth limiting layer. When the top surface 32 of the protrusion 30 includes the passivation layer 60 and the growth limiting layer, the growth limiting layer is located on the side of the passivation layer 60 away from the top surface of the protrusion 30 (see the structure shown in Figure 7 ).

[0102] The embodiment of the present invention also provides another light-emitting array. Figure 12 It is a schematic structural diagram of another light-emitting array provided by the embodiment of the present invention. Figure 13 It is a top view of a light-emitting array provided by the embodiment of the present invention. Refer to Figure 12 and Figure 13, the light-emitting array includes: a light-emitting unit layer including light-emitting units 50 arranged in an array, the light-emitting units 50 including a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer stacked in sequence; a graphic structure layer including a plurality of defining units 70 with a spacing between adjacent defining units 70, the defining units 70 having grooves 20 formed therein, the light-emitting units 50 being located in the grooves 20, and the sidewalls of the defining units 70 covering at least the sidewalls of the light-emitting layers of the light-emitting units 50; a connection layer 80 located on a side of the first-type semiconductor layer away from the light-emitting layer; a common first electrode 91 and a plurality of discrete second electrodes 92, the common first electrode 91 being on the same side of the connection layer 80 as the first-type semiconductor layer, the common first electrode 91 being disposed between the defining units 70, and the common first electrode 91 being electrically connected to the first-type semiconductor layer through the connection layer 80; and the second electrodes 92 being located on a side of the second-type semiconductor layer away from the light-emitting layer and being electrically connected to the second-type semiconductor layer.

[0103] Wherein, Figure 12 The illustrated light-emitting array can be formed by patterning the protrusions 30 and the growth-limiting layer 40 in the Figure 4 semiconductor structure to form the common first electrode 91 and the discrete second electrodes 92. Figure 4 The illustrated transition layer 12 can serve as the Figure 12 connection layer 80, and the connection layer 80 is conductive. Wherein, the preparation of the common first electrode 91 and the discrete second electrodes 92 can be formed after the light-emitting units 50. Exemplarily, after forming the light-emitting units 50 in the grooves 20, the protrusions 30 are patterned to expose the connection layer 80, the common first electrode 91 is formed on the surface of the connection layer 80, and the second electrodes 92 are respectively formed on the sides of the second-type semiconductor layers of the light-emitting units 50 away from the light-emitting layer.

[0104] The light-emitting array of this embodiment has the beneficial effects of the semiconductor structure of any of the above embodiments of the present invention, which will not be elaborated here.

[0105] It should be noted that, Figure 12 only the front-mounted chip structure prepared by using the semiconductor structure of the embodiment of the present invention is shown. In other alternative embodiments of the present invention, a flip-chip or a vertical-structure chip can be prepared by using the semiconductor structure of any embodiment of the present invention.

[0106] Based on the above embodiments, optionally, the thicknesses of the graphic structure layers on different sidewalls of the light-emitting unit 50 are equal; and / or, among two adjacent light-emitting units 50, the thickness of the graphic structure layer on the first sidewall of one light-emitting unit 50 is equal to the thickness of the graphic structure layer on the second sidewall of the other light-emitting unit 50, and the common second electrode 92 is located between the first sidewall and the second sidewall. With such a setting, the heat dissipation of different sidewalls of the light-emitting unit 50 can be made uniform, and / or the heat dissipation of different light-emitting units 50 can be made uniform, improving the heat dissipation efficiency and being beneficial to enhancing the light extraction efficiency.

[0107] In some embodiments, the graphic structure layer is a single crystal layer.

[0108] In some other embodiments, the graphic structure layer includes a substrate and a passivation layer. The substrate includes a plurality of defining units 70, and the passivation layer is located on the sidewalls of the defining units 70 and at least covers the light-emitting layer. The passivation layer is a single crystal layer. In this case, the thicknesses of the passivation layers on different sidewalls of the light-emitting unit 50 are equal, and / or the thicknesses of the passivation layers on the sidewalls of different light-emitting units 50 are equal.

[0109] Optionally, the orthographic projection of the defining unit 70 on the connection layer 80 surrounds the orthographic projection of the light-emitting unit 50 on the connection layer 80; the orthographic projection of the common first electrode 91 on the connection layer 80 surrounds the orthographic projection of the defining unit 70 on the connection layer 80. Thus, the common first electrode 91 forms an annular structure, increasing the electron injection efficiency and improving the light-emitting efficiency.

[0110] In some embodiments, the distance from the side of the common first electrode 91 away from the connection layer 80 to the side of the connection layer 80 facing the light-emitting unit 50 is greater than or equal to the distance from the side of the light-emitting unit 50 away from the connection layer 80 to the side of the connection layer 80 facing the light-emitting unit 50; in this way, the height of the common first electrode 91 in the vertical direction is greater than or equal to the height of the light-emitting unit 50 in the vertical direction. The light emitted from the side of the light-emitting unit 50 is isolated by the common first electrode 91 surrounding the light-emitting unit 50, preventing light crosstalk between adjacent light-emitting units 50.

[0111] The embodiment of the present invention also provides a preparation process of a semiconductor structure. Figure 14 It is a structural diagram after each step in the preparation process flow of a semiconductor structure provided by the embodiment of the present invention. Refer to Figure 14 and the preparation process of the semiconductor structure includes:

[0112] S110. Form a substrate 10, where the substrate 10 includes a substrate 11 and a transition layer 12 located on the substrate 11.

[0113] Optionally, in this step, a transition layer 12 can be formed on one side of the substrate 11 by epitaxial growth to form the substrate 10; alternatively, the transition layer 12 can be formed on one side of the substrate 11 by deposition or other means.

[0114] S120. Form a pattern layer 101, which is located on the side of the transition layer 12 away from the substrate 11.

[0115] Specifically, in the cleaned substrate 10, the pattern layer 101 grows on the side of the transition layer 12 away from the substrate 11. The pattern layer 101 can be a single crystal layer, and the single crystal layer is a single crystal material with high heat dissipation, high refractive index, and good insulation, such as AlN, SiC, or ZnO. The crystal structure can be wurtzite. Taking AlN as an example, the thickness of the single crystal layer is 10 - 1000 nm.

[0116] S130. Form a growth limiting layer 40, which is located on the side of the pattern layer 101 away from the substrate 11.

[0117] Specifically, the growth limiting layer 40 is formed on the side of the pattern layer 101 away from the substrate 11. The growth limiting layer 40 can be a transparent oxide. The transparent oxide can be formed by deposition or magnetron sputtering, etc. For example, SiO2 and / or Ta2O5 are deposited or magnetron sputtered on the side of the pattern layer 101 away from the substrate 11 to form a film. Both are high refractive index transparent oxides, where the thickness of SiO2 is 10 - 101 nm. In some embodiments, the SiO2 layer and the Ta2O5 layer are arranged in an overlapping manner, and one SiO2 layer and an adjacent Ta2O5 layer form a composite layer. Optionally, the composite layer is 1 - 30 layers.

[0118] S140. Etch the growth limiting layer 40 and the pattern layer 101 to form a groove 20, and the bottom of the groove 20 exposes the transition layer 12.

[0119] After the growth of the pattern layer 101 and the growth limiting layer 40 is completed, the pattern layer 101 and the growth limiting layer 40 are selectively etched using a pattern mask to form a periodic array of windows as the pattern structure layer, that is, a periodic array of grooves 20 is formed, and protrusions 30 are included between the grooves 20. Among them, the window area serves as the groove 20, and the window area can be any polygon or regular shape or irregular shape such as a circle or an ellipse, and the minimum distance between the window areas is 1 - 100 microns. For example, the window is a square with a side length of 5 μm and the distance is 15 microns. In this step, the transition layer 12 can be not etched or a part of the thickness of the transition layer 12 can be etched.

[0120] The manufacturing process of the semiconductor structure of this embodiment is patterned after forming the pattern layer and the growth limiting layer to form a pattern structure layer including protrusions and groove structures, where the pattern layer is a single crystal layer. The grooves are used to accommodate the light emitting units, so that the sidewalls of the light emitting units can form covalent bonds with the sidewalls of the protrusions of the single crystal layer, improving or even eliminating the surface states and defect states on the sidewalls of the light emitting units, forming a high-quality single crystal interface, enhancing the device performance of the light emitting units, reducing the interface thermal resistance, forming better heat conduction, and enhancing the heat dissipation performance of the semiconductor structure. Moreover, since the growth limiting layer is formed before the light emitting units, the light emitting units can be restricted to grow in the grooves. In addition, the semiconductor manufacturing process of the technical solution of the present invention is simple, which helps to improve the device yield and has good economic benefits.

[0121] The embodiment of the present invention also provides another manufacturing process of a semiconductor structure. Figure 15 It is a structural diagram after each step is completed in another manufacturing process of the semiconductor structure provided by the embodiment of the present invention. Refer to Figure 15 , the manufacturing process of this semiconductor structure includes:

[0122] S310. Provide a substrate 10.

[0123] Optionally, the material of the substrate 10 is sapphire, silicon, silicon carbide, gallium arsenide, etc.

[0124] S320. Form grooves 20 on the substrate 10, and protrusions 30 are included between adjacent grooves 20.

[0125] In this step, the surface of the substrate 10 can be patterned, and then groove 20 and protrusion 30 structures are formed on the surface of the substrate 10.

[0126] S330. Form a passivation layer 60, and the passivation layer 60 is at least located on the sidewall 31 of the protrusion 30.

[0127] Among them, the passivation layer 60 is a single crystal layer. In some embodiments, the passivation layer 60 is formed on the surfaces of the grooves 20 and the protrusions 30 by means of epitaxial growth or sputtering. Optionally, the passivation layer 60 is at least located on the sidewall 31 of the protrusion 30 and the bottom surface 21 of the groove 20.

[0128] S340. Form a growth limiting layer 40 on the side of the protrusion 30 facing away from the substrate 10.

[0129] The preparation process of the semiconductor structure of this embodiment forms a passivation layer after forming grooves and protrusions on the substrate. The passivation layer is at least located on the sidewalls of the protrusions. The grooves are used to accommodate the light-emitting units, so that the sidewalls of the light-emitting units can form covalent bonds with the sidewalls of the passivation layer protrusions, thereby improving or even eliminating the surface state and defect state of the sidewalls of the light-emitting units, forming a high-quality single crystal interface, improving the device performance of the light-emitting units, and reducing the interface thermal resistance, forming better heat conduction, and improving the heat dissipation performance of the semiconductor structure. In addition, since the growth restriction layer is formed before the light-emitting units, the light-emitting units can be restricted to grow in the grooves. In addition, the semiconductor preparation process of the technical solution of the present invention is simple, helps to improve the device yield, and has good economic benefits.

[0130] The embodiment of the present invention also provides a preparation process of a light-emitting array, which includes first forming a protrusion or a passivation layer for at least covering the side wall of the light-emitting layer of the light-emitting unit, and then forming the light-emitting unit, wherein the light-emitting unit includes a first type semiconductor layer, a light-emitting layer, and a second type semiconductor layer stacked in sequence. Among them, the protrusion is a single crystal layer or the passivation layer is a single crystal layer. In this way, the light-emitting unit can form a stable chemical bond with the protrusion or the passivation layer. This scheme is different from the traditional technology of first pixelating to form a light-emitting unit and then passivating the sidewall. The traditional sidewall passivation technology not only has a low growth temperature, a low density of the passivation layer, and some surface states cannot be effectively passivated, but also its passivation interface is still amorphous or polycrystalline domains, and there are many defect states. In addition, although the selective epitaxy and nanowires in the non-pixelated scheme can effectively avoid sidewall damage to a certain extent, the sidewall of the light-emitting unit still has some edge surface states and defect states formed by epitaxy, and these surface states or defect states will also reduce the light efficiency. This scheme also makes up for the inherent deficiencies of such schemes.

[0131] Figure 16 is a process flow chart of a light emitting array provided by an embodiment of the present invention, with reference to Figure 16 , the preparation process of the light emitting array includes:

[0132] S210, forming a substrate, the substrate including a substrate and a transition layer located on the substrate. After S210 is completed, the structure can refer to Figure 14 The structure after S110 is completed.

[0133] S220, forming a graphic layer, the graphic layer is located on the side of the transition layer away from the substrate. After S220 is completed, the structure can refer to Figure 14 The structure after S120 is completed.

[0134] S230, forming a growth restriction layer, the growth restriction layer is located on the side of the graphic layer away from the substrate. After S230 is completed, the structure can refer to Figure 14 The structure after S130 is completed.

[0135] S240. Etch the growth restriction layer and the pattern layer to form a groove, and the transition layer is exposed at the bottom of the groove. After S240 is completed, the structure can be referred to Figure 14 the structure after S140 is completed in

[0136] S250. Grow a light-emitting unit in the groove. After S250 is completed, the structure can be referred to Figure 4 .

[0137] Among them, the light-emitting unit includes a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer arranged in a stacked manner. Taking the first-type semiconductor layer as an N-type semiconductor layer and the second-type semiconductor layer as a P-type semiconductor layer as an example, N-GaN, a quantum well layer, an electron blocking layer, a P-type conductive layer P-GaN, and a P-GaN contact layer can be epitaxially grown in the groove to complete the growth of the light-emitting unit. Among them, the thickness of N-GaN is 50-5000 nm, and the silicon doping concentration is 1E18-9E19 / cm2; the quantum well layer contains 2-20 pairs of multiple quantum wells. Among them, the thickness of the barrier GaN is 5-50 nm, and the growth temperature is 800-1000 °C. The thickness of the well InGaN is 3-30 nm, and the growth temperature is 630-900 °C. The electron blocking layer is a Mg-doped P-type AlGaN layer, and the thickness of the electron blocking layer is 10-200 nm, and the growth temperature is 850-1030 °C. On the above electron blocking layer, P-GaN doped with Mg is grown as a P-type semiconductor layer. The thickness of P-GaN is 50-500 nm, and the growth temperature is 850-1000 °C. Among them, the Mg doping concentration is 1E19-5E19 / cm2; by increasing the doping amount of Mg, the Mg doping concentration is 1E19-9E19 / cm2, and a P-GaN contact layer with a thickness of 50-500 nm is grown. The total height of the epitaxial growth in the final window area is 1000-7000 nm, which does not exceed the thickness of the protrusion, and the protrusion is located between the grooves. Then, a transparent conductive layer, such as ITO, with a thickness of 50-500 nm is formed on the upper surface of the light-emitting unit (that is, the side of the P-GaN contact layer facing away from the substrate).

[0138] S260. Remove at least part of the thickness of the substrate from the side of the substrate facing away from the light-emitting unit.

[0139] Optionally, processes such as thinning and polishing are performed on the substrate from the side of the substrate facing away from the light-emitting unit to remove at least part of the thickness of the substrate.

[0140] The manufacturing process of the light-emitting array of this embodiment includes the manufacturing process of the semiconductor structure of the above embodiment of the present invention and has the beneficial effects of the manufacturing process of the semiconductor structure of the above embodiment of the present invention. In other embodiments, the semiconductor structure obtained in the above embodiment can also be directly used to form light-emitting units on the semiconductor structure, and then at least part of the thickness of the substrate is removed from the side of the substrate facing away from the light-emitting units.

[0141] The embodiment of the present invention also provides another manufacturing process of a light-emitting array. Figure 17 It is a flowchart of another manufacturing process of the light-emitting array provided by the embodiment of the present invention. Refer to Figure 17 , and the manufacturing process of the semiconductor structure includes:

[0142] S410. Provide a substrate. After S410 is completed, the structure can be referred to the structure after S310 is completed in Figure 15 .

[0143] S420. Form grooves on the substrate, and there are protrusions between adjacent grooves. After S420 is completed, the structure can be referred to the structure after S320 is completed in Figure 15 .

[0144] S430. Form a passivation layer, and the passivation layer is at least located on the side walls of the protrusions. After S430 is completed, the structure can be referred to the structure after S330 is completed in Figure 15 .

[0145] S440. Form a growth limiting layer on the side of the protrusion facing away from the substrate. After S440 is completed, the structure can be referred to the structure after S340 is completed in Figure 15 .

[0146] S450. Grow light-emitting units in the grooves.

[0147] S460. Remove at least part of the thickness of the substrate from the side of the substrate facing away from the light-emitting units.

[0148] Optionally, processes such as thinning and polishing are performed on the substrate from the side of the substrate facing away from the light-emitting units to remove at least part of the thickness of the substrate.

[0149] The manufacturing process of the light-emitting array of this embodiment includes the manufacturing process of the semiconductor structure of the above embodiment of the present invention and has the beneficial effects of the manufacturing process of the semiconductor structure of the above embodiment of the present invention. In other embodiments, the semiconductor structure obtained in the above embodiment can also be directly used to form light-emitting units on the semiconductor structure, and then at least part of the thickness of the substrate is removed from the side of the substrate facing away from the light-emitting units.

[0150] It should be understood that the various forms of processes shown above can be used, with steps reordered, added or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0151] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A plurality of grooves and protrusions, wherein the grooves are located on the substrate, the protrusions are located between adjacent grooves, and the top surfaces of the protrusions and the bottom surfaces of the grooves are connected through the side walls of the protrusions; the grooves are used to accommodate at least part of the layers of the light-emitting unit, and the light-emitting unit includes a first type semiconductor layer, a light-emitting layer, and a second type semiconductor layer that are stacked; and the side walls of the protrusions are used to cover at least the side walls of the light-emitting layer; A growth restriction layer is located on the top surface of the protrusion, and the growth restriction layer is used to restrict the growth of the light-emitting unit in the groove.

2. The semiconductor structure according to claim 1, characterized in that: The base plate includes a substrate and a transition layer. The transition layer is located on a side of the substrate close to the light-emitting unit. The transition layer is used to reduce lattice mismatch and / or thermal mismatch between the substrate and the light-emitting unit.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The protrusion is a single crystal layer.

4. The semiconductor structure according to claim 3, characterized in that: The single crystal layer is at least one of an aluminum nitride layer, a silicon carbide layer or a zinc oxide layer.

5. The semiconductor structure according to claim 3, characterized in that: The single crystal layer has a crystal structure of a wurtzite structure.

6. The semiconductor structure according to claim 3, characterized in that: The lattice mismatch between the crystal structure of the single crystal layer and the crystal structure of the light-emitting layer is less than or equal to 5%.

7. The semiconductor structure according to claim 3, characterized in that: The side wall of the protrusion covers the side wall of the light emitting unit, and the lattice mismatch between the crystal structure of the single crystal layer and the crystal structure of the light emitting unit is less than or equal to 5%.

8. The semiconductor structure according to claim 2, characterized in that: The material of the substrate is sapphire, silicon, silicon carbide or gallium arsenide.

9. The semiconductor structure according to claim 2 or 8, characterized in that: The transition layer is at least one of a low-temperature gallium nitride layer, an AlN layer, an AlGaN layer, an undoped gallium nitride layer or an N-type doped gallium nitride layer.

10. The semiconductor structure according to claim 9, characterized in that: The side of the transition layer facing away from the substrate and the side of the light emitting unit facing the substrate have the same type of semiconductor layer.

11. The semiconductor structure according to claim 10, characterized in that: The side of the transition layer facing away from the substrate is an N-type semiconductor layer.

12. The semiconductor structure according to claim 1, characterized in that The refractive index of the protrusion is greater than 1.

13. The semiconductor structure according to claim 1, characterized in that The material of the substrate is sapphire, silicon, silicon carbide or gallium arsenide, and the surface of the substrate includes the grooves and the protrusions.

14. The semiconductor structure according to claim 1 or 13, characterized in that: It also includes a passivation layer, which is at least located on the side wall of the protrusion and at least covers the side wall of the light-emitting layer.

15. The semiconductor structure according to claim 14, characterized in that: The passivation layer is at least located on the sidewalls of the protrusions and the bottom surface of the recesses.

16. The semiconductor structure according to claim 15, characterized in that The passivation layer is a single crystal layer.

17. The semiconductor structure according to claim 14, characterized in that The refractive index of the passivation layer is greater than 1.

18. The semiconductor structure according to claim 1, wherein: The distance between a side of the light emitting unit facing away from the substrate and the bottom surface of the groove is less than or equal to the distance between a side of the growth restriction layer facing away from the substrate and the bottom surface of the groove.

19. The semiconductor structure according to claim 18, characterized in that The distance between a side of the light emitting unit facing away from the substrate and the bottom surface of the groove is less than or equal to the distance between the top surface of the protrusion and the bottom surface of the groove.

20. The semiconductor structure according to claim 1, wherein: The side wall of the protrusion is perpendicular to the bottom surface of the groove; Alternatively, the angle between the side wall of the protrusion and the bottom surface of the groove is greater than or less than 90 degrees.

21. The semiconductor structure according to claim 1, characterized in that The growth limiting layer is a polycrystalline layer or an amorphous layer.

22. The semiconductor structure according to claim 21, characterized in that The growth limiting layer is at least one of a silicon dioxide layer, a tantalum pentoxide layer, and a titanium-tungsten alloy layer.

23. The semiconductor structure according to claim 1, characterized in that The refractive index of the growth limiting layer is greater than 1.

24. The semiconductor structure according to claim 1, characterized in that The first type semiconductor layer, the light emitting layer and the second type semiconductor layer include gallium nitride respectively.

25. The semiconductor structure according to claim 1, characterized in that It also includes a plurality of the light emitting units, and the light emitting units are arranged in the grooves in a one-to-one correspondence.

26. A light emitting array, characterized in that: include: A light-emitting unit layer, wherein the light-emitting unit layer comprises light-emitting units arranged in an array, and the light-emitting units comprise a first type semiconductor layer, a light-emitting layer, and a second type semiconductor layer stacked in sequence; The graphic structure layer comprises a protrusion and a plurality of grooves, wherein the protrusion is located between adjacent grooves, at least part of the layer of the light-emitting unit is located in the groove, and the side wall of the protrusion at least covers the side wall of the light-emitting layer of the light-emitting unit.

27. The light emitting array according to claim 26, characterized in that: A side wall of the protrusion contacts a side wall of the light emitting layer.

28. The light emitting array according to claim 26 or 27, characterized in that: The pattern structure layer is formed before the light emitting unit.

29. The light emitting array according to claim 26, characterized in that: The graphic structure layer is a single crystal layer.

30. A light emitting array, characterized in that: include: A graphic structure layer, the graphic structure layer comprising a protrusion and a plurality of grooves, wherein the protrusion is located between adjacent grooves; A plurality of light-emitting units, at least part of the layers of the light-emitting units are located in the grooves, and the light-emitting units include a first type semiconductor layer, a light-emitting layer, and a second type semiconductor layer stacked in sequence; A passivation layer is at least located on a side wall of the protrusion and at least covers a side wall of the light-emitting layer.

31. The light emitting array according to claim 30, characterized in that: The passivation layer is at least located on the sidewalls of the protrusions and the bottom surface of the recesses.

32. The light emitting array according to claim 31, characterized in that: The passivation layer is integrally formed.

33. The light emitting array according to any one of claims 30 to 32, characterized in that: The passivation layer is formed before the light emitting unit.

34. The light emitting array according to any one of claims 30 to 32, characterized in that: The passivation layer is a single crystal layer.

35. A light emitting array, characterized in that: include: A light-emitting unit layer, wherein the light-emitting unit layer comprises light-emitting units arranged in an array, and the light-emitting units comprise a first type semiconductor layer, a light-emitting layer, and a second type semiconductor layer stacked in sequence; A graphic structure layer, wherein the graphic structure layer comprises a plurality of defining units, adjacent defining units are spaced apart from each other, the defining units are formed with grooves, at least a portion of the light-emitting unit is located in the grooves, and the sidewalls of the defining units at least cover the sidewalls of the light-emitting layer of the light-emitting unit; a connecting layer, located on a side of the first type semiconductor layer away from the light emitting layer; A common first electrode and a plurality of discrete second electrodes, wherein the common first electrode and the first type semiconductor layer are located on the same side of the connecting layer, the common first electrode is arranged between the limiting units, and the common first electrode is electrically connected to the first type semiconductor layer through the connecting layer; the second electrode is located on a side of the second type semiconductor layer away from the light emitting layer and is electrically connected to the second type semiconductor layer.

36. The light emitting array according to claim 35, characterized in that: The thickness of the graphic structure layer on different side walls of the light-emitting unit is equal; And / or, in two adjacent light-emitting units, the graphic structure layer of the first side wall of one of the light-emitting units is equal to the thickness of the graphic structure layer of the second side wall of the other light-emitting unit, and the common first electrode is located between the first side wall and the second side wall.

37. The light emitting array according to claim 36, characterized in that: The graphic structure layer is a single crystal layer; Alternatively, the graphic structure layer includes a substrate and a passivation layer, the substrate includes a plurality of the defining units, the passivation layer is located on the side walls of the defining units and at least covers the light-emitting layer, and the passivation layer is a single crystal layer.

38. The light emitting array according to claim 35, characterized in that: The orthographic projection of the limiting unit on the connecting layer surrounds the orthographic projection of the light emitting unit on the connecting layer; The orthographic projection of the common first electrode on the connection layer surrounds the orthographic projection of the definition unit on the connection layer.

39. The light emitting array according to claim 35, characterized in that: The distance between the common first electrode away from the connection layer and the connection layer facing the light-emitting unit is greater than or equal to the distance between the light-emitting unit away from the connection layer and the connection layer facing the light-emitting unit.

40. A process for preparing a semiconductor structure, characterized in that: include: forming a substrate, the substrate comprising a substrate and a transition layer located on the substrate; forming a patterned layer, wherein the patterned layer is located on a side of the transition layer away from the substrate; The graphic layer is a single crystal layer; forming a growth restriction layer, wherein the growth restriction layer is located on a side of the pattern layer away from the substrate; The growth restriction layer and the pattern layer are etched to form a groove, and the transition layer is exposed at the bottom of the groove.

41. A process for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming grooves on the substrate, wherein protrusions are provided between adjacent grooves; forming a passivation layer, wherein the passivation layer is at least located on the sidewalls of the protrusion; The passivation layer is a single crystal layer; A growth limiting layer is formed on a side of the protrusion facing away from the substrate.

42. The preparation process according to claim 41, characterized in that: The passivation layer is at least located on the sidewalls of the protrusions and the bottom surface of the recesses.

43. A process for preparing a light emitting array, characterized in that: include: A protrusion or a passivation layer is first formed to at least cover the side wall of the light-emitting layer of the light-emitting unit, and then the light-emitting unit is formed. The light-emitting unit includes a first type semiconductor layer, a light-emitting layer, and a second type semiconductor layer stacked in sequence.

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