Display panel and display device

Abstract

The present disclosure relates to the technical field of display, and discloses a display panel and a display device. A pixel circuit column group of the display panel comprises a first pixel circuit column, a second pixel circuit column, a third pixel circuit column and a fourth pixel circuit column. The channel width of the first transistor of the first pixel circuit of the first pixel circuit column is different from the channel width of the first transistor of the second pixel circuit of the second pixel circuit column, the channel width of the first transistor of the third pixel circuit of the third pixel circuit column is different from the channel width of the first transistor of the fourth pixel circuit of the fourth pixel circuit column, the first pixel circuit drives a first color light emitting device or a third color light emitting device, the second pixel circuit drives a second color light emitting device, the third pixel circuit drives the second color light emitting device, and the fourth pixel circuit drives the third color light emitting device or the first color light emitting device. The display device comprises the display panel. The present disclosure can improve color deviation and improve display effect.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) have advantages such as low power consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed, making them a key research focus in the display field. When used in display panels, pixel circuits are typically designed to provide driving current to the OLED to drive it to emit light; variations in the driving current significantly affect the OLED's brightness.

[0003] However, in the pixel circuits of existing OLED display panels, due to fluctuations in the pixel circuit manufacturing process, there may be differences in the driving current of different pixels. When the differences are severe, they can easily cause color shift and display mura.

[0004] Therefore, providing a display panel and display device that can improve color deviation, reduce mura visual effects, and improve display performance is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned technical problems, this disclosure provides a display panel and a display device to solve the problem that existing display devices are prone to color deviation, which affects display quality.

[0006] This disclosure provides a display panel including a plurality of pixel circuits, each pixel circuit including a driving transistor and a first transistor electrically connected to each other;

[0007] The multiple pixel circuits include at least a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit;

[0008] The display panel includes multiple pixel circuit columns arranged sequentially along a first direction. Each pixel circuit column includes a first pixel circuit column, a second pixel circuit column, a third pixel circuit column, and a fourth pixel circuit column.

[0009] The first pixel circuit column includes multiple first pixel circuits, the second pixel circuit column includes multiple second pixel circuits, the third pixel circuit column includes multiple third pixel circuits, and the fourth pixel circuit column includes multiple fourth pixel circuits.

[0010] The channel width of the first transistor in the first pixel circuit is different from the channel width of the first transistor in the second pixel circuit. The channel width of the first transistor in the third pixel circuit is different from the channel width of the first transistor in the fourth pixel circuit. The channel width of the first transistor in the first pixel circuit is equal to the channel width of the first transistor in the third pixel circuit. The channel width of the first transistor in the second pixel circuit is equal to the channel width of the first transistor in the fourth pixel circuit.

[0011] The display panel includes multiple light-emitting devices, which include a first color light-emitting device, a second color light-emitting device, and a third color light-emitting device;

[0012] The first pixel circuit drives the first color light-emitting device or the third color light-emitting device, the second pixel circuit drives the second color light-emitting device, the third pixel circuit drives the second color light-emitting device, and the fourth pixel circuit drives the third color light-emitting device or the first color light-emitting device.

[0013] Based on the same inventive concept, this disclosure also provides a display device, which includes the above-described display panel.

[0014] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0015] This disclosure sets up a first pixel circuit array consisting of multiple first pixel circuits and a second pixel circuit array consisting of multiple second pixel circuits. The channel width of the first transistor in the first pixel circuit is different from the channel width of the first transistor in the second pixel circuit. The first pixel circuit drives a first color light-emitting device or a third color light-emitting device, and the second pixel circuit drives a second color light-emitting device. Meanwhile, multiple third pixel circuits form a third pixel circuit array, and multiple fourth pixel circuits form a fourth pixel circuit array. The channel width of the first transistor in the third pixel circuit is different from the channel width of the first transistor in the fourth pixel circuit. Alternatively, the channel width of the first transistor in the third pixel circuit is the same as the channel width of the first transistor in the first pixel circuit, and the channel width of the first transistor in the fourth pixel circuit is the same as the channel width of the first transistor in the second pixel circuit. In this case, the color of the light-emitting device driven by the third pixel circuit is different from the color of the light-emitting device driven by the first pixel circuit, and the third pixel circuit drives a second color light-emitting device. The color of the light-emitting device driven by the fourth pixel circuit is different from the color of the light-emitting device driven by the second pixel circuit, and the fourth pixel circuit drives either a third color light-emitting device or a first color light-emitting device. Therefore, the color shift of the light-emitting areas corresponding to the third and fourth pixel circuits neutralizes the color shift of the light-emitting areas corresponding to the first and second pixel circuits, thereby improving the overall visual effect and enhancing display quality. This disclosure requires minimal modification to the display panel's layout structure. It does not require altering the pixel circuit layout or the light-emitting device layout, nor does it employ complex brightness compensation methods. It simply requires that in a pixel circuit group consisting of four adjacent pixel circuits in the first direction, the first pixel circuit drives either the first or third color light-emitting device, the second pixel circuit drives the second color light-emitting device, the third pixel circuit drives the second color light-emitting device, and the fourth pixel circuit drives either the third or first color light-emitting device. In other words, changing the color of the light-emitting device driven by the third pixel circuit and changing the color of the light-emitting device driven by the fourth pixel circuit can improve the display's color shift problem. The structure and process are relatively simple, which is beneficial for improving process efficiency. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0018] Figure 1This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this disclosure;

[0019] Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure for a mid-pixel circuit;

[0020] Figure 3 yes Figure 1 A magnified schematic diagram of a pixel circuit in region J1;

[0021] Figure 4 This is a schematic diagram of the layout structure of a pixel circuit and a light-emitting device provided in the prior art;

[0022] Figure 5 yes Figure 4 A schematic diagram showing the pink or green tint caused by the difference in the corresponding driving current of different pixel circuits.

[0023] Figure 6 yes Figure 1 A partially enlarged schematic diagram of the pixel circuits and light-emitting devices arranged in the J1 region;

[0024] Figure 7 yes Figure 1 A schematic diagram of another electrical connection structure for the middle pixel circuit;

[0025] Figure 8 yes Figure 7 A timing diagram of a mid-pixel circuit;

[0026] Figure 9 yes Figure 1 A magnified schematic diagram of the arrangement of light-emitting devices in a certain area;

[0027] Figure 10 yes Figure 3 pixel circuit and Figure 9 A schematic diagram of a layout structure combining light-emitting devices;

[0028] Figure 11 yes Figure 3 pixel circuit and Figure 9 A schematic diagram of another layout structure combining light-emitting devices;

[0029] Figure 12 yes Figure 11 A magnified view of a portion of region J2;

[0030] Figure 13 yes Figure 12 A schematic diagram of a cross-sectional structure along the A-A' direction;

[0031] Figure 14 yes Figure 12A schematic diagram of a cross-sectional structure along the B-B' direction;

[0032] Figure 15 yes Figure 12 A schematic diagram of a cross-sectional structure along the C-C' direction;

[0033] Figure 16 yes Figure 12 A schematic diagram of a cross-sectional structure along the D-D' direction;

[0034] Figure 17 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure;

[0035] Figure 18 yes Figure 17 A magnified view of a portion of region J3;

[0036] Figure 19 yes Figure 17 Another enlarged view of the J3 region;

[0037] Figure 20 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure;

[0038] Figure 21 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure;

[0039] Figure 22 yes Figure 21 A magnified view of a portion of region J4;

[0040] Figure 23 yes Figure 22 A schematic diagram showing the corresponding layout of the mid-pixel circuit and data lines;

[0041] Figure 24 yes Figure 21 A magnified view of a portion of the area corresponding to multiple pixel circuit arrays;

[0042] Figure 25 yes Figure 24 A schematic diagram showing the corresponding layout of the mid-pixel circuit and data lines;

[0043] Figure 26 This is a schematic diagram of the planar structure of the display device provided in the embodiments of this disclosure. Detailed Implementation

[0044] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0045] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0046] Please refer to the reference. Figures 1-3 , Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this disclosure. Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure for a mid-pixel circuit. Figure 3 yes Figure 1 A partially enlarged schematic diagram of the pixel circuit in region J1 (understandably, this is for the purpose of clearly illustrating the structure of this embodiment). Figure 1 (The pixel circuit is represented by a frame diagram in the figure). This embodiment provides a display panel 000, which includes a plurality of pixel circuits 10. Each pixel circuit 10 includes a driving transistor DT and a first transistor T1 that are electrically connected.

[0047] The plurality of pixel circuits 10 include at least a first pixel circuit 101, a second pixel circuit 102, a third pixel circuit 103, and a fourth pixel circuit 104;

[0048] The display panel 000 includes a plurality of pixel circuit columns 10A arranged sequentially along the first direction X. Each pixel circuit column 10A includes a first pixel circuit column 10A1, a second pixel circuit column 10A2, a third pixel circuit column 10A3, and a fourth pixel circuit column 10A4.

[0049] The first pixel circuit column 10A1 includes a plurality of first pixel circuits 101, the second pixel circuit column 10A2 includes a plurality of second pixel circuits 102, the third pixel circuit column 10A3 includes a plurality of third pixel circuits 103, and the fourth pixel circuit column 10A4 includes a plurality of fourth pixel circuits 104.

[0050] The channel width W1 of the first transistor T1 in the first pixel circuit 101 is different from the channel width W2 of the first transistor T1 in the second pixel circuit 102. The channel width W3 of the first transistor T1 in the third pixel circuit 103 is different from the channel width W4 of the first transistor T1 in the fourth pixel circuit 104. The channel width W1 of the first transistor T1 in the first pixel circuit 101 is equal to the channel width W3 of the first transistor T1 in the third pixel circuit 103. The channel width W2 of the first transistor T1 in the second pixel circuit 102 is equal to the channel width W4 of the first transistor T1 in the fourth pixel circuit 104.

[0051] The display panel 000 includes a plurality of light-emitting devices 20, which include a first color light-emitting device 201, a second color light-emitting device 202 and a third color light-emitting device 203;

[0052] The first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, the second pixel circuit 102 drives the second color light-emitting device 202, the third pixel circuit 103 drives the second color light-emitting device 202, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201.

[0053] Specifically, the display panel 000 provided in this embodiment can be an organic light-emitting diode (OLED) display panel. The display panel 000 may include a substrate, which serves as a carrier substrate for setting pixel circuits, light-emitting devices, and other structures of the display panel 000. It is understood that this embodiment does not elaborate on the film layer structure of the display panel 000. When the display panel 000 is an OLED display panel, the pixel circuit 10 included in the display panel 000 can be fabricated by a driving array layer on the substrate. The pixel circuit 10 or other driving circuits, such as thin-film transistor structures, capacitor structures, and driving traces, are set through multiple conductive layers and insulating layers included in the driving array layer. The light-emitting device 20 can be disposed on the side of the driving array layer away from the substrate. An anode can also be disposed between the light-emitting device and the driving array layer. This embodiment does not elaborate on these details; for specific understanding, please refer to the film layer structure of OLED display panels in related technologies.

[0054] like Figure 2 As shown, the pixel circuit 10 of this embodiment includes at least a driving transistor DT and a first transistor T1 electrically connected. The driving transistor DT and the first transistor T1 are used to generate a driving current and provide it to the light-emitting device 20 electrically connected to the pixel circuit 10, thereby causing the light-emitting device 20 to emit light and display. It can be understood that the first transistor T1 in this embodiment can be any transistor electrically connected to one terminal of the driving transistor DT. For example, in the related art, the pixel circuit 10 includes a structure of 7 transistors and 1 capacitor. Then, the first transistor T1 can be understood as any one of the 7 transistors other than the driving transistor DT that is electrically connected to one terminal (gate, source, or drain) of the driving transistor DT.

[0055] like Figure 3As shown, along the first direction X, which can be understood as the direction from one edge of the display panel 000 to the opposite edge, the display panel 000 includes multiple pixel circuit columns 10A arranged sequentially along the first direction X. A pixel circuit column 10A includes a first pixel circuit column 10A1, a second pixel circuit column 10A2, a third pixel circuit column 10A3, and a fourth pixel circuit column 10A4. That is, a pixel circuit column 10A includes a first pixel circuit column 10A1, a second pixel circuit column 10A2, a third pixel circuit column 10A3, and a fourth pixel circuit column 10A4 arranged sequentially along the first direction X. The first pixel circuit column 10A1, the second pixel circuit column 10A2, the third pixel circuit column 10A3, and the fourth pixel circuit column 10A4 can be understood as four adjacent pixel circuit columns in the first direction X, thus forming a pixel circuit column 10A. The display panel 000 includes multiple pixel circuits 10, including at least a first pixel circuit 101, a second pixel circuit 102, a third pixel circuit 103, and a fourth pixel circuit 104. The first pixel circuit column 10A1 includes multiple first pixel circuits 101, the second pixel circuit column 10A2 includes multiple second pixel circuits 102, the third pixel circuit column 10A3 includes multiple third pixel circuits 103, and the fourth pixel circuit column 10A4 includes multiple fourth pixel circuits 104. That is, multiple first pixel circuits 101 constitute the first pixel circuit column 10A1, multiple second pixel circuits 102 constitute the second pixel circuit column 10A2, multiple third pixel circuits 103 constitute the third pixel circuit column 10A3, and multiple fourth pixel circuits 104 constitute the fourth pixel circuit column 10A4.

[0056] In the manufacturing process of display panels, especially in the pixel circuit process, errors are often easily generated due to process fluctuations. For example, in a pixel circuit group 10A consisting of four adjacent pixel circuit columns in the first direction X, the channel width W1 of the first transistor T1 of the first pixel circuit 101 is different from the channel width W2 of the first transistor T1 of the second pixel circuit 102, the channel width W3 of the first transistor T1 of the third pixel circuit 103 is different from the channel width W4 of the first transistor T1 of the fourth pixel circuit 104, the channel width W1 of the first transistor T1 of the first pixel circuit 101 is equal to the channel width W3 of the first transistor T1 of the third pixel circuit 103, and the channel width W2 of the first transistor T1 of the second pixel circuit 102 is equal to the channel width W4 of the first transistor T1 of the fourth pixel circuit 104. It is understandable that, for example... Figure 3 As shown, to clearly illustrate the channel region of the first transistor T1, Figure 3Other film layers in the pixel circuit are simplified and not shown. In specific implementations, the pixel circuit may also include other conductive film layers, which will not be elaborated here. The gate T1G and semiconductor part T1P of the first transistor T1 overlap to form a channel region. The scan line G1 corresponding to the gate T1G is considered to extend along the first direction X, and the semiconductor part T1P of the first transistor T1 is considered to extend along the second direction Y. The first direction X and the second direction Y intersect or are perpendicular to each other. For example, the first direction X is... Figure 3 If the horizontal direction is given, then the second direction Y is... Figure 3 In the vertical direction, the channel width of the first transistor T1 is the width of the semiconductor portion T1P of the first transistor T1 in the first direction X. The overall extension direction of the scan line G1 corresponding to the gate T1G of the first transistor T1 is the same.

[0057] It is understood that in this embodiment Figure 3 The structure of the pixel circuit 10 is merely an example, intended to clearly illustrate the channel width of the first transistor T1 in the pixel circuit. In specific implementations, the circuit layout structure of the pixel circuit 10 can be based on the actual electrical connection structure of the pixel circuit, and this embodiment does not limit it in this regard.

[0058] like Figure 4 As shown, Figure 4This is a schematic diagram of the layout structure of pixel circuits and light-emitting devices provided in the prior art. In the prior art, under the interference of process fluctuations, in multiple repeating pixel circuit groups 10A', the channel width W1' of the first transistor T1' of the first pixel circuit 101' is different from the channel width W2' of the first transistor T1' of the second pixel circuit 102', and the channel width W3' of the first transistor T1' of the third pixel circuit 103' is different from the channel width W4' of the first transistor T1' of the fourth pixel circuit 104'. The driving transistor DT' is used to generate driving current. The difference in the channel width of the first transistor T1' electrically connected to the driving transistor DT' will cause different coupling capacitances, which in turn will cause differences in driving current. For example, the channel width W1' of the first transistor T1' of the first pixel circuit 101' is small and always... Corresponding to driving the red light-emitting device R' or the blue light-emitting device B', the channel width W2' of the first transistor T1' of the second pixel circuit 102' is large and always corresponds to driving the green light-emitting device G'. The channel width W3' of the first transistor T1' of the third pixel circuit 103' is small and always corresponds to driving the red light-emitting device R' or the blue light-emitting device B'. The channel width W4' of the first transistor T1' of the fourth pixel circuit 104' is large and always corresponds to driving the green light-emitting device G'. Therefore, the coupling capacitance in the second pixel circuit 102' and the fourth pixel circuit 104' with the large channel width W1' of the first transistor T1' is large, and the driving current generated is large. That is, the driving current received by the green light-emitting device G' is large, the brightness of the green light-emitting device G' is brighter, and the color is greener, which will cause greening under high brightness display and produce color shift problem.

[0059] Similarly, if the first transistor in the first pixel circuit has a large channel width and continuously drives either the red or blue light-emitting device, the first transistor in the second pixel circuit has a small channel width and continuously drives the green light-emitting device, the first transistor in the third pixel circuit has a large channel width and continuously drives either the red or blue light-emitting device, and the first transistor in the fourth pixel circuit has a small channel width and continuously drives the green light-emitting device, then the coupling capacitance in the first pixel circuit and the third pixel circuit with the large channel width of the first transistor will be large, resulting in a large driving current. That is, the red or blue light-emitting device will receive a large driving current, making the color more pink. This will cause a pinkish tint under high brightness display, resulting in a color shift problem.

[0060] like Figure 5 As shown in Table 1, Figure 5 yes Figure 4 Table 1 illustrates the curves showing the pink or green tint caused by differences in the driving current of different pixel circuits. Figure 4The difference in the channel width of the first transistor in different pixel circuits of the display panel can cause the CIEy value to be too small, resulting in a pinkish hue, or the CIEy value to be too large, resulting in a greenish hue. (It can be understood that CIEy refers to the Y coordinate value in the color space, which is usually used to represent the brightness or lightness of a color. In the CIE XYZ color space, the Y coordinate represents the brightness component of light, while the X and Z coordinates represent the red and blue color components, respectively.)

[0061] Table 1:

[0062]

[0063] Specifically, by Figure 5 As shown in Table 1, Figure 4 In the illustrated repeating array of pixel circuits 10A', if the channel width W1' of the first transistor T1' in the first pixel circuit 101' is large and consistently drives either the red light-emitting device R' or the blue light-emitting device B', the channel width W2' of the first transistor T1' in the second pixel circuit 102' is small and consistently drives either the green light-emitting device G', the channel width W3' of the first transistor T1' in the third pixel circuit 103' is large and consistently drives either the red light-emitting device R' or the blue light-emitting device B', and the channel width W4' of the first transistor T1' in the fourth pixel circuit 104' is small and consistently drives either the green light-emitting device G', then the coupling capacitance in the first pixel circuit 101' and the third pixel circuit 103' with the larger channel width of the first transistor T1' is larger, resulting in a larger driving current. This means the driving current received by the red light-emitting device R' or the blue light-emitting device B' is larger, while the driving current received by the green light-emitting device G' is smaller, resulting in a pinker color (e.g., ...). Figure 5 The diagram illustrates the driving current magnitude for pink color shift. A negative CIEy value indicates a pinkish tint (as shown in the row of Table 1 indicating pinkish tint, illustrating the brightness and chromaticity values). This means the light-emitting device areas driven by the first pixel circuit 101' and the second pixel circuit 102' are consistently pinkish, as are the areas driven by the third pixel circuit 103' and the fourth pixel circuit 104', resulting in an overall pinkish color shift in the display panel. Similarly, if... Figure 4In the schematic repeating array of multiple pixel circuits 10A', the channel width W1' of the first transistor T1' in the first pixel circuit 101' is small and always corresponds to driving the red light-emitting device R' or the blue light-emitting device B'; the channel width W2' of the first transistor T1' in the second pixel circuit 102' is large and always corresponds to driving the green light-emitting device G'; the channel width W3' of the first transistor T1' in the third pixel circuit 103' is small and always corresponds to driving the red light-emitting device R' or the blue light-emitting device B'; and the channel width W4' of the first transistor T1' in the fourth pixel circuit 104' is large and always corresponds to driving the green light-emitting device G'. Therefore, the coupling capacitance in the second pixel circuit 102' and the fourth pixel circuit 104', where the channel width of the first transistor T1' is large, is large, resulting in a large driving current. This means that the driving current received by the red light-emitting device R' or the blue light-emitting device B' is small, while the driving current received by the green light-emitting device G' is large, resulting in a greener color (e.g., ...). Figure 5 The green color shift indicates the magnitude of the driving current. A positive CIEy value indicates a greenish tint (as shown in the row of Table 1 where the color shift is greenish, indicating the brightness and chromaticity values). This means that the light-emitting device areas driven by the first pixel circuit 101' and the second pixel circuit 102' are always greenish, and the light-emitting device areas driven by the third pixel circuit 103' and the fourth pixel circuit 104' are also always greenish, resulting in a greenish color shift problem for the entire display panel.

[0064] To solve the above problems, such as Figures 1-3 , Figure 6 As shown, Figure 6 yes Figure 1 This is a partially enlarged schematic diagram of the pixel circuits and light-emitting devices arranged in the J1 region. In this embodiment, the display panel 000 includes multiple light-emitting devices 20, and the multiple light-emitting devices 20 include a first-color light-emitting device 201, a second-color light-emitting device 202, and a third-color light-emitting device 203. Figure 6(Different colors are distinguished by different fill patterns). The first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203. The second pixel circuit 102 drives the second color light-emitting device 202. The third pixel circuit 103 drives the second color light-emitting device 202. The fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201. That is, multiple first pixel circuits 101 form a first pixel circuit column 10A1, and multiple second pixel circuits 102 form a second pixel circuit column 10A2. The channel width W1 of the first transistor T1 of the first pixel circuit 101 is different from the channel width W2 of the first transistor T1 of the second pixel circuit 102. The first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, and the second pixel circuit 102 drives the second color light-emitting device 202. The multiple third pixel circuits 103 form a third pixel circuit column 10A3. The fourth pixel circuit 104 constitutes the fourth pixel circuit array 10A4. The channel width W3 of the first transistor T1 of the third pixel circuit 103 is different from the channel width W4 of the first transistor T1 of the fourth pixel circuit 104. The channel width W3 of the first transistor T1 of the third pixel circuit 103 is the same as the channel width W1 of the first transistor T1 of the first pixel circuit 101. The channel width W4 of the first transistor T1 of the fourth pixel circuit 104 is the same as the channel width W2 of the first transistor T1 of the second pixel circuit 102. At this time, the color of the light-emitting device driven by the third pixel circuit 103 is different from the color of the light-emitting device driven by the first pixel circuit 101. The third pixel circuit 103 drives the second color light-emitting device 202. The color of the light-emitting device driven by the fourth pixel circuit 104 is different from the color of the light-emitting device driven by the second pixel circuit 102. The fourth pixel circuit 104 drives either the third color light-emitting device 203 or the first color light-emitting device 201.

[0065] Therefore, if the channel width W1 of the first transistor T1 of the first pixel circuit 101 is greater than the channel width W2 of the first transistor T1 of the second pixel circuit 102, then the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the first pixel circuit 101 is large, and the driving current of the second color light-emitting device 202 driven by the second pixel circuit 102 is small. The light-emitting areas corresponding to the first pixel circuit 101 and the second pixel circuit 102 may be biased towards the color of the first color light-emitting device 201 or the third color light-emitting device 203. Conversely, if the channel width W3 of the first transistor T1 of the third pixel circuit 103 is greater than the channel width W4 of the first transistor T1 of the fourth pixel circuit 104, then the driving current of the second color light-emitting device 202 driven by the third pixel circuit 103 is large, and the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the fourth pixel circuit 104 is small. The light-emitting areas corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 may be biased towards the color of the second color light-emitting device 202. Therefore, in the light-emitting area corresponding to a pixel circuit group 10A formed by four adjacent pixel circuit groups in the first direction X, the color shift of the light-emitting area corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 neutralizes the color shift of the light-emitting area corresponding to the first pixel circuit 101 and the second pixel circuit 102, thereby improving the color shift problem and enhancing the display quality in the overall visual effect.

[0066] Similarly, if the channel width W1 of the first transistor T1 in the first pixel circuit 101 is smaller than the channel width W2 of the first transistor T1 in the second pixel circuit 102, then the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the first pixel circuit 101 is small, and the driving current of the second color light-emitting device 202 driven by the second pixel circuit 102 is large. The light-emitting areas corresponding to the first pixel circuit 101 and the second pixel circuit 102 may be biased towards the color of the second color light-emitting device 202. Conversely, if the channel width W3 of the first transistor T1 in the third pixel circuit 103 is smaller than the channel width W4 of the first transistor T1 in the fourth pixel circuit 104, then the driving current of the second color light-emitting device 202 driven by the third pixel circuit 103 is small, and the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the fourth pixel circuit 104 is large. The light-emitting areas corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 may be biased towards the color of the first color light-emitting device 201 or the third color light-emitting device 203. Therefore, in the light-emitting area corresponding to a pixel circuit group 10A formed by four adjacent pixel circuit groups in the first direction X, the color shift of the light-emitting area corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 neutralizes the color shift of the light-emitting area corresponding to the first pixel circuit 101 and the second pixel circuit 102, thereby improving the overall visual effect, reducing the mura problem, and improving the display quality.

[0067] The structure for improving color deviation in this embodiment requires minimal modification to the layout of the display panel 000. It does not require changes to the layout of the pixel circuits or the light-emitting devices, nor does it require complex brightness compensation methods. It only requires that in a pixel circuit group 10A consisting of four adjacent pixel circuits in the first direction X, the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, the second pixel circuit 102 drives the second color light-emitting device 202, and the third pixel circuit 103 drives the second color light-emitting device 202. The fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201. That is, changing the color of the light-emitting device driven by the third pixel circuit 103 and changing the color of the light-emitting device driven by the fourth pixel circuit 104 can improve the color deviation problem. The structure and process are relatively simple, which is beneficial to improving process efficiency.

[0068] It is understood that in this embodiment, the first pixel circuit 101 driving the first color light-emitting device 201 or the third color light-emitting device 203 means that the first pixel circuits 101 located in different rows can drive light-emitting devices of different colors. For example, if the first pixel circuit 101 in the first row drives the first color light-emitting device 201, then the first pixel circuit 101 in the second row drives the third color light-emitting device 203. Similarly, the fourth pixel circuit 104 driving the third color light-emitting device 203 or the first color light-emitting device 201 means that the fourth pixel circuit 104 located in different rows can drive light-emitting devices of different colors. For example, if the fourth pixel circuit 104 in the first row drives the third color light-emitting device 203, then the fourth pixel circuit 104 in the second row drives the first color light-emitting device 201. Furthermore, the first pixel circuit 101 and the fourth pixel circuit 104 in the same row drive light-emitting devices of different colors. For example, if the first pixel circuit 101 in the first row drives the first color light-emitting device 201, then the fourth pixel circuit 104 in the first row drives the third color light-emitting device 203; if the first pixel circuit 101 in the second row drives the third color light-emitting device 203, then the fourth pixel circuit 104 in the second row drives the first color light-emitting device 201.

[0069] It is understood that the arrangement of the plurality of light-emitting devices 20 included in the display panel 000 in this embodiment can adopt the arrangement method in the prior art. Figure 6 This is just an example; in actual implementation, other known arrangement methods can be used.

[0070] Optionally, in this embodiment, the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, the second pixel circuit 102 drives the second color light-emitting device 202, the third pixel circuit 103 drives the second color light-emitting device 202, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201. This driving can be achieved through connecting lines, such as... Figure 6As shown, the first pixel circuit 101 is electrically connected to and drives either the first color light-emitting device 201 or the third color light-emitting device 203 via connecting line L1. The second pixel circuit 102 is electrically connected to and drives the second color light-emitting device 202 via connecting line L2. The third pixel circuit 103 is electrically connected to and drives the second color light-emitting device 202 via connecting line L3. The fourth pixel circuit 104 is electrically connected to and drives either the third color light-emitting device 203 or the first color light-emitting device 201 via connecting line L4. This results in the light-emitting device driven by the third pixel circuit 103 having a different color than the light-emitting device driven by the first pixel circuit 101, and the light-emitting device driven by the third pixel circuit 103 having a different color than the second pixel circuit 201. The light-emitting devices driven by circuit 102 have the same color. The light-emitting device driven by the fourth pixel circuit 104 has a different color than the light-emitting device driven by the second pixel circuit 102. The light-emitting device driven by the fourth pixel circuit 104 has the same color as the light-emitting device driven by the first pixel circuit 101. In the light-emitting area corresponding to a pixel circuit group 10A formed by four adjacent pixel circuit groups in the first direction X, the color shift of the light-emitting area corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 neutralizes the color shift of the light-emitting area corresponding to the first pixel circuit 101 and the second pixel circuit 102. This can improve the color shift problem and enhance the display quality in terms of overall visual effect.

[0071] It should be noted that in this embodiment... Figures 1-3 , Figure 6 The diagram only illustrates the structure of the display panel 000. In actual implementation, the structure of the display panel includes, but is not limited to, this. The structure of the display panel in this embodiment is also just an example. In actual implementation, the structure of the display panel does not represent the shape, quantity, or area shown in the diagram. Figure 6 The shape of the light-emitting device 20 shown is only an example, and the shape and layout of the pixel circuit 10 are also only examples. In actual implementation, the design can be based on actual needs.

[0072] Optional, such as Figure 6 As shown, the first color light-emitting device 201 is either a red light-emitting device or a blue light-emitting device, and the third color light-emitting device 203 is either a red light-emitting device or a blue light-emitting device; the second color light-emitting device 202 is a green light-emitting device. Taking the example of the first color light-emitting device 201 being a red light-emitting device, the second color light-emitting device 202 being a green light-emitting device, and the third color light-emitting device 203 being a blue light-emitting device.

[0073] If the channel width W1 of the first transistor T1 in the first pixel circuit 101 is greater than the channel width W2 of the first transistor T1 in the second pixel circuit 102, then the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the first pixel circuit 101 is large, and the driving current of the second color light-emitting device 202 driven by the second pixel circuit 102 is small. The light-emitting areas corresponding to the first pixel circuit 101 and the second pixel circuit 102 (such as...) Figure 6 The K1 region shown may be biased towards the color of the first color light-emitting device 201 or the third color light-emitting device 203, i.e., pinkish. Since the channel width W3 of the first transistor T1 in the third pixel circuit 103 is greater than the channel width W4 of the first transistor T1 in the fourth pixel circuit 104, the driving current of the second color light-emitting device 202 driven by the third pixel circuit 103 is large, while the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the fourth pixel circuit 104 is small. Therefore, the light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 (such as...) Figure 6 The K2 region shown may be biased towards the color of the second color light-emitting device 202, i.e., leaning towards green. Therefore, in the light-emitting region corresponding to a pixel circuit group 10A consisting of four adjacent pixel circuit groups in the first direction X, the green bias of the light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 neutralizes the pink bias of the light-emitting regions corresponding to the first pixel circuit 101 and the second pixel circuit 102, thereby improving the overall visual effect, enhancing the color shift problem, and improving the display quality.

[0074] Similarly, if the channel width W1 of the first transistor T1 in the first pixel circuit 101 is smaller than the channel width W2 of the first transistor T1 in the second pixel circuit 102, then the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the first pixel circuit 101 is small, and the driving current of the second color light-emitting device 202 driven by the second pixel circuit 102 is large. The light-emitting areas corresponding to the first pixel circuit 101 and the second pixel circuit 102 may be biased towards the color of the second color light-emitting device 202, i.e., leaning towards green. Conversely, if the channel width W3 of the first transistor T1 in the third pixel circuit 103 is smaller than the channel width W4 of the first transistor T1 in the fourth pixel circuit 104, then the driving current of the second color light-emitting device 202 driven by the third pixel circuit 103 is small, and the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the fourth pixel circuit 104 is large. The light-emitting areas corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 may be biased towards the color of the first color light-emitting device 201 or the third color light-emitting device 203, i.e., leaning towards pink. Therefore, in the light-emitting area corresponding to a pixel circuit group 10A formed by four adjacent pixel circuit groups in the first direction X, the pinkish tint of the light-emitting area corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 neutralizes the greenish tint of the light-emitting area corresponding to the first pixel circuit 101 and the second pixel circuit 102, thereby improving the color shift problem and enhancing the display quality in the overall visual effect.

[0075] Optional, such as Figure 3 and Figure 6As shown, in this embodiment, during the manufacturing process of the display panel 000, especially in the manufacturing process of the pixel circuit 10, errors are easily generated due to process fluctuations. This results in the following differences in the channel width W1 of the first transistor T1 of the first pixel circuit 101 and the channel width W2 of the first transistor T1 of the second pixel circuit 102, and the channel width W3 of the first transistor T1 of the third pixel circuit 103 and the channel width W4 of the first transistor T1 of the fourth pixel circuit 104, in a pixel circuit group 10A composed of four adjacent pixel circuits in the first direction X. Furthermore, the channel width W1 of the first transistor T1 of the first pixel circuit 101 is equal to the channel width W3 of the first transistor T1 of the third pixel circuit 103, and the channel width W2 of the first transistor T1 of the second pixel circuit 102 is equal to the channel width W4 of the fourth pixel circuit 104. The channel width W4 of the first transistor T1 in circuit 104 is an unavoidable difference caused by process fluctuations. However, by adjusting the process, these fluctuations can be minimized. For example, the channel width W1 of the first transistor T1 in the first pixel circuit 101 and the channel width W2 of the first transistor T1 in the second pixel circuit 102 can be achieved with a difference range of |W1-W2| ≤ 0.1μm. Similarly, the channel width W3 of the first transistor T1 in the third pixel circuit 103 and the channel width W4 of the first transistor T1 in the fourth pixel circuit 104 can be achieved with a difference range of |W3-W4| ≤ 0.1μm. This minimizes the difference in driving current between different pixel circuits 10 caused by process fluctuations within the adjustable range of the process, which helps to improve color shift, enhance visual effects, and improve display quality.

[0076] It is understood that this embodiment and subsequent embodiments use the example of the first transistor T1 of the first pixel circuit 10 having a channel width W1 smaller than the first transistor T1 of the second pixel circuit 102 having a channel width W2 smaller than the first transistor T1 of the third pixel circuit 103 having a channel width W3 smaller than the first transistor T1 of the fourth pixel circuit 104 for illustrative purposes. In specific implementation, the channel width W1 of the first transistor T1 of the first pixel circuit 10 may also be larger than the channel width W2 of the first transistor T1 of the second pixel circuit 102, and the channel width W3 of the first transistor T1 of the third pixel circuit 103 may also be larger than the channel width W4 of the first transistor T1 of the fourth pixel circuit 104. This embodiment does not impose any limitation on this.

[0077] In some alternative embodiments, please refer to the references. Figure 1 , Figure 3 , Figure 6 and Figure 7 , Figure 7 yes Figure 1A schematic diagram of another electrical connection structure for the pixel circuit is shown. In this embodiment, the first transistor T1 is electrically connected between the gate and the first terminal of the driving transistor DT. The first transistor T1 is an N-type transistor. Optionally, the first transistor T1 can be an N-type metal-oxide-semiconductor transistor, while the other transistors in the pixel circuit 10 can be P-type low-temperature polysilicon transistors. Figure 7 As shown, the pixel circuit 10 in this embodiment includes 8 transistors and 1 storage capacitor Cst as an example. The first transistor T1 can be... Figure 7 The first transistor T1 is a threshold compensation transistor electrically connected between the gate (first node N1) and the first terminal (third node N3) of the driving transistor DT; or in some other alternative embodiments, the first transistor T1 may also be... Figure 7 The transistor connected between the gate (first node N1) of the driving transistor DT and the first reference voltage signal terminal REF1 is a transistor that resets the gate of the driving transistor DT. It should be noted that in this embodiment, the first transistor T1 is electrically connected between the gate of the driving transistor DT and its first terminal. The first terminal of the driving transistor DT can be either the drain or the source, and the second terminal of the driving transistor DT can be either the drain or the source. This embodiment does not limit this; the figure only illustrates the example where the first terminal is the drain.

[0078] This embodiment uses Figure 7Taking the pixel circuit 10 shown as an example, in different pixel circuits 10, the channel width of the first transistor T1, which plays a threshold compensation role and is electrically connected between the gate (first node N1) and the first electrode (third node N3) of the driving transistor DT, varies slightly due to process fluctuations. For example, the channel width W1 of the first transistor T1 in the first pixel circuit 10 is less than the channel width W2 of the first transistor T1 in the second pixel circuit 102, the channel width W3 of the first transistor T1 in the third pixel circuit 103 is less than the channel width W4 of the first transistor T1 in the fourth pixel circuit 104, and the channel width W1 of the first transistor T1 in the first pixel circuit 10 is equal to the channel width W3 of the first transistor T1 in the third pixel circuit 103, and the channel width W2 of the first transistor T1 in the second pixel circuit 102 is equal to the channel width W4 of the first transistor T1 in the fourth pixel circuit 104. In the light-emitting stage of the driving process, the first transistor T1 is turned off. Since the first transistor T1 is an N-type transistor, the gate of the first transistor T1 is at a low potential. The potentials of the first node N1 and the third node N3 will be pulled low due to the coupling of the gate potential of the first transistor T1 (there is a coupling capacitance C' between the gate of the first node N1 and the gate of the first transistor T1, which is represented by a dashed line). The parasitic capacitance of the third node N3 is very small, meaning that the potential of the third node N3 will be pulled very low. However, during the process of pulling down the potential, it is still necessary to maintain the charge balance between the first node N1 and the third node N3. Therefore, the potential of the first node N1 will also be pulled very low along with the third node N3. If the channel width W2 of the first transistor T1 of the second pixel circuit 102 is larger, then the potential of the first node N1 of the second pixel circuit 102 will be pulled down even lower than that of the first node N1 of the first pixel circuit 101. As a result, the driving current on the driving transistor DT of the second pixel circuit 102 will be larger, and the light emission brightness will be brighter. That is, the second color light-emitting device 202 driven by the second pixel circuit 102 will be brighter. This will cause the light-emitting area driven by the second pixel circuit 102 to be more biased towards the color of the second color light-emitting device 202, such as green.

[0079] In some other alternative embodiments, if the first transistor T1 is Figure 7 The transistor connected between the gate (first node N1) of the driving transistor DT and the first reference voltage signal terminal REF1 serves to reset the gate of the driving transistor DT. The principle of color shift caused by the difference in driving current is the same as above, and will not be repeated here in this embodiment.

[0080] by Figure 7 Taking the pixel circuit 10 shown as an example, combined with Figure 8 , Figure 8 yes Figure 7A timing diagram of the operation of the pixel circuit. In this embodiment, the display panel 000 may include a first bias voltage adjustment stage tj1, a reset stage tj2, a threshold compensation and data writing stage tj3, a second bias voltage adjustment stage tj4, and a light emission stage tj5 when it is driven.

[0081] In the first bias adjustment stage tj1, that is, before the gate of the driving transistor DT is reset, the bias control signal terminal SCP* is given a low-level bias control signal to control the fourth transistor T4 to turn on, and the second scan signal terminal SCN2 is given a high-level second scan signal to control the first transistor T1 to turn on. Then the bias adjustment signal provided by the bias adjustment signal terminal DVH is transmitted to the gate of the driving transistor DT (i.e., the first node N1) through the fourth transistor T4 and the first transistor T1. The bias state of the driving transistor DT is adjusted for the first time, so that the driving transistor DT is reverse biased, the source and drain of the driving transistor DT are reversed, the degree of ion polarization inside the driving transistor DT is reduced, and the threshold voltage of the driving transistor DT is reduced. The threshold voltage of the driving transistor DT is adjusted by biasing the driving transistor DT to compensate for the threshold voltage drift problem caused by the hysteresis effect of the driving transistor due to the forward bias state of the driving transistor DT. Furthermore, at this time, the bias control signal terminal SCP* inputs a low-level bias control signal, which can also control the fifth transistor T5 to turn on. The second reference voltage signal terminal REF2 resets the anode (i.e., the fourth node N4) of the light-emitting device 20 through the fifth transistor T5, thereby initializing the anode of the light-emitting element 20. This can improve the retention of the previous frame data signal, improve the afterimage phenomenon, and enhance the display effect of the display panel 000.

[0082] During the reset phase tj2, the first scan signal terminal SCN1 is given a high-level first scan signal to control the second transistor T2 to turn on, and the second reference voltage signal terminal REF2 resets the gate of the driving transistor DT (i.e. the first node N1) and refreshes the gate potential of the driving transistor DT in the previous frame.

[0083] During the threshold compensation and data writing stage tj3, the third scan signal terminal SCP inputs a low-level third scan signal to control the third transistor T3 to turn on, and the second scan signal terminal SCN2 inputs a high-level second scan signal to control the first transistor T1 to turn on. The data line of the display panel provides the data voltage VDATA, which is transmitted to the gate of the driving transistor DT through the third transistor T3, the driving transistor DT, and the first transistor T1 to perform threshold compensation on the driving transistor DT and self-compensate for the deviation of the threshold voltage of the driving transistor DT.

[0084] In the second bias adjustment stage tj4, the bias control signal terminal SCP* inputs a low-level bias control signal to control the fourth transistor T4 to turn on. The bias adjustment signal provided by the bias adjustment signal terminal DVH is transmitted through the fourth transistor T4 to the source of the driving transistor DT (i.e., the second node N2), and the bias state of the driving transistor DT is adjusted for the second time.

[0085] During the light-emitting stage tj5, a low-level light-emitting control signal is input to the light-emitting control signal terminal EM to control the sixth transistor T6 and the seventh transistor T7 to turn on. The driving transistor DT generates a driving current under the control of its gate voltage. A conductive path is formed between the first power supply signal terminal PVDD, the sixth transistor T6, the driving transistor DT, the seventh transistor T7, the light-emitting device 20, and the second power supply signal terminal PVEE. The driving current is provided to the light-emitting device 20 to control the light-emitting device 20 to emit light.

[0086] Optionally, in this embodiment, the transistor in the pixel circuit 10 that is electrically connected to the anode of the light-emitting device 20 and drives it to emit light is the seventh transistor T7, and the fifth transistor T5 is also electrically connected to the anode of the light-emitting device 20 for reset.

[0087] It is understood that in this embodiment Figure 7 The provided electrical connection structure of the pixel circuit 10 is only an example. In specific implementations, the electrical connection structure of the pixel circuit 10 includes, but is not limited to, this, and may also be other circuit structures.

[0088] In some alternative embodiments, please continue to refer to the references. Figure 1 , Figure 3 and Figure 6 In this embodiment, in the first direction X, the first pixel circuit 101 of the first pixel circuit column 10A1 is mirror-symmetrical to the second pixel circuit 102 of the second pixel circuit column 10A2, and the third pixel circuit 103 of the third pixel circuit column 10A3 is mirror-symmetrical to the fourth pixel circuit 104 of the fourth pixel circuit column 10A4.

[0089] This embodiment explains that the pixel circuit 10 layout structure of the display panel 000 can be a mirror-symmetric structure of two adjacent pixel circuits 10. For example, in the first direction X, the first pixel circuit 101 of the first pixel circuit column 10A1 is mirror-symmetric with the second pixel circuit 102 of the second pixel circuit column 10A2, and the third pixel circuit 103 of the third pixel circuit column 10A3 is mirror-symmetric with the fourth pixel circuit 104 of the fourth pixel circuit column 10A4, which is beneficial to save the layout space of the panel. It is understood that the mirror symmetry in this embodiment is not a strict, complete consistency. It can be understood that in the first direction X, the first pixel circuit 101 of the first pixel circuit column 10A1 and the second pixel circuit 102 of the second pixel circuit column 10A2 are approximately mirror-symmetrical, and the third pixel circuit 103 of the third pixel circuit column 10A3 and the fourth pixel circuit 104 of the fourth pixel circuit column 10A4 are approximately mirror-symmetrical. That is, in actual manufacturing, due to process fluctuations, the dimensions, widths, and other structures of each film layer may not be strictly symmetrical. However, in the first direction X, the corresponding transistor and capacitor structures in the first pixel circuit 101 of the first pixel circuit column 10A1 are symmetrical to the corresponding transistor and capacitor structures in the second pixel circuit 102 of the second pixel circuit column 10A2. In actual manufacturing, the width of the semiconductor layer of the semiconductor part of the thin-film transistor used to fabricate the pixel circuit may vary due to process fluctuations, easily leading to the color shift problem caused by differences in the driving current of different pixel circuits, which is the focus of this embodiment.

[0090] In some alternative embodiments, please refer to the references. Figure 1 , Figure 3 , Figure 9 and Figure 10 , Figure 9 yes Figure 1 A magnified schematic diagram of the arrangement of light-emitting devices in a certain area. Figure 10 yes Figure 3 pixel circuit and Figure 9 A schematic diagram of a layout structure combining light-emitting devices (it can be understood that, for the purpose of clearly illustrating the structure of this embodiment, Figure 10 (The light-emitting devices in the middle are filled with transparency). In this embodiment, the display panel 000 includes a plurality of light-emitting device columns 20A arranged sequentially along the first direction X; a light-emitting device column 20A includes a first light-emitting device column 20A1, a second light-emitting device column 20A2, a third light-emitting device column 20A3 and a fourth light-emitting device column 20A4 arranged sequentially along the first direction X.

[0091] Along the second direction Y, the first light-emitting device column 20A1 includes a plurality of alternating first-color light-emitting devices 201 and third-color light-emitting devices 203; the second light-emitting device column 20A2 includes a plurality of second-color light-emitting devices 202; the third light-emitting device column 20A3 includes a plurality of alternating third-color light-emitting devices 203 and first-color light-emitting devices 201; and the fourth light-emitting device column 20A4 includes a plurality of second-color light-emitting devices 202. The first direction X and the second direction Y intersect on a plane parallel to the display panel 000. This embodiment illustrates the example where the first direction X and the second direction Y are perpendicular to each other on a plane parallel to the display panel 000.

[0092] Multiple pixel circuits 10 are arranged along the first direction X to form a pixel circuit row 10H;

[0093] Along the second direction Y, in the i-th pixel circuit row 10H(i), the first pixel circuit 101 is electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1, the second pixel circuit 102 is electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2, the third pixel circuit 103 is electrically connected to the second color light-emitting device 202 of the fourth light-emitting device column 20A4, and the fourth pixel circuit 104 is electrically connected to the third color light-emitting device 203 of the third light-emitting device column 20A3; where i is a positive integer.

[0094] Optionally, along the second direction Y, in the (i+1)th pixel circuit row 10H(i+1), the first pixel circuit 101 is electrically connected to the third color light-emitting device 203 of the first light-emitting device column 20A1, the second pixel circuit 102 is electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2, the third pixel circuit 103 is electrically connected to the second color light-emitting device 202 of the fourth light-emitting device column 20A4, and the fourth pixel circuit 104 is electrically connected to the first color light-emitting device 201 of the third light-emitting device column 20A3.

[0095] This embodiment explains that when the display panel 000 includes multiple light-emitting devices 20, and the multiple light-emitting devices 20 include a first color light-emitting device 201, a second color light-emitting device 202, and a third color light-emitting device 203 ( Figure 9(Different colors are distinguished by different fill patterns). The arrangement of multiple light-emitting devices 20 can be a first light-emitting device column 20A1, a second light-emitting device column 20A2, a third light-emitting device column 20A3, and a fourth light-emitting device column 20A4 arranged sequentially along the first direction X, forming a light-emitting device column group 20A. One light-emitting device column group 20A is driven to emit light by a pixel circuit column group 10A. Along the second direction Y, the first light-emitting device column 20A1 includes multiple alternating first-color light-emitting devices 201 and third-color light-emitting devices 203; the second light-emitting device column 20A2 includes multiple second-color light-emitting devices 202; the third light-emitting device column 20A3 includes multiple alternating third-color light-emitting devices 203 and first-color light-emitting devices 201; and the fourth light-emitting device column 20A4 includes multiple second-color light-emitting devices 202. That is, the arrangement of the light-emitting devices 20 is a commonly used arrangement in related technologies. The first color light-emitting device 201 and the third color light-emitting device 203 can be red and blue light-emitting devices, respectively, and the third color light-emitting device 203 can be green light-emitting device. Therefore, if the existing technology is used... Figure 4 The pixel circuit and light-emitting device driving structure shown can cause a difference in driving current due to process fluctuations in the pixel circuit. This will result in the first and second light-emitting device columns 20A1 and 20A2 appearing pinkish overall, as will the third and fourth light-emitting device columns 20A3 and 20A4, and so on. Consequently, the overall visual effect of the display panel will exhibit a color shift and a pinkish tint, leading to a mura visual effect problem. Alternatively, if the existing technology is used... Figure 4 The pixel circuit and the driving structure of the light-emitting device shown can cause a difference in driving current due to process fluctuations in the pixel circuit. This will result in the first light-emitting device column 20A1 and the second light-emitting device column 20A2 being predominantly green, the third light-emitting device column 20A3 and the fourth light-emitting device column 20A4 being predominantly green, and so on. As a result, the overall visual effect of the display panel will exhibit color shift and a greenish tint, causing a mura visual effect problem.

[0096] In this embodiment, when the pixel circuit 10 and the light-emitting device 20 are combined and arranged, their arrangement remains unchanged. However, by improving the arrangement in the second direction Y, in the i-th pixel circuit row 10H(i), the first pixel circuit 101 is electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1, thus driving the first color light-emitting device 201; the second pixel circuit 102 is electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2, thus driving the second color light-emitting device 202; the third pixel circuit 103 is electrically connected to the second color light-emitting device 202 of the fourth light-emitting device column 20A4, thus also driving the second color light-emitting device 202; and the fourth pixel circuit 104 is electrically connected to the third color light-emitting device 203 of the third light-emitting device column 20A3, thus driving the fourth pixel circuit 10... 4. Drive the third color light-emitting device 203; and in the (i+1)th pixel circuit row 10H(i+1) adjacent to the i-th pixel circuit row 10H(i), the first pixel circuit 101 is electrically connected to the third color light-emitting device 203 of the first light-emitting device column 20A1, so that the first pixel circuit 101 drives the third color light-emitting device 203; the second pixel circuit 102 is electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2, so that the second pixel circuit 102 drives the second color light-emitting device 202; the third pixel circuit 103 is electrically connected to the second color light-emitting device 202 of the fourth light-emitting device column 20A4, so that the third pixel circuit 103 also drives the second color light-emitting device 202; the fourth pixel circuit 104 is electrically connected to the first color light-emitting device 201 of the third light-emitting device column 20A3, so that the fourth pixel circuit 104 drives the first color light-emitting device 201.Multiple first pixel circuits 101 form a first pixel circuit array 10A1, and multiple second pixel circuits 102 form a second pixel circuit array 10A2. The channel width W1 of the first transistor T1 of the first pixel circuit 101 is different from the channel width W2 of the first transistor T1 of the second pixel circuit 102. The first pixel circuit 101 drives either the first color light-emitting device 201 or the third color light-emitting device 203, and the second pixel circuit 102 drives the second color light-emitting device 202. Multiple third pixel circuits 103 form a third pixel circuit array 10A3, and multiple fourth pixel circuits 104 form a fourth pixel circuit array 10A4. The channel width W3 of the first transistor T1 of the third pixel circuit 103 is different from the channel width W4 of the first transistor T1 of the fourth pixel circuit 104. The channel width W3 of the first transistor T1 of the third pixel circuit 103 is different from that of the first pixel circuit 101. The channel width W1 of the first transistor T1 is the same as that of the second pixel circuit 102. The channel width W4 of the first transistor T1 of the fourth pixel circuit 104 is the same as that of the first transistor T1 of the second pixel circuit 102. At this time, the color of the light-emitting device driven by the third pixel circuit 103 is different from the color of the light-emitting device driven by the first pixel circuit 101. The color of the light-emitting device driven by the third pixel circuit 103 is the same as the color of the light-emitting device driven by the second pixel circuit 102. The third pixel circuit 103 drives the second color light-emitting device 202. The color of the light-emitting device driven by the fourth pixel circuit 104 is different from the color of the light-emitting device driven by the second pixel circuit 102. The color of the light-emitting device driven by the fourth pixel circuit 104 is the same as the color of the light-emitting device driven by the first pixel circuit 101. The fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201.

[0097] If the channel width W1 of the first transistor T1 in the first pixel circuit 101 is smaller than the channel width W2 of the first transistor T1 in the second pixel circuit 102, then the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the first pixel circuit 101 is small, and the driving current of the second color light-emitting device 202 driven by the second pixel circuit 102 is large. The light-emitting areas corresponding to the first pixel circuit 101 and the second pixel circuit 102 may be biased towards the color of the second color light-emitting device 202, i.e., leaning towards green. Conversely, if the channel width W3 of the first transistor T1 in the third pixel circuit 103 is smaller than the channel width W4 of the first transistor T1 in the fourth pixel circuit 104, then the driving current of the second color light-emitting device 202 driven by the third pixel circuit 103 is small, and the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the fourth pixel circuit 104 is large. The light-emitting areas corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 may be biased towards the color of the first color light-emitting device 201 or the third color light-emitting device 203, i.e., leaning towards pink. Therefore, in the light-emitting area corresponding to a pixel circuit group 10A formed by four adjacent pixel circuit groups in the first direction X, the pinkish tint of the light-emitting area corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 neutralizes the greenish tint of the light-emitting area corresponding to the first pixel circuit 101 and the second pixel circuit 102, thereby improving the color shift problem and enhancing the display quality in the overall visual effect.

[0098] In some alternative embodiments, please refer to the references. Figure 1 , Figure 3 , Figures 9-10 , Figure 11 , Figure 11 yes Figure 3 pixel circuit and Figure 9 A schematic diagram of another arrangement structure combining the light-emitting device (it should be understood that this diagram is for the purpose of clearly illustrating the structure of this embodiment). Figure 11 (The light-emitting devices and connecting lines are filled with transparency). In this embodiment, the first pixel circuit 101 is electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1 through the first connecting line LJ1.

[0099] The second pixel circuit 102 is electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2 via the second connection line LJ2;

[0100] The third pixel circuit 103 is electrically connected to the second color light-emitting device 202 of the fourth light-emitting device column 20A4 via the third connection line LJ3;

[0101] The fourth pixel circuit 104 is electrically connected to the third color light-emitting device 203 of the third light-emitting device column 20A3 via the fourth connection line LJ4.

[0102] This embodiment explains that, along the first direction X, a light-emitting device column group 20A consists of a first light-emitting device column 20A1, a second light-emitting device column 20A2, a third light-emitting device column 20A3, and a fourth light-emitting device column 20A4 arranged sequentially. Each light-emitting device column group 20A is driven to emit light by a pixel circuit column group 10A, which in turn consists of a first pixel circuit column 10A1, a second pixel circuit column 10A2, a third pixel circuit column 10A3, and a fourth pixel circuit column 10A4 arranged sequentially. To achieve the following configuration in the i-th pixel circuit row 10H(i): first pixel circuit 101 electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1; second pixel circuit 102 electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2; third pixel circuit 103 electrically connected to the second color light-emitting device 202 of the fourth light-emitting device column 20A4; and fourth pixel circuit 104 electrically connected to the third color light-emitting device 203 of the third light-emitting device column 20A3, connecting lines can be fabricated using a conductive film layer. For example, first pixel circuit 101 is electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1 via a first connecting line LJ1; second pixel circuit 102 is electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2 via a second connecting line LJ2; and third pixel circuit 103 is electrically connected to the second color light-emitting device 202 of the fourth light-emitting device column 20A4 via a third connecting line LJ3. 104 is electrically connected to the third color light-emitting device 203 of the third light-emitting device column 20A3 via the fourth connecting line LJ4; Optionally, the first connecting line LJ1 and the second connecting line LJ1 can be anode signal lines, that is, the first pixel circuit 101 is electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1 via the anode signal line on the same layer as the anode, and the second pixel circuit 102 is electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2; while the third connecting line LJ3 and the fourth connecting line LJ4 can be a connection structure with different layers connected by vias (or when the panel space is sufficient, they can also be anode signal lines on the same film layer as the anode as the third connecting line LJ3 and the fourth connecting line LJ4), so that the third pixel circuit 103 is electrically connected to the second color light-emitting device 202 of the fourth light-emitting device column 20A4, and the fourth pixel circuit 104 is electrically connected to the third color light-emitting device 203 of the third light-emitting device column 20A3.

[0103] Optional, such as Figure 1 , Figure 3 , Figures 9-10 , Figure 11 and Figure 12 As shown, Figure 12 yes Figure 11A partially enlarged schematic diagram of region J2 shows that the first pixel circuit 101 of the first pixel circuit column 10A1 is electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1 via the first connecting line LJ1, and the second pixel circuit 102 of the second pixel circuit column 10A2 is electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2 via the second connecting line LJ2. Along the first direction X, a light-emitting device column group 20A consists of the first light-emitting device column 20A1, the second light-emitting device column 20A2, the third light-emitting device column 20A3, and the fourth light-emitting device column 20A4 arranged sequentially. A light-emitting device column group 20A... A is driven to emit light by a pixel circuit group 10A. The pixel circuit group 10A consists of a first pixel circuit group 10A1, a second pixel circuit group 10A2, a third pixel circuit group 10A3, and a fourth pixel circuit group 10A4, arranged sequentially. Therefore, the first connecting line LJ1 and the second connecting line LJ2 are generally shorter. The third pixel circuit 103 of the third pixel circuit group 10A3 is electrically connected to the second color light-emitting device 202 of the fourth light-emitting device group 20A4 via the third connecting line LJ3. The fourth pixel circuit 104 of the fourth pixel circuit group 10A4 is connected to the second color light-emitting device 202 of the third light-emitting device group 20A3 via the fourth connecting line LJ4. The three-color light-emitting devices 203 are electrically connected. Therefore, the lengths of the third connecting line LJ3 and the fourth connecting line LJ4 are generally relatively long. That is, the length of at least one of the first connecting line LJ1 and the second connecting line LJ2 is less than the length of at least one of the third connecting line LJ3 and the fourth connecting line LJ4. The first connecting line LJ1 and the second connecting line LJ2 are relatively short and can be directly fabricated using the same film layer as the anode, i.e., the anode signal line. The first pixel circuit 101 of the first pixel circuit column 10A1 is directly electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1. The second pixel circuit 102 of the second pixel circuit column 10A2 is directly connected to the second light-emitting device. The second color light-emitting device 202 of the component column 20A2 is directly electrically connected, while the third connecting line LJ3 and the fourth connecting line LJ4 can be a connecting line structure with multiple film layers connected by vias and set in different layers (or when the panel space is sufficient, it can also be the same film layer, such as the anode signal line in the same layer as the anode, as the third connecting line LJ3 and the fourth connecting line LJ4), so as to electrically connect the third pixel circuit 103 of the third pixel circuit column 10A3 to the second color light-emitting device 202 of the fourth light-emitting device column 20A4, and the fourth pixel circuit 104 of the fourth pixel circuit column 10A4 to the third color light-emitting device 203 of the third light-emitting device column 20A3.

[0104] It should be noted that in this embodiment... Figure 11 The image is merely to illustrate how the connecting lines are connected to the pixel circuit. Figure 11The connection positions of the pixel circuit and each connecting line do not represent the actual connection positions. In specific implementation, the position of the light-emitting device connected to the transistor in the pixel circuit through the connecting line can be set according to the actual layout structure of the pixel circuit. The shape and structure of the pixel circuit in this embodiment are only schematic and do not represent the actual complete layout structure of the pixel circuit.

[0105] It is understood that in this embodiment Figure 11 and Figure 12 The layout and routing of the first connecting line LJ1, the second connecting line LJ2, the third connecting line LJ3, and the fourth connecting line LJ4 are merely examples. In actual implementation, they can be set according to the actual film layer space of the panel. It is only necessary to ensure that one light-emitting device column group 20A is driven to emit light by one pixel circuit column group 10A, that the first pixel circuit 101 is electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1, that the second pixel circuit 102 is electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2, that the third pixel circuit 103 is electrically connected to the second color light-emitting device 202 of the fourth light-emitting device column 20A4, and that the fourth pixel circuit 104 is electrically connected to the third color light-emitting device 203 of the third light-emitting device column 20A3.

[0106] In some alternative embodiments, please refer to the references. Figure 1 , Figure 3 , Figures 9-12 , Figures 13-16 , Figure 13 yes Figure 12 A schematic diagram of a cross-sectional structure along the A-A' direction. Figure 14 yes Figure 12 A schematic diagram of a cross-sectional structure along the B-B' direction. Figure 15 yes Figure 12 A schematic diagram of a cross-sectional structure along the C-C' direction. Figure 16 yes Figure 12 A cross-sectional structural diagram along the D-D' direction is shown. In this embodiment, the display panel 000 includes a substrate 01, a driving array layer 02, and an anode layer 03. The anode layer 03 is located on the side of the driving array layer 02 away from the substrate 01.

[0107] The driving array layer 02 includes a pixel circuit 10, and the anode layer 03 includes a plurality of anodes 031. The light-emitting device 20 is electrically connected to the pixel circuit 10 through the anodes 031. Further optionally, the light-emitting device 20 is electrically connected to the transistor in the pixel circuit 10 through the anodes 031, and at least one of the first connection line LJ1, the second connection line LJ2, the third connection line LJ3, and the fourth connection line LJ4 is located in the anode layer 03; or, at least one of the first connection line LJ1, the second connection line LJ2, the third connection line LJ3, and the fourth connection line LJ4 is located in the driving array layer 02.

[0108] This embodiment explains that the film layer structure of the display panel 000 can be a substrate 01 and a driving array layer 02 and an anode layer 03 sequentially located on one side of the substrate 01. The substrate 01 is used as a carrier substrate for setting other film layer structures of the display panel 000. Optionally, in this embodiment, the substrate 01 of the display panel 000 can be a rigid material such as glass or ceramic, or a flexible material such as polymer materials such as polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). The substrate 01 can be any of a transparent substrate, a semi-transparent substrate, or an opaque substrate, and this embodiment does not limit it. The driving array layer 02 can set transistors, capacitors, etc. of the pixel circuit 10 through multiple conductive film layers, and can also set other driving traces and driving circuits. This embodiment does not elaborate on the layout structure of the driving array layer 02, but can refer to the film layer structure of OLED display panels in related technologies for understanding. The anode layer 03 is used to provide an anode 031 that is electrically connected to the light-emitting device 20. The anode layer 03 can be formed of various conductive materials. For example, the anode layer 03 can be formed as a transparent anode or a reflective anode depending on its intended use. When the anode layer 03 is formed as a transparent anode, the material of the anode layer 03 may include indium tin oxide (ITO), indium zinc oxide (IZO), etc.; when the anode layer 03 is formed as a reflective anode, the material of the anode layer 03 may include silver, magnesium, aluminum, or other metal mixtures. This embodiment does not specifically limit this. The anode 031 corresponding to the light-emitting device 20 can be electrically connected to at least one transistor in the pixel circuit 10 to transmit the driving signal of the pixel circuit 10 to the anode 031, thereby achieving the driving and light-emitting effect of the light-emitting device 20.

[0109] It is understood that the film layer structure of the display panel 000 in the figure of this embodiment is only an example. In specific implementation, the film layer structure of the display panel 000 includes, but is not limited to, this, and may also include a cathode layer, an encapsulation layer, and other structures on the side of the light-emitting device 20 away from the substrate 01. This embodiment will not elaborate on these details.

[0110] In this embodiment, at least one of the first connecting line LJ1, the second connecting line LJ2, the third connecting line LJ3, and the fourth connecting line LJ4 is located in the anode layer O3, such as... Figures 13-14 As shown, the first connecting line LJ1 and the second connecting line LJ2 can be located in the anode layer 03, and in a transistor of the first pixel circuit 101 (such as...). Figure 7The seventh transistor T7 in the first pixel circuit 101 is electrically connected to the anode 031 corresponding to the first color light-emitting device 201. The anode 031 corresponding to the first color light-emitting device 201 in the first light-emitting device column 20A1 is directly connected to the first pixel circuit 101 in the first pixel circuit column 10A1 through the first connection line LJ1 located in the anode layer 03. A certain transistor in the second pixel circuit 102 (such as...) Figure 7 The seventh transistor T7 in the second color light-emitting device 202 is electrically connected to the anode 031 corresponding to the second color light-emitting device 202. The anode 031 corresponding to the second color light-emitting device 202 in the second light-emitting device column 20A2 is directly electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 through the second connection line LJ2 located in the anode layer 03. Figures 15-16 As shown, the third connection line LJ3 and the fourth connection line LJ4 can be located in a certain conductive film layer of the driving array layer 02, and in a certain transistor of the third pixel circuit 103 (such as...). Figure 7 The seventh transistor T7 in the fourth pixel circuit 104 is electrically connected to the anode 031 corresponding to the second color light-emitting device 202. The anode 031 corresponding to the second color light-emitting device 202 in the fourth pixel circuit 20A4 is electrically connected to the third pixel circuit 103 of the third pixel circuit 10A3 through the third connection line LJ3 located in a certain conductive film layer of the driving array layer 02. A certain transistor in the fourth pixel circuit 104 (such as...) Figure 7 The seventh transistor T7 in the third color light-emitting device 203 is electrically connected to the anode 031 corresponding to the third color light-emitting device 203. The anode 031 corresponding to the third color light-emitting device 203 in the third light-emitting device column 20A3 is electrically connected to the fourth pixel circuit 104 of the fourth pixel circuit column 10A4 through the fourth connection line LJ4 located in a certain conductive film layer of the driving array layer 02.

[0111] In this embodiment, at least one of the first connecting line LJ1, the second connecting line LJ2, the third connecting line LJ3, and the fourth connecting line LJ4 is located in the anode layer 03, or at least one of the first connecting line LJ1, the second connecting line LJ2, the third connecting line LJ3, and the fourth connecting line LJ4 is located in the driving array layer 02. The first connecting line LJ1 and the second connecting line LJ2 can be directly set in the anode layer 03, simplifying the manufacturing process. When there is insufficient space in the anode layer 03, the third connecting line LJ3 and the fourth connecting line LJ4 can be set in the driving array layer 02, which is close to the anode layer 03, thereby avoiding the problem of short circuits in a large number of connecting lines in the anode layer 03, which is conducive to realizing the normal driving display function of the display panel.

[0112] Optionally, in this embodiment, at least a portion of the same third connecting line LJ3 may be located in the anode layer 03 and at least a portion in the drive array layer 02. Alternatively, among multiple third connecting lines LJ3, at least a portion may be located in the anode layer 03 and at least a portion in the drive array layer 02. Similarly, in the same fourth connecting line LJ4, at least a portion may be located in the anode layer 03 and at least a portion in the drive array layer 02. Alternatively, among multiple fourth connecting lines LJ4, at least a portion may be located in the anode layer 03 and at least a portion in the drive array layer 02, provided that short circuits are avoided between different connecting lines within the film layer. This embodiment does not limit the specific film layer and wiring shape for the first connecting line LJ1, second connecting line LJ2, third connecting line LJ3, and fourth connecting line LJ4. In specific implementation, the remaining space in the film layer can be fully utilized for layout.

[0113] Optional, such as Figures 13-16 As shown, the driving array layer 02 of the display panel 000 may include a first metal layer M1, and no other conductive layer is included between the first metal layer M1 and the anode layer 03; that is, the first metal layer M1 is the conductive film layer closest to the anode layer 03 in the driving array layer 02, and at least a portion of the third connection line LJ3 can be disposed on the first metal layer M1; or, at least a portion of the fourth connection line LJ4 can be disposed on the first metal layer M1, so that the transistors of the pixel circuit 10 can be connected to the third connection line LJ3 or the fourth connection line LJ4 through vias. When the third connection line LJ3 or the fourth connection line LJ4 is electrically connected to the anode 031 of the anode layer 03 through vias, the vias will not be too deep, so as to avoid the vias being too deep and affecting the process and signal transmission performance. This is beneficial to ensuring the signal transmission stability of the third connection line LJ3 and the fourth connection line LJ4 and improving the display quality.

[0114] In some alternative embodiments, please refer to the references. Figure 7 , Figure 17 and Figure 18 , Figure 17 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure. Figure 18 yes Figure 17 A partially enlarged schematic diagram of region J3 (understandably, this is for the purpose of clearly illustrating the structure of this embodiment). Figure 17 The pixel circuit is represented by a block diagram. Figure 18(Transparency filling has been performed). In this embodiment, the display panel 000 includes multiple data lines S, which include a first data line S1, a second data line S2, a third data line S3, and a fourth data line S4 arranged along a first direction X. Among them, the first data line S1 is electrically connected to the first pixel circuit 101, the second data line S2 is electrically connected to the second pixel circuit 102, the third data line S3 is electrically connected to the third pixel circuit 103, and the fourth data line S4 is electrically connected to the fourth pixel circuit 104.

[0115] Along the first direction X, the second data line S2 and the third data line S3 are arranged adjacent to each other with a spacing of D1, the first data line S1 and the second data line S2 are arranged adjacent to each other with a spacing of D2, and the third data line S3 and the fourth data line S4 are arranged adjacent to each other with a spacing of D3; wherein, D2 > D1 and D3 > D1.

[0116] Optionally, in the pixel circuit 10, the transistor electrically connected to the data line S can be... Figure 7 During the threshold compensation and data writing phases when driving the display panel 000, the third scan signal terminal SCP is given a low-level third scan signal to control the third transistor T3 to turn on, and the second scan signal terminal SCN2 is given a high-level second scan signal to control the first transistor T1 to turn on. The data voltage VDATA provided by the data line S of the display panel 000 is transmitted to the gate of the driving transistor DT through the third transistor T3, the driving transistor DT, and the first transistor T1.

[0117] This embodiment explains that multiple data lines S can be provided in the display panel 000. The data lines S are used to provide data voltage signals to the pixel circuit 10. Among the multiple data lines S, there are at least a first data line S1, a second data line S2, a third data line S3, and a fourth data line S4 arranged along the first direction X. It can be understood that the first data line S1, the second data line S2, the third data line S3, and the fourth data line S4 can be understood as being used to provide data voltage signals to the first pixel circuit column 10A1, the second pixel circuit column 10A2, the third pixel circuit column 10A3, and the fourth pixel circuit column 10A4 included in a pixel circuit column group 10A.

[0118] Optionally, if the first data line S1 is electrically connected to the first pixel circuit 101, and the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, then the first data line S1 is used to provide the data voltage signal when the first color light-emitting device 201 emits light or the data voltage signal when the third color light-emitting device 203 emits light, respectively; and the second data line S2 is electrically connected to the second pixel circuit 102, and the second pixel circuit 102 drives the second color light-emitting device 202, then the second data line S2 is used to provide the data voltage signal when the second color light-emitting device 202 emits light. Signal; the third data line S3 is electrically connected to the third pixel circuit 103, and the third pixel circuit 103 drives the second color light-emitting device 202, then the third data line S2 is used to provide the data voltage signal when the second color light-emitting device 202 emits light; the fourth data line S4 is electrically connected to the fourth pixel circuit 104, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201, then the fourth data line S4 is used to provide the data voltage signal when the first color light-emitting device 201 emits light or the data voltage signal when the third color light-emitting device 203 emits light. Since the first data line S1 and the fourth data line S4 provide data voltage signals to the third color light-emitting device 203 or the first color light-emitting device 201, while the second data line S2 and the third data line S3 provide data voltage signals to the second color light-emitting device 202, this embodiment sets the spacing D1 between adjacent second data lines S2 and S3 to be smaller along the first direction X, that is, along the direction in which the first data line S1, the second data line S2, the third data line S3, and the fourth data line S4 are arranged sequentially. The spacing D1 between adjacent first data line S1 and second data line S2 is smaller than that between adjacent first data line S2 and second data line S3. The spacing D2 between adjacent data lines S2, S3, and S4 is larger. That is, the spacing D1 between the second data line S2 and the third data line S3 is smaller than the spacing D2 between the first data line S1 and the second data line S2, and the spacing D1 between the second data line S2 and the third data line S3 is smaller than the spacing D3 between the third data line S3 and the fourth data line S4. In other words, the first data line S1 and the fourth data line S4 can be farther away from the second data line S2 and the third data line S3. This allows the two data lines that transmit different data voltage signals for different color light-emitting devices to be spaced further apart, which helps to avoid mutual interference between the data voltage signals of different color light-emitting devices and thus helps to ensure display quality.

[0119] Optionally, if the first data line S1 is electrically connected to the first pixel circuit 101, and the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, then the first data line S1 is used to provide the data voltage signal when the first color light-emitting device 201 emits light or the data voltage signal when the third color light-emitting device 203 emits light; that is, when the first color light-emitting device 201 and the third color light-emitting device 203 of the first light-emitting device column 20A1 emit light, the first data line S1 needs to switch the data voltage signal (such as switching between the data voltage signals required by the R / B light-emitting device) so as to realize that the first pixel circuit 101 drives the first color light-emitting device 201 and the third color light-emitting device 203 of the first light-emitting device column 20A1 to emit light respectively.

[0120] The second data line S2 is electrically connected to the second pixel circuit 102, and the second pixel circuit 102 drives the second color light-emitting device 202. The second data line S2 is used to provide the data voltage signal when the second color light-emitting device 202 emits light. That is, when the second color light-emitting device 202 of the second light-emitting device column 20A2 emits light, the second data line S2 does not need to switch the data voltage signal (such as the data voltage signal required by the G light-emitting device) to enable the second pixel circuit 102 to drive the second color light-emitting device 202 of the second light-emitting device column 20A2 to emit light.

[0121] The third data line S3 is electrically connected to the third pixel circuit 103, and the third pixel circuit 103 drives the second color light-emitting device 202. The third data line S2 is used to provide the data voltage signal when the second color light-emitting device 202 emits light. That is, when the second color light-emitting device 202 in the fourth light-emitting device column 20A4 emits light, the third data line S3 does not need to switch the data voltage signal (such as the data voltage signal required by the G light-emitting device) to enable the third pixel circuit 103 to drive the second color light-emitting device 202 in the fourth light-emitting device column 20A4 to emit light.

[0122] The fourth data line S4 is electrically connected to the fourth pixel circuit 104, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201. The fourth data line S4 is used to provide the data voltage signal when the first color light-emitting device 201 emits light or the data voltage signal when the third color light-emitting device 203 emits light. That is, when the first color light-emitting device 201 and the third color light-emitting device 203 of the third light-emitting device column 20A3 emit light, the fourth data line S4 needs to switch the data voltage signal (such as switching between the data voltage signals required by the R / B light-emitting device) so as to enable the fourth pixel circuit 104 to drive the first color light-emitting device 201 and the third color light-emitting device 203 of the third light-emitting device column 20A3 to emit light respectively.

[0123] As described above, during the driving process of the display panel 000, both the first data line S1 and the fourth data line S4 need to switch data voltage signals to drive different color light-emitting devices with the same data line. However, the second data line S2 and the third data line S3 do not need to switch data voltage signals to drive the same color light-emitting device with the same data line. Therefore, in this embodiment, the data line S1, the second data line S2, the third data line S3, and the fourth data line S4 can be arranged in the first direction X, i.e., along the direction in which the first data line S1, the second data line S2, the third data line S3, and the fourth data line S4 are arranged in sequence. The spacing D1 between adjacent second data line S2 and third data line S3 is smaller, and the spacing D2 between adjacent first data line S1 and second data line S2, and the spacing D2 between adjacent third data line S3 and fourth data line S4 are smaller. The spacing D3 is set to be larger, that is, the spacing D1 between the second data line S2 and the third data line S3 is smaller than the spacing D2 between the first data line S1 and the second data line S2, and the spacing D1 between the second data line S2 and the third data line S3 is smaller than the spacing D3 between the third data line S3 and the fourth data line S4. This allows the first data line S1, which needs to switch the data voltage signal, to be farther away from the second data line S2, and the fourth data line S4, which needs to switch the data voltage signal, to be farther away from the third data line S3. This prevents the switching data voltage signals of the first data line S1 and the fourth data line S4 from coupling to the second data line S2 and the third data line S3, which would affect the signal transmission performance of the second data line S2 and the third data line S3 themselves, and thus help improve the display quality. Furthermore, since the second data line S2 and the third data line S3 do not need to switch the data voltage signal, they are closer to each other. Even if the first data line S1 is farther from the second data line S2 and the fourth data line S4 is farther from the third data line S3, it will not affect the space occupied by the four data lines S1, S2, S3 and S4 in the first direction X. Therefore, it is beneficial to ensure that the panel has enough space to lay out multiple data lines, which makes it easier to simplify the wiring process.

[0124] It is understood that the data lines S in this embodiment can be set in one or two film layers in the driving array layer. Multiple data lines S can be set in different layers or in the same layer. This embodiment will not elaborate on this. For details, please refer to the film layer layout method of data lines in related technologies.

[0125] It should be noted that in this embodiment... Figure 17 and Figure 18 The data line S shown is for illustrative purposes only. In actual implementation, the layout of the data line S can be slightly adjusted in shape according to the actual space of the panel. It is only necessary to ensure that the overall extension direction of the data line S is the vertical direction shown in the figure, so as to facilitate electrical connection with the driver chip subsequently bound to the display panel 000.

[0126] Optional, such as Figure 7 , Figure 17 , Figure 18 and Figure 19 As shown, Figure 19 yes Figure 17 Another enlarged schematic diagram of the J3 region (understandably, this is for the purpose of clearly illustrating the structure of this embodiment). Figure 19 (Transparency fill has been applied). In this embodiment, the first data line S1 can be electrically connected to the transistor in the first pixel circuit 101 via the fifth connection line LJ5. Figure 7 One end of the third transistor T3, the second data line S2, can be electrically connected to the transistor in the second pixel circuit 102 via the sixth connecting line LJ6. Figure 7 One end of the third transistor T3, the third data line S3, can be electrically connected to the transistor in the third pixel circuit 103 via the seventh connection line LJ7. Figure 7 One end of the third transistor T3, the fourth data line S4, can be electrically connected to the transistor in the fourth pixel circuit 104 via the eighth connection line LJ8. Figure 7 One end of the third transistor T3 is used to realize the transmission of data voltage signals between the pixel circuit 10 and the data line S.

[0127] Further optionally, the film layers for the fifth connecting line LJ5, the sixth connecting line LJ6, the seventh connecting line LJ7, and the eighth connecting line LJ8 can be set according to the actual space of the panel. For example, at least one of the fifth connecting line LJ5, the sixth connecting line LJ6, the seventh connecting line LJ7, and the eighth connecting line LJ8 can be on the same layer as the data line S, or at least partially on a different layer from the data line S. This embodiment does not impose any limitations, as long as it can achieve the electrical connection effect between the pixel circuit and the data line and avoid short circuits.

[0128] In some alternative embodiments, please refer to the references. Figure 7 , Figures 17-19 and Figure 20 , Figure 20 This is a schematic diagram of another planar structure of the display panel provided in this embodiment. In this embodiment, the non-display area NA of the display panel 000 includes a plurality of first bonding pads 301, a plurality of second bonding pads 302, a plurality of third bonding pads 303, and a plurality of fourth bonding pads 304. The first bonding pads 301, second bonding pads 302, third bonding pads 303, and fourth bonding pads 304 are arranged sequentially along the first direction X.

[0129] The first data line S1 is electrically connected to the first bonding pad 301 through the first fan-out line LS1, the second data line S2 is electrically connected to the second bonding pad 302 through the second fan-out line LS2, the third data line S3 is electrically connected to the fourth bonding pad 304 through the third fan-out line LS3, and the fourth data line S4 is electrically connected to the third bonding pad 303 through the fourth fan-out line LS4.

[0130] The third outgoing line LS3 and the fourth outgoing line LS4 are set on different layers. The orthographic projection of the third outgoing line LS3 on the plane where the display panel 000 is located overlaps with the orthographic projection of the fourth outgoing line LS4 on the plane where the display panel 000 is located.

[0131] This embodiment explains how the display panel 000 is subsequently bonded to a driver chip or a flexible circuit board. When the driver chip or flexible circuit board provides a driving signal to the display panel 000, a bonding pad can be set in the non-display area NA of the display panel 000, which is generally the non-display area NA at the bottom edge of the display panel 000. The bonding pad is used to achieve a bonding electrical connection with the bonding driver chip or flexible circuit board. The specific display panel 000's non-display area NA includes multiple first bonding pads 301, multiple second bonding pads 302, multiple third bonding pads 303, and multiple fourth bonding pads 304, used to provide data voltage signals for multiple data lines S. The first bonding pads 301, second bonding pads 302, third bonding pads 303, and fourth bonding pads 304 are arranged sequentially along the first direction X. The first bonding pads 301, second bonding pads 302, third bonding pads 303, and fourth bonding pads 304 correspond to the first data line S1, the second data line S2, the third data line S3, and the fourth data line S4, respectively. The first data line S1 is electrically connected to the first bonding pad 301 through the first fan-out line LS1, and the second data line S2 is electrically connected to the second fan-out line LS1. The outgoing line LS2 is electrically connected to the second bonding pad 302. The third data line S3 is electrically connected to the fourth bonding pad 304 through the third fan-outgoing line LS3. The fourth data line S4 is electrically connected to the third bonding pad 303 through the fourth fan-outgoing line LS4. In related technologies, the pins that provide data voltage signals in the driver chips or flexible circuit boards that have been developed and used and are relatively mature are generally ordered as follows: the R / B pin that provides a transitional data voltage signal to drive the red or blue light-emitting device, the G pin that provides a non-transitional data voltage signal to drive the green light-emitting device, the R / B pin that provides a transitional data voltage signal to drive the red or blue light-emitting device, the G pin that provides a non-transitional data voltage signal to drive the green light-emitting device, and so on.Therefore, in this embodiment, when the first data line S1 is electrically connected to the first pixel circuit 101, and the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, the first data line S1 needs to switch the data voltage signal; the second data line S2 is electrically connected to the second pixel circuit 102, and the second pixel circuit 102 drives the second color light-emitting device 202, the second data line S2 does not need to switch the data voltage signal; the third data line S3 is electrically connected to the third pixel circuit 103, and the third pixel circuit 103 drives the second color light-emitting device 202, the third data line S3 does not need to switch the data voltage signal; the fourth data line S4 is electrically connected to the fourth pixel circuit 104, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 203. 1. When the fourth data line S4 needs to switch the data voltage signal, the driver chip or flexible circuit board that has been developed and used in related technologies and is relatively mature can still be used. The third fan-out line LS3 and the fourth fan-out line LS4 are set on different layers, and the orthographic projection of the third fan-out line LS3 on the plane where the display panel 000 is located overlaps with the orthographic projection of the fourth fan-out line LS4 on the plane where the display panel 000 is located. Therefore, it is not necessary to redevelop and design the driver chip or flexible circuit board. It is only necessary to make the third fan-out line LS3 and the fourth fan-out line LS4 overlap in the direction perpendicular to the plane where the display panel is located. That is, by crossing the third fan-out line LS3 and the fourth fan-out line LS4 on different layers, the corresponding electrical connection can be achieved without changing the order of the pins on the driver chip or flexible circuit board, which helps to reduce development and design costs.

[0132] It is understood that the third fan-out line LS3 and the fourth fan-out line LS4 in this embodiment are set in different layers. The third fan-out line LS3 and the fourth fan-out line LS4 can be set to be located in two different conductive layers in the driving array layer, such as the gate metal layer where the gate of the thin film transistor is located and the capacitor metal layer where one pole of the capacitor is located, respectively. Alternatively, they can be set in two other different conductive layers. This embodiment does not limit this.

[0133] It should be noted that in this embodiment... Figure 20 In this example, the arrangement of multiple bonding pads is only an example. In actual implementation, the arrangement of multiple bonding pads in the non-display area NA does not have to be straight along the first direction X. Instead, they can be arranged in an undulating pattern according to the space of the non-display area NA. This embodiment does not limit this, as long as the overall arrangement of multiple bonding pads is along the first direction X. For details, please refer to the design of the bonding pads when bonding the driver chip or flexible circuit board to the display panel in related technologies.

[0134] In some alternative embodiments, please refer to the references. Figure 7 , Figure 21 and Figure 22 , Figure 21 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure. Figure 22 yes Figure 21 A partially enlarged schematic diagram of region J4 (understandably, this is for the purpose of clearly illustrating the structure of this embodiment). Figure 21 The pixel circuit is represented by a block diagram. Figure 22 (Transparency fill has been applied). In this embodiment, the display panel 000 includes multiple data lines S, which are electrically connected to the pixel circuit 10. Optionally, in the pixel circuit 10, the transistors electrically connected to the data lines S can be... Figure 7 During the threshold compensation and data writing phases when driving the display panel 000, the third scan signal terminal SCP is given a low-level third scan signal to control the third transistor T3 to turn on, and the second scan signal terminal SCN2 is given a high-level second scan signal to control the first transistor T1 to turn on. The data line S of the display panel 000 provides a data voltage VDATA which is transmitted to the gate of the driving transistor DT through the third transistor T3, the driving transistor DT, and the first transistor T1.

[0135] In this embodiment, multiple pixel circuits 10 connected by the same data line S drive light-emitting devices 20 of the same color. That is, in this embodiment, only the data voltage signal required by the corresponding color light-emitting device 20 can be transmitted on one data line S. The data voltage signal on the same data line S does not need to change, allowing each data line S to transmit a stable data voltage signal. This reduces the power consumption of the driver chip or flexible circuit board subsequently bonded to the display panel, as well as the display panel itself, thereby saving overall driving power consumption.

[0136] Optionally, the multiple data lines S include a fifth data line S5, a sixth data line S6, a seventh data line S7, and an eighth data line S8 arranged along the first direction X;

[0137] The fifth data line S5 is used to provide a data voltage signal VDATA-R to the pixel circuit 10 electrically connected to the first color light-emitting device 201; the sixth data line S6 is used to provide a data voltage signal VDATA-G to the pixel circuit 10 electrically connected to the second color light-emitting device 202; the seventh data line S7 is used to provide a data voltage signal VDATA-G to the pixel circuit 10 electrically connected to the second color light-emitting device 202; and the eighth data line S8 is used to provide a data voltage signal VDATA-B to the pixel circuit 10 electrically connected to the third color light-emitting device 203.

[0138] The first pixel circuits 101 of the first pixel circuit column 10A1 include a first sub-pixel circuit 1011 and a second sub-pixel circuit 1012. The first sub-pixel circuit 1011 is electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1, and the second sub-pixel circuit 1012 is electrically connected to the third color light-emitting device 203 of the first light-emitting device column 20A1. The fifth data line S5 is electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1.

[0139] The sixth data line S6 is electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2; the second pixel circuit 102 in the second pixel circuit column 10A2 is electrically connected to the second color light-emitting device 202 in the second light-emitting device column 20A2;

[0140] The seventh data line S7 is electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3; the third pixel circuit 103 in the third pixel circuit column 10A3 is electrically connected to the second color light-emitting device 202 in the fourth light-emitting device column 20A4.

[0141] The fourth pixel circuit 104 of the fourth pixel circuit column 10A4 includes a third sub-pixel circuit 1041 and a fourth sub-pixel circuit 1042. The third sub-pixel circuit 1041 is electrically connected to the first color light-emitting device 201 of the third light-emitting device column 20A3, and the fourth sub-pixel circuit 1042 is electrically connected to the third color light-emitting device 203 of the third light-emitting device column 20A3. The eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4.

[0142] This embodiment explains that when a pixel circuit group 10A is formed by four adjacent pixel circuits in the first direction X, the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, the second pixel circuit 102 drives the second color light-emitting device 202, the third pixel circuit 103 drives the second color light-emitting device 202, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201. That is, changing the color of the light-emitting device driven by the third pixel circuit 103 and changing the color of the light-emitting device driven by the fourth pixel circuit 104 can improve the color shift of the display. In addition, the arrangement structure of the data line S can be combined to make the light-emitting devices 20 driven by multiple pixel circuits 10 electrically connected on the same data line S have the same color, avoiding the problem of increased power consumption caused by signal jumps transmitted on the data line S, and thus saving overall driving power consumption.

[0143] Furthermore, since the fifth data line S5 is only used to provide the data voltage signal VDATA-R to the pixel circuit 10 electrically connected to the first color light-emitting device 201, the sixth data line S6 is only used to provide the data voltage signal VDATA-G to the pixel circuit 10 electrically connected to the second color light-emitting device 202, the seventh data line S7 is only used to provide the data voltage signal VDATA-G to the pixel circuit 10 electrically connected to the second color light-emitting device 202, and the eighth data line S8 is only used to provide the data voltage signal VDATA-B to the pixel circuit 10 electrically connected to the third color light-emitting device 203, the fifth data line S5... The sixth data line S6, the seventh data line S7, and the eighth data line S8 are arranged sequentially along the first direction X. The first pixel circuit 101, the second pixel circuit 102, the third pixel circuit 103, and the fourth pixel circuit 104 are arranged sequentially along the first direction X. In the same row of pixel circuits, the first pixel circuit 101 drives the first color light-emitting device 201, the second pixel circuit 102 drives the second color light-emitting device 202, the third pixel circuit 103 drives the second color light-emitting device 202, and the fourth pixel circuit 104 drives the third color light-emitting device 203. Therefore, the fifth data line S5 is arranged in the same row as the first pixel circuit. The connecting sub-line when electrically connected to the first sub-pixel circuit 1011 in 10A1 can be set to a shorter length, and its connecting sub-line does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. Similarly, the connecting sub-line when electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 can be set to a shorter length, and its connecting sub-line does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. Likewise, the connecting sub-line when electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 can be set to a shorter length, and its connecting sub-line does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. At other pixel circuit positions in the other pixel circuit columns, the connecting sub-line when the eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 can also be set to be shorter. Its connecting sub-line does not need to extend to other pixel circuit positions in adjacent or other pixel circuit columns. It is the data line of the current column that is electrically connected to its corresponding pixel circuit of the current column. It is very likely that the data line of the current column can be electrically connected to its corresponding pixel circuit of the current column by drilling holes in the direction perpendicular to the plane where the display panel is located. This can greatly optimize and reduce the parasitic capacitance on the data line S, which is beneficial to improving the display effect.

[0144] Optionally, in this embodiment, the light-emitting devices 20 driven by multiple pixel circuits 10 electrically connected to the same data line S are of the same color. The fifth data line S5 is used to provide a data voltage signal VDATA-R to the pixel circuit 10 electrically connected to the first-color light-emitting device 201; the sixth data line S6 is used to provide a data voltage signal VDATA-G to the pixel circuit 10 electrically connected to the second-color light-emitting device 202; the seventh data line S7 is used to provide a data voltage signal VDATA-G to the pixel circuit 10 electrically connected to the second-color light-emitting device 202; and the eighth data line S8 is used to provide a data voltage signal VDATA-B to the pixel circuit 10 electrically connected to the third-color light-emitting device 203. Since the fifth data line S5 and the eighth data line S8... Compared to the sixth data line S6 and the seventh data line S7, which both provide data voltage signals to the second color light-emitting device 202, the fifth data line S5 provides data voltage signals to the first color light-emitting device 201, and the eighth data line S8 provides data voltage signals to the third color light-emitting device 203. Therefore, in this embodiment, the data lines are arranged along the first direction X, i.e., along the direction in which the fifth data line S5, the sixth data line S6, the seventh data line S7, and the eighth data line S8 are arranged sequentially. The spacing between adjacent sixth data line S6 and seventh data line S7 is smaller, while the spacing between adjacent fifth data line S5 and sixth data line S6, and the spacing between adjacent seventh data line S7 and eighth data line S8 are larger (e.g., ...). Figure 22 and Figure 23 As shown in the diagram, the spacing between the sixth data line S6 and the seventh data line S7 is smaller than the spacing between the fifth data line S5 and the sixth data line S6, and the spacing between the sixth data line S6 and the seventh data line S7 is smaller than the spacing between the seventh data line S7 and the eighth data line S8. In other words, the sixth data line S6 and the seventh data line S7 can both be further away from the fifth data line S5 and the eighth data line S8, so that the two data lines that transmit different data voltage signals for different color light-emitting devices can be spaced further apart. This helps to avoid mutual interference between the data voltage signals of different color light-emitting devices, and thus helps to ensure display quality.

[0145] Optionally, in this embodiment, the fifth data line S5 is electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 via the first connecting portion; the sixth data line S6 is electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 via the second connecting portion; the seventh data line S7 is electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 via the third connecting portion; and the eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 via the fourth connecting portion. The first, second, third, and fourth connecting portions can be connecting sub-lines disposed in the conductive film layer of the display panel, or they can be vias opened between different conductive layers, or a combination of connecting sub-lines and vias.

[0146] Optionally, taking the first connecting part, second connecting part, third connecting part, and fourth connecting part as examples, they can be connecting sub-wires, such as... Figure 21 , Figure 22 and Figure 23 As shown, Figure 23 yes Figure 22 A schematic diagram showing the corresponding layout of the pixel circuit and data lines (it should be understood that this is for the purpose of clearly illustrating the structure of this embodiment). Figure 23 The light-emitting devices in the diagram have been omitted. Figure 23 (Transparency filling has been performed). In this embodiment, the fifth data line S5 is electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 through the first sub-line LZ1.

[0147] The sixth data line S6 is electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 via the second sub-line LZ2;

[0148] The seventh data line S7 is electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 via the third sub-line LZ3;

[0149] The eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 via the fourth sub-line LZ4.

[0150] This embodiment explains that since all data lines in the current column are electrically connected to their corresponding pixel circuits in the current column, the first sub-line LZ1 when the fifth data line S5 is electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 can be set to a shorter length. The first sub-line LZ1 does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. Similarly, the second sub-line LZ2 when the sixth data line S6 is electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 can be set to a shorter length. The second sub-line LZ2 does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. The seventh data line S7 is electrically connected to the third pixel circuit 1011 in the third pixel circuit column 10A3. When the third sub-line LZ3 is electrically connected, it can be set to be shorter. The third sub-line LZ3 does not need to extend to the position of other pixel circuits in adjacent or other pixel circuit columns. Similarly, when the eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4, the fourth sub-line LZ4 can also be set to be shorter. The fourth sub-line LZ4 does not need to extend to the position of other pixel circuits in adjacent or other pixel circuit columns. This can realize the electrical connection between the data line of the current column and its corresponding pixel circuit of the current column, which can greatly save the layout space of the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4, optimize and reduce the parasitic capacitance on the data line S, and help improve the display effect.

[0151] Optionally, since the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 are all relatively short, at least one of the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 can be on the same layer as the data line S. That is, a sub-line can be directly pulled out from the data line S to achieve an electrical connection with the pixel circuit 10. This can reduce the number of holes when the sub-line and the data line S are on different layers, thereby optimizing the display quality.

[0152] It is understandable that if the space of the film layer where the data line S is located is insufficient, some of the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 can also be set in a different layer from the data line S. In this embodiment, there is no specific limitation on the layout of the film layer of the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4, as long as there is sufficient spacing between the wiring structures to avoid short circuits.

[0153] Optionally, if the first connecting part, the second connecting part, the third connecting part, and the fourth connecting part are taken as vias (not shown in the figure), when the distance between the fifth data line S5 and the transistor to be connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 is relatively close, a hole can be directly drilled below the fifth data line S5 in a direction perpendicular to the plane of the display panel. The fifth data line S5 can be electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 through the via, without the need to connect a sub-line;

[0154] When the distance between the sixth data line S6 and the transistor to be connected to the second pixel circuit 102 in the second pixel circuit column 10A2 is relatively close, a hole can be drilled directly below the sixth data line S6 in a direction perpendicular to the plane of the display panel. The sixth data line S6 can be electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 through the hole without the need to connect a sub-line.

[0155] When the seventh data line S7 is close to the transistor that needs to be connected to the third pixel circuit 103 in the third pixel circuit column 10A3, a hole can be drilled directly below the seventh data line S7 in a direction perpendicular to the plane of the display panel. The seventh data line S7 can be electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 through the hole without the need to connect a sub-line.

[0156] When the distance between the eighth data line S8 and the transistor to be connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 is relatively close, a hole can be drilled directly below the eighth data line S8 in a direction perpendicular to the plane of the display panel. The eighth data line S8 can be electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 through the hole without the need to connect a sub-line.

[0157] In this embodiment, the data line of the current column can be electrically connected to the pixel circuit of the corresponding current column by drilling holes in a direction perpendicular to the plane of the display panel. This helps to reduce the number of signal traces in the panel, simplify the manufacturing process, and improve the pixel density and display quality.

[0158] In some alternative embodiments, please refer to the references. Figures 21-23 and Figures 24-25 As shown, Figure 24 yes Figure 21 A magnified view of a portion of the area corresponding to multiple pixel circuit arrays. Figure 25 yes Figure 24 A schematic diagram showing the corresponding layout of the pixel circuit and data lines (it should be understood that this is for the purpose of clearly illustrating the structure of this embodiment). Figure 25 The light-emitting devices in the diagram have been omitted. Figure 24 and Figure 25 (Transparency filling has been performed). In this embodiment, along the first direction X, the display panel includes the (N-1)th pixel circuit column group 10A(N-1), the Nth pixel circuit column group 10A(N), and the (N+1)th pixel circuit column group 10A(N+1); where N is a positive integer and greater than or equal to 2.

[0159] The fifth data line S5 corresponding to the Nth pixel circuit group 10A(N) is also electrically connected to the third sub-pixel circuit 1041 of the fourth pixel circuit column 10A4 in the (N-1)th pixel circuit group 10A(N-1);

[0160] The eighth data line S8 corresponding to the Nth pixel circuit group 10A(N) is also electrically connected to the second sub-pixel circuit 1012 of the first pixel circuit column 10A1 in the N+1th pixel circuit group 10A(N+1).

[0161] Optionally, the fifth data line S5 is electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 via the first sub-line LZ1;

[0162] The sixth data line S6 is electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 via the second sub-line LZ2;

[0163] The seventh data line S7 is electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 via the third sub-line LZ3;

[0164] The eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 via the fourth sub-line LZ4;

[0165] The fifth data line S5 corresponding to the Nth pixel circuit column group 10A(N) is electrically connected to the third sub-pixel circuit 1041 of the fourth pixel circuit column 10A4 in the (N-1)th pixel circuit column group 10A(N-1) through the fifth sub-line LZ5;

[0166] The eighth data line S8 corresponding to the Nth pixel circuit column group 10A(N) is electrically connected to the second sub-pixel circuit 1012 of the first pixel circuit column 10A1 in the N+1th pixel circuit column group 10A(N+1) through the sixth sub-line LZ6;

[0167] The length of the fifth sub-line LZ5 is greater than the length of the first sub-line LZ1; and / or, the length of the sixth sub-line LZ6 is greater than the length of the fourth sub-line LZ4.

[0168] This embodiment explains that multiple pixel circuits 10 connected by the same data line S drive light-emitting devices 20 of the same color. Since the fifth data line S5 is only used to provide the data voltage signal VDATA-R to the pixel circuit 10 electrically connected to the first-color light-emitting device 201, the sixth data line S6 is only used to provide the data voltage signal VDATA-G to the pixel circuit 10 electrically connected to the second-color light-emitting device 202, the seventh data line S7 is only used to provide the data voltage signal VDATA-G to the pixel circuit 10 electrically connected to the second-color light-emitting device 202, and the eighth data line S8 is only used to provide the data voltage signal VDATA-B to the pixel circuit 10 electrically connected to the third-color light-emitting device 203, the fifth data line S5 corresponding to the Nth pixel circuit group 10A(N) also needs to be electrically connected to the adjacent preceding pixel circuit group, i.e., the (N-1)th pixel circuit group. The third sub-pixel circuit 1041 of the fourth pixel circuit column 10A4 in 10A(N-1), and the eighth data line S8 corresponding to the Nth pixel circuit column group 10A(N) also needs to be electrically connected to the second sub-pixel circuit 1012 of the first pixel circuit column 10A1 in the next adjacent pixel circuit column group 10A(N+1), i.e., the N+1th pixel circuit column 10A(N+1). This enables the second sub-pixel circuit 1012 and the first sub-pixel circuit 1011 of the first pixel circuit column 10A1 to drive light-emitting devices of different colors and connect to different data lines S. The third sub-pixel circuit 1041 and the fourth sub-pixel circuit 1042 of the fourth pixel circuit column 10A4 drive light-emitting devices of different colors and connect to different data lines S. This improves the color shift problem while ensuring that the light-emitting devices 20 driven by multiple pixel circuits 10 electrically connected to the same data line S have the same color, saving driving power consumption.

[0169] Optional, such as Figure 24 and Figure 25As shown, the length of the fifth sub-line LZ5 is greater than the length of the first sub-line LZ1; and / or, the length of the sixth sub-line LZ6 is greater than the length of the fourth sub-line LZ4. This is because the fifth sub-line LZ5 needs to be drawn from the fifth data line S5 corresponding to the Nth pixel circuit column group 10A(N) to the third sub-pixel circuit 1041 of the fourth pixel circuit column 10A4 in the adjacent (N-1)th pixel circuit column group 10A(N-1), while the first sub-line LZ1 only connects the data line of the current column to its corresponding pixel circuit. Therefore, the length of the fifth sub-line LZ5 is longer than that of the first sub-line LZ1. Similarly, the sixth sub-line LZ6 needs to be drawn from the Nth pixel... The eighth data line S8 corresponding to the circuit group 10A(N) is pulled to the second sub-pixel circuit 1012 of the first pixel circuit column 10A1 in the adjacent N+1th pixel circuit group 10A(N+1). The fourth sub-line LZ4 only connects the data line of the current column to the pixel circuit of the current column. Therefore, the pull length of the sixth sub-line LZ6 is longer than that of the fourth sub-line LZ4. By increasing the pull length of the sub-line, the electrical connection between different pixel circuit groups 10A and the data line S corresponding to non-current columns is realized. In this way, the light-emitting devices 20 driven by multiple pixel circuits 10 electrically connected by the same data line S have the same color, saving driving power consumption.

[0170] Optionally, although the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 are all relatively short, they can be on the same layer as the data line S. That is, the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 can be directly pulled out from the data line S to achieve electrical connection with the pixel circuit 10. This reduces the number of holes required when the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 are on different layers from the data line S, thereby improving display quality. However, due to the fifth sub-line LZ... The pull length of the fifth sub-line LZ5 is longer than that of the first sub-line LZ1. The pull length of the sixth sub-line LZ6 is also longer than that of the fourth sub-line LZ4. Therefore, at least part of the fifth sub-line LZ5 is on a different layer from the data line S; or, at least part of the sixth sub-line LZ6 is on a different layer from the data line S. This allows for the use of other conductive film layers besides the data line S for routing vias, avoiding excessive wiring on the film layer containing the data line S and preventing short circuits between different lines, which is beneficial for improving product yield.

[0171] In some alternative embodiments, please refer to Figure 26 , Figure 26 This is a schematic diagram of the planar structure of a display device provided in an embodiment of the present disclosure. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiments of the present invention. Figure 26This embodiment uses a mobile phone as an example to illustrate the display device 111. It is understood that the display device 111 provided in this embodiment can be any other display device 111 with display functions, such as a computer, television, or in-vehicle display device; this invention does not impose specific limitations on this. The display device 111 provided in this embodiment has the beneficial effects of the display panel 000 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 000 in the above embodiments; these will not be repeated here.

[0172] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0173] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized by, The pixel circuit comprises a driving transistor and a first transistor electrically connected; The plurality of pixel circuits comprises at least a first pixel circuit, a second pixel circuit, a third pixel circuit and a fourth pixel circuit; The display panel comprises a plurality of pixel circuit column groups arranged in a first direction, and one pixel circuit column group comprises a first pixel circuit column, a second pixel circuit column, a third pixel circuit column and a fourth pixel circuit column; The first pixel circuit column comprises a plurality of first pixel circuits, the second pixel circuit column comprises a plurality of second pixel circuits, the third pixel circuit column comprises a plurality of third pixel circuits, and the fourth pixel circuit column comprises a plurality of fourth pixel circuits; The channel width of the first transistor of the first pixel circuit is different from the channel width of the first transistor of the second pixel circuit, the channel width of the first transistor of the third pixel circuit is different from the channel width of the first transistor of the fourth pixel circuit, the channel width of the first transistor of the first pixel circuit is equal to the channel width of the first transistor of the third pixel circuit, and the channel width of the first transistor of the second pixel circuit is equal to the channel width of the first transistor of the fourth pixel circuit; The display panel comprises a plurality of light emitting devices, and the plurality of light emitting devices comprises a first color light emitting device, a second color light emitting device and a third color light emitting device; The first pixel circuit drives the first color light emitting device or the third color light emitting device, the second pixel circuit drives the second color light emitting device, the third pixel circuit drives the second color light emitting device, and the fourth pixel circuit drives the third color light emitting device or the first color light emitting device.

2. The display panel of claim 1, wherein: The channel width of the first transistor of the first pixel circuit is W1, and the channel width of the first transistor of the second pixel circuit is W2; |W1-W2|≤0.1 μm; The channel width of the first transistor of the third pixel circuit is W3, and the channel width of the first transistor of the fourth pixel circuit is W4; |W3-W4|≤0.1 μm.

3. The display panel of claim 1, wherein, The channel width of the first transistor of the first pixel circuit is less than the channel width of the first transistor of the second pixel circuit, and the channel width of the first transistor of the third pixel circuit is less than the channel width of the first transistor of the fourth pixel circuit.

4. The display panel of claim 1, wherein: The first color light emitting device is one of a red light emitting device or a blue light emitting device, and the third color light emitting device is the other of the red light emitting device or the blue light emitting device; The second color light emitting device is a green light emitting device.

5. The display panel of claim 1, wherein, The first transistor is electrically connected between the gate and the first electrode of the driving transistor, and the first transistor is an N-type transistor.

6. The display panel of claim 1, wherein, In the first direction, the first pixel circuit of the first pixel circuit column is mirror-symmetrical to the second pixel circuit of the second pixel circuit column, and the third pixel circuit of the third pixel circuit column is mirror-symmetrical to the fourth pixel circuit of the fourth pixel circuit column. 7.The display panel of claim 1, wherein, the display panel comprises a plurality of light emitting device column groups arranged in the first direction in sequence; one of the light emitting device column groups comprises a first light emitting device column, a second light emitting device column, a third light emitting device column and a fourth light emitting device column arranged in the first direction in sequence; in the second direction, the first light emitting device column comprises a plurality of the first color light emitting devices and the third color light emitting devices arranged alternately, the second light emitting device column comprises a plurality of the second color light emitting devices, the third light emitting device column comprises a plurality of the third color light emitting devices and the first color light emitting devices arranged alternately, and the fourth light emitting device column comprises a plurality of the second color light emitting devices; wherein the first direction and the second direction intersect in a plane parallel to the display panel; a plurality of the pixel circuits are arranged in the first direction to form a pixel circuit row; in the i th pixel circuit row, the first pixel circuit is electrically connected to the first color light emitting device of the first light emitting device column, the second pixel circuit is electrically connected to the second color light emitting device of the second light emitting device column, the third pixel circuit is electrically connected to the second color light emitting device of the fourth light emitting device column, and the fourth pixel circuit is electrically connected to the third color light emitting device of the third light emitting device column; wherein i is a positive integer. 8.The display panel of claim 7, wherein, in the second direction, in the i+1 th pixel circuit row, the first pixel circuit is electrically connected to the third color light emitting device of the first light emitting device column, the second pixel circuit is electrically connected to the second color light emitting device of the second light emitting device column, the third pixel circuit is electrically connected to the second color light emitting device of the fourth light emitting device column, and the fourth pixel circuit is electrically connected to the first color light emitting device of the third light emitting device column. 9.The display panel of claim 7, wherein, the first pixel circuit is electrically connected to the first color light emitting device of the first light emitting device column through a first connection line; the second pixel circuit is electrically connected to the second color light emitting device of the second light emitting device column through a second connection line; the third pixel circuit is electrically connected to the second color light emitting device of the fourth light emitting device column through a third connection line; the fourth pixel circuit is electrically connected to the third color light emitting device of the third light emitting device column through a fourth connection line. 10.The display panel of claim 9, wherein, a length of at least one of the first connection line and the second connection line is less than a length of at least one of the third connection line and the fourth connection line. 11.The display panel of claim 9, wherein, The display panel comprises a substrate, a driving array layer, and an anode layer located on a side of the driving array layer away from the substrate, The driving array layer comprises the pixel circuit, the anode layer comprises a plurality of anodes, and the light emitting device is electrically connected to the pixel circuit through the anode; at least one of the first connection line, the second connection line, the third connection line, and the fourth connection line is located on the anode layer; or at least one of the first connection line, the second connection line, the third connection line, and the fourth connection line is located on the driving array layer.

12. The display panel of claim 11, wherein, The driving array layer comprises a first metal layer, and no other conductive layer is included between the first metal layer and the anode layer; At least part of the third connection line is located on the first metal layer; or at least part of the fourth connection line is located on the first metal layer.

13. The display panel of claim 7, wherein, The display panel comprises a plurality of data lines, and the plurality of data lines comprise a first data line, a second data line, a third data line, and a fourth data line arranged along the first direction; wherein the first data line is electrically connected to the first pixel circuit, the second data line is electrically connected to the second pixel circuit, the third data line is electrically connected to the third pixel circuit, and the fourth data line is electrically connected to the fourth pixel circuit; Along the first direction, the second data line and the third data line are adjacently arranged with a spacing of D1, the first data line and the second data line are adjacently arranged with a spacing of D2, and the third data line and the fourth data line are adjacently arranged with a spacing of D3; D2>D1, and D3>D1.

14. The display panel of claim 13, wherein, The non-display area of the display panel comprises a plurality of first binding pads, a plurality of second binding pads, a plurality of third binding pads, and a plurality of fourth binding pads, which are sequentially arranged along the first direction; The first data line is electrically connected to the first binding pad through a first fan-out line, the second data line is electrically connected to the second binding pad through a second fan-out line, the third data line is electrically connected to the fourth binding pad through a third fan-out line, and the fourth data line is electrically connected to the third binding pad through a fourth fan-out line; The third fan-out line and the fourth fan-out line are arranged in different layers, and the orthographic projection of the third fan-out line on the plane where the display panel is located overlaps the orthographic projection of the fourth fan-out line on the plane where the display panel is located.

15. The display panel of claim 7, wherein The display panel comprises a plurality of data lines, and the data lines are electrically connected to the pixel circuit; The light emitting devices driven by the plurality of pixel circuits electrically connected to the same data line are of the same color.

16. The display panel of claim 15, wherein, The plurality of data lines comprise a fifth data line, a sixth data line, a seventh data line, and an eighth data line arranged along the first direction; The fifth data line is configured to provide a data voltage signal for the pixel circuit electrically connected with the first color light emitting device, the sixth data line is configured to provide a data voltage signal for the pixel circuit electrically connected with the second color light emitting device, the seventh data line is configured to provide a data voltage signal for the pixel circuit electrically connected with the second color light emitting device, and the eighth data line is configured to provide a data voltage signal for the pixel circuit electrically connected with the third color light emitting device. The first pixel circuit column includes a first sub-pixel circuit and a second sub-pixel circuit, the first sub-pixel circuit is electrically connected with the first color light emitting device of the first light emitting device column, and the second sub-pixel circuit is electrically connected with the third color light emitting device of the first light emitting device column; the fifth data line is electrically connected with the first sub-pixel circuit in the first pixel circuit column. The sixth data line is electrically connected with the second pixel circuit in the second pixel circuit column. The seventh data line is electrically connected with the third pixel circuit in the third pixel circuit column. The fourth pixel circuit column includes a third sub-pixel circuit and a fourth sub-pixel circuit, the third sub-pixel circuit is electrically connected with the first color light emitting device of the third light emitting device column, and the fourth sub-pixel circuit is electrically connected with the third color light emitting device of the third light emitting device column; the eighth data line is electrically connected with the fourth sub-pixel circuit in the fourth pixel circuit column.

17. The display panel of claim 16, wherein The fifth data line is electrically connected with the first sub-pixel circuit in the first pixel circuit column through a first sub-line. The sixth data line is electrically connected with the second pixel circuit in the second pixel circuit column through a second sub-line. The seventh data line is electrically connected with the third pixel circuit in the third pixel circuit column through a third sub-line. The eighth data line is electrically connected with the fourth sub-pixel circuit in the fourth pixel circuit column through a fourth sub-line. At least one of the first sub-line, the second sub-line, the third sub-line, and the fourth sub-line is in the same layer as the data line.

18. The display panel of claim 16, wherein The display panel includes an N-1th pixel circuit column group, an Nth pixel circuit column group, and an N+1th pixel circuit column group along the first direction, where N is a positive integer greater than or equal to 2. The fifth data line corresponding to the Nth pixel circuit column group is also electrically connected with the third sub-pixel circuit of the fourth pixel circuit column in the N-1th pixel circuit column group. The eighth data line corresponding to the Nth pixel circuit column group is also electrically connected with the second sub-pixel circuit of the first pixel circuit column in the N+1th pixel circuit column group.

19. The display panel of claim 18, wherein The fifth data line is electrically connected with the first sub-pixel circuit in the first pixel circuit column through a first sub-line. The sixth data line is electrically connected with the second pixel circuit in the second pixel circuit column through a second sub-line; The seventh data line is electrically connected with the third pixel circuit in the third pixel circuit column through a third sub-line; The eighth data line is electrically connected with the fourth pixel circuit in the fourth pixel circuit column through a fourth sub-line; The fifth data line corresponding to the Nth pixel circuit column group is electrically connected with the third pixel circuit in the fourth pixel circuit column in the N-1th pixel circuit column group through a fifth sub-line; The eighth data line corresponding to the Nth pixel circuit column group is electrically connected with the second pixel circuit in the first pixel circuit column in the N+1th pixel circuit column group through a sixth sub-line; The length of the fifth sub-line is greater than the length of the first sub-line; and / or, the length of the sixth sub-line is greater than the length of the fourth sub-line.

20. The display panel of claim 19, wherein, At least part of the fifth sub-line is in a layer different from the data line; or, at least part of the sixth sub-line is in a layer different from the data line.

21. A display device comprising: The display panel comprises the display panel of any one of claims 1-20.

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