Active layer, artificial synaptic transistor and preparation method and application of artificial synaptic transistor

Abstract

The invention belongs to the technical field of electronic devices, and particularly relates to an active layer, an artificial synapse transistor and a preparation method and application of the artificial synapse transistor. The active layer for the synaptic transistor is innovatively prepared, and the active layer is characterized in that ethanol is added into a PDPP-TT solution, and the measure promotes a unique trap structure to be formed on the interface of the active layer, namely, a high-density shallow trap and a low-density deep trap coexist along with the generation of a discrete trap center of the interface. The trap distribution significantly optimizes the ion mobility of the active layer, which not only greatly widens the simulation dynamic range of the device, but also effectively enhances the charge accumulation effect, thereby achieving the significant improvement of the post-synaptic current responsivity. On the basis of the active layer, an artificial synapse transistor is further prepared. The transistor not only shows excellent short-range plasticity, but also has excellent synaptic plasticity and high-current response characteristics, and provides powerful support for application of the transistor in wider fields.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic devices. More specifically, it relates to an active layer, an artificial synaptic transistor, and a preparation method and application thereof. Background Art

[0002] Artificial synaptic transistors, as the core technology for simulating the working mode of the human brain, play a crucial role in promoting the development of brain-like computing systems and neuromorphic computing technologies. This innovative technology not only has the potential to break through the limitations of the von Neumann architecture relied on by traditional binary computing systems, but also can significantly reduce the latency and energy consumption of data transmission by integrating storage and processing functions. More importantly, by precisely simulating the functions of biological neural synapses, artificial synaptic transistors exhibit high plasticity similar to biological synapses, capable of adding and conducting the received electrical pulse signals, thus opening up a promising application prospect.

[0003] When the gate of an artificial synaptic transistor is stimulated by a negative pulse, anions will migrate towards the interface of the active layer, forming a charge / ion double-layer interface, and inducing the migration of hole carriers in the channel, thereby outputting an excitatory postsynaptic current. When the pulse stimulation is removed, the anions accumulated at the double-layer interface will quickly return to their initial positions, resulting in the decay of the excitatory postsynaptic current and realizing the reset function of the system. However, although the artificial synaptic transistor with a conventional poly(2,5-bis(3-dodecylthiophen-2-yl)pyrrolo[3,4-c]pyrrole-1,4-dione) (PDPP-TT) thin film as the active layer constructs a double layer with very few deep traps and has a weak ability to capture ions, thus enabling an ultra-fast reset after the pulse is removed and showing excellent short-term memory characteristics, the number of carriers in its active layer is limited, resulting in the output postsynaptic current being less sensitive to changes in the number and frequency of stimuli, that is, the amplitude change of the postsynaptic current is not obvious, thereby making the synaptic plasticity lower. This defect directly limits the analog dynamic range of the device, and further affects its performance in time-frequency signal processing applications, making it difficult to efficiently simulate the learning and memory functions of synapses in biological nervous systems.

[0004] Therefore, there is an urgent need in the art to develop an artificial synaptic transistor with both excellent short-term memory characteristics and high synaptic plasticity. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the defect and deficiency in the prior art that the number of carriers of the artificial synaptic transistor prepared with a PDPP-TT thin film as the active layer is limited, resulting in an unclear amplitude change of the postsynaptic current, thereby making the synaptic plasticity of the device lower, and to provide a preparation method for the active layer of an artificial synaptic transistor.

[0006] Another object of the present invention is to provide an active layer prepared by the above preparation method.

[0007] Another object of the present invention is to provide an application of the above active layer in the preparation of synaptic transistors.

[0008] Another object of the present invention is to provide an artificial synaptic transistor.

[0009] Another object of the present invention is to provide a preparation method of the above artificial synaptic transistor.

[0010] Another object of the present invention is to provide an application of the above active layer or the above artificial synaptic transistor in the preparation of bionic sensing devices, neuromorphic memories or brain-like computing chips.

[0011] The above objects of the present invention are achieved by the following technical solutions:

[0012] The present invention protects a preparation method of an active layer for an artificial synaptic transistor, comprising the following steps:

[0013] Add ethanol to a poly(2,5-bis(3-tetradecylthiophen-2-yl)pyrrolo[3,4-c]pyrrole-1,4-dione) (PDPP-TT) solution, mix well to obtain a PDPP-TT-ethanol suspension, uniformly coat the obtained suspension on a substrate, and then perform annealing treatment on the coated substrate to obtain an active layer.

[0014] The present invention ingeniously introduces ethanol as an anti-solvent into the PDPP-TT solution, significantly reducing the solubility of PDPP-TT in the original solvent, increasing the solute supersaturation in the PDPP-TT-ethanol suspension, and greatly promoting the nucleation and growth of PDPP-TT crystals. Secondly, in the mixing step, an interaction occurs between ethanol and the solvation shell of PDPP-TT, effectively replacing the original solvent molecules and further accelerating the crystal growth. Due to Brownian motion or because the density of the precipitated small particle crystals is similar to that of the suspension, these small crystals do not deposit at the bottom of the container but are uniformly dispersed throughout the suspension. These chemical and physical effects not only greatly improve the crystallization quality of PDPP-TT but also optimize its surface roughness and reduce the deep trap concentration, thereby improving the overall performance and stability of the device. In addition, this method ensures that the device maintains good hydrophilic and polar properties, which are crucial for the application of the device in different environments.

[0015] Further, the preparation method of the PDPP-TT solution comprises the following steps:

[0016] Disperse PDPP-TT powder into a solvent and fully dissolve it to obtain a PDPP-TT solution.

[0017] Further, the solvent includes one or more of chlorobenzene, chloroform, and dichlorobenzene.

[0018] Preferably, the dissolution time is 10 - 20 h.

[0019] Furthermore, the volume ratio of the ethanol to the PDPP-TT solution is 1:(7 - 13). Within this volume ratio range, the addition of ethanol can effectively promote the nucleation and growth of PDPP-TT crystals.

[0020] Preferably, the volume ratio of the ethanol to the PDPP-TT solution is 1:(8 - 11).

[0021] More preferably, the volume ratio of the ethanol to the PDPP-TT solution is 1:9. Under this ratio condition, ethanol has a better effect on promoting the crystal nucleation of PDPP-TT, further improving the quality of the crystals.

[0022] Preferably, the mixing time is 15 - 60 min.

[0023] Furthermore, the mixing further includes a standing step.

[0024] Preferably, the standing time is 8 - 12 h. Standing can further promote the uniform dispersion of each component in the suspension, enabling the precipitation reaction to proceed fully, thereby improving the stability of the PDPP-TT solution; moreover, since the amount of solution required for each spin-coated film is very small, long-term standing can also ensure that the taken suspension is relatively uniform, and thus the solute of the spin-coated film is also relatively uniform, effectively reducing problems such as uneven film thickness caused by unstable solution during the spin-coating process.

[0025] Furthermore, the use of the substrate includes pretreatment.

[0026] Even further, as a preferred method, the pretreatment includes the following steps:

[0027] The substrate is ultrasonically cleaned successively with water, acetone, and isopropyl alcohol solution, then dried with nitrogen, and treated with ozone for 15 - 20 min; the purpose of the ozone treatment is to hydroxylate the substrate surface and enhance the wettability.

[0028] Preferably, the rotation speed of the coating is 1000 - 3000 rpm.

[0029] Preferably, the coating time is 30 - 60 s.

[0030] Furthermore, the annealing temperature is 180 - 220 °C.

[0031] Even further, the annealing temperature is 190 - 210 °C.

[0032] Preferably, the annealing temperature is 200 °C.

[0033] Preferably, the annealing time is 10 to 20 minutes.

[0034] Preferably, the thickness of the active layer is 10-30 nm. Within this range, there are relatively fewer defects on the active layer and the performance is better.

[0035] More preferably, the thickness of the active layer is 15-25 nm. The active layer within this thickness range can further reduce defects, thereby more effectively improving the overall performance of the device.

[0036] The present invention protects the active layer prepared by the above preparation method.

[0037] The present invention protects the use of the above active layer in preparing a synaptic transistor.

[0038] The present invention protects an artificial synaptic transistor, comprising a substrate, an active layer, a gate dielectric layer, and a source electrode and a drain electrode arranged on both sides of the gate dielectric layer, which are stacked in sequence;

[0039] Wherein, the active layer is the aforementioned active layer.

[0040] The artificial synaptic transistor of the present invention integrates a substrate, an active layer, a gate dielectric layer, and a source electrode and a drain electrode to construct a stable and reliable device structure. Among them, the active layer prepared by the anti-solvent method significantly improves the ion mobility, which not only broadens the simulated dynamic range of the device, but also greatly enhances the charge accumulation effect, thereby significantly improving the responsiveness of the postsynaptic current. This innovative breakthrough solves the problem of limited number of carriers when the traditional artificial synaptic transistor uses PDPP-TT film as the active layer, making the postsynaptic current output by the device more sensitive to the number and frequency changes of stimuli, and the synaptic plasticity is significantly improved. The gate dielectric layer provides a solid guarantee for the efficient and stable operation of the device, and the cooperation of the source electrode and the drain electrode ensures the accurate transmission of the signal. In summary, by cleverly combining the above structures, the artificial synaptic transistor of the present application exhibits excellent synaptic plasticity and high current response characteristics.

[0041] Specifically, in the artificial synaptic transistor of the present application, the gate dielectric layer is designed to cover only the area between the source electrode and the drain electrode. This design aims to achieve refined gate control and significantly improve the response speed and switching performance of the transistor by more directly regulating the charge carriers between the source electrode and the drain electrode. At the same time, the design can also effectively avoid the introduction of unnecessary charge storage on the source electrode and the drain electrode, thereby reducing parasitic effects and improving the overall performance of the device.

[0042] Furthermore, the substrate includes any one of silicon dioxide, polyethylene terephthalate (PET), and a glass substrate.

[0043] Preferably, the thickness of the substrate is 290 - 310 nm. A substrate within this range has better mechanical stability and processing feasibility, thus ensuring that it can reliably carry the device without directly affecting the device performance.

[0044] Furthermore, the source electrode and the drain electrode are made of the same material; the source electrode and the drain electrode are gold, silver or copper.

[0045] Preferably, the thickness of the source electrode and the drain electrode is 30 - 60 nm. The source electrode and the drain electrode within this thickness range can adhere more firmly to the substrate, significantly reducing the risk of detachment, while ensuring excellent electrical contact performance.

[0046] More preferably, the thickness of the source electrode and the drain electrode is 35 - 45 nm.

[0047] Furthermore, the gate dielectric layer is an ionic gel.

[0048] Even further, the ionic gel includes any one of [PVDF - HFP][EMIM - TFSI] ionic gel, polyethylene oxide - sodium ionic gel, and polyethylene oxide - lithium ionic gel. These ionic gel materials are all rich in mobile anions and cations inside, thus being able to meet the requirements of the artificial synaptic transistor in this application.

[0049] Preferably, the gate dielectric layer is [PVDF - HFP][EMIM - TFSI] ionic gel. [PVDF - HFP][EMIM - TFSI] ionic gel has higher ionic conductivity, a wider working voltage range, and better mechanical strength and flexibility, and can exhibit more excellent performance in the artificial synaptic transistor in this application.

[0050] Furthermore, the preparation method of the [PVDF - HFP][EMIM - TFSI] ionic gel includes the following steps:

[0051] Mix the polyvinylidene fluoride - hexafluoropropylene copolymer (PVDF - HFP) solution and 1 - ethyl - 3 - methylimidazolium bis(trifluoromethylsulfonyl)imide (EMIM - TFSI) ionic liquid evenly, and after curing, obtain the [PVDF - HFP][EMIM - TFSI] ionic gel.

[0052] Furthermore, the specific preparation method of the PVDF - HFP solution includes the following steps:

[0053] Fully dissolve the PVDF - HDP powder in the solvent to obtain the PVDF - HDP solution.

[0054] Furthermore, the solvent includes one or more of acetone, N - methylpyrrolidone, and dimethylformamide.

[0055] Preferably, the temperature of the dissolution is 40 to 80 °C.

[0056] Preferably, the time of the dissolution is 5 to 20 min.

[0057] Furthermore, the mass ratio of PVDF-HFP to EMIM-TFSI is 1:(1 - 6). Within this mass ratio range, the synergistic effect of PVDF-HFP and EMIM-TFSI can significantly improve the performance of the material.

[0058] Even further, the mass ratio of PVDF-HFP to EMIM-TFSI is 1:(2 - 4).

[0059] Preferably, the mass ratio of PVDF-HFP to EMIM-TFSI is 1:3. Under this ratio condition, the synergistic effect of PVDF-HFP and EMIM-TFSI is better, further improving the performance of the material.

[0060] Preferably, the temperature of the mixing is 40 to 80 °C.

[0061] Preferably, the time of the mixing is 6 to 24 h.

[0062] Furthermore, as a preferred method, the curing is carried out using a mold.

[0063] Specifically, the curing is to uniformly pour the obtained uniformly mixed solution into a mold and dry and cure it at 80 to 85 °C.

[0064] Preferably, the time of the drying is 1 to 5 h.

[0065] Preferably, the thickness of the gate dielectric layer is 5 to 20 μm. The gate dielectric layer within this thickness range exhibits better ion conductive performance, can effectively reduce the leakage current, thereby improving the reliability and overall performance of the device.

[0066] The present invention protects the preparation method of the above artificial synaptic transistor, including the following steps:

[0067] S1. Prepare a substrate covering the active layer;

[0068] S2. Attach a mask plate to the surface of the active layer obtained in step S1, and then evaporate and deposit the source electrode and the drain electrode;

[0069] S3. Prepare the gate dielectric layer;

[0070] S4. Remove the mask plate in step S2, and then attach the gate dielectric layer obtained in step S3 to obtain the artificial synaptic transistor.

[0071] This application proposes a method for fabricating an artificial synaptic transistor. During the fabrication process, the inventors ingeniously used ethanol as an anti-solvent, effectively improving the crystallinity of the active layer, thereby significantly optimizing the charge transport performance of the transistor. At the same time, to ensure the stable operation of the device, the interface roughness was also controlled to avoid an increase in interface roughness that might be brought about by the increase in crystallinity. In addition, the hydrophilicity and polarity of the materials were fully considered during the fabrication process. Good hydrophilicity ensured ion transport, and appropriate polarity promoted efficient charge transport. By comprehensively regulating these factors, this fabrication method successfully achieved an accurate balance of crystallinity, interface roughness, hydrophilicity, and polarity, thus significantly improving the performance of the artificial synaptic transistor.

[0072] Preferably, in step S2, the evaporation rate of the evaporation coating

[0073] Further, as a preferred method, in step S3, the ionic gel is the [PVDF-HFP][EMIM-TFSI] ionic gel.

[0074] The present invention protects the application of the above-mentioned active layer or the above-mentioned artificial synaptic transistor in the preparation of bionic sensing devices, neuromorphic memories, or brain-inspired computing chips.

[0075] Compared with the prior art, the present invention has the following beneficial effects:

[0076] The present invention innovatively fabricates an active layer for a synaptic transistor, which is characterized by adding ethanol to the PDPP-TT solution. This measure promotes the formation of a unique trap structure at the active layer interface, that is, the coexistence of high-density shallow traps and low-density deep traps, accompanied by the generation of interface discrete trap centers. This trap distribution significantly optimizes the ion mobility of the active layer, not only greatly broadening the analog dynamic range of the device, but also effectively enhancing the charge accumulation effect, thereby achieving a significant improvement in the synaptic post-current response. On this basis, an artificial synaptic transistor is further fabricated. This transistor not only exhibits excellent short-term plasticity, but also has excellent synaptic plasticity and high current response characteristics, providing strong support for its application in a wider range of fields. Description of the Drawings

[0077] Figure 1 It is a schematic structural diagram of the artificial synaptic transistor in Example 1; the schematic diagram mainly focuses on expressing the structural relationship, rather than accurately reflecting the actual thickness of each layer.

[0078] Figure 2 It is an excitatory postsynaptic current diagram of the artificial synaptic transistor in Example 1 under 5 groups of pulse stimulations.

[0079] Figure 3Excitatory postsynaptic current diagram of the artificial synaptic transistor in Comparative Example 1 under 5 groups of pulse stimulations.

[0080] Figure 4 Spike number-dependent plasticity index diagram of the artificial synaptic transistors in Example 1 and Comparative Example 1.

[0081] Figure 5 Excitatory postsynaptic current diagram of the artificial synaptic transistor in Example 1 under pulse stimulations of different frequencies.

[0082] Figure 6 Excitatory postsynaptic current diagram of the artificial synaptic transistor in Comparative Example 1 under pulse stimulations of different frequencies. Detailed implementation manners

[0083] The present invention will be further described below in conjunction with the specification drawings and specific embodiments, but the embodiments do not impose any form of limitation on the present invention. Unless otherwise specified, the reagents, methods and equipment used in the present invention are conventional reagents, methods and equipment in the technical field.

[0084] Unless otherwise specified, the reagents and materials used in the following examples are all commercially available.

[0085] Example 1 An artificial synaptic transistor and its preparation method

[0086] 1. An artificial synaptic transistor (the structural schematic diagram is as shown in Figure 1 ) includes a substrate - SiO 2 , an active layer - PDPP - TT - ethanol thin film, a gate dielectric layer - [PVDF - HFP][EMIM - TFSI] ionic gel, and a source electrode - Au and a drain electrode - Au on both sides of the gate dielectric layer.

[0087] 2. The preparation method of the above artificial synaptic transistor includes the following steps:

[0088] S1. Pretreatment of the substrate:

[0089] Put the SiO 2 thin film substrate into deionized water, acetone solution, and isopropanol in sequence, ultrasonically clean for 30 min respectively, then blow dry with nitrogen, and put it into an ultraviolet ozone cleaning machine for ozone treatment for 20 min to obtain the pretreated SiO 2 thin film substrate with a thickness of 300 nm.

[0090] S2. Preparation of the active layer:

[0091] S2-1. Add polydithiophene-pyrrolopyrrole diketoacetate (PDPP-TT) powder to chlorobenzene solution to prepare a 5 mg / mL solution, heat to 60 ° C, stir for 15 h, the solute is completely dissolved and turns orange-red to obtain a PDPP-TT solution;

[0092] S2-2. Mix ethanol and the PDPP-TT solution obtained in step S2-1 at a volume ratio of 1:9, stir for 30 minutes, and let stand for 12 hours to obtain a PDPP-TT-ethanol suspension.

[0093] S2-3. Use a pipette to transfer the PDPP-TT-ethanol suspension obtained in step S2-2 and evenly drop it on the pretreated SiO 2 The film substrate was spin-coated at a rotation speed of 2000 rpm / s for 50 seconds, and then annealed at 200° C. for 15 minutes on a heating plate to obtain a substrate covered with an active layer, the thickness of the active layer being 19 nm.

[0094] S3. Evaporation electrode:

[0095] The customized mask is attached to the surface of the active layer prepared in step S2, and then placed in the coating machine before 5nm was deposited at a deposition rate of , and then the deposition rate was increased to The Au layer was plated with a thickness of 30 nm, and finally a 35 nm thick Au layer was obtained on both sides of the active layer as the source electrode and the drain electrode.

[0096] S4. Preparation of gate dielectric layer:

[0097] S4-1. Mix polyvinylidene fluoride-hexafluoropropylene copolymer (PVDF-HFP) and acetone in a mass ratio of 1:4, and stir at 60°C for 10 min until completely dissolved to obtain a PVDF-HFP solution;

[0098] S4-2. The PVDF-HFP solution obtained in step S4-1 was mixed with 1-ethyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide (EMIM-TFSI) in a mass ratio of 1:3, and stirred at 60°C for 12h until the solution was clear and transparent without bubbles to obtain [PVDF-HFP] [EMIM-TFSI] ion gel solution;

[0099] S4-3. The [PVDF-HFP] [EMIM-TFSI] ion gel solution obtained in step S4-2 is evenly poured into the mold, and then transferred to a drying oven at 80 ° C. and dried for 2 hours to obtain a strippable [PVDF-HFP] [EMIM-TFSI] ion gel;

[0100] S4-4. Remove the mask in step S3, and then attach the peeled [PVDF-HFP][EMIM-TFSI] ionic gel film obtained in step S4-3 to the channel region as the gate dielectric layer. The thickness of the gate dielectric layer is 10 μm, and the resulting device is the artificial synaptic transistor.

[0101] Example 2 An artificial synaptic transistor and its manufacturing method

[0102] The difference from Example 1 is that in step S2-2 of the manufacturing method of the artificial synaptic transistor, the volume ratio of ethanol to the PDPP-TT solution is replaced from 1:9 to 1:13.

[0103] Other steps and conditions are the same as those in Example 1.

[0104] Example 3 An artificial synaptic transistor and its manufacturing method

[0105] The difference from Example 1 is that in step S2-2 of the manufacturing method of the artificial synaptic transistor, the volume ratio of ethanol to the PDPP-TT solution is replaced from 1:9 to 1:8.

[0106] Other steps and conditions are the same as those in Example 1.

[0107] Comparative Example 1 An artificial synaptic transistor and its manufacturing method

[0108] The difference from Example 1 is that in step S2-2 of the manufacturing method of the artificial synaptic transistor, ethanol is not added in the preparation of the active layer.

[0109] 1. An artificial synaptic transistor, comprising a substrate-SiO 2 , an active layer-PDPP-TT thin film, a gate dielectric layer-[PVDF-HFP][EMIM-TFSI] ionic gel, and source electrode-Au and drain electrode-Au on both sides of the gate dielectric layer.

[0110] 2. The manufacturing method of the above artificial synaptic transistor includes the following steps:

[0111] S1. Pretreatment of the substrate:

[0112] Put the SiO 2 thin film substrate into deionized water, acetone solution, and isopropyl alcohol in sequence, ultrasonically clean for 30 min respectively, then dry with nitrogen, and put it into an ultraviolet ozone cleaning machine for ozone treatment for 20 min to obtain the pretreated SiO 2 thin film substrate with a thickness of 300 nm.

[0113] S2. Preparation of the active layer:

[0114] S2-1. Add polydithiophene-pyrrolopyrrole diketoacetate (PDPP-TT) powder to chlorobenzene solution to prepare a 5 mg / mL solution, heat to 60 ° C, stir for 15 h, the solute is completely dissolved and turns orange-red to obtain a PDPP-TT solution;

[0115] S2-2. Use a pipette to transfer the PDPP-TT solution obtained in step S2-1 and evenly drop it on the pretreated SiO 2 The film substrate was spin-coated at a rotation speed of 2000 rpm / s for 50 seconds, and then annealed at 200° C. for 15 minutes on a heating plate to obtain a substrate covered with an active layer, the thickness of the active layer being 19 nm.

[0116] S3. Evaporation electrode:

[0117] The customized mask is attached to the surface of the active layer prepared in step S2, and then placed in the coating machine before 5nm was deposited at a deposition rate of , and then the deposition rate was increased to The Au layer was plated with a thickness of 30 nm, and finally a 35 nm thick Au layer was obtained on both sides of the active layer as the source electrode and the drain electrode.

[0118] S4. Preparation of gate dielectric layer:

[0119] S4-1. Mix polyvinylidene fluoride-hexafluoropropylene copolymer (PVDF-HFP) and acetone in a mass ratio of 1:4, and stir at 60°C for 10 min until completely dissolved to obtain a PVDF-HFP solution;

[0120] S4-2. The PVDF-HFP solution obtained in step S4-1 was mixed with 1-ethyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide (EMIM-TFSI) in a mass ratio of 1:3, and stirred at 60°C for 12h until the solution was clear and transparent without bubbles to obtain [PVDF-HFP] [EMIM-TFSI] ion gel solution;

[0121] S4-3. The [PVDF-HFP] [EMIM-TFSI] ion gel solution obtained in step S4-2 is evenly poured into the mold, and then transferred to a drying oven at 80 ° C. and dried for 2 hours to obtain a strippable [PVDF-HFP] [EMIM-TFSI] ion gel;

[0122] S4-4. Remove the mask in step S3, and then adhere the [PVDF-HFP][EMIM-TFSI] ion adhesive film obtained in step S4-3 to the channel area as a gate dielectric layer. The thickness of the gate dielectric layer is 10 μm. The resulting device is an artificial synaptic transistor.

[0123] Test of excitatory postsynaptic current performance of artificial synaptic transistors under 5 groups of pulse stimuli

[0124] 1. Experimental method

[0125] Take the artificial synaptic transistors prepared in Example 1 and Comparative Example 1 as test samples, and use a Keithley 4200-SCS semiconductor characteristic analyzer for testing. Test process: Connect the probe of electrode SUM1 to the source electrode, the probe of electrode SUM2 to the drain electrode, and the probe of electrode SUM3 to the ionic colloid of the gate dielectric layer as the top electrode. Continuously apply a reading voltage of -1V to electrode SUM2, and apply 5 groups of pulse sequences to electrode SUM3. Among them, the pulse sequences respectively contain 1, 2, 3, 4, and 5 negative pulses, and a signal with a single pulse duration of 0.05s is used as the presynaptic spike, and the excitatory postsynaptic current diagrams of the artificial synaptic transistors obtained by testing under 5 groups of different negative pulse numbers are obtained.

[0126] 2. Experimental results

[0127] It can be seen from Figure 2 that as the number of spikes increases, the concentration of negative charges accumulated at the interface between the PDPP-TT-ethanol suspension and the ionic conductor film in Example 1 gradually increases, which in turn leads to a corresponding increase in the postsynaptic current. Specifically, when the number of spikes is 1, 2, 3, 4, and 5 respectively, the corresponding maximum postsynaptic currents are 16.8 μA, 50.78 μA, 686.67 μA, 1281.41 μA, and 1575.44 μA. In contrast, Figure 3 in Comparative Example 1 (i.e., the PDPP-TT system without adding ethanol) has significantly lower maximum postsynaptic currents under the same number of spikes, which are 14.17 μA, 39.94 μA, 92.38 μA, 104.93 μA, and 122.1 μA respectively. The reason for this significant difference is that the addition of ethanol significantly enhances the charge accumulation effect, thereby improving the response degree of the postsynaptic current in the PDPP-TT-ethanol system; while Comparative Example 1 without adding ethanol is relatively weak in charge accumulation and conduction, resulting in a lower response degree to spike stimulation.

[0128] Furthermore, Figure 4Intuitively demonstrates the significant difference in the spike number-dependent plasticity index (SNDP index, calculation formula: ΔAn / ΔA1×100%) between the synaptic transistor prepared based on PDPP-TT (Comparative Example 1) and the artificial synaptic transistor prepared based on PDPP-TT-ethanol suspension (Example 1). Specifically, when only using the synaptic transistor prepared with PDPP-TT solution, as the input spike number increases from 1 to 5, its SNDP index increases successively to 100.00%, 281.86%, 651.94%, 740.51% and 861.67%. For the synaptic transistor prepared with PDPP-TT-ethanol suspension, under the same condition of increasing spike number, the SNDP index is significantly increased to 100.00%, 302.26%, 4087.32%, 7627.44% and 9377.62%, and the increase amplitude is about 10 times that of the former. This data clearly shows that by introducing ethanol as an antisolvent into the PDPP-TT solution, as the spike number continuously increases, the synaptic transistor prepared based on PDPP-TT-ethanol suspension exhibits an increasingly enhanced postsynaptic current response intensity. This phenomenon directly reflects the significant improvement of the device in spike number-dependent plasticity, further emphasizing the high flexibility and adaptability demonstrated by the device in processing information.

[0129] Experimental Example 2: Excitatory postsynaptic current performance test of artificial synaptic transistors under different frequency pulse stimulations

[0130] 1. Experimental method

[0131] Take the artificial synaptic transistors prepared in Example 1 and Comparative Example 1 as test samples, and use a Keithley 4200-SCS semiconductor characterization analyzer for testing. Test process: Connect the probe of electrode SUM1 to the source electrode, the probe of electrode SUM2 to the drain electrode, and the probe of electrode SUM3 to the ionic colloid of the gate dielectric layer as the top electrode. Continuously apply a reading voltage of -1V to electrode SUM2, and apply a series of different frequency pulse sequences to electrode SUM3 as presynaptic spikes. Among them, each sequence contains 10 pulse spikes, with an amplitude of -3.5V and a duration of 0.05s, and set different time intervals between adjacent pulses to generate different frequencies: 10Hz frequency is generated at 0.1s interval, 5Hz frequency is generated at 0.2s interval, 2.5Hz frequency is generated at 0.4s interval, 1.25Hz frequency is generated at 0.8s interval, and 0.625Hz frequency is generated at 1.6s interval, and obtain the excitatory postsynaptic current diagrams of the artificial synaptic transistors under negative pulse stimulations at different frequencies (5 frequencies).

[0132] 2. Experimental results

[0133] From Figure 5As shown, in Example 1, when the frequency of the stimulation spike increases from 0.625Hz to 10Hz, the postsynaptic current of the artificial synaptic transistor increases significantly from 23.24μA to 1069.42μA, and the regulation range is as high as 1046.2μA. This result clearly demonstrates the excellent current regulation ability of the device under different frequency stimulation drive and exhibits excellent stimulation frequency synaptic plasticity. More importantly, after the stimulation is removed, the postsynaptic current can quickly return to the initial value, which reflects its excellent short-term memory. In contrast, in Comparative Example 1 ( Figure 6 ), in the same frequency variation range (increasing from 0.625 Hz to 10 Hz), although the postsynaptic current of the artificial synaptic transistor also increased from 26.79 μA to 353.18 μA, its control range was only 326.39 μA. Specifically, the postsynaptic current control range of the synaptic transistor in Example 1 is 3.2 times that of Comparative Example 1.

[0134] In summary, the synaptic transistor prepared using the PDPP-TT-ethanol suspension in Example 1 shows even better performance in terms of stimulation frequency-dependent synaptic plasticity while maintaining excellent short-term memory. In Examples 2 to 3, the performance of the synaptic transistors prepared by the experiments was verified to be substantially the same as that of Example 1 by only changing the volume ratio of the PDPP-TT and ethanol solutions, so it will not be repeated here.

[0135] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A method for preparing an active layer for a synaptic transistor, characterized in that: The steps include: Ethanol is added to the polydithiophene-pyrrolopyrrole diketo solution and mixed to obtain a polydithiophene-pyrrolopyrrole diketo-ethanol suspension, the obtained suspension is evenly coated on a substrate, and the coated substrate is annealed to obtain an active layer.

2. The preparation method according to claim 1, characterized in that: The volume ratio of the ethanol to the PDPP-TT solution is 1:(7-13).

3. The active layer prepared by the preparation method according to claim 1 or 2.

4. Use of the active layer according to claim 3 in preparing a synaptic transistor.

5. An artificial synaptic transistor, characterized in that: It includes a substrate, an active layer, a gate dielectric layer, and a source electrode and a drain electrode arranged on both sides of the gate dielectric layer. Wherein, the active layer is the active layer described in claim 3.

6. The artificial synaptic transistor according to claim 5, characterized in that: The gate dielectric layer is an ion glue.

7. The artificial synaptic transistor according to claim 6, characterized in that: The ion glue includes any one of [PVDF-HFP] [EMIM-TFSI] ion glue, polyethylene oxide-sodium ion glue, and polyethylene oxide-lithium ion glue.

8. The artificial synaptic transistor according to claim 5, characterized in that: The source electrode and the drain electrode are made of the same material; the source electrode and the drain electrode are made of gold, silver or copper.

9. The method for preparing the artificial synaptic transistor according to any one of claims 5 to 8, characterized in that: The following steps are involved: S1. Preparing a substrate covering an active layer; S2. Laminating the mask on the surface of the active layer obtained in step S1, and then evaporating the source electrode and the drain electrode; S3. preparing a gate dielectric layer; S4. Remove the mask in step S2, and then attach the gate dielectric layer obtained in step S3 to obtain an artificial synaptic transistor.

10. Use of the active layer according to claim 3 or the artificial synaptic transistor according to any one of claims 5 to 8 in the preparation of bionic sensor devices, neuromorphic memories or brain-like computing chips.

Images