Neural microelectrode based on silicon nanostructure and preparation method thereof

Abstract

The invention discloses a neural microelectrode based on a silicon nanostructure and a preparation method of the neural microelectrode. The neural microelectrode comprises a silicon substrate with the silicon nanostructure, and a first insulating layer, a conductive layer and a second insulating layer which are sequentially stacked on the silicon substrate, wherein the silicon nanostructure is a silicon nanocolumn structure, and the second insulating layer partially covers the conductive layer, so that a stimulation site, a recording site and a welding site of the conductive layer are exposed. According to the invention, the silicon substrate with the silicon nanostructure is used as a substrate material of the neural microelectrode, the silicon nanostructure is a high-density three-dimensional nanostructure formed by the silicon nanorod array, the diameter and height of the silicon nanorod can be flexibly adjusted, and the silicon nanorod has a relatively large specific surface area, so that the overall effective surface area of the neural microelectrode is increased; furthermore, the impedance of the microelectrode is reduced and the electrochemical performance of the microelectrode is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of microsensors, and particularly to a neural microelectrode based on silicon nanostructures and a preparation method thereof. Background Art

[0002] Neural microelectrodes are key tools in neuroscience research and the treatment of neurological diseases, and their performance directly affects the quality of neural signal recording and the effect of neural stimulation. In the design of neural microelectrodes, how to effectively increase the contact area between the electrode and neural tissue, and thus reduce the electrochemical impedance, is one of the core issues for improving the electrode performance. Currently, the widely used neural microelectrodes usually present a planar or simple geometric structure at the stimulation and recording sites, resulting in a limited actual contact area with neural tissue.

[0003] To improve the electrochemical performance of neural microelectrodes, researchers have developed various surface treatment techniques to increase the effective contact area of the electrodes. Ding Yaping et al. prepared nano-platinum black on the surface of microelectrodes by electrochemical deposition, and used the rough particle surface of nano-platinum black to increase the effective surface area of the electrode; Zeng Qi et al. effectively increased the surface area of the electrode and improved the comprehensive performance of the electrode by modifying the doped conductive polymer structure on the surface of metal nanodendrites; Zhao Zongya et al. disclosed a surface modification method for silicon-based electrodes based on porous gold-platinum nanoparticles. A layer of gold-platinum-copper trimetallic alloy nanoparticles was deposited on the sites of silicon-based microelectrodes by electro-deposition, and then the silicon-based microelectrodes modified with gold-platinum-copper trimetallic alloy nanoparticles were immersed in a copper etching solution to selectively etch away the copper component in the alloy nanoparticles, and finally silicon-based microelectrodes modified with porous gold-platinum alloy nanoparticles were obtained; IMEC et al. prepared titanium nitride nanostructures by hydrothermal method to increase the specific surface area of titanium nitride, so as to reduce the electrochemical impedance of the corresponding electrodes; Pei Weihua et al. proposed a method for preparing silicon-based microelectrodes. The method mixed a suspension of noble metal nanoparticles with a silicon etching solution to form a nano-hole array on the surface of the silicon wafer, and then an insulating layer, a conductive layer and an upper insulating layer were prepared on the nano-hole array to obtain a rough micro-recording point electrode with a nano-hole array; Edward et al. effectively reduced the electrode impedance and enhanced the charge transfer ability on the electrode surface by coating carbon nano-pores on the electrode surface using electrochemical technology.

[0004] In the prior art, although methods such as electrochemically depositing noble metal materials, growing conductive polymers, dealloying, and hydrothermal treatment can increase the electrode surface area, these methods have the following technical problems: First, wet processes such as electrochemical deposition and conductive polymer modification have complex processes, and the materials have poor stability in the long-term implantation environment, are prone to falling off, affect the electrode performance, and pose a threat to the implanted recipient at the same time; Second, the dealloying and hydrothermal treatment methods are limited by the material itself and cannot be applied to a variety of materials as a general method. Chinese Patent CN103101878A provides a good idea for increasing the specific surface area of the electrode by catalytically corroding a nanohole array on the surface of a silicon wafer using noble metal nanoparticles. However, this method mainly uses a noble metal nanoparticle suspension to catalytically corrode the surface of the silicon wafer, and there are problems such as uneven surface dispersion of noble metal nanoparticles, limited coverage area, difficult control of the corrosion process, and the consumption of photoresist during etching affecting its protection effect. At the same time, its underlying insulating layer is thermally oxidized silicon, which requires a process preparation at a temperature exceeding 1000 °C, and the process conditions are harsh. The prior art lacks a general method that can form a regular three-dimensional structure on the electrode surface, especially it is difficult to construct a three-dimensional structure template with a high specific surface area and a simple and controllable process. Summary of the Invention

[0005] In order to overcome the above defects of the prior art, the purpose of the present invention is to provide a neural microelectrode based on a silicon nanostructure and its preparation method, and solve the technical problem that it is difficult to construct a neural microelectrode with a high specific surface area and a simple and controllable process in the prior art.

[0006] To achieve the above purpose, the present invention is realized through the following technical solutions: In a first aspect, the present invention provides a neural microelectrode based on a silicon nanostructure, including a silicon substrate having a silicon nanostructure, and a first insulating layer, a conductive layer, and a second insulating layer sequentially stacked on the silicon substrate; wherein the silicon nanostructure is a silicon nanowire, and the second insulating layer partially covers the conductive layer, exposing the stimulation site, recording site, and welding site of the conductive layer.

[0007] In the present invention, the diameter of the silicon nanowires can be adjusted within the range of several nanometers to several hundred nanometers, and the height can be adjusted within the range of several hundred nanometers to several tens of micrometers. For example, in some embodiments, the diameter of the silicon nanowires is 1 - 500 nm, and the height is 10 nm - 50 μm. In other embodiments, the diameter of the silicon nanowires is 100 - 500 nm, and the height is 5 - 20 μm.

[0008] In some embodiments, the preparation method of the silicon substrate having a silicon nanostructure includes the following steps: Prepare a patterned catalytic layer on the silicon substrate; Etch the silicon substrate with an etching solution under the catalysis of a patterned catalyst layer to obtain a silicon substrate with silicon nanostructures.

[0009] In some embodiments, the method for obtaining a patterned catalyst layer on a silicon substrate includes: performing a photolithography process on the silicon substrate to obtain a preset pattern; the preset pattern includes the stimulation sites and recording sites of the electrode, or the stimulation sites, recording sites of the electrode, and the pattern of the wire connecting the stimulation sites and recording sites; depositing a catalyst layer on the preset pattern of the silicon substrate by physical vapor deposition; and removing the remaining photoresist on the silicon substrate by a lift-off process to obtain a patterned catalyst layer.

[0010] In some embodiments, the method for obtaining a patterned catalyst layer on a silicon substrate includes: depositing a catalyst layer on the silicon substrate by physical vapor deposition; performing a photolithography process on the catalyst layer of the silicon substrate to obtain a preset pattern; the preset pattern includes the stimulation sites and recording sites of the electrode, or the stimulation sites, recording sites of the electrode, and the pattern of the wire connecting the stimulation sites and recording sites; and removing the catalyst layer outside the preset pattern on the silicon substrate by an etching process to obtain a patterned catalyst layer.

[0011] In the present invention, the catalyst layer is a discontinuous thin film, which is obtained by controlling the thickness of the catalyst layer, deposition temperature, and / or post-annealing temperature. For example, in some embodiments, the thickness of the catalyst layer is 0.5 - 10 nm; the deposition temperature of the catalyst layer is 20 - 1000 °C, and the annealing temperature is 100 - 1000 °C. In some other embodiments, the deposition temperature for depositing the catalyst layer by physical vapor deposition is 200 - 400 °C, the annealing temperature is 400 - 600 °C; the thickness of the catalyst layer is 1 - 5 nm. The material for forming the catalyst layer is a noble metal material, including but not limited to noble metals such as gold, silver, and platinum.

[0012] In some embodiments, the silicon substrate is a common silicon wafer or an SOI silicon wafer.

[0013] In some embodiments, the method for preparing the above-mentioned silicon substrate with silicon nanostructures further includes using a wet chemical method to remove the residual catalyst material on the silicon substrate with silicon nanostructures. Among them, the wet chemical method can soak and wash the silicon substrate with a nitric acid solution or a mixed solution of iodine and potassium iodide, so that the residual catalyst material on the silicon substrate reacts chemically with the nitric acid solution or the mixed solution of iodine and potassium iodide and is removed.

[0014] In some embodiments, the etching solution contains HF and H 2 O 2 。In some preferred embodiments, the molar ratio of HF and H 2 O 2 in the etching solution is 4:(0.1 - 1.5).

[0015] Second aspect, the present invention provides a method for preparing a neural microelectrode based on a silicon nanostructure as described in the first aspect, comprising the following steps: Deposit a first insulating layer on the surface of a silicon substrate having a silicon nanostructure; Fabricate a patterned conductive layer on the first insulating layer; deposit a second insulating layer on the conductive layer, and then, using a photolithography process and an etching technique, expose the stimulation sites, recording sites, and welding sites of the conductive layer. Use a photolithography process to expose the contour of the neural microelectrode, and use an etching technique to thin the silicon substrate until a preset thickness is reached; the etching technique includes one or more of deep silicon etching and wet etching techniques. Based on the contour of the neural microelectrode, use an etching technique or a cutting process to remove the excess portion of the silicon substrate to obtain the neural microelectrode.

[0016] In some embodiments, the method for fabricating a patterned conductive layer on the first insulating layer includes: performing a photolithography process on the first insulating layer to obtain an electrode pattern; the electrode pattern includes the stimulation sites, recording sites, and welding sites of the electrode, as well as the pattern of the wires connecting the stimulation sites, recording sites, and welding sites; deposit a conductive layer on the surface of the first insulating layer, and then, strip and remove the remaining photoresist on the surface of the first insulating layer to obtain the patterned conductive layer.

[0017] In some embodiments, the method for fabricating a patterned conductive layer on the first insulating layer includes: deposit a conductive layer on the surface of the first insulating layer, and then perform a photolithography process to obtain an electrode pattern; the electrode pattern includes the stimulation sites, recording sites, and welding sites of the electrode, as well as the pattern of the wires connecting the stimulation sites, recording sites, and welding sites; etch away the conductive layer outside the electrode pattern to obtain the patterned conductive layer.

[0018] In some embodiments, the deposition methods of the first insulating layer, the conductive layer, and the second insulating layer include at least one of electrochemical deposition, atomic layer deposition, physical vapor deposition, and chemical vapor deposition; the deposition methods of the first insulating layer, the conductive layer, and the second insulating layer are the same or different.

[0019] In some embodiments, the material for forming the first insulating layer is one or more of insulating oxides and insulating nitrides, including but not limited to aluminum oxide, hafnium oxide, silicon oxide, silicon nitride, etc. The material for forming the conductive layer is one or more of metal materials, carbon-based materials, semiconductor materials, and conductive polymers. Metal materials include but are not limited to platinum, gold, silver, titanium, etc. Carbon-based materials include but are not limited to graphene, carbon nanotubes, etc. Semiconductor materials include but are not limited to titanium nitride, silicon carbide, etc. Conductive polymers include but are not limited to PEDOT:PSS (poly(2,3-dihydrothieno[3,4-b][1,4]dioxin)-poly(styrenesulfonate)), PPy (polypyrrole), etc. The material for forming the second insulating layer is one or more of insulating oxides and insulating nitrides, including but not limited to silicon oxide, hafnium oxide, aluminum oxide, silicon nitride, etc.

[0020] In the present invention, the preset thickness of the overall structure of the neural microelectrode can be controlled by thinning a common silicon wafer, or by controlling the thickness of the top silicon in an SOI (silicon-on-insulator) silicon wafer.

[0021] The beneficial effects of the present invention are as follows: 1. The present invention uses a silicon substrate with a silicon nanostructure as the substrate material of the neural microelectrode. This silicon nanostructure is a high-density three-dimensional nanocolumn structure. Since the silicon nanocolumns have regular morphological characteristics and a large specific surface area, the deposited conductive metal material can conformally and uniformly grow along the contour of the silicon nanocolumns, forming a continuous and dense functional layer (conductive layer). Thus, not only the effective surface area of the electrode is increased, but also the impedance of the electrode is reduced, and the electrochemical performance of the electrode is improved.

[0022] 2. By depositing an insulating layer and a functional layer on the silicon substrate with a silicon nanostructure, the present invention can achieve good coverage uniformity and strong bonding force of the materials, and they are not easy to fall off, ensuring the stability of the electrode during long-term use.

[0023] 3. The present invention uses a metal-assisted chemical etching method to form a three-dimensional silicon nanostructure with highly controllable height in a specific area of the silicon substrate. By simply adjusting process parameters (such as the type and thickness of the catalyst, the ratio of the etching solution, the etching time, etc.), the morphological characteristics such as the diameter, length, and spacing of the silicon nanocolumns can be precisely controlled. The nanostructure formed by this top-down etching method has good uniformity and regularity, and at the same time has an adjustable aspect ratio, which can significantly increase the specific surface area of the electrode.

[0024] 4. The method for constructing the silicon nanostructure provided by the present invention is fully compatible with the standard micro-nano processing technology. It can precisely control the local formation on the electrode surface through lithography, lift-off process, etching process, etc., to achieve surface selective etching. The characteristics of this selective etching enable the performance of other functional regions of the electrode to be unaffected, and at the same time, no additional photoresist is required to protect other functional regions during the etching process. Brief Description of the Drawings

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below.

[0026] Figure 1 It is an optical microscope image of the silicon substrate with silicon nanostructures prepared in Example 1; Figure 2 It is an SEM image of the silicon nanostructures prepared in Examples 1 to 3; Figure 3 It is a process flow chart for preparing the neural microelectrode in Examples 1 to 4; Figure 4 It is a picture of the neural microelectrode prepared in Example 1; Figure 5 It is an optical microscope image of the silicon substrate with silicon nanostructures prepared in Example 4; Figure 6 It is an electrochemical impedance spectrum of the recording electrode and the stimulating electrode of the neural microelectrode in Examples 1 to 2 and Comparative Example 1; Figure 7 It is a cyclic voltammogram of the recording electrode and the stimulating electrode of the neural microelectrode in Examples 1 to 2 and Comparative Example 1. Detailed Embodiments

[0027] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the scope of protection of the present invention.

[0028] Example 1 A method for preparing a neural microelectrode based on silicon nanostructures, comprising the following steps: S1. Prepare a silicon substrate with silicon nanostructures S1.1 Configure a 0.5 mol / L HF solution to clean the silicon wafer for 1 minute to remove the native silicon oxide on the surface of the silicon wafer. Use the standard photolithography process to form a preset pattern on the silicon wafer: Photolithography is a technology that uses a photosensitive material (photoresist) to transfer fine patterns. In this step, first coat a layer of S1805 photoresist on the silicon wafer, then align and expose through a mask, and finally develop to form a preset pattern. As Figure 1 shown, the preset pattern includes the stimulation sites of the electrodes (isosceles triangles with a base of 60 μm and a height of 228 μm), the recording sites (circles with a diameter of 20 μm), and the patterns of the wires connecting the stimulation sites and the recording sites.

[0029] S1.2 Use an electron beam evaporation device to deposit a 1 nm thick gold catalyst layer on the silicon wafer, and then use the lift-off process to remove the remaining photoresist on the silicon substrate to obtain a patterned gold catalyst layer.

[0030] S1.3 Use a mixed solution of HF and H 2 O 2 to perform metal-assisted chemical etching on the gold on the surface of the patterned gold catalyst layer. Among them, the molar ratio of HF and H 2 O 2 is 4:0.5, and the etching time is 30 minutes to form a silicon nanowire structure on the preset pattern of the silicon wafer. Then, use an iodine-potassium iodide mixed solution to remove the residual gold catalyst to obtain a silicon substrate with a silicon nanostructure. Figure 2 is the SEM image of the silicon nanostructure. It can be seen that when 1 nm thick gold is used as the catalyst in this embodiment, the silicon nanowires are closely arranged, and their height is about 6.7 μm.

[0031] S2. Fabricate neural microelectrodes S2.1 As shown in a of Figure 3 , use atomic layer deposition technology to deposit a 50 nm thick hafnium oxide on the surface of the silicon substrate with a silicon nanostructure as the first insulating layer.

[0032] S2.2 Use the standard photolithography process to over-etch the electrode pattern on the first insulating layer: First, coat a layer of S1813 photoresist on the surface of the first insulating layer, then align and expose through a mask, and finally develop to form an electrode pattern. The electrode pattern includes the stimulation sites of the electrodes (isosceles triangles with a base of 60 μm and a height of 228 μm), the recording sites (circles with a diameter of 20 μm), the welding sites, and the patterns of the wires connecting the stimulation sites, the recording sites, and the welding sites.

[0033] S2.3 As shown in Figure 3As shown in b of [reference], a conductive layer is deposited on the surface of the first insulating layer by magnetron sputtering. The conductive layer includes 20 nm of Ti and 170 nm of Pt.

[0034] S2.4 After the deposition of the metal conductive layer is completed, the remaining photoresist on the first insulating layer is removed by a lift-off process to obtain a patterned conductive layer.

[0035] S2.5 As shown in Figure 3 c of [reference], a 200 nm thick silicon dioxide layer is deposited on the surface of the conductive layer by plasma-enhanced chemical vapor deposition technology as the second insulating layer.

[0036] S2.6 In order to construct the stimulation sites, recording sites, and metal welding sites of the electrode, a photolithography process is required to form the required opening pattern. This step also uses the standard photolithography process: First, a layer of S1813 photoresist is coated on the surface of the second insulating layer, then aligned and exposed through a mask, and finally developed to form the patterns of the stimulation sites, recording sites, and metal welding sites of the electrode. As shown in Figure 3 d of [reference], the stimulation sites, recording sites, and metal welding sites are opened by inductively coupled plasma etching technology to a depth reaching the conductive layer, that is, the chemical reaction and physical bombardment generated by the plasma are used to remove the silicon dioxide covering the stimulation sites, recording sites, and metal welding sites of the conductive layer, so that the stimulation sites, recording sites, and welding sites of the conductive layer on the silicon nanostructure are exposed.

[0037] S2.7 As shown in Figure 3 e of [reference], a photolithography process is used to over-etch the overall contour pattern (needle shape) of the electrode on the back of the silicon wafer, and a deep reactive ion etching (DRIE) technology is used to thin the thickness of the electrode to less than 80 μm.

[0038] S2.8 As shown in Figure 3 f of [reference], a photolithography process is used to over-etch the contour pattern (needle shape) of the electrode on the front of the silicon wafer, and the deep reactive ion etching technology is used again to etch through along the thickness direction of the silicon wafer to remove the redundant silicon substrate part, obtaining a neural microelectrode with a needle shape as shown in Figure 4 denoted as B-Au1-Pt.

[0039] Example 2 A neural microelectrode based on silicon nanostructures, the preparation method of which is basically the same as that of Example 1, except that: in step S1.2, an electron beam evaporation device is used to deposit a 3 nm thick gold catalytic layer on the silicon wafer, and then the remaining photoresist on the silicon substrate is removed by a lift-off process to obtain a patterned gold catalytic layer. From Figure 2It can be seen that when 3 nm thick gold is used as the catalyst in this embodiment, the arrangement of silicon nanocolumns is relatively dispersed, and irregular continuous holes are presented when viewed from the front. This is due to the aggregation of gold particles with the increase of the thickness of the gold catalytic layer. The height of the silicon nanocolumns is about 10.9 μm. The obtained neural microelectrode is denoted as B-Au3-Pt.

[0040] Example 3 A neural microelectrode based on silicon nanostructure, the preparation method of which is basically the same as that of Example 1, except that: in step S1.2, an electron beam evaporation device is used to deposit a 5 nm thick gold catalytic layer on the silicon wafer, and then the remaining photoresist on the silicon substrate is removed by a lift-off process to obtain a patterned gold catalytic layer. From Figure 2 It can be seen that when 5 nm thick gold is used as the catalyst in this embodiment, the arrangement of silicon nanocolumns is looser, and the height of the silicon nanocolumns is about 12.3 μm.

[0041] Example 4 A neural microelectrode based on silicon nanostructure, the preparation method of which is basically the same as that of Example 1, except that: in step S1.1, a preset pattern is formed on the surface of the silicon wafer by a standard photolithography process, such as Figure 5 shown, the preset pattern only includes the triangular stimulation site and the circular recording site of the electrode.

[0042] Comparative Example 1 A neural microelectrode, the preparation method of which is basically the same as that of Example 1, except that: silicon nanostructures are not constructed on the silicon wafer. That is, during the preparation of the neural microelectrode, the cleaned silicon wafer is directly used as the substrate to obtain a traditional planar neural microelectrode, denoted as Planer-Pt.

[0043] Performance Test (1)Electrochemical Impedance Test An electrochemical workstation with the model of Ivium Technologies BV, CompactStat.h is used for impedance testing. The experiment is carried out at room temperature, and a three-electrode system is used, where the working electrode is the neural microelectrode based on silicon nanostructure prepared in the example, the reference electrode is an Ag / AgCl electrode, and the counter electrode is a platinum wire electrode. The electrolyte solution is a phosphate buffer solution (PBS, pH = 7.4, NaCl: 136.89 mM; KCl: 2.67 mM; Na 2 HPO 4 : 8.1 mM; KH 2 PO 4 : 1.76 mM). The test frequency range is set to 10 - 10 4 Hz, and the amplitude of the AC excitation signal is 10 mV. The test results are asFigure 6 As shown, SE in the figure refers to the stimulation electrode site, and RE refers to the recording electrode site.

[0044] From Figure 6 It can be seen that the impedance value of the silicon nanostructure-based neural stimulation electrode prepared in the embodiment of the present invention is as low as 18.59 kΩ at a frequency of 1 kHz, while the impedance value of the traditional planar electrode at the same frequency is 364.2 kΩ. And the impedance value of the silicon nanostructure-based neural recording electrode of the present invention is as low as 118.2 kΩ at a frequency of 1 kHz, while the impedance value of the traditional planar electrode at the same frequency is 3205 kΩ. By comparing the impedance values, it is clearly shown that the impedance value of the electrode of the present invention is reduced by more than 90% compared with the traditional planar electrode. This is because the silicon nanostructure in the substrate of the electrode of the present invention is composed of a highly uniform and regularly arranged silicon nanowire array, which provides a huge specific surface area. According to the electrochemical impedance theory, the increase in the specific surface area increases the double-layer capacitance at the electrode / solution interface, thereby reducing the impedance. At the same time, the platinum conductive material uniformly covered on the surface of the silicon nanostructure by physical vapor deposition further optimizes the charge transfer path, so that the conductive material is uniformly distributed on the surface of the three-dimensional structure, and the combined effect significantly reduces the impedance, which is beneficial to improving the signal recording quality and neural stimulation efficiency of the electrode.

[0045] (2) Cyclic voltammetry test The cyclic voltammetry test was carried out on the same electrochemical workstation as above. The scanning rate was set at 50 mV / s, and the potential scanning range was -0.6 - 0.8 V. The cyclic voltammetry curve of the electrode of the present invention shows a large curve area. As Figure 7 shown, within -0.6 - 0.8 V, by comparing the curve areas, it is shown that the neural microelectrode prepared in the present invention has a larger charge storage capacity, which is more than 10 times higher than that of the traditional planar electrode. This is because the three-dimensional silicon nanostructure significantly increases the electrochemical active area of the electrode. During the cyclic voltammetry test, more active sites participate in the electrochemical reaction, increasing the current density. According to the relationship between the charge storage capacity and the electrochemical active area, the increase in the active area directly promotes the increase in the charge storage capacity, which is manifested as a larger curve area in the cyclic voltammetry curve.

[0046] In summary, in the present invention, first, a metal-assisted chemical etching method is used to form silicon nanostructures on the surface of a silicon substrate. This top-down growth method can form a high-density and highly ordered silicon nanocolumn array on the electrode surface, with controllable diameter, length, and spacing. This regular three-dimensional structure provides an ideal template for the uniform deposition of subsequent functional materials. Second, the present invention combines the silicon nanostructures with methods such as physical vapor deposition and chemical vapor deposition, and forms a novel composite electrode interface by conformally depositing functional materials on the surface of the silicon nanostructures. This method not only overcomes the stability problems existing in traditional electrochemical deposition and conductive polymer modification, but also realizes the doubling effect of the electrode surface area.

[0047] It should be noted that the above embodiments all belong to the same inventive concept. The descriptions of the embodiments have their own emphases. For the parts not described in detail in individual embodiments, reference can be made to the descriptions in other embodiments.

[0048] The above-described embodiments only represent the implementation manners of the present invention. The descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the inventive concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A neural microelectrode based on silicon nanostructure, characterized in that: It comprises a silicon substrate having a silicon nanostructure, and a first insulating layer, a conductive layer and a second insulating layer which are sequentially stacked on the silicon substrate; Wherein, the silicon nanostructure is a silicon nanocolumn structure, and the second insulating layer partially covers the conductive layer, so that the stimulation site, the recording site and the welding site of the conductive layer are exposed.

2. The neural microelectrode based on silicon nanostructure according to claim 1, characterized in that: The silicon nanocolumn has a diameter of 1-500 nm and a height of 10 nm-50 μm.

3. The neural microelectrode based on silicon nanostructure according to claim 1, characterized in that: The method for preparing the silicon substrate having the silicon nanostructure comprises the following steps: A patterned catalyst layer is prepared on a silicon substrate; The silicon substrate is corroded by using an etching solution under the catalytic action of the patterned catalytic layer to obtain a silicon substrate with a silicon nanostructure.

4. The neural microelectrode based on silicon nanostructure according to claim 3, characterized in that: The method for obtaining a patterned catalytic layer on the silicon substrate comprises: Performing a photolithography process on a silicon substrate to obtain a preset pattern; the preset pattern includes a stimulation site and a recording site of an electrode, or a stimulation site, a recording site, and a pattern of a wire connecting the stimulation site and the recording site of an electrode; Depositing a catalytic layer on the silicon substrate having a preset pattern by physical vapor deposition; Using a stripping process to strip off the remaining photoresist on the silicon substrate to obtain a patterned catalyst layer; Alternatively, the method for obtaining a patterned catalytic layer on the silicon substrate comprises: Depositing a catalyst layer on a silicon substrate using physical vapor deposition; Performing a photolithography process on the catalyst layer of the silicon substrate to obtain a preset pattern; the preset pattern includes the stimulation site and the recording site of the electrode, or the stimulation site, the recording site, and the pattern of the wire connecting the stimulation site and the recording site of the electrode; The catalyst layer outside the preset pattern on the silicon substrate is removed by an etching process to obtain a patterned catalyst layer.

5. The neural microelectrode based on silicon nanostructure according to claim 4, characterized in that: The material forming the catalytic layer is a precious metal material; The thickness of the catalytic layer is 0.5-10 nm; The deposition temperature of the catalytic layer is 20-1000°C, and the annealing temperature is 100-1000°C; The silicon substrate is a common silicon wafer or a SOI (Silicon on Insulator) silicon wafer.

6. The neural microelectrode based on silicon nanostructure according to claim 3, characterized in that: The method also includes removing residual catalytic materials on the silicon substrate having the silicon nanostructures by using a wet chemical method.

7. The neural microelectrode based on silicon nanostructure according to claim 3, characterized in that: The etching solution contains HF and H2O2.

8. A method for preparing a neural microelectrode based on a silicon nanostructure according to any one of claims 1 to 7, characterized in that: The following steps are involved: Depositing a first insulating layer on the surface of the silicon substrate having the silicon nanostructure; preparing a patterned conductive layer on the first insulating layer; Depositing a second insulating layer on the conductive layer, and then using photolithography and etching techniques to expose the stimulation sites, recording sites and welding sites of the conductive layer; The outline of the neural microelectrode is exposed by a photolithography process, and the silicon substrate is thinned by an etching technique until a preset thickness is reached; the etching technique includes one or more of deep silicon etching and wet etching techniques; Based on the outline of the neural microelectrode, an etching technique or a cutting process is used to remove the redundant silicon substrate to obtain the neural microelectrode.

9. The method for preparing a neural microelectrode based on silicon nanostructure according to claim 8, characterized in that: The method for preparing a patterned conductive layer on the first insulating layer comprises: Performing a photolithography process on the first insulating layer to obtain an electrode pattern; the electrode pattern includes a stimulation site, a recording site, a welding site, and a pattern of wires connecting the stimulation site, the recording site, and the welding site; Depositing a conductive layer on the surface of the first insulating layer, and then stripping off the remaining photoresist on the surface of the first insulating layer to obtain a patterned conductive layer; Alternatively, the method for preparing a patterned conductive layer on the first insulating layer comprises: Depositing a conductive layer on the surface of the first insulating layer, and then performing a photolithography process to obtain an electrode pattern; the electrode pattern includes a stimulation site, a recording site, a welding site, and a pattern of wires connecting the stimulation site, the recording site, and the welding site; The conductive layer other than the electrode pattern on the surface of the first insulating layer is removed by etching to obtain a patterned conductive layer.

10. The method for preparing a neural microelectrode based on silicon nanostructure according to claim 8, characterized in that: The deposition method of the first insulating layer, the conductive layer and the second insulating layer comprises at least one of electrochemical deposition, atomic layer deposition, physical vapor deposition and chemical vapor deposition; The deposition methods of the first insulating layer, the conductive layer and the second insulating layer are the same or different; The material forming the first insulating layer is one or more of insulating oxides and insulating nitrides; the material forming the conductive layer is one or more of metal materials, carbon-based materials, semiconductor materials, and conductive polymers; the material forming the second insulating layer is one or more of insulating oxides and insulating nitrides; The preset thickness of the overall structure of the neural microelectrode can be controlled by thinning a common silicon wafer, or by the thickness of the top silicon in the SOI silicon wafer.

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