High quality nitride and oxide fabrication and systems

Abstract

The invention relates to high quality nitride and oxide fabrication and systems. A method (200) to form at least one of a nitride or oxide layer for an integrated circuit, the method comprising: (i) positioning (202) a semiconductor wafer in a processing chamber, the semiconductor wafer comprising a wafer front side, and the processing chamber comprising a differential surface adapted to couple to a plasma ignition external radio frequency source; (ii) depositing (208) one of a nitride or an oxide by reacting in the chamber at least two precursor gases for a selected one of the nitride or oxide layers when the plasma ignition external radio frequency source is enabled on at least one exposed portion of the semiconductor wafer or a layer attached relative to a front side of the wafer; and (iii) post-processing (210) the one of the nitride or the oxide by exposure to helium and nitrogen in the absence of at least one of the at least two precursor gases with the plasma-ignited external radio frequency source enabled and in the absence of the at least one of the at least two precursor gases.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 63 / 604,137, filed on November 29, 2023, entitled "PECVD Front side High Quality Nitride and Oxide Processes", which is hereby incorporated by reference herein. Technical Field

[0003] The described examples relate to semiconductor manufacturing, for example, with respect to forming silicon nitride layers and silicon oxide layers in integrated circuits (ICs). Background Art

[0004] ICs are found in all forms of electronic devices, and the material layers (or "films") that are commonly used in many of those ICs are silicon nitride and silicon oxide (sometimes simply referred to as "nitride" and "oxide"). For example, in a flash memory structure, any one or more of blanket and / or conformal nitride, conformal nitride, and blanket and / or conformal oxide can be implemented. Such layers can be used in connection with the placement, isolation, and function of each of the flash memory floating gate, control gate, and erase gate. Each or all of these layers can also be implemented in other types of IC devices.

[0005] In some processes, nitride and oxide layers are formed using a furnace-based batch process, that is, with a relatively large number (e.g., 125) of wafers in the furnace at a time. Such films can be referred to as "thermal nitride" or "thermal oxide". This method typically involves relatively long heat cycles (e.g., several hours) and relatively high temperatures (e.g., 700 °C and higher). These processes form the layers on both the front and back sides of the semiconductor wafer, and in cases where such layers are subsequently undesirable on the back side of the wafer, additional steps, costs, time, and typically chemicals are required to remove such layers. In other cases, these processes may provide satisfactory film properties, but these heat cycles and temperatures may provide additional drawbacks.

[0006] Accordingly, there may be a need to provide improved IC nitride and oxide layers, and this document provides embodiments that can improve certain of the above concepts, as detailed below. Summary of the Invention

[0007] A method of forming at least one of a nitride or oxide layer for an integrated circuit, the method comprising: (i) positioning a semiconductor wafer in a processing chamber, the semiconductor wafer comprising a wafer front side, and the processing chamber comprising a differential surface adapted to be coupled to a plasma ignition external radio frequency source; (ii) depositing one of a nitride or oxide on at least one exposed portion of the semiconductor wafer or a layer attached relative to the wafer front side by reacting at least two precursor gases for a selected one of the nitride or oxide layer in the chamber when the plasma ignition external radio frequency source is enabled; and (iii) post-treating one of the nitride or oxide by exposure to helium and nitrogen in the presence of the plasma ignition external radio frequency source and in the absence of at least one of the at least two precursor gases.

[0008] Other aspects are also described and claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of an IC manufacturing system.

[0010] Figure 2 is for operating Figure 1 a flowchart of an example of the system.

[0011] Figure 3A illustrates a cross-section of several blanket dielectric layers over a semiconductor substrate.

[0012] Figure 3B illustrates after adding two additional blanket dielectric layers Figure 3A the structure.

[0013] Figure 3C illustrates after an additional processing step including forming a stack and two conformal layers Figure 3B the structure.

[0014] Figure 3D illustrates after an additional processing step including forming sidewall spacers and a floating gate Figure 3C the structure. DETAILED DESCRIPTION

[0015] The various disclosed methods and apparatuses of the present disclosure can be beneficially used in aspects of semiconductor technology, for example, by replacing a furnace-grown dielectric layer that would otherwise be formed on the back side of a wafer with a plasma-deposited dielectric layer having a similar quality to that of a film grown in a similar furnace tube and being limited to the wafer front side. Although such examples are expected to reduce process complexity or improve thermal budget management of the produced wafers, no specific results are required unless explicitly recited in a particular claim.

[0016] Figure 1is a block diagram of an IC manufacturing system 100, which can be used as an example of forming high-quality nitride and / or oxide layers (sometimes referred to as films). The layers can be implemented in various IC structures, such as flash memories, as described subsequently in Figures 3A - 3D The system 100 has some properties known in the art, but is improved as further detailed herein. Therefore, only certain aspects are described. In an example, the system 100 processes a relatively small number of semiconductor wafers simultaneously, such as one or two semiconductor wafers. The processing can include plasma-enhanced chemical vapor deposition (PECVD) of the desired layer.

[0017] The system 100 includes a mechanical handler 102 for moving a semiconductor (e.g., silicon) wafer 104 between the mechanical handler 102 and a processing chamber 106. For reference, Figure 1 the semiconductor wafer 104 is described as semiconductor wafer 104A when supported by the mechanical handler 102 and as semiconductor wafer 104B (or collectively, as semiconductor wafer 104A / 104B) when inside the processing chamber 106. The semiconductor wafer 104A can be positioned relative to the mechanical handler 102 in cooperation with other equipment (e.g., received from a wafer cassette or a front-opening unified (or universal) pod (FOUP)). The semiconductor wafer 104A can also travel to various other locations for processing, such as for additional steps before and / or after processing in the processing chamber 106. Additionally, although Figure 1 the processing chamber 106 is described as the only chamber within the reach or proximity of the mechanical handler 102, other chambers can also be within the same proximity, including other chambers that perform other steps when forming other structures (e.g., nitridation, annealing, polysilicon deposition, etc.).

[0018] The mechanical handler 102 includes an actuator 108 that is coupled and operable to change the position of a shaft 110. The actuator 108 can move the shaft 110 in different directions, including vertically, rotationally, and laterally, as Figure 1Illustrated via the arrows. The shaft 110 is coupled to the platform 112, on which the semiconductor wafer 104A is supported. The system 100 also includes a controller 114 or a plurality of controllers, which may or may not communicate with other controllers, and the controller 114 causes the actuator 108 to move and thus guides the movement of the semiconductor wafer 104A. The controller 114 is a programmable / computing device known in the art and includes various forms of hardware and software for controlling semiconductor wafer processing. For example, such hardware may include a microprocessor (including a digital signal processor) or a microcontroller, a computer-readable medium such as a memory or a memory access for reading / writing data and programming, and a communication (including networking) interface for input / output, such as a user interface through which a user can input or select and execute wafer processing parameters that are sometimes partially referred to as a recipe. The software associated with and stored in the computer-readable medium of the controller 114 provides program instructions to the controller hardware to control the various processing steps described herein.

[0019] The processing chamber 106 includes aspects for receiving and processing the semiconductor wafer 104B. For example, the processing chamber 106 includes a first passage 116 that is close to the mechanical handler 102, and the semiconductor wafers 104A / 104B are passed through the first passage into and out of the interior of the processing chamber 106. Specifically, the mechanical handler 102 conveys the semiconductor wafer 104A through the first passage 116 and positions the semiconductor wafer within a support platform 118 (e.g., an edge ring) that is attached inside the processing chamber 106 (e.g., to a chuck, not shown) and within which the semiconductor wafer 104B is located. Once the semiconductor wafer 104B is so positioned, the first passage 116 is closed, and the semiconductor wafer 104B is processed as further described below. The support platform 118 may be directly heatable or may be coupled to or near a separate heater (not shown) for controlling the temperature inside the processing chamber 106 and the temperature of the surface of the semiconductor wafer 104B. The support platform 118 is also electrically connected to ground. Once processing is complete, the first passage 116 is opened, and the mechanical handler 102 retrieves the semiconductor wafer 104B from the interior of the processing chamber 106, after which the semiconductor wafers 104A / 104B are passed to an additional chamber or possibly a series of corresponding chambers for additional processing steps. The processing chamber 106 also includes a showerhead 120 for receiving one or more externally supplied gases through a second passage 122 and for subsequently distributing the gases into the interior of the chamber. For later reference, the showerhead 120 is positioned at a distance d from the upper surface of the semiconductor wafer 104B HThere. The showerhead 120 is also electrically connected to an external radio frequency (RF) source 124. When the external RF source 124 is enabled, it provides an electrical signal that generates a differential potential between the showerhead 120 and the grounded support platform 118, as part of the plasma generation operation of the system 100. And, although not shown, the interior of the processing chamber 106 may contain other elements, such as windows and possibly water-cooled reflectors, for isolating and directing heat to the semiconductor wafer 104B.

[0020] At Figure 1 the top of, the IC manufacturing system 100 also includes a gas distribution system 126. The gas distribution system 126 includes several different gas sources, and in the illustrated example there are five such sources: (i) a silane (SiH 4 ) source 128; (ii) a helium (He) source 130; (iii) an ammonia (NH 3 ) source 132; (iv) a nitrous oxide (N 2 O) source 134; and (v) a nitrogen (N 2 ) source 136. The flow of each of these gas sources is under the control of the controller 114. Each of the gas sources 128 to 136 is coupled to a supply chamber 138 that is in fluid communication with the second passage 122, and the second passage may include the use of one or more additional valves (not shown) that may also be controlled by the controller 114. The supply chamber 138 may include various individual devices (not shown), such as manifolds, mixing chambers, and mass flow controllers. Thus, when the second passage 122 is opened, the selected gas in the supply chamber 138 is delivered to the interior of the processing chamber 106.

[0021] Finally, the system 100 includes a pump 140, a valve 142 in the fluid communication path between the pump 140 and the interior of the processing chamber 106, and a pressure gauge 144 that is also in fluid communication with the interior of the processing chamber 106 via a respective passage 146. Collectively, these devices maintain an appropriate environment and ensure the quality and consistency of the deposition process. For example, the pump 140 may create a vacuum within the processing chamber 106, remove gas from the processing chamber, maintain pressure, and assist in stabilizing and maintaining pressure before introducing precursor gases and plasma ignition. Relatedly, the pressure gauge 144 permits accurate and safety-related pressure monitoring and feedback to the controller 114 for controlling the operation of the pump 140 and the amount of opening of the valve 142 (e.g., throttle valve position).

[0022] Figure 2 For operating Figure 1Flowchart of an example method 200 of system 100. Method 200 forms an oxide or nitride layer on semiconductor wafer 104A / 104B (either directly on the surface of the front side of the wafer or on exposed material attached to said surface or attached to another layer relative to the front side of the wafer surface). Method 200 begins at step 202, where a Figure 1 wafer 104A / 104B is obtained and positioned within processing chamber 106. At this stage, semiconductor wafer 104A / 104B may have undergone some earlier processing steps. Such processing steps may include, for example, wafer cleaning (e.g., chemical and / or mechanical), isolation, possible formation of device wells and / or channels and / or source / drain regions, and defining the area where the oxide or nitride layer is to be formed.

[0023] By way of another example related to step 202, Figure 3A a cross-section of semiconductor wafer 104A / 104B related to the formation of split-gate flash memory cell 300 is illustrated. At the point in the manufacturing sequence represented in Figure 3A , memory cell 300 includes several layers, which from bottom to top include: (i) a substrate 302 (e.g., silicon); (ii) a floating gate (FG) insulator layer 304 (e.g., silicon dioxide (SiO 2 ), or silicon nitride (Si 3 N 4 ), which, for example, has a to (2 nm to 15 nm) thickness range and is formed along and facing the front side of substrate 302; (iii) an FG polysilicon (polycrystalline) layer 306, which is formed along FG insulator layer 304; (iv) a control gate (CG) insulator layer 308 (e.g., SiO 2 ), which is formed, for example, by in-situ steam generation (ISSG) and, for example, has a thickness range from to (1 nm to 2 nm) and is along FG polysilicon layer 306; and (v) a CG polysilicon layer 310, which is formed along CG insulator layer 308. Thus, at the process stage shown in Figure 3A , the illustrated structure is ready for the next layer to be formed on the topmost exposed layer, i.e., on top of CG polysilicon layer 310.

[0024] Returning to Figure 2Method 200 and its method, next perform a sequence of even-numbered steps 204 to 214. The steps are performed, for example, under the operation of the controller 114 and form the next desired layer, where such a layer is a blanket oxide layer or a blanket or conformal nitride layer, but such steps can also be used equally for other layers. Generally, in those steps 204 to 214, five steps occur for the formation of an oxide or nitride layer, and step 212 is a conditional step that can repeat certain steps in the case where the nitride is a conformal nitride, as will be further detailed later. In addition, Figure 2 Method 200 for forming a blanket oxide layer or forming a blanket or conformal nitride layer can be used to form layers other than those shown by way of example in the context of the combined split-gate flash memory cell 300.

[0025] Before any plasma reaction is induced in the processing chamber 106, step 204 stabilizes the conditions inside the chamber. For example, when the RF source 124 is deactivated, that is, before the external RF source 124 is activated and the appropriate precursor gas is introduced into contact with the corresponding RF energy, step 204 can stabilize all gas flows, pressures, temperatures, etc. A non-reactive (inert or near-inert) gas can be introduced inside the processing chamber 106, for example, using He or N 2 One or more of which assist in the upcoming deposition of the nitride or oxide layer. A reactive precursor gas is also introduced during the stabilization of step 204, for example, containing SiH for forming a nitride 4 and NH 3 or, for example, containing SiH for forming an oxide 4 and N 2 O. The temperature of the stabilization step 204 is stabilized, and for all subsequent layer formation steps up to step 210, a nitride can be formed in the range of 525 °C to 575 °C, and an oxide can be formed in the range of 280 °C to 560 °C. It is worth noting that such temperatures (or the selection within that temperature range) can provide various benefits or criticalities and are significantly lower compared to the temperatures required in a furnace tube process for forming such nitrides or oxides. In addition, during the stabilization step 204 (and subsequent steps 206 and 208), starting from the upper surface of the semiconductor wafer 104B, Figure 1 distance d HIt can be set in the range of 350 to 700 mils (thousandths of an inch) (9 - 18 mm) for nitride formation, or in the range of 400 to 900 mils (10 - 23 mm) for oxide formation. Additionally, for each of the blanket nitride layer, conformal nitride layer, or blanket oxide layer, example ranges of the gas flow rate (in standard cubic centimeters per minute (sccm)) and example ranges of the pressure inside the processing chamber 106 (in torr and pascals in parentheses) for step 204 during the stabilization step 204 are shown in Tables 1 to 3 below.

[0026]

[0027] Table 1

[0028]

[0029] Table 2

[0030]

[0031] Table 3

[0032] After step 204, step 206 is a pre - deposition treatment, which further processes the upper exposed surface (e.g., the CG polycrystalline layer 310 in 4 where the layer to be deposited will come) by enabling the external RF source 124 while interrupting the flow of the precursor SiH Figure 3A so that no film deposition occurs. Step 206 removes moisture and volatile materials from the upper exposed surface where the layer to be deposited will come. For example, if the top - most exposed layer is an oxide film from a previous treatment, non - reactive He and / or N 2 is introduced to reduce / eliminate moisture, remove volatile materials from the oxide, and enrich the surface with bonded nitrogen so that the subsequently deposited nitride film can have a desirable adhesion to the oxide film and a more gradual interface from oxide to nitride. Non - reactive He and / or N 2 can provide similar surface benefits when depositing an oxide along a polysilicon surface. For each of the blanket nitride layer, conformal nitride layer, or blanket oxide layer, example ranges of the gas flow rate (in sccm), example ranges of the pressure inside the processing chamber 106 (in torr and pascals in parentheses), and the RF power of the external RF source 124 (in watts) for step 206 are shown in Tables 4A to 6A below. Additionally, the duration of the pre - deposition treatment step 206 can be in the range of 5 to 25 seconds for the blanket nitride layer, 5 to 20 seconds for the conformal nitride layer, and 5 to 35 seconds for the blanket oxide layer.

[0033]

[0034] Table 4A

[0035]

[0036] Table 5A

[0037]

[0038] Table 6A

[0039] The ranges of the various pre - deposition parameters above can be tightened to achieve certain desired characteristics, for example. Additionally, non - reactive He can have specific benefits and / or be critical for the formation of nitrides or oxides. Thus, Tables 4B to 6B below provide additional limitations on the ranges:

[0040]

[0041] Table 4B

[0042]

[0043] Table 5B

[0044]

[0045] Table 6B

[0046] After step 206, step 208 is a deposition step of a desired material (nitride or oxide) on the uppermost exposed surface in the processing chamber 106, which is achieved by continuing to enable the external RF source 124 while also supplying an appropriate precursor gas to the processing chamber 106. In some instances, the RF power of the external RF source 124 is higher in the deposition step 208 than in the pre - deposition processing step 206. Additionally, for example, for nitrides, SiH 4 is a silicon source and NH 3 is a nitrogen source, and for oxides, SiH 4 is a silicon source and N 2 O is an oxygen source.

[0047] For depositing nitrides or oxides, there is one or more additional non - reactive diluent gases, such as N 2 and / or He, and in fact for both nitrides and oxides, He is present in a relatively large flow. Helium does not participate in chemical reactions, and N 2(If present) There is no reaction at all, but it is believed that these gases have an in-situ sputtering effect on the deposited film, thereby removing bound hydrogen from the growing film, which can subsequently be replaced by nitrogen in the case of a nitride film or by oxygen in the case of an oxide film. The resulting film is expected to have properties more similar to a thermal oxide or nitride film, e.g., greater breakdown strength and density, and lower leakage. Such films are also expected to produce less hydrogen (protons), which might otherwise diffuse and potentially reduce the reliability of the IC. It is noted that the flow rate of the dilution gas or gases can be significantly greater than the flow rate in typical baseline oxide and nitride PECVD processes. In some instances, the dilution gas flow rate can be equal to or greater than the flow rate of one or more reactant gases, and can be two times or more (even ten times) higher than the reactant gas flow rate, and in fact for a specific ratio of He / SiH 4 the reactant gas flow rate is two times or more (even ten times) higher, and in fact for a specific ratio of He / SiH 4 the ratio can range from 65 to 1,000 (for blanket nitride) or greater (for conformal nitride or oxide). It is believed that such high flow rates (or flow rate ratios) cause the aforementioned dehydrogenation of the resulting film and also reduce the film growth rate, thereby further assisting in dehydrogenation. For each of a blanket nitride layer, a conformal nitride layer, or a blanket oxide layer, example ranges of gas flow (sccm), pressure inside the processing chamber 106 (torr and pascal in parentheses), and RF power (W) of the external RF source 124 for step 208 are shown in Tables 7A to 9A below. It is noted that, for example, a relatively high RF power can be beneficial or critical with respect to any one or more of nitride deposition rate, uniformity, and film quality. A relatively lower RF power can be achieved compared to oxide formation, where the deposition rate is slower. Specifically, the duration of deposition step 208 can range from 125 to 190 seconds for a blanket nitride layer, from 125 to 190 seconds for a conformal nitride layer, and from 30 to 70 seconds for a blanket oxide layer, while for a blanket nitride, the deposition rate is about for a conformal nitride, the deposition rate is less than and for a blanket oxide, the deposition rate is less than

[0048]

[0049] Table 7A

[0050]

[0051] Table 8A

[0052]

[0053] Table 9A

[0054] The ranges of the above various deposition parameters can be tightened, for example, to achieve certain desired properties. During the deposition step, RF power, pressure, reactant flow rates and their ratios (e.g., for nitride, SiH 4 or NH 3 One or both of; for oxides, SiH 4 or N 2 O), He flow (including for nitrides or oxides, which are combined with SiH 4 ratio, and for nitrides, its ratio to NH 3 Any one or more of the ratio of ) may provide benefits or criticality to nitride or oxide formation, while for oxides, temperature may also additionally demonstrate such attributes. Therefore, the following Tables 7B to 9B provide additional limits for the ranges:

[0055]

[0056] Table 7B

[0057]

[0058] Table 8B

[0059]

[0060] Table 9B

[0061] After step 208, step 210 is a post-deposition treatment of the deposited and exposed material (nitride or oxide) in the process chamber 106, during which the external RF source 124 remains enabled, but all precursor gases for the nitride (SiH 4 and NH 3 ) and at least one precursor gas for the oxide (SiH 4 ) no longer flows into the chamber. In addition, one or more non-reactive gases (e.g., He, N, etc.) are again provided at a relatively high flow rate compared to the reactant flow rate in the previous deposition step 208. 2 ), and the RF power of the external RF source 124 may be reduced compared to the deposition step 208, but provided at a level greater than 0 watts. In addition, for the example of an oxide layer, the N 2O also continues to flow. During this step, nitrogen acts as a sputtering gas rather than a reactant. Thus, step 210 densifies the deposited film and produces a more stoichiometric composition. For example, for a nitride, step 210 can reduce Si-H bonds by removing hydrogen from Si and reacting the ionized nitrogen with the resulting dangling Si bonds, thereby improving the film quality and purity. As previously described, removing hydrogen also makes the film more electrically stable. Similar benefits can be achieved when forming an oxide film by removing hydrogen while making oxygen available to reactive silicon atoms. For each of the blanket nitride layer, conformal nitride layer, or blanket oxide layer, example ranges for the gas flow (sccm), the pressure inside the processing chamber 106 (torr and pascals in parentheses), and the RF power (W) of the external RF source 124 are shown in Tables 10A through 12A below. Additionally, for each of the blanket nitride layer, conformal nitride layer, and blanket oxide layer, the duration of the post-deposition processing step 210 can range from 10 to 60 seconds.

[0062]

[0063] Table 10A

[0064]

[0065] Table 11A

[0066]

[0067] Table 12A

[0068] For the post-deposition step 210, any one or more of temperature, power, pressure, and dilution gas flow rate can provide benefits and / or be critical. Thus, Tables 10B through 12B below provide additional limitations on the ranges:

[0069]

[0070] Table 10B

[0071]

[0072] Table 11B

[0073]

[0074] Table 12B

[0075] As previously introduced, step 212 is a conditional step which may repeat certain steps in some applications such as when the nitride is a conformal spacer nitride. Thus, although method 200 is applicable to three different types of layers (blanket or conformal nitride; conformal oxide), for the conformal nitride embodiment, step 212 will return the method flow to step 208 and its subsequent step 210 for a desired number of iterations. The number of iterations may depend on, for example, the overall desired thickness of the final conformal nitride, that is, the nitride may be formed of multiple nitride sub-layers, each nitride sub-layer having a thickness of a few nanometers. This scenario is thought to provide benefits through the incremental densification of the intermediate nitride layer and the removal of bound hydrogen. In such cases, step 206 provides a single pre-deposition treatment for all nitride sub-layers, while deposition step 208 and post-deposition treatment step 210 are performed for each of the nitride sub-layers. When the last conformal nitride sub-layer is completed (i.e., the final desired iteration), method 200 proceeds to evacuation chamber step 214.

[0076] Step 214 evacuates the interior of process chamber 106. As part of the evacuation, a desired amount of N 2 may flow through the interior of process chamber 106 to remove any residual gases and particles from the chamber. Thus, step 214 completes the process for the deposition of the layer(s) reasonably. Thereafter, one or more additional other layers may be deposited, including, for example, another one of the three types of layers described herein.

[0077] Figure 3B Description Figure 3A A split-gate flash memory cell 300 after adding two additional layers, namely, a blanket oxide layer 312 on top of the CG polycrystalline layer 310, and a blanket nitride layer 314 on top of the blanket oxide layer 312. Each of layer 312 and layer 314 can be formed by Figure 2 method 200 and has parameter values of the corresponding tables described above for the blanket oxide and blanket nitride layers respectively. The thickness of each of layer 312 and 314 can be selected based on various considerations, which include the overall device (and gate) size and functionality. For example, the blanket oxide layer 312 can be (3 - 6 nm) thick, while the blanket nitride layer 314 can be to (150 - 200 nm) thick (not shown to scale in the figure).

[0078] Figure 3C Description Figure 3BSplit-gate flash memory cell 300 after additional processing steps. An additional uniform layer of oxide 316 is formed over the layer, for example as a protection against subsequent etching and cleaning. The structure is then patterned and etched down to the FG polysilicon layer 306 to form a first gate stack 318 and a second gate stack 320. Two conformal layers are then formed over the entire structure: (i) a conformal oxide layer 322 that provides the CG spacer oxide; and (ii) a conformal nitride layer 324 that provides the CG spacer nitride. The conformal oxide layer 322 can be formed using known processes or using Figure 2 the steps of Figure 2 Method 200 forms the conformal nitride layer 324, and can have a high compressive stress (-700 MPa) and a conformality of 85% or greater. Thus, Figure 2 Method 200 thus facilitates the formation of nitride or oxide or both in ICs, including those containing flash memory cells.

[0079] Finally, Figure 3D illustrates the split-gate flash memory cell 300 after additional processing steps, in which the conformal nitride layer 324 and the conformal oxide layer 322 are partially removed, thereby forming control gate sidewall spacers, and the FG polysilicon layer 306 and the FG insulator layer 304 are partially removed, thereby forming the floating gates and FG insulators of each of the gate stacks 318, 320. Source lines 326 have been formed, for example, by ion implantation, and a pre-metal dielectric layer 328 has been formed over the substrate 302. Metal vias 330 (e.g., tungsten) connect the drain lines 332 to the bit lines 334. The gate stacks 318, 320 can be part of an array of similar gate stacks to provide a memory storage device of any desired size.

[0080] The nitride and / or oxide layers formed according to Method 200 can provide favorable wet etch rates. In other words, once the layers are formed, subsequent wet etching processes provide one or more of precision, selectivity, and uniformity. Table 13 below provides examples of wet etch rates achievable in the case of etching by dilute hydrofluoric acid (DHF) with a wafer-to-HF ratio equal to approximately 100:1 (0.5 - 0.6% HF) for three of the Method 200 layers described above. In some process sequences or process flows, a silicon oxide film can be formed on or over the silicon nitride film, and a portion of the silicon oxide film can be removed during the formation of certain device features. A relatively low etch rate of the silicon nitride layer relative to the silicon oxide layer is expected to provide selective removal of the silicon oxide film in such instances.

[0081]

[0082] Table 13

[0083] As described above, those skilled in the art will appreciate, for example, examples for IC semiconductor manufacturing regarding forming both IC blanket oxides and blanket and conformal nitride layers and, for example, using a PECVD process. The combination of one or more parameters described herein together with the PECVD process can generally provide one or more of various advantageous oxide or nitride layer properties, as described above. Additionally, although only certain oxide or nitride layers in the memory cell 300 have been shown as being formed using the PECVD process, the scope of the present invention can be applicable to other layers in such cells, or to other layers in other semiconductor devices. Further, although blanket oxides have been described, certain teachings herein can also be applicable to conformal oxides. Additionally, using PECVD further provides benefits compared to what would be incurred when using a baseline furnace process in an effort to form comparable structures. For example, compared to a furnace process at higher temperatures (e.g., forming nitride at about 740 °C to 780 °C and forming oxide at about 650 °C), PECVD allows for the use of relatively lower temperatures, such as forming nitride at about 350 °C and forming oxide at about 550 °C. As another example, when performed as described above, the PECVD throughput time can be faster than that of the furnace process. As yet another example, the furnace process presents its environment and chemical reactions to both sides of the semiconductor wafer, such that the formation of certain oxide and / or nitride layers will occur on both sides of the wafer, that is, where the first layer faces the front side of the wafer (either directly, or attached to one or more other layers on the front side), and where the second layer faces the back side of the wafer (either directly, or attached to one or more other layers on the back side). Thus, typically the back side of the wafer subsequently requires various processes, time, cost, and chemicals involved in removing the back side layer. In contrast, the improved examples described herein permit selective layer deposition only with respect to the front side of the semiconductor wafer, thereby eliminating all resource generation and subsequent removal of back side oxide and nitride layers required by furnace production. As yet another example, the furnace process used to form nitride to date typically produces layers that contain some non-negligible amount of oxygen (e.g., greater than one atomic percentage) that may occur due to atmospheric contamination. In contrast, the PECVD method 200 for depositing blanket or conformal nitride will result in the layer being substantially oxygen-free (e.g., 1 ppm (0.0001%) or less). As a final example, within the scope of the appended claims, modifications to the described embodiments are possible, and other embodiments are possible.

Claims

1. A method for forming at least one of a nitride or oxide layer for an integrated circuit, the method comprising: Positioning a semiconductor wafer in a processing chamber, the semiconductor wafer comprising a wafer front side and the processing chamber comprising a differential surface adapted to be coupled to an external radio frequency source for plasma ignition; depositing one of a nitride or an oxide on the wafer front side by reacting at least two precursor gases for a selected one of the nitride or oxide layers in the chamber while the plasma ignition external RF source is enabled; as well as The one of the nitride or the oxide is post-processed by exposure to helium and nitrogen with the plasma ignition external RF source enabled and in the absence of at least one of the at least two precursor gases.

2. The method of claim 1 , wherein the selected one of the nitride or oxide layer is a blanket nitride and the at least two precursor gases include SiH4 flowing into the processing chamber at a rate of 100 sccm to 200 sccm and NH3 flowing into the processing chamber at a rate of 600 sccm to 1000 sccm during the deposition.

3. The method of claim 2, and further comprising flowing helium into the chamber at a rate of 7000 sccm to 15000 sccm during the depositing.

4. The method of claim 1 , wherein the selected one of the nitride or oxide layer is a conformal nitride and the at least two precursor gases include SiH 4 flowing into the processing chamber at a rate of 5 sccm to 40 sccm and NH 3 flowing into the processing chamber at a rate of 100 sccm to 500 sccm during the deposition.

5. The method of claim 4, and further comprising flowing helium into the chamber at a rate of 7000 sccm to 18000 sccm during the depositing.

6. The method of claim 1, wherein the selected one of the nitride or oxide layer is a nitride and during the depositing, the plasma ignition external RF source is enabled at a power of 120 W to 350 W.

7. The method of claim 1 , wherein the selected one of the nitride or oxide layer is an oxide, and the at least two precursor gases include SiH 4 flowing into the processing chamber at a rate of 5 sccm to 50 sccm and N 2 O flowing into the processing chamber at a rate of 1000 sccm to 8000 sccm during the deposition.

8. The method of claim 1, wherein the selected one of the nitride or oxide layer is an oxide and during the depositing, the plasma ignition external RF source is enabled at a power of 50 W to 550 W.

9. The method of claim 1, wherein the selected one of the nitride or oxide layer is a blanket nitride, and during the deposition, a pressure in the chamber is 1.5 Torr to 5 Torr.

10. The method of claim 1, wherein the selected one of the nitride or oxide layer is a conformal nitride and during the depositing, a pressure in the chamber is 5 to 13 Torr.

11. The method of claim 1 , wherein the selected one of the nitride or oxide layer is an oxide, and during the depositing, a pressure in the chamber is 2 to 12 Torr.

12. The method of claim 1, wherein the selected one of the nitride or oxide layer is a nitride and a temperature in the chamber during the post-processing is in a range of 525°C to 575°C.

13. The method of claim 1, wherein the selected one of the nitride or oxide layer is an oxide, and a temperature in the chamber during the post-processing is in a range of 280°C to 560°C.

14. The method of claim 1, wherein during the post-processing, the plasma ignition external RF source is enabled at a power of 150 W to 550 W.

15. The method of claim 1, wherein during the post-processing, helium is flowed into the chamber at a rate of 6000 sccm to 15000 sccm.

16. The method of claim 1, wherein the selected one of the nitride or oxide layer is a blanket nitride, and during the post-treatment, N2 is flowed into the chamber at a rate of 10,000 sccm to 18,000 sccm.

17. The method of claim 1, wherein the selected one of the nitride or oxide layer is a conformal nitride, and during the post-processing, N2 is flowed into the chamber at a rate of 6000 sccm to 15000 sccm.

18. The method of claim 1, wherein the selected one of the nitride or oxide layer is an oxide, and during the post-treatment, N2O is flowed into the chamber at a rate of 1000 sccm to 8000 sccm, and N2 is flowed into the chamber at a rate of 500 sccm to 1500 sccm.

19. The method of claim 1, wherein during the post-processing, a pressure in the chamber is 2.5 Torr to 8 Torr.

20. An integrated circuit comprising: Semiconductor wafers; as well as The silicon nitride layer, which is overlying the semiconductor wafer, is substantially free of oxygen.

21. The integrated circuit of claim 20, wherein the silicon nitride layer has a / min or less wet etching rate.

22. The integrated circuit of claim 20, wherein the silicon nitride layer contains 1 ppm or less of oxygen.

Images