Monocrystalline silicon wafer and processing method of monocrystalline silicon wafer
By forming asymmetric chamfers on the edges of the single crystal silicon wafer, the problems of edge collapse and dark grain fragments under high temperature processes are solved, and the preparation yield is improved and production costs are reduced.
Patent Information
- Application Number
- CN202510229599.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-05-30
AI Technical Summary
During the manufacturing process of semiconductor devices, single crystal silicon wafers are prone to collapse and dark grain fragments under high temperature processes, resulting in a decrease in production yield and an increase in production costs.
By forming asymmetric chamfers on the edges of the single crystal silicon wafer, the second side of the chamfer is more fitted with the base of the reaction device and the stress-bearing surface is more uniform, thereby reducing stress during the rapid heating process and reducing the generation of edge collapse and dark grain debris.
It effectively improves the production yield of semiconductor devices, reduces production costs, and maintains the original requirements for semiconductor device processing.
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Figure CN120060974A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a single crystal silicon wafer and a method for processing a single crystal silicon wafer. Background Art
[0002] A substrate single crystal silicon wafer is an intermediate product in the manufacturing process of semiconductor devices and is a polished wafer among the substrate wafers used to fabricate chips. When epitaxial growth is carried out on a single crystal silicon wafer using epitaxial technology, a reaction device of the Centura AMAT type is generally used. When annealing treatment is carried out on a single crystal silicon wafer using rapid annealing technology, a reaction device of the Centura AMAT type is also generally used. Since the process of processing using this reaction device belongs to high-temperature processes, during the processing, the single crystal silicon wafer is prone to chipping and dark line fragments. For example, according to product requirements, such as thick epitaxy (5 - 7 epitaxial layers) and high-temperature TRO (1150 degrees), repeated high-temperature processes are carried out on the substrate, and the main process temperature increases, resulting in an increase in the incidence rate of chipping and dark line fragments. Therefore, there is an urgent need for a new solution to reduce chipping and dark line fragments caused by stress. In the existing substrate single crystal silicon wafers, relatively large chamfers are provided on both the upper and lower surfaces at the edge positions, and the risk of generating chipping and dark line fragments is very high.
[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention
[0004] Aiming at the problems in the prior art, the purpose of this application is to provide a single crystal silicon wafer and a method for processing a single crystal silicon wafer, which form an asymmetric chamfer at the edge of the single crystal silicon wafer. The second side of the chamfered part can fit better with the base of the reaction device, the stress-bearing surface is more uniform, and the stress can be effectively reduced during the rapid heating process, reducing the generation of chipping and dark line fragments.
[0005] An embodiment of this application provides a single crystal silicon wafer, which includes a main body part and a chamfered part located outside the main body part. A first chamfered surface is formed on the first side of the chamfered part, and a second chamfered surface is formed on the second side of the chamfered part;
[0006] The inner edge and the outer edge of the first chamfered surface have a first distance in the width direction, the inner edge and the outer edge of the second chamfered surface have a second distance in the width direction, and the second distance is less than the first distance;
[0007] The inner edge and the outer edge of the first chamfered surface have a third distance in the thickness direction, the inner edge and the outer edge of the second chamfered surface have a fourth distance in the thickness direction, and the fourth distance is less than the third distance.
[0008] In some embodiments, the second distance is 120 μm ± 40 μm.
[0009] In some embodiments, the outer edges of the first chamfered surface and the second chamfered surface have a fifth distance in the thickness direction, and the ratio of the fifth distance to the thickness of the main body is 0.34 ± 0.04.
[0010] In some embodiments, the first distance is 420 μm ± 100 μm.
[0011] In some embodiments, the first chamfered surface and the second chamfered surface are respectively flat inclined surfaces.
[0012] In some embodiments, the first chamfered surface and the second chamfered surface are respectively at least partially arc surfaces.
[0013] In some embodiments, a first arc surface is formed at the outer edge of the first chamfered surface, and the radius of the first arc surface is 200 μm ± 50 μm.
[0014] In some embodiments, a second arc surface is formed at the outer edge of the second chamfered surface, and the radius of the second arc surface is 200 μm ± 50 μm.
[0015] By using the single-crystal silicon wafer of the present application, the following beneficial effects can be achieved:
[0016] In the present application, an asymmetric chamfer is formed at the edge of the single-crystal silicon wafer. The first side of the chamfered portion can remain unchanged, so there is no need to change the original requirements for semiconductor device processing. The second side of the chamfered portion can fit better with the base of the reaction equipment, and the stress-bearing surface is more uniform. During the rapid heating process, the stress can be effectively reduced, the generation of chipping, dark lines and fragments can be reduced, the preparation yield of semiconductor devices can be effectively improved, and the production cost of semiconductor devices can be reduced.
[0017] The embodiment of the present application also provides a method for processing a single-crystal silicon wafer, including the following steps:
[0018] Grind the two side surfaces of the periphery of the main body of the single-crystal silicon wafer respectively to form a chamfered portion; wherein, a first chamfered surface is formed on the first side of the chamfered portion, and a second chamfered surface is formed on the second side of the chamfered portion; the inner edge and the outer edge of the first chamfered surface have a first distance in the width direction, the inner edge and the outer edge of the second chamfered surface have a second distance in the width direction, and the second distance is less than the first distance; the inner edge and the outer edge of the first chamfered surface have a third distance in the thickness direction, and the inner edge and the outer edge of the second chamfered surface have a fourth distance in the thickness direction, and the fourth distance is less than the third distance.
[0019] In some embodiments, after the two side surfaces of the periphery of the main body of the single crystal silicon wafer are respectively ground to form chamfered portions, the following steps are further included:
[0020] Place the single crystal silicon wafer on the base of the reaction device, with the second side of the chamfered portion facing the base, and perform epitaxial growth treatment or annealing treatment on the single crystal silicon wafer based on the reaction device.
[0021] By adopting the processing method of the single crystal silicon wafer, a single crystal silicon wafer with the above chamfered portion structure can be obtained, thereby obtaining the beneficial effects of the above single crystal silicon wafer.
[0022] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. Description of the Drawings
[0023] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.
[0024] Figure 1 is a schematic partial structure diagram of a single crystal silicon wafer according to an embodiment of the present application;
[0025] Figure 2 is a schematic diagram of the base of the reaction device according to an embodiment of the present application;
[0026] Figure 3 is a schematic diagram of the cooperation between the base of the reaction device and the single crystal silicon wafer according to an embodiment of the present application;
[0027] Figure 4 is a schematic partial structure diagram of the cooperation between the single crystal silicon wafer and the reaction device according to another embodiment of the present application.
[0028] Reference Signs:
[0029] 1. Single crystal silicon wafer, 11. Main body portion, 12. Chamfered portion, 121. First chamfered surface, 122. Second chamfered surface;
[0030] 9. Base of the reaction device, 91. Silicon wafer groove, 92. Side edge. Detailed Embodiments
[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their repetitive description will be omitted. The terms "or" and "or" in the specification may both mean "and" or "or". Spatial relationship terms such as "on..." can be used herein to describe the relationship of one element or feature shown in the figure with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the figure is flipped, the element or feature described as "on..." will be oriented "under..." other elements or features. Therefore, the exemplary term "on..." can include both the upper and lower orientations. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptive terms used herein are accordingly interpreted.
[0032] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from being present or added. At the same time, as used herein, the term "and / or" includes any and all combinations of the related listed items. Although terms such as "first" or "second" are used in this specification to denote certain features, they are only for representational purposes and do not limit the quantity and importance of the specific features.
[0033] The purpose of the silicon wafer chamfering process is to eliminate the edges, burrs, chipping, cracks or other defects and various edge surface contaminations generated on the edge surface of the silicon wafer due to cutting, thereby reducing the surface roughness of the silicon wafer, increasing the mechanical strength of the edge surface of the silicon wafer, and reducing the surface contamination of particles. As described above, relatively large chamfers are provided on both the upper and lower surfaces of the edge position of the substrate single-crystalline silicon wafer in the prior art. Under high-temperature process stress, the risk of chipping and dark stripe fragments is very high, which in turn reduces the yield rate of semiconductor device products and increases the production cost of semiconductor devices.
[0034] To solve the technical problems of the prior art, the embodiment of the present application provides a single-crystalline silicon wafer 1, which improves the chamfer at the edge position of the single-crystalline silicon wafer 1, reduces the chamfer on the second side, so that the second side of the edge of the single-crystalline silicon wafer 1 can be closer to the base 9 of the reaction equipment, reducing the risk of chipping and dark stripe fragments. Figure 1It is a schematic diagram of a partial structure of a single-crystal silicon wafer 1 according to an embodiment of the present application. Figure 2 It is a schematic diagram of a pedestal 9 of a reaction device according to an embodiment of the present application. Figure 3 It is a schematic diagram of the cooperation between the pedestal 9 of the reaction device and the single-crystal silicon wafer 1 according to an embodiment of the present application. In Figure 1 this perspective, the left-right direction is defined as the width direction, and the up-down direction is defined as the thickness direction.
[0035] As Figure 1 shown, the single-crystal silicon wafer 1 includes a main body portion 11 and a chamfered portion 12 located on the periphery of the main body portion 11. A first chamfered surface 121 is formed on the first side of the chamfered portion 12, and a second chamfered surface 122 is formed on the second side of the chamfered portion 12. In Figure 1 this perspective, the first side of the chamfered portion 12 is the upper side of the chamfered portion 12, and the second side of the chamfered portion 12 is the lower side of the chamfered portion 12. As Figure 2 shown, the pedestal 9 of the reaction device includes a silicon wafer groove 91 and a side edge 92 outside the silicon wafer groove 91. As Figure 3 shown, when processing the single-crystal silicon wafer 1 using the reaction device, the single-crystal silicon wafer 1 is placed in the silicon wafer groove 91, and the second chamfered surface 122 of the chamfered portion 12 of the single-crystal silicon wafer 1 faces the pedestal 9.
[0036] A single-crystal silicon wafer refers to a single crystal of silicon, which is a crystal with a basically complete lattice structure. It has different properties in different directions and is a good semiconductor material. After the silicon ingot is processed into a single-crystal silicon wafer, the edge of the wafer is a sharp edge with corners, burrs, chipped edges, and even there are tiny cracks and other defects, and the surface of the edge is also relatively rough. And this sharp edge will rub or impact with the carrier cassette and other mechanical components during subsequent processing and use, causing stress concentration at the edge of the silicon wafer, resulting in micro-cracks, chipped edges, and breakage of the silicon wafer, causing the silicon wafer to be defective and discarded. At the same time, the broken silicon wafers and silicon slag generated due to the breakage of the silicon wafer will indirectly or directly affect other silicon wafers and processing machines. For processing procedures with high requirements for the cleanliness of the silicon wafer, it will cause greater losses. Therefore, in order to improve the edge utilization rate, enhance the mechanical strength of the edge of the silicon wafer, facilitate chip cutting, and reduce edge particle contamination, it is necessary to perform edge chamfering processing on the silicon wafer. In addition, during the epitaxial growth process, the growth rate in the acute angle region of the silicon wafer is higher than that in the planar region. Using an un-chamfered silicon wafer is likely to produce protrusions in the edge region. Therefore, chamfering the silicon wafer can improve the flatness of the epitaxial layer and the photoresist layer. Therefore, the present application can effectively improve the quality of the single-crystal silicon wafer by forming a chamfered portion 12 at the edge of the single-crystal silicon wafer 1.
[0037] As Figure 1As shown, the inner edge and the outer edge of the first chamfered surface 121 have a first distance d1 in the width direction, the inner edge and the outer edge of the second chamfered surface 122 have a second distance d2 in the width direction, and the second distance d2 is less than the first distance d1. The inner edge and the outer edge of the first chamfered surface 121 have a third distance d3 in the thickness direction, the inner edge and the outer edge of the second chamfered surface 122 have a fourth distance d4 in the thickness direction, and the fourth distance d4 is less than the third distance d3. Therefore, the chamfered portion 12 of the single-crystal silicon wafer 1 is an asymmetric chamfered structure, and the chamfered portion on the second side is smaller than the chamfered portion on the first side.
[0038] Compared with the prior art, the chamfered portion on the second side is reduced in the present application. When the single-crystal silicon wafer 1 is placed in the silicon wafer groove 91, the second side of the chamfered portion 12 of the single-crystal silicon wafer 1 is closer to the surface of the base 9. The chamfered portion on the first side can be the same as the existing chamfered portion, that is, the first distance and the third distance corresponding to the first chamfered surface 121 are the same as those in the prior art, and there is no need to change the original requirements for the processing of existing semiconductor devices. By reducing the chamfered portion on the second side in the present application, when the single-crystal silicon wafer 1 is in the reaction equipment, the stress-bearing surface is more uniform, and the stress can be effectively reduced during the rapid heating process. Even under high-temperature process stress, the generation of chipping, dark lines, and fragments can be effectively reduced, effectively improving the preparation yield of semiconductor devices and reducing the production cost of semiconductor devices.
[0039] In this embodiment, the thickness t1 of the single-crystal silicon wafer 1 is, for example, 725 μm. Here, the thickness of the single-crystal silicon wafer 1 is only an example. In different application scenarios, the thickness of the single-crystal silicon wafer 1 is selected and set as needed, and all belong to the protection scope of the present application. Optionally, the first distance d1 is 420 μm ± 100 μm. The second distance d2 is 120 μm ± 40 μm. Here, the numerical values of the first distance d1 and the second distance d2 are only examples. In different application scenarios, with different thicknesses and diameters of the single-crystal silicon wafer 1, the corresponding first distance d1 and second distance d2 may also be different, and the specific distance values can be selected and set as needed, and all belong to the protection scope of the present application.
[0040] In this embodiment, the outer edges of the first chamfered surface 121 and the second chamfered surface 122 have a fifth distance d5 in the thickness direction, and the ratio of the fifth distance d5 to the thickness t1 of the main body portion 11 is 0.34 ± 0.04. Taking the thickness t1 of the main body portion 11 as 725 μm as an example, the fifth distance d5 is, for example, 250 μm. Here, the ratio range of the fifth distance d5 to the thickness t1 of the main body portion 11 is only an example, and in different application scenarios, it can be selected and set as needed. The specific value of the fifth distance d5 also changes due to the change of the thickness t1 of the main body portion 11 and the change of the ratio range, and all belong to the protection scope of the present application. This fifth distance d5 is increased compared with the corresponding parameter at the same position of the single-crystal silicon wafer 1 in the prior art. When the third distance d3 is the same as the corresponding parameter at the same position of the single-crystal silicon wafer 1 in the prior art, the fourth distance d4 is decreased compared with the corresponding parameter at the same position of the single-crystal silicon wafer 1 in the prior art.
[0041] As Figure 1 shown, the first chamfered surface 121 and the second chamfered surface 122 are at least partially arc surfaces respectively. Specifically, a first arc surface is formed at the outer edge of the first chamfered surface 121, and the radius R of the first arc surface is 200 μm ± 50 μm. A second arc surface is formed at the outer edge of the second chamfered surface 122, and the radius R of the second arc surface is 200 μm ± 50 μm. Here, the sizes of the first arc surface and the second arc surface are only examples and do not limit the protection scope of the present application. The specific values of their radii can be set as needed and all belong to the protection scope of the present application.
[0042] Figure 4 is a partial structural schematic diagram of the cooperation between the single-crystal silicon wafer 1 of another embodiment of the present application and the reaction equipment. As Figure 4 shown, the single-crystal silicon wafer 1 includes a main body portion 11 and a chamfered portion 12 located at the periphery of the main body portion 11. A first chamfered surface 121 is formed on the first side of the chamfered portion 12, and a second chamfered surface 122 is formed on the second side of the chamfered portion 12. The inner edge and the outer edge of the first chamfered surface 121 have a first distance in the width direction, and the inner edge and the outer edge of the second chamfered surface 122 have a second distance in the width direction, and the second distance is less than the first distance. The inner edge and the outer edge of the first chamfered surface 121 have a third distance in the thickness direction, and the inner edge and the outer edge of the second chamfered surface 122 have a fourth distance in the thickness direction, and the fourth distance is less than the third distance. Therefore, the chamfered portion 12 of the single-crystal silicon wafer 1 is an asymmetric chamfer structure, and the chamfer portion on the second side is smaller than the chamfer portion on the first side.
[0043] In this embodiment, the first chamfered surface 121 and the second chamfered surface 122 are respectively flat inclined surfaces. Optionally, the first distance is 420 μm ± 100 μm. The second distance is 120 μm ± 40 μm. The outer edges of the first chamfered surface 121 and the second chamfered surface 122 have a fifth distance in the thickness direction, and the ratio of the fifth distance to the thickness of the main body portion 11 is 0.34 ± 0.04. Taking the thickness of the main body portion 11 as 725 μm as an example, the fifth distance d5 is, for example, 250 μm ± 30 μm.
[0044] As can be seen from Figure 4 , in this embodiment, an asymmetric chamfer is formed at the edge of the single-crystal silicon wafer 1. The first side of the chamfered portion 12 can have the same structure as the first side of the existing chamfered portion 12, so there is no need to change the original requirements for semiconductor device processing, and it has no adverse effect on subsequent semiconductor device manufacturing processes. The second side of the chamfered portion 12 can fit more closely to the surface of the base 9 of the reaction equipment, and the stress-bearing surface is more uniform, which can effectively reduce stress during the rapid heating process and reduce the generation of chipping and dark pattern fragments.
[0045] Figure 1 and Figure 4 only exemplarily show two optional shapes of the first chamfered surface and the second chamfered surface, but the present application is not limited thereto. In other alternative embodiments, the first chamfered surface and the second chamfered surface can also adopt other shapes. For example, the first chamfered surface and the second chamfered surface are respectively an integral arc surface, or the first chamfered surface and the second chamfered surface are respectively formed by connecting arc surfaces with different radii, etc., all of which fall within the protection scope of the present application.
[0046] In the above embodiments, the present application takes a single-crystal silicon wafer with a thickness of 725 μm as an example to illustrate the structural parameters of the chamfered portion of the single-crystal silicon wafer, but it is not intended to limit the protection scope of the present application. In different application scenarios, parameters such as the thickness and diameter of the single-crystal silicon wafer can be adjusted according to the needs of semiconductor devices. Correspondingly, the structural parameters of the chamfered portion are also adjusted accordingly, all of which fall within the protection scope of the present application.
[0047] The embodiment of the present application also provides a processing method for a single-crystal silicon wafer, including the following steps:
[0048] Grind the two side surfaces of the periphery of the main body portion of the single-crystal silicon wafer respectively to form a chamfered portion. The chamfered portion can, for example, adopt such as Figure 1 or Figure 4The structure of the chamfered portion shown, but the present application is not limited thereto, and the chamfered portion may also adopt other shapes. Among them, a first chamfered surface is formed on the first side of the chamfered portion, and a second chamfered surface is formed on the second side of the chamfered portion; the inner edge and the outer edge of the first chamfered surface have a first distance in the width direction, the inner edge and the outer edge of the second chamfered surface have a second distance in the width direction, and the second distance is less than the first distance; the inner edge and the outer edge of the first chamfered surface have a third distance in the thickness direction, the inner edge and the outer edge of the second chamfered surface have a fourth distance in the thickness direction, and the fourth distance is less than the third distance.
[0049] By adopting the processing method of the single-crystal silicon wafer, a single-crystal silicon wafer with the above-mentioned chamfered portion structure can be obtained, thereby obtaining the beneficial effects of the above-mentioned single-crystal silicon wafer.
[0050] Silicon wafers belong to brittle materials. By chamfering the edges of the silicon wafers, the sharp and rough edges of the silicon wafers can be trimmed into a smooth shape that is beneficial to subsequent processing. The chamfering process is used to grind the edges of the silicon wafers through a chamfering machine. The silicon wafers are usually vacuum-adsorbed on the wafer stage and rotated, maintaining a certain distance from the grinding wheel. By controlling the movement of the silicon wafers, the end faces of the silicon wafers are chamfered by the high-speed rotation of the grinding wheel with diamond abrasive grains. When chamfering the second side of the chamfered portion by the chamfering machine, the number of chamfering grinding circles and the grinding amount are reduced. Moreover, no damaged layer is required on the second chamfered surface of the chamfered portion. The processing parameters and processing environment of the chamfering machine can be set as needed, as long as the chamfered portion structure of the single-crystal silicon wafer of the present application can be obtained.
[0051] In this embodiment, after the two side surfaces of the periphery of the main body portion of the single-crystal silicon wafer are respectively ground to form a chamfered portion, the processing method of the single-crystal silicon wafer further includes the following steps:
[0052] Place the single-crystal silicon wafer on the base of the reaction equipment, with the second side of the chamfered portion facing the base, and perform epitaxial growth treatment or annealing treatment on the single-crystal silicon wafer based on the reaction equipment. This reaction equipment is, for example, a Centura AMAT type of equipment, which is an AMAT automated multi-chamber equipment platform. However, the present application is not limited thereto, and this single-crystal silicon wafer can also be used in other types of reaction equipment. When this single-crystal silicon wafer is placed on the base surface of other types of reaction equipment, the technical effects of the present application can also be achieved.
[0053] The single-crystal silicon wafer and the processing method of the single-crystal silicon wafer provided by the present application have the following advantages:
[0054] By adopting the present application, an asymmetric chamfer is formed at the edge of the single-crystal silicon wafer. The first side of the chamfer portion can remain unchanged, so there is no need to change the original requirements for semiconductor device processing. The second side of the chamfer portion can fit better with the base of the reaction equipment, and the stress-bearing surface is more uniform, which can effectively reduce stress during the rapid heating process. Even under high-temperature process stress, it can effectively reduce the generation of chipping and dark stripe fragments, effectively improve the preparation yield of semiconductor devices, and reduce the production cost of semiconductor devices.
[0055] The above content is a further detailed description of the present application in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present application is only limited to these descriptions. For those of ordinary skill in the technical field to which the present application belongs, without departing from the concept of the present application, several simple deductions or substitutions can still be made, which should all be regarded as belonging to the protection scope of the present application.
Claims
1. A single crystal silicon wafer, characterized in that: The single crystal silicon wafer comprises a main body and a chamfered portion located at the periphery of the main body, a first side of the chamfered portion forms a first chamfered surface, and a second side of the chamfered portion forms a second chamfered surface; An inner edge of the first chamfered surface and an outer edge have a first distance in the width direction, and an inner edge of the second chamfered surface and an outer edge have a second distance in the width direction, and the second distance is smaller than the first distance; An inner edge and an outer edge of the first chamfered surface have a third distance in the thickness direction, and an inner edge and an outer edge of the second chamfered surface have a fourth distance in the thickness direction, and the fourth distance is smaller than the third distance.
2. The single crystal silicon wafer according to claim 1, characterized in that: The second distance is 120 μm±40 μm.
3. The single crystal silicon wafer according to claim 1, characterized in that: An outer edge of the first chamfered surface and an outer edge of the second chamfered surface have a fifth distance in the thickness direction, and a ratio of the fifth distance to the thickness of the main body is 0.34±0.
04.
4. The single crystal silicon wafer according to claim 1, characterized in that: The first distance is 420 μm±100 μm.
5. The single crystal silicon wafer according to claim 1, characterized in that: The first chamfered surface and the second chamfered surface are respectively straight inclined surfaces.
6. The single crystal silicon wafer according to claim 1, characterized in that: The first chamfered surface and the second chamfered surface are respectively at least partially arc surfaces.
7. The single crystal silicon wafer according to claim 6, characterized in that: A first arc surface is formed at the outer edge of the first chamfered surface, and the radius of the first arc surface is 200 μm±50 μm.
8. The single crystal silicon wafer according to claim 6, characterized in that: A second arc surface is formed at the outer edge of the second chamfered surface, and the radius of the second arc surface is 200 μm±50 μm.
9. A method for processing a single crystal silicon wafer, characterized in that: The steps include: The two side surfaces of the outer periphery of the main body of the single crystal silicon wafer are respectively ground to form a chamfered portion; wherein the first side of the chamfered portion forms a first chamfered surface, and the second side of the chamfered portion forms a second chamfered surface; the inner edge and the outer edge of the first chamfered surface have a first distance in the width direction, and the inner edge and the outer edge of the second chamfered surface have a second distance in the width direction, and the second distance is smaller than the first distance; the inner edge and the outer edge of the first chamfered surface have a third distance in the thickness direction, and the inner edge and the outer edge of the second chamfered surface have a fourth distance in the thickness direction, and the fourth distance is smaller than the third distance.
10. The method for processing a single crystal silicon wafer according to claim 9, characterized in that: After the surfaces on both sides of the periphery of the main body of the single crystal silicon wafer are ground respectively to form the chamfered portion, the following steps are also included: The single crystal silicon wafer is placed on a base of a reaction device, with the second side of the chamfered portion facing the base, and an epitaxial growth process or an annealing process is performed on the single crystal silicon wafer based on the reaction device.