Light source device and distance measuring device

Abstract

The invention relates to a light source device and a distance measuring device. The light source device includes a plurality of semiconductor light emitting elements configured to sequentially stack a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on a first surface side of a semiconductor substrate, and stacking a second electrode on a second surface of the semiconductor substrate opposite to the first surface. The power supply pad supplies power to the plurality of semiconductor light-emitting elements. The plurality of semiconductor light emitting elements are divided into a plurality of groups according to a distance from the power supply pad. The semiconductor light emitting elements in the group having a shorter distance from the power supply pad are configured to have a larger resistance value between the first electrode and the second electrode.

Description

Technical Field

[0001] The present disclosure relates to a light source device and a distance measuring device. Background Art

[0002] Conventionally, as a distance measuring device for measuring the distance to an object, a LiDAR (Light Detection and Ranging) system using a ToF (Time of Flight) method is known. As a light source used in the LiDAR system, it is desirable to use a VCSEL (Vertical-Cavity Surface-Emitting LASER) because of advantages such as low wavelength dependence with respect to temperature.

[0003] Since a LiDAR system's light source has a longer ranging distance with greater power, multiple semiconductor light-emitting elements can be arranged in an array to enable flash driving for simultaneous light emission over the entire surface. Additionally, the light source of the LiDAR system can be configured to support sequential driving that causes one row or several rows to emit light sequentially. Japanese Patent Application Laid-Open No. 2021-136307 describes an example where the number of semiconductor light-emitting elements can be 100 to 1000, and the output is increased by increasing the number of semiconductor light-emitting elements.

[0004] Here, since the power consumption of a LiDAR system's light source increases as the output of the semiconductor light-emitting element increases, it is designed to reduce the element resistance to reduce power consumption. Japanese Patent Application Laid-Open No. 2021-136319 discloses an example where the element resistance is reduced by increasing the doping concentration of the upper reflector, which is a current path in the semiconductor light-emitting element. Summary of the Invention

[0005] However, in the case of constructing a light source device including multiple semiconductor light-emitting elements using the above-described prior art, the light emission in each semiconductor light-emitting element is uneven.

[0006] Therefore, an object of the present invention is to provide a light source device capable of improving the uniformity of light emission among multiple semiconductor light-emitting elements.

[0007] According to one disclosure of the present specification, a light source device is provided, which includes: a plurality of semiconductor light-emitting elements configured to sequentially stack a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on a first surface side of a semiconductor substrate, and stack a second electrode on a second surface of the semiconductor substrate opposite to the first surface; a power supply pad configured to supply power to the plurality of semiconductor light-emitting elements; and a wiring configured to connect each of the semiconductor light-emitting elements in the plurality of semiconductor light-emitting elements to the power supply pad, wherein the plurality of semiconductor light-emitting elements are divided into a plurality of groups according to the distance from the power supply pad, and each group in the plurality of groups includes at least one semiconductor light-emitting element, and wherein the semiconductor light-emitting elements in the group with a shorter distance from the power supply pad are configured to have a larger resistance value between the first electrode and the second electrode.

[0008] More features of the present invention will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a plan view illustrating a structural example of a VCSEL array according to a first embodiment.

[0010] Figure 2A and Figure 2B is a cross-sectional view illustrating a structural example of a VCSEL according to a first embodiment.

[0011] Figure 3 is a table illustrating an example of materials added to a semiconductor layer of a VCSEL according to a first embodiment and an increase rate of a resistance value due to the addition of the semiconductor layer.

[0012] Figure 4 is a plan view illustrating a structural example of a VCSEL array according to a comparative example.

[0013] Figure 5 is a graph illustrating a current distribution in each VCSEL array according to the first embodiment and the second embodiment.

[0014] Figure 6 is a cross-sectional view illustrating a structural example of an epitaxial wafer according to a first embodiment.

[0015] Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 7E 、 Figure 7F 、 Figure 7G 、 Figure 7H 、 Figure 7I and Figure 7JIs a cross-sectional view illustrating a manufacturing process of a VCSEL array according to the first embodiment.

[0016] Figure 8 Is a cross-sectional view illustrating a structural example of an epitaxial wafer according to the second embodiment.

[0017] Figure 9 Is a cross-sectional view illustrating a structural example of a VCSEL according to the second embodiment.

[0018] Figure 10 Is a plan view illustrating a structural example of a VCSEL array according to the third embodiment.

[0019] Figure 11 Is a cross-sectional view illustrating a structural example of a VCSEL according to the third embodiment.

[0020] Figure 12 Is a graph illustrating the relationship between the width of an insulating opening and the magnification of resistance according to the third embodiment.

[0021] Figure 13 Is a graph illustrating the current distribution in each VCSEL array according to the third and fourth embodiments.

[0022] Figure 14 Is a plan view illustrating a structural example of a VCSEL array according to the fourth embodiment.

[0023] Figure 15 Is a table illustrating the relationship between the width of an insulating opening and the resistance value according to the fourth embodiment.

[0024] Figure 16 Is a graph illustrating the relationship between the current density and the pulse generation timing according to the fifth embodiment.

[0025] Figure 17 Is a graph illustrating the relationship between the current density and the pulse delay time according to the fifth embodiment.

[0026] Figure 18 Is a plan view illustrating a structural example of a VCSEL array according to the fifth embodiment.

[0027] Figure 19 Is a cross-sectional view illustrating a structural example of a high peak value VCSEL according to the fifth embodiment.

[0028] Figure 20 Is a plan view illustrating a structural example of a VCSEL array according to the sixth embodiment.

[0029] Figure 21A and Figure 21B Is a cross-sectional view illustrating a structural example of a VCSEL according to the sixth embodiment.

[0030] Figure 22 It is a graph illustrating the relationship between the area of the non-oxidized region and the resistance value according to the sixth embodiment.

[0031] Figure 23 It is a plan view illustrating a structural example of the VCSEL array according to the seventh embodiment.

[0032] Figure 24 It is a table illustrating the relationship between the width of the non-oxidized region and the resistance value according to the eighth embodiment.

[0033] Figure 25 It is a graph illustrating the current distribution in each VCSEL array according to the eighth embodiment.

[0034] Figure 26 It is a plan view illustrating a structural example of the VCSEL array according to the ninth embodiment.

[0035] Figure 27A and Figure 27B It is a cross-sectional view illustrating a structural example of the VCSEL according to the ninth embodiment.

[0036] Figure 28 It is a cross-sectional view illustrating a structural example of the VCSEL array according to the tenth embodiment.

[0037] Figure 29 It is a block diagram illustrating a structural example of the distance measuring device according to the eleventh embodiment. Detailed Description of the Invention

[0038] [First Embodiment]

[0039] The VCSEL array (light source device) 100 according to the first embodiment will be described. The VCSEL array 100 is a semiconductor laser including a plurality of VCSELs 1 arranged in an array and emitting laser light from each VCSEL 1. Here, the array refers to a state in which a plurality of VCSELs 1 are two-dimensionally arranged according to a predetermined pattern.

[0040] In the following description, the first direction (row direction) when arranging a plurality of VCSELs 1 in an array is referred to as the X direction. The second direction (column direction) when arranging a plurality of VCSELs 1 in an array is referred to as the Y direction. The direction intersecting the X direction and the Y direction is referred to as the Z direction. The X direction, the Y direction, and the Z direction are generally orthogonal to each other.

[0041] For example, as Figure 1 illustrated, the VCSEL array 100 includes a plurality of VCSELs 1 as a plurality of semiconductor light-emitting elements, a plurality of anode wirings 101 as wirings, and a plurality of anode power supply pads 102 as power supply pads.Figure 1 Illustrate 4 VCSELs 1 on one side in the Y direction and 3 VCSELs 1 on the other side in the Y direction among multiple VCSELs 1.

[0042] Each VCSEL 1 is a vertical cavity surface emitting laser including a distributed Bragg reflector (DBR). Multiple VCSELs 1 are arranged in an array in multiple rows and multiple columns. For example, twenty VCSELs 1 are arranged in a column in the Y direction, and twenty beams of twenty arrays in the Y direction are arranged in the X direction. As a result, a total of four hundred (20×20) VCSELs 1 are arranged in an array and have a rectangular shape as a whole when viewed from the Z direction.

[0043] Multiple anode wirings 101 are wirings that connect each of the multiple VCSELs 1 to an anode power supply pad 102. Each anode wiring among the multiple anode wirings 101 extends in the Y direction and is arranged side by side in the X direction. One anode wiring 101 is electrically connected to twenty VCSELs 1 in the Y direction. In other words, twenty VCSELs 1 in the Y direction are connected in parallel to one anode wiring 101. Then, twenty such anode wirings 101 are arranged side by side in the X direction. As described above, the multiple anode wirings 101 are configured as sequential anode wirings. Each anode wiring 101 supplies current to the twenty VCSELs 1 connected in parallel.

[0044] The anode power supply pad 102 is a part for connecting an Au wiring (not illustrated). The anode power supply pad 102 is a power supply pad for supplying power to the multiple VCSELs 1 and is provided at one end in the Y direction of the anode wiring 101. The anode power supply pad 102 has a function of supplying the current supplied from the outside through the Au wiring to the anode wiring 101.

[0045] The VCSEL array 100 configured as described above can cause the four hundred VCSELs 1 to emit light by supplying current to the twenty anode power supply pads 102 from the outside via the Au wiring. By sequentially supplying current to the twenty anode power supply pads 102 from the outside, sequential driving in which each column emits light at different timings can be performed.

[0046] Here, multiple VCSELs 1 according to the first embodiment are configured to include a VCSEL1A as a semiconductor light emitting element and a VCSEL 1B as a semiconductor light emitting element. In the following description, when it is not necessary to distinguish between VCSEL 1A and VCSEL 1B from each other, VCSEL 1A and VCSEL 1B may be simply referred to as "VCSEL 1".

[0047] As Figure 2BIllustratively, the VCSEL 1B includes an n-type GaAs substrate 10 as a semiconductor substrate, a first DBR 20 as a first reflector, a semiconductor resonator 30 as a first semiconductor resonator, and a second DBR 40 as a second reflector. In addition, the VCSEL 1B includes an insulating film 50, an upper electrode 60 (e.g., an upper annular electrode) as a first electrode, and a back electrode 70 as a second electrode. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. Although in Figure 2B these members are in direct contact with each other, other members can be provided between these members in the VCSEL 1B. In addition, the above description represents a structure and does not limit the order of manufacturing each member. Figure 2B is a cross-sectional view along Figure 1 the line V2-V2.

[0048] The n-type GaAs substrate 10 is made of n-type GaAs single crystal. The n-type GaAs substrate 10 has a first surface on which various members are stacked, and a second surface located at a position opposite to the first surface in the Z direction.

[0049] The first DBR 20 is provided on the first surface of the n-type GaAs substrate 10. The first DBR 20 is formed by stacking 35 pairs of Al 0.1 GaAs layers and Al 0.9 GaAs layers each having an optical film thickness of 1 / 4λc. Here, the center wavelength λc of the high reflection band of the second DBR 40 is, for example, 940 nm.

[0050] The semiconductor resonator 30 is provided on the first DBR 20 and includes an n-type AlGaAs layer, a first active layer, and a p-type layer starting from the first DBR 20 side. The first active layer is an undoped layer, and three quantum well layers 31 are provided in the first active layer. Each of the three quantum well layers 31 includes an InGaAs well layer having a thickness of 8 nm and an AlGaAs barrier layer having a thickness of 10 nm that sandwiches the InGaAs well layer.

[0051] The second DBR 40 is provided on the semiconductor resonator 30 and is formed by stacking 35 pairs of Al 0.1 GaAs layers and Al 0.9Formed by stacking 20 pairs of GaAs layers. A current confinement layer 41 with a thickness of 30 nm is provided in the second DBR 40. The current confinement layer 41 is partially oxidized in the lateral direction (X direction, Y direction) of the mesa from the mesa sidewalls by being exposed to a water vapor atmosphere during the manufacturing process. The current confinement layer 41 is divided into an oxidized region having a predetermined width starting from the mesa sidewalls and a non-oxidized region near the center of the mesa. Since the current injected into the VCSEL 1B flows only in the non-oxidized region, only the central portion of the VCSEL 1B oscillates the laser. The upper electrode 60 is in electrical contact with the second DBR 40. The uppermost layer of the second DBR 40 is Al 0.1 A part of the GaAs layer is replaced by a GaAs contact layer having a thickness of 50 nm and a carrier concentration of 1×10 19 cm -3 . Thus, the electrical contact between the second DBR 40 and the upper electrode 60 is improved. The semiconductor resonator 30 and the second DBR 40, which are the layers on the upper side of the first DBR 20, are configured in such a way that a part of the surface of the chip is removed during the manufacturing process and the remaining part is formed in a mesa shape.

[0052] The insulating film 50 covers the mesa-shaped semiconductor resonator 30, the second DBR 40, etc., and suppresses the alteration of these elements.

[0053] The upper electrode 60 is provided on the second DBR 40 and is electrically connected to the anode wiring 101. The upper electrode 60 has an annular conductive pattern, and the central opening of the upper electrode 60 serves as a circular window for light extraction. The upper electrode 60 makes an ohmic contact with the second DBR 40 through a part where a part of the insulating film 50 is removed.

[0054] The back electrode 70 has conductivity and is provided on the second surface of the n-type GaAs substrate 10. The back electrode 70 makes an ohmic contact with the n-type GaAs substrate 10.

[0055] In the VCSEL 1B configured as described above, when current is applied to the upper electrode 60 via the anode wiring 101, the current flows through the semiconductor resonator 30 via the upper electrode 60, and thus light is generated in the semiconductor resonator 30. Then, the light generated in the semiconductor resonator 30 resonates between the first DBR 20 and the second DBR 40 to cause laser oscillation, and the laser-oscillated light exits in the Z direction from the central opening of the upper electrode 60.

[0056] Next, the VCSEL 1A will be described. The VCSEL 1A is different from the VCSEL 1B in that a semiconductor layer 80 is provided, and has the same structure as the VCSEL 1B in other aspects. That is, as Figure 2AIllustratively, the VCSEL 1A includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper electrode 60, a back electrode 70, and a semiconductor layer 80. The first DBR 20, the semiconductor resonator 30, the second DBR 40, the semiconductor layer 80, and the upper electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. Figure 2A is a cross-sectional view along Figure 1 the line V1-V1. Since the n-type GaAs substrate 10, the first DBR 20, the semiconductor resonator 30, the second DBR 40, the insulating film 50, the upper electrode 60, and the back electrode 70 have the same structure as the above-described VCSEL 1B, their detailed description will be omitted.

[0057] The semiconductor layer 80 is used to set the resistance value (device resistance value) between the upper electrode 60 and the back electrode 70 of the VCSEL 1A to a value different from the resistance value between the upper electrode 60 and the back electrode 70 of the VCSEL 1B. The semiconductor layer 80 is provided between the upper electrode 60 and the second DBR 40. In other words, the semiconductor layer 80 is stacked in the Z direction on the side of the second DBR 40 opposite to the semiconductor resonator 30. Since the VCSEL 1A includes the semiconductor layer 80, the series resistance component between the upper electrode 60 and the second DBR 40 is larger than that of the VCSEL 1B. That is, the VCSEL 1A is formed such that the distance between the upper electrode 60 and the back electrode 70 is longer than that of the VCSEL 1B. Since the distance of the VCSEL 1A is longer than that of the VCSEL 1B, the resistance value between the upper electrode 60 and the back electrode 70 of the VCSEL 1A is larger than that of the VCSEL 1B. The resistance value of the VCSEL 1A can be changed by changing the material, composition, and film thickness of the semiconductor layer 80.

[0058] As described above, the VCSEL 1A has a semiconductor layer 80 between the upper electrode 60 and the second DBR 40, while the VCSEL 1B does not have a semiconductor layer 80 between the upper electrode 60 and the second DBR 40. Thus, the VCSEL 1A and the VCSEL 1B have different resistance values between the upper electrode 60 and the back electrode 70. When the first resistance value between the upper electrode 60 and the back electrode 70 of the VCSEL 1A is R1 and the second resistance value between the upper electrode 60 and the back electrode 70 of the VCSEL 1B is R2, R1 > R2. That is, the VCSEL 1A has a resistance value larger than that of the VCSEL 1B.

[0059] Figure 3 This is a table showing examples of the materials of the semiconductor layer 80 and their various electrical characteristics. In this figure, the increase rate of the device resistance value indicates the increase rate of the resistance value for each thickness of 1 μm. It is assumed that the doping concentration of each material is 1×10 17 cm -3 . By disposing the semiconductor layer 80 on the second DBR 40, the resistance of the VCSEL 1A can be increased. In the semiconductor layer 80, AlInP having a carrier concentration of 1×10 17 cm -3 is stacked starting from the side closer to the second DBR 40, and a GaAs contact layer having a thickness of 50 nm and a carrier concentration of 1×10 19 cm -3 is formed on the AlInP. Thus, the semiconductor layer 80 forms a two-layer structure. The optical film thickness of the semiconductor layer 80 is desirably selected from integer multiples of 1 / 2λc to suppress the added optical influence of this layer. In the first embodiment, by setting the thickness of the AlInP layer to 403 nm, the optical film thickness of the semiconductor layer 80 is 3 / 2λc. With such a structure, the resistance value of the VCSEL 1A can be 1.33 times that of the VCSEL 1B.

[0060] In the VCSEL array 100, two types of VCSELs, VCSEL 1A and VCSEL 1B, having different resistance values are arranged such that the current injected into VCSEL 1A and VCSEL 1B is uniform. Here, the plurality of VCSELs 1 are divided into a plurality of groups according to the wiring resistance from the anode power supply pad 102. For example, the plurality of VCSELs 1 can be divided into a plurality of groups according to the distance from the anode power supply pad 102. The plurality of groups can include, for example, a first group and a second group. The first group can include VCSELs 1 having a shorter distance from the anode power supply pad 102 compared to the second group. The second group can include VCSELs 1 having a longer distance from the anode power supply pad 102 compared to the first group. Here, the VCSELs 1 included in the first group and the VCSELs 1 included in the second group have different resistance values. That is, the VCSELs 1 included in the second group have a smaller resistance value compared to the resistance value of the VCSELs 1 included in the first group. In other words, the VCSELs 1 included in the first group have a larger resistance value compared to the resistance value of the VCSELs 1 included in the second group. As described above, the VCSELs are configured such that the group with a shorter distance from the anode power supply pad 102 has a higher resistance value. For example, the VCSELs are configured such that the group with a lower wiring resistance from the anode power supply pad 102 has a higher resistance value. Specifically, VCSEL 1A constitutes the VCSELs of the first group with a short distance from the anode power supply pad 102, and VCSEL 1B constitutes the VCSELs of the second group with a long distance from the anode power supply pad 102. More specifically, as Figure 1 illustrated, among the twenty VCSELs in the Y direction, the first group of VCSELs including the first to sixth VCSELs closer to the anode power supply pad 102 includes VCSEL 1A. The second group of VCSELs including the remaining sixth to twentieth VCSELs includes VCSEL 1B.

[0061] Figure 4 is a plan view illustrating a structural example of a VCSEL array 900 according to a comparative example. In the VCSEL array 900 according to the comparative example, as Figure 4Illustratively, all the VCSELs (four hundred VCSELs) are VCSEL 1B and are arranged in an array. In the VCSEL array 900 according to the comparative example, when the VCSEL 1B is arranged at a high density with a narrow interval between the VCSEL 1Bs due to a reduction in chip size or the like, it is difficult to thicken the wiring for supplying power to each VCSEL 1B. Therefore, the VCSEL 1B located far from the anode power supply pad 102 and having a long current path has a larger voltage drop due to the wiring resistance than the VCSEL 1B located near the anode power supply pad 102. As a result, the voltage applied between the anode and the cathode of the VCSEL 1B decreases, and as a result, the injected current amount decreases.

[0062] Then, the non-uniformity of the current injected into each VCSEL 1B of the VCSEL array 900 causes various adverse effects. For example, in order to allow a predetermined current to flow through the VCSEL 1B having the minimum current, the input power is increased, and the intensity of the light of each VCSEL 1B varies in the VCSEL array 900. As a result, the signal of the dark image detected by the distance measuring device becomes weak. Therefore, the ratio between the signal and the noise in the light receiving unit becomes small, the distance measuring accuracy varies, and in the case of an illumination application, various adverse effects such as the influence of uneven illuminance in the plane occur.

[0063] In contrast, in the VCSEL array 100 according to the first embodiment, the first group of VCSELs 1A having a high resistance value are arranged closer to the anode power supply pad 102 than the second group of VCSELs 1B having a low resistance value. In other words, the current path from the anode power supply pad 102 to the VCSEL 1A having a high resistance value is shorter than the current path from the anode power supply pad 102 to the VCSEL 1B having a low resistance value. With this structure, the resistance values of the VCSEL 1A and VCSEL 1B including the resistance value of the anode wiring 101 can be made closer to each other. Thus, even if a voltage drop occurs due to the wiring resistance, the current injected into the VCSEL 1A and VCSEL 1B can be made more uniform, and the current distribution can be smoothed. Here, the current distribution represents the distribution of the values of the current injected into each VCSEL in the VCSEL array. Since the current distribution can be smoothed, the variation in the light amount of the VCSEL 1A and VCSEL 1B can be suppressed, and thereby the uniformity of the light emission of the VCSEL 1A and VCSEL 1B can be improved. Due to the uniformity of the light emission of the VCSEL 1A and VCSEL 1B, the variation in the lifetimes of the VCSEL 1A and VCSEL 1B is also suppressed. In addition, since the current distribution is smoothed, the input power to the VCSEL array 100 is reduced. As described above, the effect of reducing the input power due to smoothing the current distribution is greater than the effect of increasing the input power due to increasing some of the resistors in the resistor.

[0064] In addition, since the heat generation amount of the VCSEL array 100 is proportional to the product of the power of the resistance and the square of the current value, from the perspective of heat generation, the effect of reducing the current value due to smoothing the current distribution is also significant.

[0065] Figure 5 is a graph showing the current distribution in each VCSEL array. In Figure 5 it, the vertical axis represents the current value, and the horizontal axis represents the nth VCSEL counted from the side closer to the anode power supply pad 102 in one array (twenty VCSELs 1 in a column). Figure 5 Illustrates the current distribution L2 of one array in the VCSEL array 100 according to the first embodiment. Figure 5 Also illustrates the current distribution L1 of one array in the VCSEL array 900 according to the comparative example.

[0066] In the VCSEL array 900 according to the comparative example, the ratio between the maximum value MAX and the minimum value MIN of the current flowing through each VCSEL 1B in one array is 0.63 ( Figure 5The current distribution L1) in it. In addition, in the VCSEL array 900, when the minimum current value required for one VCSEL 1B is 0.06 A, considering the variation in the current value, the current value required for one array is estimated to be 1.44 A, and the input power is 7.29 W. On the other hand, in the VCSEL array 100 according to the first embodiment, the ratio between the maximum value and the minimum value of the current flowing through the VCSEL 1A and VCSEL 1B in one array is 0.76( Figure 5 The current distribution L2) in it. In addition, in the VCSEL array 100, when the minimum current value required for one VCSEL 1A or 1B is 0.06 A, considering the variation in the current value, the current value required for one array is estimated to be 1.33 A, and the input power is 6.70 W. As described above, in the VCSEL array 100, since the ratio of the maximum value to the minimum value is closer to 1.0 compared with the VCSEL array 900 according to the comparative example, the current distribution can be made smooth. In addition, compared with the VCSEL array 900 according to the comparative example, the VCSEL array 100 can reduce the current value required for one array and suppress the input power.

[0067] Next, a method for manufacturing the VCSEL array 100 including two types of VCSELs 1A and 1B will be described. Figure 6 is a cross-sectional view illustrating a structural example of an epitaxial wafer including an epitaxial growth portion. As Figure 6 illustrated, first, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an AlInP resistance layer 181 forming a semiconductor layer 80, and a second p-type GaAs contact layer 182 are sequentially epitaxially grown on an n-type GaAs substrate 10. The uppermost layer of the second DBR 40 is a first p-type GaAs contact layer 180.

[0068] Next, the manufacturing process will be described with reference to Figures 7A to 7J . Figures 7A to 7J By selecting the portions where the VCSEL 1A and VCSEL 1B are configured to be adjacent to each other in the Figure 1 Y direction in it, the cross-sections of the two VCSELs 1A and VCSEL 1B are illustrated, but the other portions can be formed by the same manufacturing process.

[0069] First, a SiOx layer 183 serving as a hard mask during dry etching is formed on the second p-type GaAs contact layer 182 by plasma CVD( Figure 7A ).

[0070] Next, the SiOx layer 183 is patterned by photolithography and wet etching. This pattern serves as a hard mask during dry etching( Figure 7B ).

[0071] Next, a mesa structure is formed by dry etching. When forming the mesa structure, the second DBR 40 including the second p-type GaAs contact layer 182, the AlInP resistance layer 181, and the first p-type GaAs contact layer 180 is etched. In addition, the semiconductor resonator 30 is etched, and a part of the first DBR 20 is also etched. When it is desired to arrange the VCSELs 1 at a high density, it is desirable to make the sidewall angle of the mesa structure close to perpendicular to the n-type GaAs substrate 10. On the other hand, in the films formed on the sidewalls of the mesa structure (such as the insulating film 50 and the anode wiring 101), when the disconnection caused by the mesa step adversely affects the device characteristics, the sidewall angle is desirably less than the perpendicular angle. Therefore, the sidewall angle is appropriately selected by changing the etching conditions according to the required specifications and performance.

[0072] Next, heat treatment is performed in a water vapor atmosphere to selectively oxidize a part of the second DBR 40 from the mesa sidewalls, thereby forming a current confinement layer 41 ( Figure 7C ).

[0073] Next, a resist R including a resist opening is formed on the VCSEL 1B by photolithography, and the SiOx layer 183 on the VCSEL 1B is selectively exposed ( Figure 7D ).

[0074] Next, the SiOx layer 183 in the region including the resist opening is selectively etched by wet etching using buffered hydrofluoric acid. In addition, the second p-type GaAs contact layer 182 is selectively etched using a citric acid-based etchant, and then the AlInP resistance layer 181 is selectively etched using a hydrochloric acid-based etchant ( Figure 7E ). After that, the resist pattern is removed at once ( Figure 7F ).

[0075] Next, a resist R including a resist opening is formed on the VCSEL 1A by photolithography, and the SiOx layer 183 on the VCSEL 1A is selectively exposed ( Figure 7G ).

[0076] Next, the SiOx layer 183 in the region including the resist opening is selectively etched by wet etching using buffered hydrofluoric acid ( Figure 7H ), and then the resist pattern is removed ( Figure 7I ).

[0077] Next, an insulating film 50 is formed to cover the mesa structure, and an opening is formed in the insulating film 50 by photolithography and etching techniques. The upper electrode 60 and the anode wiring 101 are formed by photolithography, vacuum deposition, and lift-off techniques, and then the emission port is formed. Next, after polishing the back surface of the n-type GaAs substrate 10, a back electrode 70 is formed on the back surface side of the n-type GaAs substrate 10( Figure 7J ).

[0078] By continuing the above steps, two types of VCSELs can be fabricated, namely, VCSEL 1A including the semiconductor layer 80 containing the AlInP resistance layer 181 and VCSEL 1B not including the semiconductor layer 80.

[0079] In this embodiment, an example in which VCSEL 1B does not include the semiconductor layer 80 is illustrated, but the present invention is not limited thereto, and by changing the resistance values of the two types of VCSELs 1A and VCSEL 1B, the current distribution can be improved compared with the comparative example. Specifically, VCSEL 1B can have a semiconductor layer 80 thinner than that of the semiconductor layer 80 of VCSEL 1A. This also applies to the following embodiments.

[0080] In addition, in this embodiment, an example in which the power supply pad 102 is provided at one end of the anode wiring 101 in the Y direction is illustrated, but the present invention is not limited thereto, and the power supply pad 102 can be provided at both ends of the anode wiring 101 in the Y direction. Even in this case, VCSEL 1A and VCSEL 1B are arranged in the same manner with respect to the power supply pad 102. Specifically, VCSEL 1A can be arranged on the side closer to the power supply pad 102, and VCSEL 1B can be arranged on the side farther from the power supply pad 102 (the center of the array). This also applies to the following embodiments.

[0081] [Second Embodiment]

[0082] Next, the VCSEL array 100A according to the second embodiment will be described. The VCSEL array 100A according to the second embodiment includes three types of VCSELs 1A, VCSEL 1Aa, and VCSEL 1B having different resistance values.

[0083] VCSEL 1A, VCSEL 1Aa, and VCSEL 1B have different resistance values between the upper electrode 60 and the back electrode 70. The first resistance value between the upper electrode 60 and the back electrode 70 of VCSEL 1A is represented by R1, and the second resistance value between the upper electrode 60 and the back electrode 70 of VCSEL 1B is represented by R2. When the third resistance value between the upper electrode 60 and the back electrode 70 of VCSEL 1Aa is R3, R1 > R3 > R2. That is, the resistance value of VCSEL 1Aa is less than the resistance value of VCSEL 1A and greater than the resistance value of VCSEL 1B.

[0084] In VCSEL 1Aa, the semiconductor layer 80 has a two-layer structure of an AlInP layer and a GaAs contact layer starting from the side close to the second DBR 40. The AlInP layer has a thickness of 0.25 μm and a carrier concentration of 1×10 17 cm -3 , and the GaAs contact layer has a thickness of 50 nm and a carrier concentration of 1×10 19 cm -3 . The optical film thickness of the semiconductor layer 80 is λc. With this structure, the resistance value of VCSEL 1Aa is 1.2 times the resistance value of VCSEL 1B. In VCSEL 1A, the semiconductor layer 80 has a four-layer structure starting from the side close to the second DBR 40. In this four-layer structure, the AlInP layer and the GaAs contact layer similar to those of the semiconductor layer 80 of VCSEL 1Aa are stacked twice. The optical film thickness of the semiconductor layer 80 can be 2λc. With this structure, the resistance value of VCSEL 1A is 1.4 times the resistance value of VCSEL 1B.

[0085] Multiple VCSELs 1 are divided into three groups (a first group to a third group) according to the distance relative to the anode power supply pad 102. The third group is disposed between the first group and the second group. The third group includes VCSELs 1Aa having a resistance value smaller than that of the VCSELs 1A in the first group and larger than that of the VCSELs 1B in the second group. As described above, the VCSEL array 100A is configured such that the VCSELs in the group closer to the anode power supply pad 102 have higher resistance values. That is, the VCSELs 1A in the first group, the VCSELs 1Aa in the third group, and the VCSELs 1B in the second group are arranged in this order in descending order of resistance value starting from the anode power supply pad 102. Specifically, among the twenty VCSELs in the Y direction, the first group including the first to fourth VCSELs closest to the anode power supply pad 102 is composed of the VCSELs 1A having the highest resistance value. In addition, the third group including the fifth to ninth VCSELs is composed of the VCSELs 1Aa having the second highest resistance value, and the second group including the tenth to twentieth VCSELs is composed of the VCSELs 1B having the lowest resistance value.

[0086] In the VCSEL array 100A, the ratio between the maximum value and the minimum value of the current flowing through the VCSELs 1A, 1Aa, and 1B is 0.86 ( Figure 5 the current distribution L3 in). As described above, the VCSEL array 100A according to the second embodiment can make the current distribution smoother compared with the VCSEL array 100 ( Figure 5 the current distribution L2 in) according to the first embodiment. In the VCSEL array 100A according to the second embodiment, when the minimum current value required for each VCSEL is 0.06 A, the input power is 6.35 W. Therefore, compared with the input power (6.70 W) of the VCSEL array 100 according to the first embodiment including two types of VCSELs, the VCSEL array 100A can reduce the input power.

[0087] Next, a method of manufacturing the VCSEL array 100A including three types of VCSELs 1A, 1Aa, and 1B according to the second embodiment will be described. In the second embodiment, compared with the case of manufacturing two types of VCSELs 1A and 1B according to the first embodiment, in the epitaxial growth stage, the semiconductor layer 80 has a four-layer structure. Figure 8 is a cross-sectional view illustrating a structural example of an epitaxial wafer including an epitaxial growth portion.

[0088] As Figure 8Illustratively, as the semiconductor layer 80, an AlInP resistance layer 181, a second p-type GaAs contact layer 182, an AlInP resistance layer 183a, and a third p-type GaAs contact layer 184 are epitaxially grown in this order.

[0089] As Figure 9 Illustratively, in the VCSEL 1B, the third p-type GaAs contact layer 184, the AlInP resistance layer 183a, the second p-type GaAs contact layer 182, and the AlInP resistance layer 181 are removed by etching. That is, for the VCSEL 1B, the entire semiconductor layer 80 is removed. In the VCSEL 1Aa, the third p-type GaAs contact layer 184 and the AlInP resistance layer 183a are removed by etching, and the second p-type GaAs contact layer 182 and the AlInP resistance layer 181 are left. That is, a part of the semiconductor layer 80 is removed from the VCSEL 1Aa. In the VCSEL 1A, all the layers forming the semiconductor layer 80 are left. Thus, three types of VCSELs 1A, 1Aa, and 1B having different resistance values can be manufactured. In the second embodiment, as Figure 9 Illustratively, the VCSELs 1A, 1Aa, and 1B are not arranged adjacent to each other, but in Figure 9 For convenience, the VCSELs of the three types of resistors are illustrated side by side to explain the cross-sectional structure.

[0090] [Third Embodiment]

[0091] Next, the VCSEL array 100B according to the third embodiment will be described. Figure 10 is a plan view illustrating a structural example of the VCSEL array 100B according to the third embodiment. The VCSEL array 100B according to the third embodiment includes VCSELs 2A and 2B different from the VCSELs 1A and 1B according to the first embodiment. Hereinafter, the VCSELs 2A and 2B will be described in detail. In the following description, components identical to those of the VCSELs 1A and 1B according to the first embodiment are denoted by the same reference numerals, and their detailed description will be omitted.

[0092] For example, as Figure 10 Illustratively, the VCSEL array 100B includes a plurality of VCSELs 2, an anode wiring 101, and an anode power supply pad 102. Note that Figure 10 illustrates four VCSELs 2 on one side in the Y direction and three VCSELs 2 on the other side in the Y direction among the plurality of VCSELs 2 connected to each anode wiring 101.

[0093] Twenty VCSELs 2 are arranged in a column in the Y direction, and the twenty beams of the twenty arrangements in the Y direction are arranged in the X direction. As a result, a total of four hundred (20×20) VCSELs 2 are arranged in an array and have a rectangular shape as a whole when viewed from the Z direction.

[0094] The plurality of anode wirings 101 are each arranged to extend in the Y direction and arranged side by side in the X direction. One anode wiring 101 is electrically connected to twenty VCSELs 2 in the Y direction. Then, twenty such anode wirings 101 are arranged side by side in the X direction. Each anode wiring 101 supplies current to the twenty VCSELs 2 connected in parallel.

[0095] The VCSEL array 100B configured as described above can cause the four hundred VCSELs 2 to emit light by supplying current to the twenty anode power supply pads 102 from the outside via the Au wiring. By sequentially supplying current to the twenty anode power supply pads 102 from the outside, sequential driving in which each column emits light at different timings can be performed.

[0096] Here, the VCSEL array 100B according to the third embodiment includes VCSEL 2A and VCSEL 2B as the plurality of VCSELs 2. In the following description, when it is not necessary to distinguish VCSEL 2A and VCSEL 2B from each other, VCSEL 2A and VCSEL 2B may be simply referred to as "VCSEL 2".

[0097] As Figure 11 illustrated, the VCSEL 2A includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper electrode 60, and a back electrode 70. The VCSEL 2A further includes an ITO (indium tin oxide) layer 90 as a transparent conductive film. The first DBR 20, the semiconductor resonator 30, the second DBR 40, the insulating film 50, the ITO layer 90, and the upper electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. Figure 11 is a cross-sectional view along Figure 10 the line V1-V1. Although these components are in direct contact in the VCSEL 2A in Figure 11 , other components may be provided between these components. In addition, the above description is a description of the structure and does not limit the order of manufacturing each component.

[0098] The semiconductor resonator 30 and the second DBR 40 are processed into a mesa shape, and an insulating film 50 is provided on the side surface and the upper surface of the mesa. Further, an ITO layer 90 is formed on the insulating film 50. That is, the ITO layer 90 covers the mesa-shaped semiconductor resonator 30 and the second DBR 40 from above the insulating film 50.

[0099] The central portion of the insulating film 50 is partially removed from the upper surface of the second DBR 40, and in the removed portion, the ITO layer 90 is in contact with the upper surface of the second DBR 40. The portion where the insulating film 50 is removed is referred to as an "insulating opening". The shape of the insulating opening is, for example, a square, and the width of the insulating opening is represented by d2 (see Figure 11 ). The ITO layer 90 is provided between the upper electrode 60 and the second DBR 40 and is in contact with the upper surface of the second DBR 40 in the insulating opening. The upper electrode 60 is in electrical contact with a part of the ITO layer 90. The optical film thickness of the ITO layer 90 is 1 / 2λc.

[0100] The second DBR 40 has a GaAs contact layer (not illustrated) having a thickness of 50 nm and a carrier concentration of 1×10 19 cm -3 in the uppermost layer, and the electrical contact with the ITO layer 90 is improved.

[0101] In the third embodiment, the resistance value is changed by changing the contact area between the GaAs contact layer of the second DBR 40 and the ITO layer 90. Specifically, the contact area is changed by changing the width d2 of the insulating opening, and the amount of current flowing into the second DBR 40 is adjusted. For example, by relatively reducing the width d2 of the insulating opening, the contact area is reduced, thereby increasing the resistance value and reducing the amount of current flowing into the second DBR 40. On the other hand, by relatively increasing the width d2 of the insulating opening, the contact area increases, thereby decreasing the resistance value and increasing the amount of current flowing into the second DBR 40.

[0102] Figure 12 is a graph illustrating the relationship between the width d2 of the insulating opening and the resistance value (calculated result and measured value). In Figure 12 , the horizontal axis represents the width d2 of the insulating opening, and the vertical axis represents the relative resistance value, where for the case where the width d2 of the insulating opening is 10.6 μm, the resistance value is 1.0. Here, as Figure 12 illustrates, when d2 = 7.5 μm, the resistance value changes to 1.15 times, and when d2 = 20 μm, the resistance value changes to 0.93 times. Further, according to Figure 12, it can be confirmed that the measured value also follows the calculation result. When the insulating opening is located inside the non-oxidized region, the insulating opening may adversely affect the light emitted from VCSEL2A. In the case where this is a problem, it is desirable that the width d2 of the insulating opening is greater than the width d1 of the non-oxidized region. Except that the width d2 of the insulating opening is different, VCSEL 2B is configured in the same manner as VCSEL 2A.

[0103] By adjusting the width d2 of the insulating opening of VCSEL 2A, the contact area between the ITO layer 90 and the second DBR 40 in VCSEL 2A is smaller than the contact area between the ITO layer 90 and the second DBR 40 in VCSEL 2B. Thus, when the first resistance value between the upper electrode 60 and the back electrode 70 of VCSEL 2A is R1 and the second resistance value between the upper electrode 60 and the back electrode 70 of VCSEL 2B is R2, R1 > R2. That is, VCSEL 2A has a larger resistance value compared to the resistance value of VCSEL 2B. For example, based on Figure 12 , the width d2 of the insulating opening of VCSEL 2A can be 10.6 μm, and the width d2 of the insulating opening of VCSEL2B can be 16.8 μm. At this time, the width d1 of the non-oxidized region of the current confinement layer 41 can be 10.6 μm. With this design, the resistance value of VCSEL 2A is about 1.07 times the resistance value of VCSEL 2B.

[0104] In the VCSEL array 100B, the arrangement of two types of VCSELs 2A and 2B with different resistance values is designed so that the current injected into VCSEL 2A and VCSEL 2B is more uniform. Here, the plurality of VCSELs 2 are divided into two groups (the first group and the second group) according to the distance from the anode power supply pad 102. The VCSEL array 100B is configured such that the VCSELs in the group closer to the anode power supply pad 102 have a higher resistance value. Specifically, VCSEL 2A constitutes the VCSELs of the first group with a shorter distance from the anode power supply pad 102, and VCSEL 2B constitutes the VCSELs of the second group with a longer distance from the anode power supply pad 102. More specifically, as Figure 10 illustrated, among the twenty VCSELs in the Y direction, the first to fifth VCSELs of the first group closer to the anode power supply pad 102 are constituted by VCSELs 2A with a large resistance value. The remaining sixth to twentieth VCSELs of the second group are constituted by VCSELs 2B with a small resistance value.

[0105] Figure 13 is a graph illustrating the current distribution in each VCSEL array. In Figure 13In [the figure], the vertical axis represents the current value, and the horizontal axis represents the nth VCSEL counted from the side closer to the anode power supply pad 102 in an array. Figure 13 Illustrate the current distribution L5 of an array in the VCSEL array 100B according to the third embodiment. Figure 13 Also illustrate the current distribution L4 of an array in the VCSEL array according to the comparative example. In the VCSEL array according to the comparative example, all the VCSELs (four hundred VCSELs) are VCSEL 2B and are arranged in an array.

[0106] In the VCSEL array according to the comparative example, the ratio between the maximum value MAX and the minimum value MIN of the current flowing through each VCSEL 2B is 0.80 ( Figure 13 the current distribution L4 in [the figure]). In contrast, in the VCSEL array 100B according to the third embodiment, the ratio between the maximum value and the minimum value of the current flowing through VCSEL 2A and VCSEL 2B is 0.86 ( Figure 13 the current distribution L5 in [the figure]). Therefore, in the VCSEL array 100B, compared with the VCSEL array 900 according to the comparative example, the ratio of the maximum value to the minimum value is closer to 1.0, and this can smooth the current distribution. In addition, in the VCSEL array of the comparative example, when adjusting the injection current amount to an array such that the lowest current density injected into each VCSEL 2B is 20 kA / cm 2 or more, the input power is 90.4 mW (0.49 A). In the VCSEL array 100B of the third embodiment, when adjusting the injection current amount to an array such that the lowest current density injected into each of VCSEL 2A and VCSEL 2B is 20 kA / cm 2 or more, the input power is 90.2 mW (0.48 A). From this, it can be seen that the VCSEL array 100B of the third embodiment can also reduce the power input to the array.

[0107] The VCSEL array 100B is characterized in that, like the first embodiment, multiple types of VCSEL 2 can be simultaneously realized only by changing the width d2 of the insulating opening on the photomask without increasing the number of epitaxial layers, etc. Therefore, in the VCSEL array 100B, the width d2 of the insulating opening can be increased without being limited to two types. On the other hand, in the VCSEL array 100B, since the variable width of the width d2 of the insulating opening is limited compared with the VCSEL array 100 of the first embodiment, the change amount of the resistance value is small.

[0108] [Fourth Embodiment]

[0109] Next, the VCSEL array 100C according to the fourth embodiment will be described. The VCSEL array 100C according to the fourth embodiment includes six types of VCSELs 2A, 2Aa1, 2Aa2, 2Aa3, 2Aa4, and 2B having different resistance values. In the case where the current value changes rapidly at the boundary between the VCSEL 2A and the VCSEL 2B as in the current distribution L5 in the VCSEL array 100B according to the third embodiment ( Figure 13 ), the current distribution can be made smoother by finely setting the resistance values of the respective VCSELs 2. Figure 14 FIG. is a plan view illustrating a structural example of the VCSEL array 100C according to the fourth embodiment. The plurality of VCSELs 2 include six types of VCSELs 2 having different resistance values from each other, and are divided into six groups (first group to sixth group) according to the distance from the anode power supply pad 102. The VCSEL array 100C is configured such that the VCSELs in the group closer to the anode power supply pad 102 have higher resistance values. Specifically, the VCSEL 2A in the first group, the VCSEL 2Aa1 in the second group, and the VCSEL 2Aa2 in the third group are arranged one by one in sequence from the side closer to the anode power supply pad 102. Then, after the VCSEL 2Aa2 in the third group, the VCSEL 2Aa3 in the fourth group and the VCSEL 2Aa4 in the fifth group (not illustrated) are formed, and the sixth to twentieth VCSELs are formed by the VCSEL 2B in the sixth group.

[0110] In the VCSEL array 100C according to the fourth embodiment, as Figure 15 illustrated, the width d2 of the insulating opening is in the relationship of VCSEL 2B > VCSEL 2Aa4 > VCSEL 2Aa3 > VCSEL 2Aa2 > VCSEL 2Aa1 > VCSEL 2A. That is, as the distance from the anode power supply pad 102 becomes closer, the width d2 of the insulating opening becomes smaller. Therefore, the resistance values are in the relationship of VCSEL 2A > VCSEL 2Aa1 > VCSEL 2Aa2 > VCSEL 2Aa3 > VCSEL 2Aa4 > VCSEL 2B, and the resistance values of the VCSELs in the group closer to the anode power supply pad 102 become larger. This enables fine adjustment of the resistance values of the respective VCSELs 2 in a graded manner. As a result, compared with the current distribution L5 in the VCSEL array 100B ( Figure 13 ), the VCSEL array 100C can reduce the ratio between the maximum value and the minimum value of the current flowing through each VCSEL 2, and can further smooth the current distribution ( Figure 13 the current distribution L6).

[0111] [Fifth Embodiment]

[0112] Next, the VCSEL array 100D according to the fifth embodiment will be described. The VCSEL array 100D has short high-peak pulse characteristics suitable for LiDAR. A structure using a saturable absorption layer or the like (hereinafter, also referred to as "high-peak VCSEL") is known. The problems peculiar to the high-peak VCSEL can be solved by combining the structure of the high-peak VCSEL with a structure that makes the current value more uniform.

[0113] The high-peak VCSEL is characterized in that it can output an optical pulse having a pulse width of about several hundred ps and a high peak at the start of oscillation, and this is effective in increasing the ranging distance and ranging accuracy of the LiDAR system.

[0114] On the other hand, the high-peak VCSEL is characterized in that the timing of generating a pulse at the start of oscillation varies according to the current density. Figure 16 is a graph illustrating the relationship between the current density and the pulse generation timing. In Figure 16 , the vertical axis represents the light intensity, and the horizontal axis represents the time. Figure 17 is a graph illustrating the relationship between the current density and the pulse delay time. In Figure 17 , the vertical axis represents the pulse delay time, and the horizontal axis represents the current density. As Figure 16 and Figure 17 illustrate, a pulse generation timing shift of 1.27 ns is generated at a current density of 21 to 29 kA / cm 2 .

[0115] Therefore, in the case of arranging a plurality of high-peak VCSELs, when the current injected into each high-peak VCSEL becomes uneven, the light emission timings of the respective high-peak VCSELs are different. Therefore, the temporal variation of the light intensity of the entire array becomes wider than the pulse width of the high-peak VCSEL, and there is a problem that the advantages of the LiDAR system are reduced.

[0116] Therefore, making the current more uniform makes it possible to suppress the deviation of the oscillation start timing in the VCSEL array when arranging the high-peak VCSELs. In addition, an increase in the width of the optical pulse when combining the light from each VCSEL through an optical system or the like can be suppressed.

[0117] Figure 19 is a cross-sectional view illustrating a structural example of the high-peak VCSEL 3A according to the fifth embodiment, and for example, is Figure 18Cross-sectional view of V1-V1. In the high-peak VCSEL 3A according to the fifth embodiment, components that are the same as those of the VCSEL 2A according to the fourth embodiment are denoted by the same reference numerals, and their detailed description will be omitted. The high-peak VCSEL 3A is different from the VCSEL 2A in that the barrier layer sandwiching the quantum well layer 31 is made of a GaAs layer. In addition, the high-peak VCSEL 3A is different from the VCSEL 2A in that the high-peak VCSEL 3A has a spacer layer 110 including a saturable absorption layer 111. The spacer layer 110 is provided in the first DBR 20 (in the first reflector). With this structure, the high-peak VCSEL 3A can emit optical pulses having a short high peak. In the fifth embodiment, the width d2 of the insulating opening of the high-peak VCSEL 3A is 10.4 μm, and the width d2 of the insulating opening of the high-peak VCSEL 3B is 16.8 μm. As a result, the high-peak VCSEL 3A has a higher resistance value compared to the resistance value of the high-peak VCSEL 3B.

[0118] Figure 18 is a plan view illustrating a structural example of the VCSEL array 100D according to the fifth embodiment. A plurality of VCSELs 3 are divided into two groups (a first group and a second group) according to the distance from the anode power supply pad 102. The VCSEL array 100D is configured such that the VCSELs in the group closer to the anode power supply pad 102 have a higher resistance value. Specifically, the VCSELs in the first group, which are closer to the anode power supply pad 102, are composed of high-peak VCSELs 3A, and the VCSELs in the second group, which are farther from the anode power supply pad 102, are composed of high-peak VCSELs 3B. More specifically, the VCSELs in the first group of the first to fifth VCSELs closer to the anode power supply pad 102 are composed of high-peak VCSELs 3A, and the VCSELs in the second group of the remaining sixth to twentieth VCSELs are composed of high-peak VCSELs 3B.

[0119] With this structure, the current injected into the high-peak VCSEL 3A and the high-peak VCSEL 3B can be made more uniform, and the deviation in the emission timing of the high-peak VCSEL 3A and the high-peak VCSEL 3B can be suppressed. By arranging them, the light output can be increased, and pulses having a high peak of about several hundred ps generated by the high-peak VCSEL 3A and the high-peak VCSEL 3B can be appropriately used. Here, the current value injected into one array is adjusted so that the minimum current density becomes 20 kA / cm 2 or more. In this case, in a comparative example in which one array is composed of all the same high-peak VCSELs 3B, the maximum current density is 25.1 kA / cm 2, and the pulse delay time difference in one array is 1.07 ns. In contrast, in the VCSEL array 100D according to the fifth embodiment, since one array is composed of the high-peak VCSEL 3A and the high-peak VCSEL 3B, the maximum current density is 23.3 kA / cm 2 , and the pulse delay time difference in one array can be suppressed to 0.76 ns.

[0120] [Sixth Embodiment]

[0121] Next, the VCSEL array 100E according to the sixth embodiment will be described. Figure 20 is a plan view illustrating a structural example of the VCSEL array 100E according to the sixth embodiment. The VCSEL array 100E according to the sixth embodiment includes VCSELs 4A and 4B different from the VCSEL 1A etc. according to the first to fifth embodiments. Hereinafter, the VCSELs 4A and 4B will be described in detail. In the following description, components that are the same as those of the VCSEL 1A etc. according to the first to fifth embodiments are denoted by the same reference numerals, and their detailed description will be omitted.

[0122] For example, as Figure 20 illustrated, the VCSEL array 100E includes a plurality of VCSELs 4, anode wirings 101, and anode power supply pads 102. Note that Figure 20 illustrates four VCSELs 4 on one side in the Y direction and three VCSELs 4 on the other side in the Y direction among the plurality of VCSELs 4 connected to each anode wiring 101.

[0123] Twenty VCSELs 4 are arranged in a row in the Y direction, and twenty bundles arranged in the Y direction are arranged in the X direction. As a result, a total of four hundred (20×20) VCSELs 4 are arranged in an array, and the whole has a rectangular shape when viewed from the Z direction.

[0124] The anode wirings 101 extend in the Y direction and are arranged in the X direction. One anode wiring 101 is electrically connected to twenty VCSELs 4 in the Y direction. Then, twenty such anode wirings 101 are arranged side by side in the X direction. Each anode wiring 101 supplies current to the twenty VCSELs 4 connected in parallel.

[0125] The VCSEL array 100B configured as described above can cause the four hundred VCSELs 4 to emit light by supplying current from the outside to the twenty anode power supply pads 102 via Au wirings. By sequentially supplying current to the twenty anode power supply pads 102 from the outside, sequential driving in which each column emits light at different timings can be performed.

[0126] Here, the VCSEL array 100E according to the sixth embodiment includes VCSEL 4A and VCSEL 4B as a plurality of VCSELs 4. In the following description, when it is not necessary to distinguish VCSEL 4A and VCSEL 4B from each other, VCSEL 4A and VCSEL 4B may be simply referred to as "VCSEL 4".

[0127] As Figure 21B illustrated, VCSEL 4B includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper electrode 60, and a back electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. In VCSEL 4B, the semiconductor resonator 30 and the second DBR 40 are processed into a mesa shape. Although these components are in direct contact with each other in Figure 21B , other components may be provided between these components in VCSEL 4B. In addition, the above description is an explanation of the structure and does not limit the order of manufacturing each component. Figure 21B is a cross-sectional view along Figure 20 the line V2-V2.

[0128] Next, VCSEL 4A will be described. VCSEL 4A is configured similarly to the above-described VCSEL 4B. That is, as Figure 21A illustrated, VCSEL 4A includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper electrode 60, and a back electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. In VCSEL 4A, the semiconductor resonator 30 and the second DBR 40 are processed into a mesa shape. Figure 21A is a cross-sectional view along Figure 20 the line V1-V1.

[0129] The size of the mesa of VCSEL 4A is smaller than the size of the mesa of VCSEL 4B. That is, the width d2 of the mesa of VCSEL 4A is narrower than the width d4 of the mesa of VCSEL 4B. Thus, as Figure 21AAs illustrated, the width d1 of the non-oxidized region of the current confinement layer 41 of VCSEL 4A is narrower than the width d3 of the non-oxidized region of the current confinement layer 41 of VCSEL 4B. This is because when oxidation is performed in the same manner on the same wafer, the oxidation distance with respect to the mesa end becomes substantially the same. Since the current path in the mesa is narrowed by the non-oxidized region of the current confinement layer 41, the current path can be narrowed by making the non-oxidized region of VCSEL 4A smaller than that of VCSEL 4B, and the resistance value of VCSEL 4A can be made greater than that of VCSEL 4B.

[0130] Figure 22 is a graph illustrating the relationship between the area of the non-oxidized region of the current confinement layer 41 and the resistance value. In Figure 22 the horizontal axis indicates the area of the non-oxidized region of the current confinement layer 41, and the vertical axis indicates the relative resistance value, where for the case where the area of the non-oxidized region of the current confinement layer 41 is 300 μm 2 the resistance value can be 1.0. The width d3 of the non-oxidized region of VCSEL 4B is 17.3 μm, that is, the area of the non-oxidized region is approximately 300 μm 2 and the width d1 of the non-oxidized region of VCSEL 4A is 15.1 μm, that is, the area of the non-oxidized region is approximately 227 μm 2 . In this case, the resistance value of VCSEL 4A is 1.27 times that of VCSEL 4B.

[0131] The plurality of VCSELs 4 are divided into two groups (a first group and a second group) according to the distance from the anode power supply pad 102. The VCSEL array 100E is configured such that the VCSELs in the group closer to the anode power supply pad 102 have a higher resistance value. Specifically, VCSEL 4A constitutes the VCSELs of the first group with a short distance from the anode power supply pad 102, and VCSEL 4B constitutes the VCSELs of the second group with a long distance from the anode power supply pad 102. More specifically, as Figure 20 illustrated, the first to seventh VCSELs of the first group closer to the anode power supply pad 102 are constituted by VCSEL 4A with a large resistance value. The remaining eighth to twentieth VCSELs of the second group are constituted by VCSEL 4B with a small resistance value.

[0132] With this structure, the current distribution of the VCSEL array 100E becomes similar to Figure 5 the current distribution L2 illustrated. Compared with the case where the array is constituted by VCSEL 4B as in the comparative example ( Figure 5As compared with the illustrated current distribution L1), the current distribution of the VCSEL array 100E can be smoothed. In addition, by smoothing the current distribution, the amount of current required for the VCSEL array 100E can be reduced, and the input power can also be reduced.

[0133] [Seventh Embodiment]

[0134] Next, the VCSEL array 100F according to the seventh embodiment will be described. As Figure 23 illustrated, the VCSEL array 100F according to the seventh embodiment includes three types of VCSELs 4A, 4Aa, and 4B having different resistance values.

[0135] In the seventh embodiment, the width of the non-oxidized region of the VCSEL 4B is 17.3 μm, and the area of the non-oxidized region is 300 μm 2 . The width of the non-oxidized region of the VCSEL 4A is 14.2 μm, and the area of the non-oxidized region is 203 μm 2 . The width of the non-oxidized region of the VCSEL 4Aa is 15.8 μm, and the area of the non-oxidized region is 250 μm 2 . Therefore, the resistance value of the VCSEL 4A becomes 1.40 times the resistance value of the VCSEL 4B, and the resistance value of the VCSEL 4Aa becomes 1.17 times the resistance value of the VCSEL 4B.

[0136] A plurality of VCSELs 4 are divided into three groups (first group to third group) according to the distance from the anode power supply pad 102. The VCSEL array 100F is configured such that the VCSELs in the group closer to the anode power supply pad 102 have a higher resistance value. Specifically, as Figure 23 illustrated, the first to fourth VCSELs in the first group closer to the anode power supply pad 102 are composed of the VCSEL 4A having the maximum resistance value. The fifth to ninth VCSELs in the third group are composed of the VCSEL 4Aa having the second largest resistance value, and the tenth to twentieth VCSELs in the second group are composed of the VCSEL 4B having the minimum resistance value.

[0137] In this case, the current distribution of the VCSEL array 100F according to the seventh embodiment has substantially the same tendency as the current distribution L3 (see Figure 5 ). As in the comparative example, compared with the case where the array is composed of the VCSEL 4B ( Figure 5Compared with the current distribution L1) in [it], the current distribution of the VCSEL array 100F can be smoothed. Additionally, by smoothing the current distribution, the amount of current required for the VCSEL array 100F is reduced, and the input power is also reduced. As described above, in the VCSEL array 100F, by increasing the types of resistance values of the VCSELs and appropriately setting the magnification and arrangement of each resistance value, it is possible to smooth the current distribution and reduce the input power.

[0138] [Eighth Embodiment]

[0139] Next, a VCSEL array (not illustrated) according to the eighth embodiment will be described. The VCSEL array according to the eighth embodiment has the following structure: the width of the non-oxidized region of the VCSEL 4 is set in more levels, and the resistance value of the VCSEL 4 is changed step by step. Figure 24 is a table illustrating the relationship between the non-oxidized region and the resistance value of each VCSEL 4. The plurality of VCSELs 4 are divided into 14 groups (the first group to the fourteenth group) according to the distance from the anode power supply pad 102. The VCSEL array is configured such that the VCSELs in the group closer to the anode power supply pad 102 have higher resistance values. Specifically, as Figure 24 illustrated, 14 types of VCSELs 4 are arranged for each group such that the resistance value of the VCSEL 4 gradually increases toward the anode power supply pad 102. In the VCSEL array, for example, the maximum magnification of the resistance value can be 1.53 times, and the width of the non-oxidized region can be 13.5 μm.

[0140] Figure 25 is a graph illustrating the current distribution in the VCSEL array. Figure 25 Illustrates the current distribution L8 of one array in the VCSEL array according to the eighth embodiment. Figure 25 Also illustrates the current distribution L7 of one array in the VCSEL array according to the comparative example. In the VCSEL array according to the comparative example, all the VCSELs (four hundred VCSELs) are VCSEL 4 and are arranged in an array. As Figure 25 illustrated, the ratio of the maximum value to the minimum value of the current flowing through each VCSEL 4 in the VCSEL array is 0.97 ( Figure 25 in the current distribution L8), which indicates that compared with the VCSEL array according to the comparative example ( Figure 25 in the current distribution L7), the current distribution can be smoothed.

[0141] In addition, according to the VCSEL array, various types of VCSELs can be manufactured simultaneously by simply changing the width of the mesa of the VCSEL 4 on the photomask during the manufacturing process. In addition, compared with the change amount of the resistance value of the VCSEL array 100B of the third embodiment, the change amount of the resistance value of the VCSEL array can be increased. In the VCSEL array, by appropriately increasing the type of resistance value compared with the example illustrated by Figure 24 it is possible to make the ratio between the maximum value and the minimum value closer to 1.

[0142] Since the VCSEL array changes the width of the non-oxidized region, the oscillation mode, FFP (far-field pattern), and current density distribution may affect the assumed usage conditions. In such a case, it is desirable to adopt a method of suppressing the change of the non-oxidized region to a small value by combining with other embodiments. In this case, instead of defining the resistance value based on the length of the current path starting from the anode power supply pad 102, it is conceivable to define the resistance value of the VCSEL based on the actual current value applied to the VCSEL. Specifically, by arranging VCSELs with a high resistance value in a place with a high current value, the current distribution of the entire array can be made smoother.

[0143] [Ninth Embodiment]

[0144] Next, the VCSEL array 100H according to the ninth embodiment will be described. Figure 26 is a plan view illustrating a structural example of the VCSEL array 100H according to the ninth embodiment. The VCSEL array 100H according to the ninth embodiment includes VCSELs 5A and 5B that are different from the VCSEL 1A etc. according to the first to eighth embodiments. Hereinafter, the VCSEL 5A and the VCSEL 5B will be described in detail. In the following description, components that are the same as those of the VCSEL 1A etc. according to the first to eighth embodiments are denoted by the same reference numerals, and their detailed description will be omitted.

[0145] For example, as Figure 26 illustrated, the VCSEL array 100H includes a plurality of VCSELs 5, anode wirings 101, and an anode power supply pad 102. Note that Figure 26 illustrates four VCSELs 5 on one side in the Y direction and three VCSELs 5 on the other side in the Y direction among the plurality of VCSELs 5 connected to each anode wiring 101.

[0146] Twenty VCSELs 5 are arranged in a column in the Y direction, and twenty bundles arranged in the Y direction are arranged in the X direction. As a result, a total of four hundred (20×20) VCSELs 5 are arranged in an array, and the whole has a rectangular shape when viewed from the Z direction.

[0147] The anode wiring 101 extends in the Y direction and is arranged in the X direction. One anode wiring 101 is electrically connected to twenty VCSELs 5 in the Y direction. Then, twenty such anode wirings 101 are arranged side by side in the X direction. Each anode wiring 101 supplies current to the twenty VCSELs 5 connected in parallel.

[0148] The VCSEL array 100H configured as described above can cause four hundred VCSELs 5 to emit light by supplying current to the twenty anode power supply pads 102 from the outside via the Au wiring. By sequentially supplying current to the twenty anode power supply pads 102 from the outside, sequential driving in which each column emits light at different timings can be performed.

[0149] Here, the VCSEL array 100H according to the ninth embodiment includes VCSEL 5A and VCSEL 5B as a plurality of VCSELs 5. In the following description, when it is not necessary to distinguish between VCSEL 5A and VCSEL 5B from each other, VCSEL 5A and VCSEL 5B can be simply referred to as "VCSEL 5".

[0150] As Figure 27B illustrated, the VCSEL 5B includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper electrode 60, and a back electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. Although these members are in direct contact with each other in Figure 27B these members, other members can be provided between these members in the VCSEL 5B. In addition, the above description is a description of the structure and does not limit the order of manufacturing each member. Figure 27B is a cross-sectional view along Figure 26 the line V2-V2.

[0151] Next, the VCSEL 5A will be described. The VCSEL 5A is different from the VCSEL 5B in that the VCSEL 5A has a proton implantation region 120 and has the same structure as the VCSEL 5B in other respects. That is, as Figure 27AIllustratively, the VCSEL 5A includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper electrode 60, and a back electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. Figure 27A is a cross-sectional view along Figure 26 the line V1-V1.

[0152] In the ninth embodiment, a proton implantation region 120 is provided as a component for changing the resistance value. The proton implantation region 120 is provided in a part of the second DBR 40 of the VCSEL 5A. As a result, the VCSEL 5A can reduce the carrier density in the second DBR 40 in the current path flowing from the upper electrode 60 to the current confinement layer 41, and thus can increase the resistance value compared to the VCSEL 5B.

[0153] The proton implantation region 120 can be formed by a conventional method. Here, as described in the third embodiment, in the VCSEL 2 including an ITO layer 90 in the upper part, since the current path is close to the center of the mesa, when the proton implantation region 120 is provided in such a structure, the resistance value can be increased efficiently. In the ninth embodiment, since the light absorption rate of the second DBR 40 is also changed by implanting protons into the proton implantation region 120, the extraction efficiency is changed. Therefore, when it is desired to smooth the light quantity distribution in the array, it is desirable to design the arrangement of the VCSELs in the array considering not only the current distribution but also the light quantity distribution.

[0154] Thus, the VCSEL 5A has a proton implantation region 120 in the second DBR 40, while the VCSEL 5B does not have a proton implantation region 120 in the second DBR 40. With this structure, the VCSEL 5A and the VCSEL 5B have different resistance values between the upper electrode 60 and the back electrode 70. When the resistance value between the upper electrode 60 and the back electrode 70 of the VCSEL 5A is R1 and the resistance value between the upper electrode 60 and the back electrode 70 of the VCSEL 5B is R2, R1 > R2. That is, since the VCSEL 5A has a proton implantation region 120, the resistance value is larger than that of the VCSEL 5B.

[0155] Multiple VCSELs 5 are divided into two groups (a first group and a second group) according to the distance from the anode power supply pad 102. The VCSEL array 100H is configured such that the VCSELs in the group closer to the anode power supply pad 102 have a higher resistance. Specifically, the VCSEL 5A constitutes the VCSELs of the first group with a short distance from the anode power supply pad 102, and the VCSEL 5B constitutes the VCSELs of the second group with a long distance from the anode power supply pad 102. More specifically, as Figure 26 illustrated, the first to fifth VCSELs of the first group closer to the anode power supply pad 102 are constituted by the VCSEL 5A with a large resistance value. The remaining sixth to twentieth VCSELs of the second group are constituted by the VCSEL 5B with a small resistance value. The VCSEL array 100H can make the current injected into the VCSEL 5A and the VCSEL 5B more uniform by designing the arrangement of the two types of VCSELs 5A and 5B with different resistance values.

[0156] [Tenth Embodiment]

[0157] Next, an example of applying the VCSEL array 100 to the SWIR (short-wave infrared region) band will be described. Figure 28 is a cross-sectional view illustrating a structural example of the VCSEL array 100M according to the tenth embodiment.

[0158] The VCSEL array 100M includes the VCSEL array 100 of the first embodiment and the VCSEL chip 200, and has a structure in which the VCSEL chip 200 is bonded to the VCSEL array 100.

[0159] The VCSEL chip 200 oscillates by optical excitation, and as Figure 28 illustrated, includes a lower reflector 201 as a third reflector and a semiconductor resonator 202 as a second semiconductor resonator including a second active layer. In addition, the VCSEL chip 200 includes an upper reflector 203 as a fourth reflector, an InP substrate 206, and an AR (antireflection) coating 207. In the VCSEL chip 200, the lower reflector 201, the semiconductor resonator 202, the upper reflector 203, the InP substrate 206, and the AR coating 207 are stacked on the VCSEL array 100 in this order. The lower reflector 201 is composed of an SiO 2 layer with an optical film thickness of 1 / 4λc and TiO 2It is composed of seven pairs of alternating laminations of layers. The semiconductor resonator 202 includes an InGaAsP optical absorption layer 204 and five quantum well layers 205 (only one layer is illustrated) made of 8-nm-thick InGaAs. The quantum well layers 205 are excited by light of the first wavelength emitted from the VCSEL array 100. The upper reflector 203 is composed of an alternating lamination of InP / InGaAsP with an optical film thickness of 1 / 4λc. The upper reflector 203 is configured to have a lower reflectivity than the lower reflector 201. Therefore, the light of the second wavelength oscillated by the VCSEL chip 200 is extracted through the InP substrate 206. The AR coating 207 prevents reflection. Note that the light of the second wavelength is light having a wavelength different from that of the light of the first wavelength.

[0160] The VCSEL array 100 emits light having a wavelength of, for example, 940 nm to the VCSEL chip 200, and the light emitted to the VCSEL chip 200 passes through the lower reflector 201 and is absorbed by the InGaAsP optical absorption layer 204 in the semiconductor resonator 202. The absorbed light generates electrons and holes, and these electrons and holes enter the quantum well layers 205 and reach a density exceeding the transparent carrier density, which results in gain. In this way, the VCSEL array 100M generates laser oscillation in the VCSEL chip 200 and emits laser light having a wavelength band of 1550 nm.

[0161] In the VCSEL array 100M, the portion that emits light at a wavelength of 1550 nm can be selected by selecting the anode wiring 101 to be energized from among the plurality of anode wirings 101 forming the VCSEL array 100. In addition, with a structure that smooths the current distribution of the VCSEL array 100, it is possible to minimize the space used for the wiring between the VCSEL 1A and the VCSEL 1B while smoothing the light emission intensity distribution of the VCSEL 1A and the VCSEL 1B forming the VCSEL array 100. Thus, the VCSEL array 100M can reduce the chip size. The reduction in the chip size not only results in a reduction in the chip cost but also leads to the miniaturization of the optical system including the lens and a reduction in its cost.

[0162] The VCSEL chip 200 on the side excited by light having a wavelength of 940 nm is a VCSEL having a wavelength of 1550 nm, but is not limited thereto. For example, an LED or a VCSEL array that is excited by light having a wavelength of 940 nm and emits light in a wavelength band of 1900 nm can be used.

[0163] Although the VCSEL array 100 according to the first embodiment is used as the VCSEL array to be excited, the structures according to the second to tenth embodiments have the same effect. In any case, this makes it possible to minimize the wiring space and reduce the size of the VCSEL chip.

[0164] [Eleventh Embodiment]

[0165] Next, the distance measuring device 300 according to the eleventh embodiment will be described. The distance measuring device 300 is, for example, a LiDAR that uses the VCSEL array 100 or the like according to the first embodiment as a light source unit.

[0166] As Figure 29 illustrated, the distance measuring device 300 includes an overall control unit 310, a surface emitting laser array driver 320, a surface emitting laser array 330, an optical system 340, an optical system 350, an image sensor 360, and a distance data processing unit 370.

[0167] The overall control unit 310 is constituted by an information processing device including a microcomputer and a logic circuit or the like, and has a function as a central processing unit that manages operations in the distance measuring device 300, such as operation control of each unit and various arithmetic processes.

[0168] The surface emitting laser array driver 320 is a driving unit that receives a driving signal from the overall control unit 310, generates a driving current for causing the surface emitting laser array 330 to oscillate, and outputs the driving current to the surface emitting laser array 330.

[0169] The surface emitting laser array 330 is constituted by mounting the VCSEL array described in the first to tenth embodiments in a package.

[0170] The optical system 340 is an optical system that emits the laser generated by the surface emitting laser array 330 toward the range to be measured.

[0171] The optical system 350 is an optical system that guides the laser reflected by the measurement object OJ included in the range to be distance - measured to the imaging element 360. Although in Figure 29 the optical system 340 and the optical system 350 are represented by a single convex - lens - shaped member, they are not constituted by only one convex - lens system, but by a lens group combining a plurality of lenses.

[0172] The image sensor 360 is, for example, a light - receiving device in which CMOS (Complementary Metal Oxide Semiconductor) optical sensors are arranged in an array. The image sensor 360 may be a light - receiving device in which SPAD (Single Photon Avalanche Diode) optical sensors are arranged in an array.

[0173] The distance data processing unit 370 functions as a distance information acquisition unit that generates information related to the distance to the measurement object OJ existing within the distance measurement target range based on the signal from the imaging element 360, and outputs the generated information. The distance data processing unit 370 acquires information related to the distance to the measurement object OJ, for example, based on the time difference between the timing of emitting light from the surface emitting laser array 330 and the timing of receiving light by the image sensor 360. The distance data processing unit 370 can be electrically connected to the image sensor 360, and can be configured in the same package as the image sensor 360 or in a different package from the image sensor 360.

[0174] Next, the operation of the distance measuring device 300 will be described. First, a drive signal is output from the overall control unit 310 to the surface emitting laser array driver 320. When receiving the drive signal, the surface emitting laser array driver 320 outputs a drive current of a predetermined current value to the surface emitting laser array 330 to cause the surface emitting laser array 330 to oscillate. The laser generated by the surface emitting laser array 330 is emitted toward the measurement object OJ via the optical system 340, and the light reflected by the measurement object OJ is incident on the image sensor 360 via the optical system 350. The image sensor 360 converts the optical signal of the incident light into an electrical signal, and outputs the converted electrical signal to the distance data processing unit 370. The distance data processing unit 370 calculates distance information based on the time difference between the timing of emitting light from the surface emitting laser array 330 and the timing of receiving light by the image sensor 360, and generates three-dimensional information based on the distance information.

[0175] The distance data processing unit 370 outputs the generated three-dimensional information to the overall control unit 310.

[0176] In the automotive field, the distance measuring device 300 is applicable to controls such as not colliding with other vehicles and following other vehicles for autonomous driving control. In addition, the distance measuring device 300 can be used in moving bodies (mobile devices) and mobile body detection systems such as ships, airplanes, or industrial robots. In addition, the distance measuring device 300 can be widely applied to devices that identify objects in a three-dimensional manner with distance information.

[0177] In addition, by using three-dimensional information with depth, the distance measuring device 300 can display virtual objects in the real world without discomfort in a camera device, an image processing device, and a display device. In addition, the distance measuring device 300 can also be applied to a device that stores three-dimensional information together with image information and has a function of correcting blurring, etc. in the captured image after shooting.

[0178] [Modified Embodiment]

[0179] The present invention is not limited to the above embodiments and can be variously modified. For example, an example in which a part of the structure of any embodiment is added to another embodiment or an example in which a part of the structure of another embodiment is replaced by another embodiment is also an embodiment of the present invention.

[0180] For example, a semiconductor layer 80 and a proton implantation region 120 can be further provided for the VCSEL 2A including the ITO layer 90, or a semiconductor layer 80 and a proton implantation region 120 can be provided for the high-peak VCSEL 3A. Additionally, a semiconductor layer 80 and a proton implantation region 120 can be provided for the VCSEL 4A having different widths of non-oxidized regions of the current limiting layer 41, or a semiconductor layer 80 can be further provided for the VCSEL 5A including the proton implantation region 120.

[0181] In this way, the means for changing the resistance value can be appropriately combined. Thus, the number of types of resistance of the VCSELs in the VCSEL array can be increased, and the current distribution can be further smoothed.

[0182] Furthermore, a semiconductor layer 80 can be further provided for the VCSEL 3A and the VCSEL 3B having different widths of non-oxidized regions of the current limiting layer 41, or a semiconductor layer 80 can be further provided for the high-peak VCSEL 3A. Thus, the number of types of resistance of the VCSELs in the VCSEL array can be increased, and the current distribution can be further smoothed.

[0183] The plurality of VCSELs can include at least two types of VCSELs among the VCSEL 1A, VCSEL 2A, VCSEL 3A, VCSEL 4A, and VCSEL 5A.

[0184] The VCSEL 1A includes a semiconductor layer 80 between the upper electrode 60 and the second DBR 40, and the VCSEL 1B does not include a semiconductor layer 80 between the upper electrode 60 and the second DBR 40, but the structure is not limited to these examples. For example, each of the VCSEL 1A and the VCSEL 1B can have a semiconductor layer 80 between the upper electrode 60 and the second DBR 40, and the film thickness of the semiconductor layer 80 of the VCSEL 1A can be thicker than the film thickness of the semiconductor layer 80 of the VCSEL 1B.

[0185] Although an example in which the VCSEL array includes four hundred VCSELs is described, the number of VCSELs is not limited to this and can be other numbers.

[0186] In addition, in each embodiment, a sequential anode wiring structure in which an array that emits light simultaneously is arranged in each column has been described, but the present invention is not limited thereto. For example, the present invention can be similarly applied to a case where an array that emits light simultaneously is arranged in every two columns, every three columns, every four columns, or more than four columns. In addition, the present invention can be similarly applied to, for example, a flash-type anode wiring structure in which the entire surface emits light simultaneously. Specifically, for example, in a case where twenty arrays are arranged in the Y direction and twenty arrays are arranged in the X direction, and the anode wiring is uniformly connected to all the arrays, the current injection amount at the center of the VCSEL array tends to be smaller than that at the outer side. Even in such a structure, when the resistance value of the VCSEL on the side closer to the anode power supply pad 102 in the current path is R1 and the resistance value of the VCSEL on the side farther from the anode power supply pad is R2, the first to tenth embodiments are appropriately applied individually or in combination so that R1 > R2. Therefore, this enables the current distribution to be smoothed over the entire array. In addition, the current distribution can be further smoothed by increasing the types of resistors and appropriately arranging the VCSELs.

[0187] In addition, although the current limiting structure has been described by taking, as an example, an oxidation confinement layer formed by selectively oxidizing a part of the semiconductor layer, the current limiting structure is not limited thereto. The current limiting structure can be formed by other methods such as ion implantation.

[0188] Although an example in which a proton implantation region 120 is provided in the second DBR 40 which is a P-type semiconductor has been described, the present invention is not limited thereto. For example, instead of protons, donor impurities having a hole compensation effect can be ion implanted. When the second DBR 40 is an N-type semiconductor, acceptor impurities having an electron compensation effect can be ion implanted instead of protons.

[0189] In addition, in the VCSEL 4A and the VCSEL 4B, an example in which both the semiconductor resonator 30 and the second DBR 40 are processed into a mesa shape has been described, but the present invention is not limited thereto, and at least the second DBR 40 can be processed into a mesa shape.

[0190] The disclosure of the above embodiments includes the following structures.

[0191] [Structure 1]

[0192] A light source device, comprising:

[0193] a plurality of semiconductor light emitting elements, which are configured to sequentially stack a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on a first surface side of a semiconductor substrate, and stack a second electrode on a second surface of the semiconductor substrate opposite to the first surface;

[0194] A power supply pad configured to supply power to the plurality of semiconductor light-emitting elements; and

[0195] Wiring configured to connect each of the plurality of semiconductor light-emitting elements to the power supply pad,

[0196] wherein the plurality of semiconductor light-emitting elements are divided into a plurality of groups according to the distance from the power supply pad, and each of the plurality of groups includes at least one semiconductor light-emitting element, and

[0197] wherein the semiconductor light-emitting elements in the group with a shorter distance from the power supply pad are configured to have a larger resistance value between the first electrode and the second electrode.

[0198] [Structure 2]

[0199] A light source device, comprising:

[0200] A plurality of semiconductor light-emitting elements configured to sequentially stack a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on a first surface side of a semiconductor substrate, and stack a second electrode on a second surface of the semiconductor substrate opposite to the first surface;

[0201] A power supply pad configured to supply power to the plurality of semiconductor light-emitting elements; and

[0202] Wiring configured to connect each of the plurality of semiconductor light-emitting elements to the power supply pad,

[0203] wherein the plurality of semiconductor light-emitting elements are divided into a plurality of groups according to the length of the current path of the wiring starting from the power supply pad, and each of the plurality of groups includes at least one semiconductor light-emitting element, and

[0204] wherein the semiconductor light-emitting elements in the group with a shorter length of the current path of the wiring starting from the power supply pad are configured to have a larger resistance value between the first electrode and the second electrode.

[0205] [Structure 3]

[0206] The light source device according to Structure 1 or 2, wherein the plurality of groups include a first group and a second group, and the resistance value of the semiconductor light-emitting elements included in the second group is smaller than that of the semiconductor light-emitting elements in the first group.

[0207] [Structure 4]

[0208] The light source device according to Structure 3,

[0209] Among them, the multiple groups include the first group, the second group, and the third group. The resistance value of the semiconductor light-emitting elements included in the third group is smaller than that of the semiconductor light-emitting elements in the first group and larger than that of the semiconductor light-emitting elements in the second group, and

[0210] Among them, the third group is arranged between the first group and the second group.

[0211] [Structure 5]

[0212] The light source device according to any one of Structures 1 to 4, wherein the multiple semiconductor light-emitting elements include a transparent conductive film between the first electrode and the second reflector.

[0213] [Structure 6]

[0214] The light source device according to any one of Structures 1 to 5, wherein the multiple semiconductor light-emitting elements include a saturable absorption layer in the first reflector.

[0215] [Structure 7]

[0216] The light source device according to Structure 3 or 4, wherein the semiconductor light-emitting elements in the first group are formed such that the distance between the first electrode and the second electrode is longer than that between the first electrode and the second electrode of the semiconductor light-emitting elements in the second group, and since the distance between the first electrode and the second electrode of the semiconductor light-emitting elements in the first group is longer than that between the first electrode and the second electrode of the semiconductor light-emitting elements in the second group, the resistance value between the first electrode and the second electrode of the semiconductor light-emitting elements in the first group is larger than that between the first electrode and the second electrode of the semiconductor light-emitting elements in the second group.

[0217] [Structure 8]

[0218] The light source device according to Structure 5, wherein the contact area between the transparent conductive film and the second reflector of the semiconductor light-emitting elements in the first group among the multiple groups is smaller than the contact area between the transparent conductive film and the second reflector of the semiconductor light-emitting elements in the second group among the multiple groups.

[0219] [Structure 9]

[0220] The light source device according to Structure 3, 4, 7, or 8, wherein at least the second reflector of the multiple semiconductor light-emitting elements is in a mesa shape, and the width of the second reflector of the semiconductor light-emitting elements in the first group is narrower than the width of the second reflector of the semiconductor light-emitting elements in the second group.

[0221] [Structure 10]

[0222] The light source device according to Structure 3, 4, 7 or 8, wherein the semiconductor light-emitting elements of the first group include a proton implantation region in the second reflector, and by including the proton implantation region, the resistance value between the first electrode and the second electrode of the semiconductor light-emitting elements of the first group is larger than the resistance value between the first electrode and the second electrode of the semiconductor light-emitting elements of the second group.

[0223] [Structure 11]

[0224] The light source device according to any one of Structures 1 to 10,

[0225] wherein the plurality of semiconductor light-emitting elements sequentially stack a third reflector, a second semiconductor resonator including a second active layer, and a fourth reflector on a side of the second reflector opposite to the first semiconductor resonator, and

[0226] wherein the second active layer is excited by light of a first wavelength emitted from the plurality of semiconductor light-emitting elements and emits light of a second wavelength different from the first wavelength.

[0227] [Structure 12]

[0228] A light source device, comprising:

[0229] A plurality of semiconductor light-emitting elements configured to sequentially stack a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on a first surface side of a semiconductor substrate, and stack a second electrode on a second surface of the semiconductor substrate opposite to the first surface;

[0230] A power supply pad configured to supply power to the plurality of semiconductor light-emitting elements; and

[0231] A wiring configured to connect each of the semiconductor light-emitting elements among the plurality of semiconductor light-emitting elements to the power supply pad,

[0232] wherein the plurality of semiconductor light-emitting elements are divided into a plurality of groups according to the resistance of the wiring starting from the power supply pad, and each of the plurality of groups includes at least one semiconductor light-emitting element, and

[0233] wherein the semiconductor light-emitting elements in the group with a smaller resistance of the wiring starting from the power supply pad are configured to have a larger resistance value between the first electrode and the second electrode.

[0234] [Structure 13]

[0235] The light source device according to Structure 5, wherein the plurality of semiconductor light-emitting elements include a saturable absorption layer in the first reflector.

[0236] [Structure 14]

[0237] The light source device according to Structure 13,

[0238] wherein the plurality of groups include a first group and a second group, the resistance value of the semiconductor light-emitting elements included in the second group is smaller than the resistance value of the semiconductor light-emitting elements in the first group, and

[0239] wherein the semiconductor light-emitting elements in the first group are formed such that the distance between the first electrode and the second electrode is longer than the distance between the first electrode and the second electrode of the semiconductor light-emitting elements in the second group, and since the distance between the first electrode and the second electrode of the semiconductor light-emitting elements in the first group is longer than the distance between the first electrode and the second electrode of the semiconductor light-emitting elements in the second group, the resistance value between the first electrode and the second electrode of the semiconductor light-emitting elements in the first group is larger than the resistance value between the first electrode and the second electrode of the semiconductor light-emitting elements in the second group.

[0240] [Structure 15]

[0241] The light source device according to Structure 14, wherein the contact area between the transparent conductive film and the second reflector in the semiconductor light-emitting elements in the first group is smaller than the contact area between the transparent conductive film and the second reflector in the semiconductor light-emitting elements in the second group.

[0242] [Structure 16]

[0243] The light source device according to Structure 15, wherein at least the second reflector of the plurality of semiconductor light-emitting elements is in a mesa shape, and the width of the second reflector of the semiconductor light-emitting elements in the first group is narrower than the width of the second reflector of the semiconductor light-emitting elements in the second group.

[0244] [Structure 17]

[0245] The light source device according to Structure 16, wherein the semiconductor light-emitting elements in the first group include a proton implantation region in the second reflector, and by including the proton implantation region, the resistance value between the first electrode and the second electrode of the semiconductor light-emitting elements in the first group is larger than the resistance value between the first electrode and the second electrode of the semiconductor light-emitting elements in the second group.

[0246] [Structure 18]

[0247] A ranging device, comprising:

[0248] A light source device according to any one of Structures 1 to 17;

[0249] A light receiving device configured to receive light emitted from the light source device and reflected by an object to be measured; and

[0250] A distance information acquisition unit configured to acquire information related to the distance relative to the object to be measured based on a time difference between a timing of emitting light from the light source device and a timing of receiving light by the light receiving device.

[0251] The present invention enables the realization of a light source device capable of improving the light emission uniformity on a plurality of semiconductor light emitting elements.

[0252] Although the present invention has been illustrated with reference to exemplary embodiments, it should be understood that the present invention is not limited to the disclosed exemplary embodiments. The scope of the appended claims is to be accorded the broadest interpretation so as to encompass all such modifications, equivalent structures and functions.

Claims

1. A light source device, comprising: a plurality of semiconductor light emitting elements configured to sequentially stack a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on a first face side of a semiconductor substrate, and stack a second electrode on a second face of the semiconductor substrate opposite to the first face; a power supply pad configured to supply power to the plurality of semiconductor light emitting elements; as well as a wiring configured to connect each of the plurality of semiconductor light emitting elements to the power supply pad, wherein the plurality of semiconductor light emitting elements are divided into a plurality of groups according to distances relative to the power supply pad, and each of the plurality of groups includes at least one semiconductor light emitting element, and The semiconductor light emitting elements in the group having a shorter distance to the power supply pad are configured to have a larger resistance value between the first electrode and the second electrode.

2. A light source device, comprising: a plurality of semiconductor light emitting elements configured to sequentially stack a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on a first face side of a semiconductor substrate, and stack a second electrode on a second face of the semiconductor substrate opposite to the first face; a power supply pad configured to supply power to the plurality of semiconductor light emitting elements; as well as a wiring configured to connect each of the plurality of semiconductor light emitting elements to the power supply pad, wherein the plurality of semiconductor light emitting elements are divided into a plurality of groups according to the length of the current path of the wiring from the power supply pad, and each of the plurality of groups includes at least one semiconductor light emitting element, and The semiconductor light emitting element in the group in which the length of the current path of the wiring from the power supply pad is shorter is configured to have a larger resistance value between the first electrode and the second electrode.

3. The light source device according to claim 1 or 2, wherein: The plurality of groups include a first group and a second group, and the second group includes semiconductor light emitting elements having a resistance value smaller than that of the semiconductor light emitting elements of the first group.

4. The light source device according to claim 3, in, The plurality of groups include the first group, the second group, and a third group, the third group including semiconductor light emitting elements having a resistance value smaller than that of the semiconductor light emitting elements of the first group and larger than that of the semiconductor light emitting elements of the second group, and Wherein, the third group is configured between the first group and the second group.

5. The light source device according to claim 1 or 2, wherein: The plurality of semiconductor light emitting elements include a transparent conductive film between the first electrode and the second reflector.

6. The light source device according to claim 1 or 2, wherein: The plurality of semiconductor light emitting elements include a saturable absorption layer in the first reflector.

7. The light source device according to claim 3, wherein: The semiconductor light emitting elements of the first group are formed so that the distance between the first electrode and the second electrode is longer than the distance between the first electrode and the second electrode of the semiconductor light emitting elements of the second group, and since the distance between the first electrode and the second electrode of the semiconductor light emitting elements of the first group is longer than the distance between the first electrode and the second electrode of the semiconductor light emitting elements of the second group, the resistance value between the first electrode and the second electrode of the semiconductor light emitting elements of the first group is greater than the resistance value between the first electrode and the second electrode of the semiconductor light emitting elements of the second group.

8. The light source device according to claim 5, wherein: A contact area between the transparent conductive film in the semiconductor light emitting elements of a first group among the plurality of groups and the second reflector is smaller than a contact area between the transparent conductive film in the semiconductor light emitting elements of a second group among the plurality of groups and the second reflector.

9. The light source device according to claim 3, wherein: At least the second reflector of the plurality of semiconductor light emitting elements is in a terrace shape, and the width of the second reflector of the semiconductor light emitting elements in the first group is narrower than the width of the second reflector of the semiconductor light emitting elements in the second group.

10. The light source device according to claim 3, wherein: The semiconductor light emitting elements of the first group include a proton injection region in the second reflector, and by including the proton injection region, the resistance value between the first electrode and the second electrode of the semiconductor light emitting elements of the first group is greater than the resistance value between the first electrode and the second electrode of the semiconductor light emitting elements of the second group.

11. The light source device according to claim 1 or 2, in, The plurality of semiconductor light emitting elements sequentially stack a third reflector, a second semiconductor resonator including a second active layer, and a fourth reflector on a side of the second reflector opposite to the first semiconductor resonator, and The second active layer is excited by light of a first wavelength emitted from the plurality of semiconductor light emitting elements, and emits light of a second wavelength different from the first wavelength.

12. The light source device according to claim 5, wherein: The plurality of semiconductor light emitting elements include a saturable absorption layer in the first reflector.

13. The light source device according to claim 12, in, The plurality of groups include a first group and a second group, the second group including semiconductor light emitting elements having a resistance value smaller than that of the semiconductor light emitting elements of the first group, and In which, the semiconductor light emitting elements of the first group are formed so that the distance between the first electrode and the second electrode is longer than the distance between the first electrode and the second electrode of the semiconductor light emitting elements of the second group, and since the distance between the first electrode and the second electrode of the semiconductor light emitting elements of the first group is longer than the distance between the first electrode and the second electrode of the semiconductor light emitting elements of the second group, the resistance value between the first electrode and the second electrode of the semiconductor light emitting elements of the first group is greater than the resistance value between the first electrode and the second electrode of the semiconductor light emitting elements of the second group.

14. The light source device according to claim 13, wherein: A contact area between the transparent conductive film in the semiconductor light emitting element of the first group and the second reflector is smaller than a contact area between the transparent conductive film in the semiconductor light emitting element of the second group and the second reflector.

15. The light source device according to claim 14, wherein: At least the second reflector of the plurality of semiconductor light emitting elements is in a terrace shape, and the width of the second reflector of the semiconductor light emitting elements in the first group is narrower than the width of the second reflector of the semiconductor light emitting elements in the second group.

16. The light source device according to claim 15, wherein: The semiconductor light emitting elements of the first group include a proton injection region in the second reflector, and by including the proton injection region, the resistance value between the first electrode and the second electrode of the semiconductor light emitting elements of the first group is greater than the resistance value between the first electrode and the second electrode of the semiconductor light emitting elements of the second group.

17. A light source device, comprising: a plurality of semiconductor light emitting elements configured to sequentially stack a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on a first face side of a semiconductor substrate, and stack a second electrode on a second face of the semiconductor substrate opposite to the first face; a power supply pad configured to supply power to the plurality of semiconductor light emitting elements; as well as a wiring configured to connect each of the plurality of semiconductor light emitting elements to the power supply pad, wherein the plurality of semiconductor light emitting elements are divided into a plurality of groups according to the resistance of the wiring from the power supply pad, and each of the plurality of groups includes at least one semiconductor light emitting element, and The semiconductor light emitting element in the group in which the wiring from the power supply pad has a smaller resistance is configured to have a larger resistance value between the first electrode and the second electrode.

18. A distance measuring device, comprising: The light source device according to any one of claims 1, 2 and 17; a light receiving device configured to receive light emitted from the light source device and reflected by the object to be measured; as well as A distance information acquisition unit is configured to acquire information on the distance to the object to be measured based on a time difference between a timing at which light is emitted from the light source device and a timing at which the light is received by the light receiving device.

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