Quadrature error detection device, method, rotational digital converter and medium

Abstract

The present application discloses an orthogonal error detection device, method, rotary digital converter and medium, which relate to the technical field of rotary digital converters, including: processing the excitation phase output by the rotation phase and excitation phase correction module through a frequency synthesis module to obtain a first excitation signal and a second excitation signal; processing the resolver sine signal, the resolver cosine signal, the first excitation signal and the second excitation signal through a demodulation module to obtain a demodulation signal and a detection signal; controlling the demodulation signal to output the rotation phase through a rotation phase extraction module; and controlling the detection signal to output an output signal through a filter module, and then controlling the output signal to pass through an orthogonality error detection module to obtain an orthogonality error signal. By only adding the filter module and the orthogonality error detection module to the main demodulation device, the orthogonality error detection function can be taken into account on the basis of the main demodulation function with very little hardware expenditure.

Description

Technical Field

[0001] The present application relates to the technical field of rotational digitizers, and in particular to an orthogonal error detection device, method, rotational digitizer, and medium. Background Art

[0002] The rotary digital converter (RDC) provides an interface between the resolver and the system microprocessor, decoding the angular position and rotational speed of the motor shaft from the resolver input signal.

[0003] Orthogonality errors in the rotary digitizer can cause amplitude and phase mismatches in the decoded data. Therefore, detecting the orthogonality error can determine whether amplitude and phase mismatches exist. Therefore, it is currently proposed to add a hardware structure for orthogonality error detection to the rotary digitizer. This hardware structure performs orthogonality error detection and outputs the corresponding orthogonality detection results for calibration to ensure amplitude and phase accuracy. However, this additional hardware architecture not only increases hardware overhead but also requires the rotary digitizer to reserve space for this hardware architecture. Furthermore, when the quantizer uses a Delta Sigma modulator, quantization noise aliasing may occur, which also increases circuit area and hardware cost. Summary of the Invention

[0004] The main purpose of the present application is to provide an orthogonal error detection device, method, rotary digital converter and medium, aiming to solve the technical problems of quantization noise aliasing, increased circuit area and increased hardware cost in the current hardware structure solution for orthogonality error detection added to ensure the accuracy of demodulation.

[0005] To achieve the above-mentioned object, the present application proposes an orthogonality error detection device, which is applied to a rotary digital converter. The orthogonality error detection device includes an excitation phase correction module, a frequency synthesis module, a demodulation module, a rotation phase extraction module, and an orthogonality error detection module.

[0006] The excitation phase output by the rotation phase and excitation phase correction module is processed by the frequency synthesis module to obtain a first excitation signal and a second excitation signal;

[0007] The resolver sine signal, the resolver cosine signal, the first excitation signal and the second excitation signal are processed by a demodulation module to obtain a demodulation signal and a detection signal;

[0008] Controlling the demodulated signal to output a rotation phase through a rotation phase extraction module; and,

[0009] The control detection signal is output through the filter module to output the output signal, and then the control output signal is passed through the orthogonality error detection module to obtain the orthogonality error signal.

[0010] In one embodiment, the frequency synthesis module includes a first adder and a second adder;

[0011] The input ends of the first adder are respectively connected to the rotation phase and the excitation phase for addition, and output a first target input signal;

[0012] The input ends of the second adder are respectively connected to the rotation phase and the excitation phase for subtraction, and output a second target input signal;

[0013] The frequency synthesis module further includes a search combination unit, a third adder and a fourth adder;

[0014] The input end of the search combination unit is connected to the output end of the first adder and the output end of the second adder, and is used to search for corresponding sine values ​​and cosine values ​​according to the first target input signal and the second target input signal, and output a first sine signal, a second sine signal, a first cosine signal, and a second cosine signal;

[0015] The input end of the third adder is connected to the cosine output end of the search combination unit, and is used to operate the first cosine signal and the second cosine signal output from the cosine output end to output a first excitation signal;

[0016] The input end of the fourth adder is connected to the sinusoidal output end of the search combination unit, and is used to operate the first sinusoidal signal and the second sinusoidal signal output from the sinusoidal output end to output a second excitation signal.

[0017] In one embodiment, the demodulation module includes a first multiplier, a second multiplier, and a fifth adder;

[0018] The input end of the first multiplier is connected to the output end of the fourth adder and the modulator in the rotary digital converter respectively, and is used to multiply the resolver sinusoidal signal in the modulation signal by the second excitation signal input, and output a first output signal;

[0019] The input end of the second multiplier is connected to the output end of the third adder and the modulator respectively, and is used to multiply the first excitation signal and the resolver cosine signal in the modulation signal to output a second output signal;

[0020] The input end of the fifth adder is connected to the output end of the first multiplier and the output end of the second multiplier respectively, and is used to subtract the received first output signal and the second output signal to output a demodulated signal.

[0021] In one embodiment, the orthogonality error detection module includes a third multiplier, a fourth multiplier, and a sixth adder;

[0022] The input end of the third multiplier is connected to the output end of the third adder and the modulator respectively, and is used to multiply the first excitation signal and the resolver sinusoidal signal to output a third output signal;

[0023] The input end of the fourth multiplier is connected to the output end of the fourth adder and the modulator respectively, and is used to multiply the input second excitation signal and the resolver cosine signal to output a fourth output signal;

[0024] The input end of the sixth adder is connected to the output end of the third multiplier and the output end of the fourth multiplier respectively, and is used to add the connected third output signal and fourth output signal to output a detection signal.

[0025] In addition, to achieve the above-mentioned purpose, the present application also proposes an orthogonality error detection method, which is applied to the above-mentioned orthogonality error detection device. The orthogonality error detection method includes:

[0026] The excitation phase output by the rotation phase and excitation phase correction module is processed by the frequency synthesis module to obtain a first excitation signal and a second excitation signal;

[0027] The resolver sine signal, the resolver cosine signal, the first excitation signal and the second excitation signal are processed by a demodulation module to obtain a demodulation signal and a detection signal;

[0028] Suppressing quantization noise in the detection signal by using a filter;

[0029] Suppress the double excitation frequency interference in the detection signal through the filter;

[0030] The detection signal after the suppression operation is judged and the orthogonality error result is output.

[0031] In one embodiment, before the step of performing operation on the received modulated signal and outputting the detection signal, the step further includes:

[0032] Add the excitation phase correction factor in the excitation phase.

[0033] In one embodiment, the step of processing the resolver sine signal, the resolver cosine signal, the first excitation signal, and the second excitation signal by a demodulation module to obtain a demodulated signal and a detection signal includes:

[0034] Multiplying the received second excitation signal and the resolver sine signal in the modulation signal to output a first output signal, and multiplying the received first excitation signal and the resolver cosine signal in the modulation signal to output a second output signal;

[0035] subtracting the first output signal from the second output signal to output a demodulated signal; and

[0036] Performing a multiplication operation on the first excitation signal and the resolver sine signal to output a third output signal, and performing a multiplication operation on the second excitation signal and the resolver cosine signal to output a fourth output signal;

[0037] The third output signal and the fourth output signal are added to output a detection signal.

[0038] In one embodiment, the step of suppressing double excitation frequency interference in the detection signal by using a filter includes:

[0039] In the case where the filter includes a digital integrator, the integral of a quarter of the excitation frequency period of each integral is controlled to be subtracted based on the digital integrator to suppress double excitation frequency interference; or

[0040] In the case that the filter comprises a notch filter or a half-band notch filter, the double excitation frequency interference is suppressed based on the notch filter or the half-band notch filter.

[0041] In addition, to achieve the above-mentioned objectives, the present application also proposes a rotation digitizer, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the orthogonality error detection method described above.

[0042] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the steps of the orthogonality error detection method described above are implemented.

[0043] One or more technical solutions proposed in this application have at least the following technical effects:

[0044] A quadrature error detection device is proposed for use in a rotary digitizer (RTD). The device is well-suited for use with the main demodulation device of the RTD system. The device comprises: a frequency synthesis module processes the rotation phase and excitation phase (the excitation phase can be the original signal or a signal processed by an excitation phase correction module) to obtain a first excitation signal and a second excitation signal; a demodulation module processes the resolver sine signal, resolver cosine signal, and the first and second excitation signals to obtain a demodulated signal and a detection signal; a rotation phase extraction module extracts the demodulated signal (the rotation phase serves as the input signal of the frequency synthesis module); and the detection signal passes the output signal of a filter module and then passes it through an orthogonality error detection module to obtain a quadrature error signal. This technical solution aims to address the large circuit area requirements of existing quadrature error detection technologies and avoid the quantization noise aliasing problem when a quantizer uses a Delta Sigma modulator. Furthermore, this technical solution only adds a filter module and an orthogonality error detection module to the main demodulation device, thereby achieving orthogonality error detection in addition to the main demodulation function with minimal hardware overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figure 1 Schematic diagram of the system architecture of the orthogonal error detection device of the present application;

[0048] Figure 2 This is a schematic diagram of an embodiment of a frequency synthesis module and a demodulation module of the orthogonal error detection device of the present application;

[0049] Figure 3 This is a schematic diagram of the structure of the filter module of this application;

[0050] Figure 4 Schematic diagram of the structure of a conventional orthogonality error detection device;

[0051] Figure 5 A flowchart illustrating an embodiment of an orthogonality error detection method of the present application;

[0052] Figure 6 This is another structural diagram of the filter module of this application;

[0053] Figure 7 This is a schematic diagram of the structure of the traditional square sum detection method to achieve orthogonality error detection;

[0054] Figure 8 The input signal for this application is Figure 7 Schematic diagram of the waveform obtained by the square sum operation;

[0055] Figure 9 For this application Figure 8 Schematic diagram of the waveform obtained by performing periodic area integration;

[0056] Figure 10 For this application Figure 8 Schematic diagram of the waveform obtained by envelope extraction;

[0057] Figure 11 DSM ADC output Schematic diagram of the spectrum of the signal after noise shaping;

[0058] Figure 12 for The signal is generated by the square sum operation Schematic diagram of the signal spectrum;

[0059] Figure 13 for Signal, Signal and Schematic diagram of the signal spectrum;

[0060] Figure 14 Schematic diagram of the device structure of the hardware operating environment involved in the orthogonality error detection method in the embodiment of the present application.

[0061] Description of Figure Numbers:

[0062] 10. Frequency synthesis module; a. First adder; b. Second adder; c. Third adder; d. Fourth adder; LUT, lookup combination unit; 20. Rotation phase extraction module; 30. Orthogonality error detection module;

[0063] m1, first multiplier; m2, second multiplier; e, fifth adder; m3, third multiplier; m4, fourth multiplier; f, sixth adder; 301, filter module.

[0064] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0065] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0066] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0067] The main solution of the embodiment of the present application is: the excitation phase output by the rotation phase and excitation phase correction module is processed by the frequency synthesis module to obtain the first excitation signal and the second excitation signal; the resolver sine signal, the resolver cosine signal and the first excitation signal and the second excitation signal are processed by the demodulation module to obtain a demodulated signal and a detection signal; the demodulated signal is controlled to output the rotation phase through the rotation phase extraction module; and the detection signal is controlled to output the output signal through the filter module, and then the output signal is controlled to pass through the orthogonality error detection module to obtain an orthogonality error signal.

[0068] Because the orthogonality error of a rotary digitizer is a significant factor affecting the accuracy of amplitude and phase, to minimize its impact, it is necessary to detect the orthogonality error to determine if there is amplitude mismatch or phase mismatch. Therefore, a current proposal is to incorporate an additional hardware structure within the rotary digitizer for orthogonality error detection. This hardware structure performs orthogonality error detection and outputs the corresponding orthogonality detection results for calibration to ensure amplitude and phase accuracy. However, this additional hardware architecture not only increases hardware overhead but also requires the rotary digitizer to reserve space for this additional hardware architecture. Furthermore, when a Delta Sigma modulator is used as the quantizer, quantization noise aliasing may occur, increasing circuit area and hardware cost.

[0069] This application provides a solution by proposing an orthogonal error detection device for use in a rotary digital converter. The device comprises a frequency synthesis module that processes the rotation phase and excitation phase (the excitation phase can be the original signal or a signal processed by an excitation phase correction module) to obtain a first excitation signal and a second excitation signal; a demodulation module that processes the resolver sine signal, resolver cosine signal, and the first and second excitation signals to obtain a demodulated signal and a detection signal; a rotation phase extraction module that extracts the demodulated signal (the rotation phase serves as the input signal of the frequency synthesis module); and an orthogonality error detection module that passes the output signal of a filter module to obtain a quadrature error signal. This technical solution aims to address the large circuit area problem of existing orthogonal error detection technologies and also avoid the quantization noise aliasing problem when a quantizer uses a Delta Sigma modulator. Furthermore, this technical solution only adds a filter module and an orthogonality error detection module to the main demodulation device, thereby achieving orthogonality error detection in addition to the main demodulation function with minimal hardware expenditure.

[0070] It should be noted that the execution subject of this embodiment may be a computing service device with data processing, network communication, and program execution capabilities, such as a tablet computer, personal computer, mobile phone, or other electronic device capable of performing the aforementioned functions. This embodiment and the following embodiments will be described below using a rotation digitizer as an example.

[0071] Based on this, the embodiment of the present application provides an orthogonal error detection device, referring to Figure 1 , Figure 1 This is a module diagram of the orthogonality error detection device of the present application.

[0072] In this embodiment, the orthogonality error detection device includes an excitation phase correction module, a frequency synthesis module 10, a demodulation module, a rotation phase extraction module 20 and an orthogonality error detection module 30;

[0073] The frequency synthesis module 10 processes the excitation phase output by the rotation phase and excitation phase correction module to obtain a first excitation signal and a second excitation signal;

[0074] The resolver sine signal, the resolver cosine signal, the first excitation signal and the second excitation signal are processed by a demodulation module to obtain a demodulation signal and a detection signal;

[0075] The demodulated signal is controlled to output the rotation phase through the rotation phase extraction module 20; and the detection signal is controlled to output the output signal through the filter module, and then the output signal is controlled to pass through the orthogonality error detection module 30 to obtain the orthogonality error signal.

[0076] In this embodiment, based on the similarities between the current deformation formula of the demodulation signal and the deformation formula of the detection signal, a frequency synthesis module 10 is provided that can simultaneously generate a first excitation signal for demodulation and a second excitation signal for error detection. The demodulation module outputs not only a demodulation signal but also a detection signal. The detection signal then passes through a filter module and an orthogonality error detection module 30 to obtain an orthogonality error signal. In this way, the functions of implementing the demodulation operation and the functions of implementing the orthogonality error detection are provided on the same device circuit board, avoiding the increase in hardware cost and the increase in required circuit area caused by the need to separately provide the demodulation module and the orthogonality error detection module.

[0077] A rotation phase extraction module 20 is also provided on the circuit board for extracting the rotation phase from the demodulated signal output by the demodulation module and returning it to the frequency synthesis module 10. Furthermore, the frequency synthesis module 10 can also be connected to an excitation phase. To increase the sensitivity of the inspection, this excitation phase is corrected by adding an excitation phase correction coefficient, where the excitation phase correction coefficient can be a fixed constant.

[0078] It should be noted that, referring to Figure 1 It can be seen that the excitation phase input to the frequency synthesis module 10 is the phase corrected by the excitation phase correction module, and the output signal output by the demodulation module to the orthogonality error detection module 30 needs to be filtered by the filter module to eliminate the error.

[0079] In one possible implementation, refer to Figure 2 As shown, the frequency synthesis module 10 includes a first adder a and a second adder b;

[0080] The input end of the first adder a is respectively connected to the output end of the clock module and the output end of the demodulation module, and is used to add according to the connected excitation phase and rotation phase, and output the first target input signal; the input end of the second adder b is respectively connected to the output end of the clock module and the output end of the demodulation module, and is used to subtract according to the connected excitation phase and rotation phase, and output the second target input signal.

[0081] Specific, combined Figure 2 The first adder a is connected to the excitation phase The rotation phase of the demodulation module output , the excitation phase of the input and rotation phase Perform addition processing and output the first target input signal At the same time, the second adder b will also be connected to the excitation phase The rotation phase of the demodulation module output The difference is that the second adder b will be connected to the excitation phase and rotation phase Perform subtraction and output the second target input signal .

[0082] The frequency synthesis module 10 further includes a lookup combination unit LUT, a third adder c and a fourth adder d;

[0083] The input end of the search combination unit LUT is connected to the output end of the first adder a and the output end of the second adder b, and is used to search for corresponding sine values ​​and cosine values ​​according to the first target input signal and the second target input signal, and output a first sine signal, a second sine signal, a first cosine signal and a second cosine signal; the input end of the third adder c is connected to the cosine output end of the search combination unit LUT, and is used to operate on the first cosine signal and the second cosine signal output from the cosine output end, and output the first excitation signal; the input end of the fourth adder d is connected to the sine output end of the search combination unit LUT, and is used to operate on the first sine signal and the second sine signal output from the sine output end, and output the second excitation signal.

[0084] The first target input signal is obtained by the first adder a and the second adder b. and the second target input signal Then, the first target input signal and the second target input signal Input into the search combination unit LUT, according to Figure 2 It can be seen that the search combination unit LUT in this embodiment is provided with two sine values and two cosine values , according to the first adder a and the second adder b respectively with the sine value and cosine The search relationship between Figure 2 ), and the sine value and cosine Combined output first sinusoidal signal , the second sine signal and the first cosine signal , the second cosine signal .

[0085] In the third adder c, the third adder c receives the first cosine signal output from the cosine output terminal according to the cosine output terminal of the lookup combination unit LUT connected to its input terminal. and the second cosine signal Perform subtraction operation and output the first excitation signal .

[0086] In the fourth adder d, the fourth adder d receives the first sinusoidal signal output from the sinusoidal output terminal according to the sinusoidal output terminal of the lookup combination unit LUT connected to its input terminal. and the second sinusoidal signal Perform subtraction processing and output the second excitation signal .

[0087] It should be noted that, in this embodiment, the rotation phase output by the rotation phase extraction module 20 is the angular position output by the previous demodulation process.

[0088] In one possible implementation, refer to Figure 2 As shown, the demodulation module includes a first multiplier m1, a second multiplier m2 and a fifth adder e;

[0089] The input end of the first multiplier m1 is respectively connected to the output end of the fourth adder d and the modulator in the rotary digital converter, and is used to multiply the received second excitation signal and the resolved sine signal output by the modulator according to the received sine input signal, and output a first output signal; the input end of the second multiplier m2 is respectively connected to the output end of the third adder c and the modulator, and is used to multiply the received first excitation signal and the resolved cosine signal output by the modulator according to the received cosine input signal, and output a second output signal; the input end of the fifth adder e is respectively connected to the output end of the first multiplier m1 and the output end of the second multiplier m2, and is used to subtract the received first output signal from the second output signal, and output the demodulated signal.

[0090] Specific, combined Figure 2 In this embodiment, the first multiplier m1 and the second multiplier m2 are connected in parallel.

[0091] The input end of the first multiplier m1 is connected to the output end of the fourth adder d and the output end of the modulation module, and is used to receive the second excitation signal and resolver sinusoidal signal Perform multiplication processing and output the first output signal .

[0092] At the same time, the input end of the second multiplier m2 is connected to the output end of the third adder c and the output end of the modulation module, so as to receive the first excitation signal. and resolver cosine signal Perform multiplication processing and output the second output signal .

[0093] At this time, the fifth adder e receives the first output signal and the second output signal Perform subtraction and output the demodulated signal .

[0094] In one possible implementation, refer to Figure 2 As shown, the orthogonality error detection module 30 includes a third multiplier m3, a fourth multiplier m4 and a sixth adder f;

[0095] The input end of the third multiplier m3 is respectively connected to the output end of the third adder c and the modulator, and is used to multiply the first excitation signal and the resolver sine signal connected thereto, and output a third output signal; the input end of the fourth multiplier m4 is respectively connected to the output end of the fourth adder d and the modulator, and is used to multiply the second excitation signal and the resolver cosine signal connected thereto, and output a fourth output signal; the input end of the sixth adder f is respectively connected to the output end of the third multiplier m3 and the output end of the fourth multiplier m4, and is used to add the third output signal and the fourth output signal connected thereto, and output a detection signal.

[0096] Specific, combined Figure 2 In the third multiplier m3, according to the first excitation signal and the resolver sinusoidal signal output by the modulator Perform multiplication and output the third output signal .

[0097] In the fourth multiplier m4, according to the second excitation signal and the resolver cosine signal output by the modulator Perform multiplication and output the fourth output signal .

[0098] At this time, the third output signal and the fourth output signal are sent to the sixth adder f, and the sixth adder f adds them to output the detection signal .

[0099] Further, according to Figure 2 It can be seen that the input end of the filter module 301 is connected to the output end of the sixth adder f, and is used to perform filtering processing on the received detection signal.

[0100] In one feasible implementation, the filter module 301 in this embodiment includes a cascaded integrator comb filter and a notch filter. First, a low-pass filter is implemented by the cascaded integrator comb filter CIC using a phase-shift addition or phase-shift subtraction method. Then, a notch point is created at 2 times the excitation frequency by the notch filter Notch to eliminate the harmonic components at 2 times the excitation frequency in the detection signal. It should be noted that if the downsampling filter of the cascaded integrator comb filter is eight times the excitation frequency, the notch filter Notch can be converted into a half-band notch filter HB Notch.

[0101] It should be noted that, referring to Figure 3As shown, when the filter is a half-band notch filter, it needs to be connected to a cascaded integrator comb filter in front. After the interference caused by the excitation frequency is suppressed by the cascaded integrator comb filter, the target signal is extracted by the half-band notch filter.

[0102] In a feasible implementation manner, the filter module 301 in this embodiment may also be a CDS digital integrator, and each integrated quarter of the excitation frequency period is directly subtracted by the CDS digital integrator.

[0103] The detection signal is filtered by the filter module 301 in the above steps. After filtering, it is determined whether the orthogonality error result corresponding to the detection signal after filtering is within a preset threshold range. If the orthogonality error result is greater than the upper threshold within the preset threshold range, and combined with the previous orthogonality error detection operations, the orthogonality error result obtained in this judgment that is greater than the upper threshold within the preset threshold range has exceeded the preset rising upper threshold of the counter for a number of times, then based on the orthogonality error result, it is determined that amplitude mismatch and phase mismatch exist at this time; if the orthogonality error result is less than the lower threshold within the preset threshold range, and combined with the previous orthogonality error detection operations, the orthogonality error result obtained in this judgment that is less than the lower threshold within the preset threshold range has exceeded the preset falling lower threshold of the counter for a number of times, then based on the orthogonality error result, it is determined that amplitude mismatch and phase mismatch exist at this time.

[0104] It should be noted that according to Figure 4 It can be seen from the conventional orthogonality error detection device shown in FIG that the resolver sinusoidal signal is and sinusoidal output angle Passed to a multiplier, and the resolver cosine signal Sum and cosine output angle Passed into the b multiplier, outputting the a output signal respectively and b output signal Do addition to get a stimulus signal , the a excitation signal and the b excitation signal Input to the last stage multiplier and output detection signal .

[0105] It can be seen from this that in a conventional orthogonality error detection device, two Multiplier and Multiplier, where The operation of the multiplier is to A set of data is first shifted to obtain m groups After the data is Each bit of data in the data is multiplied and added with other bit data, so a The multiplier is equivalent to m The multipliers and m adders are needed, so there is a huge problem of hardware implementation cost. The orthogonality error detection module 30 in this embodiment is used, and the modules in the embodiment of the present invention require multipliers. Multiplier, not required Multiplier, greatly reducing the hardware implementation cost.

[0106] The present application also proposes an orthogonality error detection method, referring to Figure 5 As shown, Figure 5 This is a flow chart of an embodiment of the orthogonality error detection method of the present application.

[0107] In this embodiment, the orthogonality error detection method includes steps S10 to S50:

[0108] Step S10, processing the excitation phase output by the rotation phase and excitation phase correction module through the frequency synthesis module to obtain a first excitation signal and a second excitation signal;

[0109] Step S20: Processing the resolver sine signal, the resolver cosine signal, the first excitation signal, and the second excitation signal through a demodulation module to obtain a demodulated signal and a detection signal.

[0110] Step S30: Suppressing quantization noise in the detection signal through a filter.

[0111] Step S40: suppressing the double excitation frequency interference in the detection signal through a filter.

[0112] Step S50 , judging the detection signal after the suppression operation, and outputting an orthogonality error result.

[0113] The implementation process of step S10 to step S50 can refer to Figures 1-4 The corresponding descriptions will not be repeated here.

[0114] In step S20, the orthogonality error detection method further includes step S21:

[0115] Step S21: adding an excitation phase correction coefficient to the excitation phase.

[0116] The implementation process of step S21 can refer to Figure 5 The corresponding descriptions will not be repeated here.

[0117] In step S20, the orthogonality error detection method further includes steps S22 to S24:

[0118] Step S22, multiplying the second excitation signal received and the resolver sine signal in the modulation signal to output a first output signal, and multiplying the first excitation signal received and the resolver cosine signal in the modulation signal to output a second output signal;

[0119] Step S23, subtracting the first output signal from the second output signal, outputting the demodulated signal, multiplying the first excitation signal and the resolver sine signal, outputting a third output signal, and multiplying the second excitation signal and the resolver cosine signal, outputting a fourth output signal;

[0120] Step S24: Add the third output signal and the fourth output signal to output a detection signal.

[0121] The implementation process of step S23 to step S24 can refer to Figure 2 The corresponding descriptions will not be repeated here.

[0122] Here, the principle that the demodulation module and the orthogonality error detection module 30 can be connected to the frequency synthesis module 10 to perform corresponding operations is explained.

[0123] In step S40, the orthogonality error detection method further includes step S41 or S42:

[0124] Step S41, when the filter includes a digital integrator, based on the digital integrator, control the subtraction of the integral of one quarter of the excitation frequency period of each integration to suppress the double excitation frequency interference; or, step S42, when the filter includes a notch filter or a half-band notch filter, suppress the double excitation frequency interference based on the notch filter or the half-band notch filter.

[0125] The implementation process of step S41 to step S42 can refer to Figure 2 The corresponding descriptions will not be repeated here.

[0126] It should be noted that, referring to Figure 6 As shown in the figure, after suppressing the interference of twice the excitation frequency through a notch filter or a comb filter (i.e. eliminating the harmonic component at twice the excitation frequency in the detection signal), it is still necessary to extract the useful signal at the low frequency through a low-pass filter.

[0127] First, let me explain that the traditional method is to detect orthogonality errors by using the sum of squares method. Figure 7 Provide explanation.

[0128] Figure 7The traditional square sum detection method is used to realize orthogonality error detection. and input signal 2 Multiply them by the corresponding multipliers to get the square signal of the input signal The square of the input signal Then, the two squares are input into the adder to add and the detection signal is obtained. .

[0129] Specific process reference Figure 8 As shown, Figure 8 The input signal passes through Figure 7 The square sum operation is performed. Figure 8 The signal frequency is twice the input signal frequency, that is, Figure 8 The time required for the signal in the dotted box corresponds to the time of one signal cycle of the resolver input signal.

[0130] Figure 9 Yes Figure 8 Obtained by periodic area integration. Figure 8 Performing periodic area integration, we can obtain Figure 9 The waveform of . Figure 8 The dotted box is a cycle of area integration.

[0131] Figure 9 The amplitude of the waveform represents the sum of the squares of cosθ and sinθ. If the input sine and cosine signals are orthogonal, the amplitude after each integration will reach 1. If the input sine and cosine signals are not orthogonal, the amplitude after each integration will be less than 1.

[0132] In addition to the periodic area integration method, the square sum operation can also be used to detect orthogonality by extracting the envelope method.

[0133] Figure 10 Yes Figure 8 The waveform obtained by envelope extraction. If the input sine and cosine signals are orthogonal, the extracted envelope amplitude will be 1. If the input sine and cosine signals are not orthogonal, the extracted envelope amplitude will be less than 1.

[0134] For Nyquist sampling rate ADCs like SAR ADCs, orthogonality can be detected by performing a square sum operation followed by periodic area integration or envelope extraction. This method has certain drawbacks. Because the SAR ADC outputs a multi-bit digital code, the square sum operation requires a large multiplier, resulting in excessively high device hardware costs. This leads to the following issues:

[0135] ① If Signal 1 and Signal 2 are not converted into digital codes by ADC (Analog-to-Digital Converter), then Signal 1 and Signal 2 are analog signals. Figure 7 The multiplier in the circuit is an analog multiplier, which has the disadvantages of poor linearity, harmonic distortion and high power consumption.

[0136] ② If signal 1 and signal 2 are digital codes converted by ADC, then Figure 2 The multiplier in the example is a digital multiplier, but an ADC, such as a DSM ADC (Delta-Sigma Modulation Analog-to-Digital Converter), has a noise shaping function. Therefore, the 1-bit digital code converted by the ADC needs to be filtered before the square sum detection method can be performed. This requires the establishment of two additional filters.

[0137] If the 1-bit digital code is directly subjected to the square sum detection method without filtering, quantization noise aliasing will occur. Figure 11 Assume that the DSM ADC outputs a If the signal is , then after the signal is noise shaped, the noise component at the high frequency of the signal will be very large. So if the signal is directly squared and operated without filtering, the result will be as follows Figure 12 The spectrum diagram shown is based on Figure 12 It can be seen that due to the process of quantized convolution, the useful signal at DC will be aliased, that is, after the square and operation The noise at low frequencies is very loud, and the signal It will be drowned in the noise and no effective output can be obtained, so it needs to be filtered.

[0138] ③ If Signal 1 and Signal 2 are generated by a multi-bit non-noise shaping ADC, such as a SAR ADC (Successive Approximation Register Analog-to-Digital Converter), then since there is no noise shaping, Signal 1 and Signal 2 will not have the problem of high-frequency noise, so there is no need to add a filter. However, this type of ADC outputs an n-bit digital code, so two filters are required. multiplier, and because a The multiplier is equivalent to n The multiplier and n adders may result in excessively high device hardware costs.

[0139] In response to the above problems, conventional proposals are as follows Figure 4 The conventional orthogonality error detection device is shown. Figure 4 Sine output angle in Sum and cosine output angle It is not generated by the ADC, so the sinusoidal output angle Sum and cosine output angle There is no noise component at the high frequency of the resolver cosine signal. and resolver sinusoidal signal The 1-bit digital code generated by a DSM ADC has noise components at high frequencies, but the corresponding sinusoidal output angles are Sum and cosine output angle There is no noise component at the high frequency of , so the multiplied signal is a valid signal, refer to Figure 13 The spectrum diagram shown.

[0140] Figure 13 (a) in The spectrum diagram shows that after DSM ADC noise shaping, There is a noise component at high frequencies, but Figure 13 From (b) in the above, we can see that is not generated by the DSM ADC, so There is no noise component at high frequencies. and Multiply to get Figure 13 (c) in the figure, we can see that It will not be drowned in noise, that is, effective output can be obtained.

[0141] Therefore, the above implementation method has the following advantages:

[0142] ① Avoid the use of analog multipliers, thereby avoiding the defects of analog multipliers.

[0143] ② Because the sinusoidal output angle Sum and cosine output angle There is no noise component at the high frequency of the signal, so no filtering is required before the detection signal is output, thus avoiding the addition of filters.

[0144] ③ Because the modulated signal is multiplied by the corresponding output angle instead of the modulated signal being squared, there is no aliasing of quantization noise.

[0145] At this time Figure 4 Detection signal in After transformation, we get equation ①:

[0146] —Equation ①

[0147] in, and It is determined by the modulator and cannot be changed, so it can only be and After transformation, we get equation ②:

[0148] ————Equation ②

[0149] Substituting formula ② into formula ①, we can get the following equation ③:

[0150]

[0151] In the conventional demodulation process, the output conventional demodulation signal is as shown in the following equation ④:

[0152]

[0153] Transform equation ④ into equation ⑤ as follows:

[0154]

[0155] According to the conversion equation shown in equation ②, equation ⑤ can be transformed into equation ⑥:

[0156]

[0157] Equation ③ represents the orthogonality error detection operation flow of the rotary digitizer, and Equation ⑥ represents the demodulation operation flow of the rotary digitizer. Observing Equations ③ and ⑥, it can be seen that in Equations ③ and ⑥, except for the same modulation signal, the excitation signal and stimulus signal The same is true, and the excitation signal and stimulus signal You can use the LUT / CORDIC method, and Through mapping, we can get 、 、 and , based on this point, this embodiment is designed as follows Figure 2The architecture shown in the search combination unit in the embodiment can obtain the excitation signals required for the demodulation operation process and the orthogonality error detection operation process, so that the orthogonality error detection operation process and the demodulation operation process can share a frequency synthesis module, thereby integrating the architecture required for the orthogonality error detection operation and the architecture required for the demodulation operation into one device, thereby avoiding the problem of increased hardware cost caused by the need to set up relatively independent devices for the two operations, and avoiding the problem of increased circuit area cost caused by the need to set up relatively independent devices for the two operations.

[0158] LUT stands for Look-Up Table, which is a lookup table method that can obtain the sine and cosine values ​​of a specific phase through mapping. The CORDIC algorithm is a "complexity-simplifying" algorithm that converts many complex calculations into an iterative operation that "only requires shifting and adding."

[0159] In this embodiment, the excitation phase output by the rotation phase and excitation phase correction module is processed by the frequency synthesis module to obtain the first excitation signal and the second excitation signal; the resolver sine signal, the resolver cosine signal, the first excitation signal, and the second excitation signal are processed by the demodulation module to obtain a demodulated signal and a detection signal, and the detection signal is judged to output the orthogonality error result. Because the module corresponding to the demodulation operation and the module corresponding to the orthogonality error detection operation are in the same orthogonal error detection device, the problem of increased circuit area cost caused by the need to set up relatively independent devices for the two operations and the corresponding circuit area being occupied is avoided.

[0160] The present application provides a rotational digitizer, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the orthogonality error detection method in the above-mentioned embodiment.

[0161] Reference below Figure 14 , which shows a schematic diagram of the structure of a rotary digitizer suitable for implementing embodiments of the present application. The rotary digitizer in the embodiments of the present application can include, but is not limited to, mobile terminals such as laptop computers, PADs (Portable Application Descriptions), PMPs (Portable Media Players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 14The illustrated rotary digitizer is merely an example and should not limit the functionality and scope of use of the embodiments of the present application.

[0162] like Figure 14 As shown, the rotary digitizer may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in a read-only memory (ROM) 1002 or programs loaded from a storage device 1003 into a random access memory (RAM) 1004. RAM 1004 also stores various programs and data required for the operation of the rotary digitizer. Processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to I / O interface 1006: input devices 1007, such as a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, etc.; output devices 1008, such as a speaker, vibrator, etc.; storage device 1003, such as a magnetic tape, hard disk, etc.; and communication device 1009. Communication device 1009 may allow the rotary digitizer to communicate with other devices wirelessly or wiredly to exchange data. Although the figures show a rotation digitizer with various systems, it should be understood that it is not required to implement or have all of the systems shown. More or fewer systems may be implemented or have instead.

[0163] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program comprising program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0164] The rotational digitizer provided by this application utilizes the orthogonality error detection method of the aforementioned embodiment, resolving the technical issues of quantization noise aliasing, increased circuit area, and increased hardware cost associated with existing hardware structures for orthogonality error detection to ensure demodulation accuracy. Compared to the prior art, the rotational digitizer provided by this application achieves the same beneficial effects as the orthogonality error detection method of the aforementioned embodiment. Other technical features of this rotational digitizer are the same as those disclosed in the aforementioned embodiment and are not further elaborated here.

[0165] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0166] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0167] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, a computer program) stored thereon, wherein the computer-readable program instructions are used to execute the orthogonality error detection method in the above embodiment.

[0168] The computer-readable storage medium provided herein may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including, but not limited to, wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0169] The computer-readable storage medium may be included in the rotational digitizer, or may exist independently without being incorporated into the rotational digitizer.

[0170] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the rotary digital converter, the rotary digital converter: processes the excitation phase output by the rotation phase and excitation phase correction module through the frequency synthesis module to obtain a first excitation signal and a second excitation signal; processes the resolver sine signal, the resolver cosine signal, the first excitation signal, and the second excitation signal through the demodulation module to obtain a demodulated signal and a detection signal; suppresses quantization noise in the detection signal through the filter; suppresses double excitation frequency interference in the detection signal through the filter; and judges the detection signal after the suppression operation and outputs an orthogonality error result.

[0171] Computer program code for performing the operations of the present application may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0172] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0173] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0174] The computer-readable storage medium provided in this application is a computer-readable storage medium storing computer-readable program instructions (i.e., a computer program) for executing the above-described orthogonality error detection method. This computer-readable storage medium can address the technical issues of quantization noise aliasing, increased circuit area, and increased hardware cost associated with existing hardware structures for orthogonality error detection designed to ensure demodulation accuracy. Compared to the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the orthogonality error detection method provided in the above-described embodiments, and are not further elaborated here.

[0175] The above description is only part of the embodiments of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made by using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A quadrature error detection device, characterized in that: The orthogonal error detection device is applied to a rotary digital converter, and the orthogonal error detection device includes an excitation phase correction module, a frequency synthesis module, a demodulation module, a rotation phase extraction module and an orthogonality error detection module; Processing the rotation phase and the excitation phase output by the excitation phase correction module through the frequency synthesis module to obtain a first excitation signal and a second excitation signal; The resolver sine signal, the resolver cosine signal, the first excitation signal, and the second excitation signal are processed by the demodulation module to obtain a demodulated signal and a detection signal; Controlling the demodulated signal to output the rotation phase through the rotation phase extraction module; as well as, Controlling the detection signal to pass through the filter module to output an output signal, and then controlling the output signal to pass through the orthogonality error detection module to obtain an orthogonality error signal; Wherein, the frequency synthesis module includes a first adder and a second adder; The input ends of the first adder are respectively connected to the rotation phase and the excitation phase for addition, and output a first target input signal; The input ends of the second adder are respectively connected to the rotation phase and the excitation phase for subtraction, and output a second target input signal; The frequency synthesis module determines the first excitation signal and the second excitation signal according to the first target input signal and the second target input signal; The demodulation module includes a first multiplier, a second multiplier and a fifth adder; The input end of the first multiplier is connected to the output end of the fourth adder in the frequency synthesis module and the modulator in the rotational digital converter, respectively, and is used to multiply the second excitation signal and the resolver sinusoidal signal in the modulation signal to output a first output signal; The input end of the second multiplier is connected to the output end of the third adder in the frequency synthesis module and the modulator respectively, and is used to multiply the first excitation signal and the resolver cosine signal in the modulation signal to output a second output signal; The input end of the fifth adder is connected to the output end of the first multiplier and the output end of the second multiplier respectively, and is used to subtract the first output signal and the second output signal received therefrom, and output the demodulated signal; The orthogonality error detection module includes a third multiplier, a fourth multiplier and a sixth adder; The input end of the third multiplier is connected to the output end of the third adder and the modulator respectively, and is used to multiply the first excitation signal and the resolver sinusoidal signal to output a third output signal; The input end of the fourth multiplier is connected to the output end of the fourth adder and the modulator respectively, and is used to multiply the second excitation signal and the resolver cosine signal to output a fourth output signal; The input end of the sixth adder is connected to the output end of the third multiplier and the output end of the fourth multiplier respectively, and is used to add the connected third output signal and the fourth output signal to output a detection signal.

2. The quadrature error detection device according to claim 1, wherein: The frequency synthesis module further includes a search combination unit, a third adder and a fourth adder; The input end of the search and combination unit is connected to the output end of the first adder and the output end of the second adder, and is used to search for corresponding sine values ​​and cosine values ​​according to the first target input signal and the second target input signal, and output a first sine signal, a second sine signal, a first cosine signal, and a second cosine signal; The input end of the third adder is connected to the cosine output end of the search combination unit, and is used to operate the first cosine signal and the second cosine signal output from the cosine output end to output the first excitation signal; The input end of the fourth adder is connected to the sinusoidal output end of the search combination unit, and is used to operate the first sinusoidal signal and the second sinusoidal signal output from the sinusoidal output end to output the second excitation signal.

3. A method for detecting orthogonality errors, characterized in that: The orthogonality error detection method is applied to the orthogonality error detection device according to claim 1 or 2, and the orthogonality error detection method includes: The excitation phase output by the rotation phase and excitation phase correction module is processed by the frequency synthesis module to obtain a first excitation signal and a second excitation signal; The resolver sine signal, the resolver cosine signal, the first excitation signal, and the second excitation signal are processed by a demodulation module to obtain a demodulated signal and a detection signal; Suppressing quantization noise in the detection signal by a filter; Suppressing the double excitation frequency interference in the detection signal by using a filter; Judging the detection signal after the suppression operation and outputting the orthogonality error result; The step of processing the excitation phase output by the rotation phase and excitation phase correction module through the frequency synthesis module to obtain the first excitation signal and the second excitation signal includes: adding the rotation phase and the excitation phase to output a first target input signal, and subtracting the rotation phase and the excitation phase to output a second target input signal; determining the first excitation signal and the second excitation signal according to the first target input signal and the second target input signal; The step of processing the resolver sine signal, the resolver cosine signal, the first excitation signal, and the second excitation signal by a demodulation module to obtain a demodulated signal and a detection signal includes: Performing a multiplication operation on the second excitation signal received and the resolver sine signal in the modulation signal to output a first output signal, and performing a multiplication operation on the first excitation signal received and the resolver cosine signal in the modulation signal to output a second output signal; performing subtraction on the first output signal and the second output signal to output the demodulated signal; and Performing a multiplication operation on the first excitation signal and the resolver sine signal to output a third output signal, and performing a multiplication operation on the second excitation signal and the resolver cosine signal to output a fourth output signal; The third output signal and the fourth output signal are added to output the detection signal.

4. The orthogonality error detection method according to claim 3, wherein: Before the step of performing operation on the received modulated signal and outputting the detection signal, the step further includes: Add the excitation phase correction factor in the excitation phase.

5. The orthogonality error detection method according to claim 3, wherein: The step of suppressing the double excitation frequency interference in the detection signal by using a filter comprises: In the case where the filter includes a digital integrator, based on the digital integrator, the integral of a quarter of the excitation frequency period of each integral is controlled to be subtracted to suppress the double excitation frequency interference; or, In a case where the filter includes a notch filter or a half-band notch filter, the double excitation frequency interference is suppressed based on the notch filter or the half-band notch filter.

6. A rotation digitizer, characterized in that The rotation digitizer comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the orthogonality error detection method according to any one of claims 3 to 5.

7. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the orthogonality error detection method according to any one of claims 3 to 5 are implemented.

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