Semiconductor nonlinear output junction capacitance measurement method based on fitting iteration

Abstract

The invention relates to the technical field of semiconductor device measurement, and provides a semiconductor nonlinear output junction capacitance measurement method based on fitting iteration, and the method comprises the steps: firstly building a junction capacitance extraction circuit, collecting the turn-off transient waveform of a to-be-measured device through a test platform, extracting the oscillation frequency fexp through fast Fourier transform, and carrying out the measurement of the to-be-measured device; based on the relation between the oscillation frequency and the junction capacitance and parasitic parameters, the initial junction capacitance Coss is reversely deduced; then, fitting is carried out by adopting a hyperbolic tangent function, fitting parameters are optimized through a least square method, a preliminary junction capacitance Coss-test voltage udc relation curve under different voltage grades is obtained, an oscillation frequency simulation circuit is further built, simulation frequency fm is obtained, fm is compared with fexp, if deviation exists, the fitting curve is adjusted and iterative optimization is carried out, and the test voltage udc relation curve of the junction capacitance under different voltage grades is obtained. And ending until the error of two adjacent rounds of fitting results is lower than a set error threshold value, thereby obtaining a final accurate junction capacitance Coss-test voltage udc relation curve.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor device measurement, in particular to a semiconductor nonlinear output junction capacitance measurement method based on fitting iteration. Background Art

[0002] The nonlinear variation of the output junction capacitance of high-voltage semiconductor devices with voltage has brought a series of challenges to the design and application of power devices. This trend makes it more difficult to accurately measure and model the output junction capacitance under high-voltage conditions, and traditional low-voltage measurement methods may not cover the capacitance variation range under high-voltage conditions. At the same time, in high-voltage and high-frequency applications, the nonlinear variation of the output junction capacitance may cause unstable switching speed and energy loss during soft switching, thereby affecting the efficiency and reliability of power devices. Therefore, accurately extracting the output junction capacitance of high-voltage semiconductor devices under corresponding working conditions is crucial to optimizing the performance of power devices and improving system efficiency.

[0003] At present, the methods for extracting the output junction capacitance of semiconductor devices can be mainly divided into instrumentation and simulation. The instrumentation method usually uses special instruments such as high-frequency Q meters, small capacitance meters, and impedance analyzers for measurement.

[0004] The measurement results of the first two instruments are reliable, but they are limited by the low measurement voltage range and cannot accurately extract the output junction capacitance value in the high voltage range. Although the impedance analyzer can measure the output capacitance under high voltage conditions, its use and maintenance costs are high. The simulation method usually requires the use of commercial simulation software such as TCAD and Multiphysics to model the device structure more accurately in order to simulate the junction capacitance behavior mode under high voltage and high frequency conditions. Due to the wide variety of high-voltage semiconductor devices, it is impossible to carry out detailed modeling and accurate simulation of each type of device in practice, and there are great limitations in terms of versatility. Summary of the invention

[0005] The purpose of the present invention is to address the deficiencies in the prior art and to provide a semiconductor nonlinear output junction capacitance measurement method based on fitting iteration. Through semiconductor model fitting and multiple rounds of frequency matching iterations, high-precision modeling of the nonlinear characteristics of the output junction capacitance is achieved, which can effectively reduce the measurement error in the strong nonlinear region and is suitable for various high-voltage semiconductor device wide voltage range junction capacitance tests.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A semiconductor nonlinear output junction capacitance measurement method based on fitting iteration comprises the following steps:

[0008] Step 1, build a semiconductor device junction capacitance extraction circuit;

[0009] Step 2: Connect the device under test to the junction capacitance extraction circuit, obtain the turn-off transient waveform of the device under test through the test platform, and use the fast Fourier transform to obtain the oscillation frequency f exp ; Use the oscillation frequency f exp and the relational expression between the junction capacitance and the platform parasitic parameters to inversely deduce the initial junction capacitance C oss value of the device under test. Combine the actual test voltage u dc to generate an initial junction capacitance C oss - test voltage u dc data set;

[0010] Step 3: Use the hyperbolic tangent function to fit the initial junction capacitance C oss - test voltage u dc data set in Step 2, optimize the fitting parameters by the least squares method, and obtain a preliminary junction capacitance C oss - test voltage u dc relationship curve;

[0011] Step 4: Build an oscillation frequency simulation circuit, simulate and output the dynamic behavior of the junction capacitance C oss , obtain the simulation frequency f m , and compare f m with f exp to judge the accuracy of the fitting curve;

[0012] Step 5: If there is a deviation between f m and f exp , then fine-tune the C oss values corresponding to each voltage point in the fitting curve, update the junction capacitance C oss - test voltage u dc data set, and refit using the hyperbolic tangent function;

[0013] Step 6: Repeat the iterative process of Step 4 and Step 5 until the error between adjacent two-round fitting results meets the preset convergence condition, so as to obtain the final accurate output junction capacitance C oss - test voltage u dc relationship curve.

[0014] Preferably, the semiconductor device junction capacitance test platform in Step 1 includes: a DC power supply unit u dc , DUT port, diode D, and load inductor L load connected in series in sequence; a power device S is connected in parallel at both ends of the DUT port, and the power device S, the diode, and the DC power supply unit form a turn-off transient oscillation loop. When the test voltage is relatively high, the power device S can adopt a form of multiple devices connected in series for voltage division.

[0015] Preferably, in step 2, the device under test is connected to the extraction circuit, and the turn-off transient oscillation is excited under different test voltages u dc conditions, the time-domain waveform is collected, and the measured oscillation frequency is calculated using the following formula:

[0016]

[0017] where L loop is the platform parasitic inductance, C serial is the equivalent capacitance of the power device, and C oss is the output junction capacitance of the device under test.

[0018] Preferably, the specific expression of the hyperbolic tangent function fitting in step 3 is:

[0019] C oss = C 0 + A·tanh(B·u dc );

[0020] where C 0 , A, and B are parameters to be fitted and are determined by the least squares method.

[0021] Preferably, step 4 simulates the transient behavior of the device under test at different test voltages through the following formula:

[0022]

[0023] where i oss (t) is the transient current, C oss (u ds (t)) is the junction capacitance corresponding to the voltage u ds (t), u ds (t) is the drain-source voltage during the turn-off transient oscillation, and i load (t) is the load current.

[0024] Preferably, in step 6, when the relative error between the C oss values obtained from two adjacent rounds of fitting is less than the set error threshold, the iterative process terminates, and the final accurate C oss - test voltage u dc relationship curve is output.

[0025] The present invention discloses a semiconductor non-linear output junction capacitance measurement method based on fitting iteration, which has the following beneficial effects.

[0026] The present invention can effectively improve the measurement accuracy, avoid the errors caused by the traditional method ignoring the non-linear characteristics of the junction capacitance, extract the oscillation frequency through the Fast Fourier Transform (FFT), and combine the hyperbolic tangent function fitting and the least squares method optimization to obtain a more accurate junction capacitance C oss - Test voltage u dc relationship curve. At the same time, an iterative optimization strategy is adopted. Through the dynamic comparison of the oscillation frequency simulation and the measured data, the fitting result is continuously optimized, ensuring the accuracy and convergence of the measurement, and effectively eliminating the influence of the parasitic parameters of the test platform on the measurement result, improving the stability and universality of the measurement. Compared with the traditional measurement method, the present invention does not require a complex external test circuit, has higher measurement efficiency, and can optimize the calculation amount while ensuring the measurement accuracy. Description of the Drawings

[0027] Figure 1 is the test platform for the junction capacitance of the semiconductor device of the present invention.

[0028] Figure 2 is the measured time-domain waveform diagram when the test voltage is set to 200V in the embodiment of the present invention.

[0029] Figure 3 is the simulation frequency iteration model of the present invention.

[0030] Figure 4 is the curve of multiple iterations and the output result in the embodiment of the present invention and the curve in the data manual.

[0031] Figure 5 is the flowchart of the semiconductor non-linear output junction capacitance measurement method based on fitting iteration of the present invention. Detailed Embodiments

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0033] Referring to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment can be included in at least one embodiment of the present application. The term "embodiment" appearing in various positions in the specification does not necessarily refer to the same embodiment, nor is it particularly limited to its independence or relevance to other embodiments. In principle, in the present application, as long as there is no technical contradiction or conflict, the technical features mentioned in each embodiment can be combined in any way to form the corresponding implementable technical solution.

[0034] Unless otherwise defined, the technical terms used herein have the same meanings as those commonly understood by those skilled in the technical field to which this application belongs; the use of relevant terms herein is only for describing specific embodiments and is not intended to limit this application.

[0035] In the description of this application, the term "and / or" is an expression used to describe the logical relationship between objects, indicating that three relationships can exist. For example, A and / or B means: there is A, there is B, and there is both A and B at the same time. In addition, the character " / " herein generally represents an "or" logical relationship between the associated objects before and after.

[0036] Unless otherwise clearly specified or limited, in the description of the embodiments of this application, the terms "installed", "connected", "linked", "fixed", "set", etc. shall be understood in a broad sense. For example, the "connection" may be a fixed connection, a detachable connection, or an integral setting; it may be a mechanical connection, an electrical connection, or a communication connection; it may be directly connected, or indirectly connected through an intermediate medium; it may be the communication inside two components or the interaction relationship between two components. For those skilled in the technical field to which this application belongs, the specific meanings of the above terms in the embodiments of this application can be understood according to specific circumstances.

[0037] Embodiment

[0038] In this embodiment, a MOSFET module with a rated withstand voltage of 3.3 kV is used as the device under test. Please refer to Figures 1 to 5 , a semiconductor non-linear output junction capacitance measurement method based on fitting iteration, includes the following steps:

[0039] Step 1, build a semiconductor device junction capacitance extraction circuit as shown in Figure 1 ;

[0040] Specifically, the semiconductor device junction capacitance test platform in Step 1 includes: a DC power supply unit u dc , DUT port, diode D, load inductor L load ; a power device S is connected in parallel at both ends of the DUT port. The power device S, the diode, and the DC power supply unit form a turn-off transient oscillation loop. When the test voltage is relatively high, the power device S can adopt a series connection form of multiple devices for voltage division;

[0041] Step 2, connect the device under test to the junction capacitance extraction circuit, obtain the turn-off transient waveform of the device under test through the test platform, and use the fast Fourier transform to obtain the oscillation frequency f exp ; use the relational expression between the oscillation frequency f exp and the junction capacitance and the parasitic parameters of the platform to inversely deduce the initial junction capacitance C of the device under test ossvalue to generate an initial junction capacitance C oss - test voltage u dc data set;

[0042] Specifically, in step 2, the device under test is connected to the extraction circuit, and the turn-off transient oscillation is excited under different test voltages u dc conditions, the time-domain waveform is collected, and the turn-off transient time-domain waveforms of the semiconductor device under different test voltages are as Figure 2 shown, and the measured oscillation frequency is calculated using the following formula:

[0043]

[0044] where L loop is the platform parasitic inductance, C serial is the equivalent capacitance of the power device, and C oss is the output junction capacitance of the device under test; in this embodiment, L loop , C serial need to be pre-measured, and the measurement steps are as follows:

[0045] Pre-short the experimental platform to obtain the switching transient oscillation frequency f 0 , and connect a capacitor with a known capacitance value of C add in parallel to the switching transistor to obtain the switching transient oscillation frequency f add .

[0046] where The value of L loop , C serial can be calculated inversely from the measured frequencies.

[0047] Step 3: Use the hyperbolic tangent function to fit the initial junction capacitance C oss - test voltage u dc data set generated in step 2, optimize the fitting parameters using the least squares method, and obtain a preliminary junction capacitance C oss - test voltage u dc relationship curve;

[0048] Specifically, the specific expression for the hyperbolic tangent function fitting in step 3 is:

[0049] C oss = C 0 + A·tanh(B·u dc );

[0050] where C 0 , A and B are fitting parameters to be determined by the least squares method; in this embodiment, the fitting parameter steps are as follows:

[0051] 1. Set the fitting model as the hyperbolic tangent function shown above.

[0052] 2. The data set is the voltage u dc , and the initial capacitance value is C oss .

[0053] 3. Set C 0 , and the initial values of parameters A and B are 35000, 35000, and -0.001 respectively.

[0054] 4. Obtain the optimal fitting result according to the least square method. C 0 is 24508.6625, and A and B are 19344.8979 and -0.0043888 respectively;

[0055] Step 4. Build an oscillation frequency simulation circuit as shown in Figure 3 , simulate the dynamic behavior of the output junction capacitance C oss , obtain the simulation frequency f m , and compare f m with f exp to judge the accuracy of the fitting curve;

[0056] Specifically, in Step 4, the transient behavior of the device under test at different test voltages is simulated through the following formula:

[0057]

[0058] where i oss (t) is the transient current, C oss (u ds (t)) is the junction capacitance corresponding to the voltage u ds (t), u ds (t) is the drain-source voltage during the turn-off transient oscillation process, and i load (t) is the load current;

[0059] It should be noted that for C oss forming the oscillation waveform, the change of u ds will cause the change of C oss . Therefore, in actual operation, the C oss at each moment is obtained from the voltage-capacitance curve obtained from the previous round of fitting according to the voltage. The specific process is as shown in Figure 3 .

[0060] Functional module 1: Determine the C oss values at different voltages during the oscillation process in the relationship curve of the junction capacitance C dc -test voltage u oss .

[0061] Functional module 2: Used to simulate the voltage change during the turn-off transient oscillation process. C during the turn-off transient processoss With the load current i load and u ds The relationship can be expressed by Equation (1). Therefore, functional module 2 can calculate the voltage value at the next moment through C oss and u ds and i load at each moment, as shown in Equation (2). The calculation result is output to the drain-source voltage u ds , completing the transient simulation of the oscillation process. Performing a fast Fourier transform on the transient time-domain waveform of the formed u ds can obtain the simulation oscillation frequency f m .

[0062] Step 5: If there is a deviation between f m and f exp , then fine-tune the C oss values corresponding to each voltage point in the fitting curve, update the junction capacitance C oss -test voltage u dc data set, and refit using the hyperbolic tangent function; in this embodiment, the maximum test error between the adjusted capacitance value and the capacitance value in the previous round is 5.5%. If the maximum error between the adjusted capacitance value and the capacitance value in the previous round does not meet the convergence condition, continue fitting and iteration. In this embodiment, the maximum error is 5.5%, so continue iterative optimization, and continue fitting and iteration; the parameter C 0 obtained by fitting is 24566.2855, and A and B are 19708.2705 and -0.0043313 respectively.

[0063] Step 6: Repeat the iterative process of Step 4 and Step 5 until the error between the fitting results of two adjacent rounds meets the preset convergence condition, and the iterative process terminates. More specifically, in this embodiment, the error convergence threshold is set to 2%. When the relative error between the C oss values obtained by fitting two adjacent rounds is lower than 2%, the iterative process terminates. After the second fitting adjustment, the maximum test error between the capacitance value and the capacitance value in the previous round is 1.9%, meeting the condition of iterative convergence, and obtaining the output junction capacitance C Figure 4 -test voltage u oss relationship curve optimized by each round of iteration as shown in dc , thereby obtaining the final accurate output junction capacitance C oss -test voltage u dc relationship curve; as shown in Figure 4As shown in the figure, to verify the measurement accuracy of the method, the output junction capacitance measurement curve in the embodiment is compared with the corresponding data sheet, and the maximum measurement error does not exceed 0.1%; which proves the measurement accuracy of the present invention. Based on the analysis of the turn-off transient oscillation, the present invention significantly reduces the oscillation frequency deviation caused by the nonlinearity of the junction capacitance through multiple rounds of fitting iteration, improving the measurement accuracy. Combining experimental data and theoretical fitting, it is possible to dynamically correct the measurement error at different voltage points, especially showing superiority in the strongly nonlinear region. This method can be applied to the measurement of the nonlinear characteristics of different types of semiconductor devices (such as MOSFET, IGBT, etc.). And good measurement results are shown on semiconductor discrete devices or modules of the 3.3 kV level.

[0064] The above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The substitution can be the substitution of some structures, devices, and method steps, or a complete technical solution. Any equivalent substitution or change made according to the technical solution of the present invention and its inventive concept should be covered within the protection scope of the present invention.

Claims

1. A semiconductor nonlinear output junction capacitance measurement method based on fitting iteration, characterized in that: The following steps are involved: Step 1, build a semiconductor device junction capacitance extraction circuit; Step 2: Initial data acquisition: Connect the device under test to the junction capacitance extraction circuit, obtain the turn-off transient waveform of the device under test through the test platform, and use fast Fourier transform to obtain the oscillation frequency f exp ; Using the oscillation frequency f exp The relationship between the junction capacitance and platform parasitic parameters is used to infer the initial junction capacitance C of the device under test. oss value, combined with the actual test voltage u dc , generating the initial junction capacitance C oss -Test voltage u dc Datasets; Step 3: Preliminary fitting: Use the hyperbolic tangent function to fit the initial junction capacitance C generated in step 2. oss -Test voltage u dc The data set is fitted and the least squares method is used to optimize the fitting parameters to obtain the preliminary junction capacitance C oss -Test voltage u dc Relationship curve; Step 4: Simulate frequency matching; build an oscillation frequency simulation circuit and simulate the output junction capacitance C oss Dynamic behavior of the simulation frequency f m , and f m With f exp Compare and judge the accuracy of the fitting curve; Step 5: Iterative optimization of fitting curve; if f m With f exp There is a deviation between the C and the voltage points in the fitting curve. oss value to fine-tune the junction capacitance C oss -Test voltage u dc The data set was refitted using the hyperbolic tangent function; Step 6. Obtain the final accurate output junction capacitance C oss -Test voltage u dc Relationship curve; Repeat the iterative process of step 4 and step 5 until the error of the fitting results of two consecutive rounds meets the preset convergence condition, thereby obtaining the final accurate output junction capacitance C oss -Test voltage u dc Relationship curve.

2. The semiconductor nonlinear output junction capacitance measurement method based on fitting iteration according to claim 1, characterized in that: The semiconductor device junction capacitance test platform in step 1 comprises: a DC power supply unit u connected in series in sequence dc , DUT port, diode D, load inductance L load A power device S is connected in parallel at both ends of the DUT port. The power device S, the diode and the DC power supply unit form a shutdown transient oscillation circuit. When the test voltage is high, the power device S can be divided by connecting multiple devices in series.

3. The semiconductor nonlinear output junction capacitance measurement method based on fitting iteration according to claim 1, characterized in that: In step 2, the device under test is connected to the extraction circuit and tested at different test voltages u dc The shutdown transient oscillation is excited under the conditions, the time domain waveform is collected, and the measured oscillation frequency is calculated using the following formula: Among them, L loop is the platform parasitic inductance, C serial is the equivalent capacitance of the power device, C oss is the output junction capacitance of the device under test.

4. The semiconductor nonlinear output junction capacitance measurement method based on fitting iteration according to claim 1, characterized in that: The specific expression of the hyperbolic tangent function fitting in step 3 is: C oss =C0+A·tanh(B·u dc ); Among them, C0, A and B are the parameters to be fitted, which are determined by the least squares method.

5. The semiconductor nonlinear output junction capacitance measurement method based on fitting iteration according to claim 1, characterized in that: Step 4 simulates the transient behavior of the device under test at different test voltages by the following formula: Among them, i oss (t) is the transient current, C oss (u ds (t)) is the voltage u ds (t) The corresponding junction capacitance, u ds (t) is the drain-source voltage during the turn-off transient oscillation process, i load (t) is the load current.

6. The semiconductor nonlinear output junction capacitance measurement method based on fitting iteration according to claim 1, characterized in that: In step 6, when the C oss When the relative errors between the values ​​are all less than the set error threshold, the iteration process is terminated and the final accurate output junction capacitance C is output. oss -Test voltage u dc Relationship curve.

Images