Display substrate and display panel

Abstract

The invention provides a display substrate and a display panel, and belongs to the technical field of display. The display substrate comprises a substrate body, a plurality of grid lines, a plurality of data lines and a plurality of sub-pixels, wherein the grid lines, the data lines and the sub-pixels are arranged on the substrate body. The plurality of sub-pixels form a plurality of first pixel groups arranged side by side along a first direction and a plurality of second pixel groups arranged side by side along a second direction; a first area is defined between any two adjacent first pixel groups, and a second area is defined between any two adjacent second pixel groups; common electrode wires are further arranged in at least part of the first areas, and the common electrode wires and the data lines are located in different first areas; the common electrode line comprises a plurality of common electrode line segments and bosses connected between the two common electrode line segments, and the width of the bosses in any direction is larger than that of the common electrode line segments in the first direction; the boss is located in the second area.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a display substrate and a display panel. Background Art

[0002] A thin film transistor liquid crystal display (TFT-LCD) is an important flat panel display device. With the development of display technology, high resolution, high transmittance, large size, low power consumption, and low cost have become the development direction of the future display field. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate and a display panel.

[0004] An embodiment of the present disclosure provides a display substrate, which includes: a substrate; a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels disposed on the substrate; the plurality of sub-pixels form a plurality of first pixel groups arranged side by side in a first direction and a plurality of second pixel groups arranged side by side in a second direction; each of the plurality of first pixel groups includes a plurality of the sub-pixels arranged side by side in the second direction; each of the plurality of second pixels includes a plurality of the sub-pixels arranged side by side in the first direction; one gate line is disposed on each side of each second pixel group in the second direction; for two adjacent sub-pixels in any one of the second pixel groups, the gate line connected to one of them is located on one side of the opposite sides of the sub-pixel in the second direction, and the gate line connected to the other one is located on the other side of the opposite sides of the sub-pixel in the second direction; each sub-pixel in each two adjacent first pixel groups is connected to the same data line, and each sub-pixel connected to the same data line is connected to a different gate line; wherein, a first region is defined between any two adjacent first pixel groups, and a second region is defined between any two adjacent second pixel groups; a common electrode line is further disposed in at least part of the first region, and the common electrode line and the data line are located in different first regions;

[0005] The common electrode line includes a plurality of common electrode line segments, and a boss connected between the two common electrode line segments, and the width of the boss in any direction is greater than the width of the common electrode line segment in the first direction; the boss is located in the second region.

[0006] Wherein, a thin film transistor and a pixel electrode are disposed in the sub-pixel; the gate of the thin film transistor is connected to the gate line, the source is connected to the data line, and the drain is connected to the pixel electrode;

[0007] Each of the pixel electrodes within the same second pixel group forms a pixel electrode group, and thin film transistors located within any two adjacent sub-pixels in the same second pixel group are respectively located on two opposite sides of the pixel electrode group in the second direction.

[0008] Among them, for any two thin film transistors connected to the same data line and located within sub-pixels of two adjacent first pixel groups, the connection node of one of them to the data line is the first node, and the connection node of the other to the data line is the second node. Taking the midpoint of the first node and the second node as the center of symmetry, the two thin film transistors are centrosymmetric.

[0009] Among them, the data line includes a plurality of data line segments and connection line segments connecting two adjacent data line segments; the connection line segment includes a first sub-connection line segment and a second sub-connection line; the first sub-connection line is connected to the data line segment through the second sub-connection segment; the first sub-connection line segment is located in the second region; the source electrode of the thin film transistor is connected to the first sub-connection line segment; the extension direction of the data line segment forms an angle of 5° to 10° with the first direction; the angle formed by the second sub-connection line segment and the data line segment is 100° to 130°.

[0010] Among them, a common electrode is further provided within the pixel region; one of the pixel electrode and the common electrode is a slit electrode, and the other is a plate-shaped electrode; the extension direction of the slit of the slit electrode is the same as the extension direction of the data line segment.

[0011] Among them, the extension direction of the common electrode line segment is the same as the extension direction of the data line segment.

[0012] Among them, the display substrate includes a first metal layer provided on the substrate; the first metal layer includes the data line, the common electrode line, the source electrode and the drain electrode of the thin film transistor.

[0013] Among them, the display substrate includes a second metal layer provided on the substrate; the second metal layer includes the gate line and the gate electrode of the thin film transistor.

[0014] Among them, the display substrate includes a second metal layer, a first interlayer insulating layer, a semiconductor layer, a first transparent conductive layer, a first metal layer, a second interlayer insulating layer, and a second transparent conductive layer sequentially provided in a direction away from the substrate.

[0015] The first metal layer includes the data line, the common electrode line, the source electrode and the drain electrode of the thin film transistor.

[0016] The second metal layer includes the gate line and the gate of the thin film transistor;

[0017] The first transparent conductive layer includes the pixel electrode;

[0018] The second transparent conductive layer includes the common electrode.

[0019] Wherein, the data line and the common electrode line are alternately arranged in the first direction.

[0020] Wherein, the positive projection of the gate of the thin film transistor on the substrate covers the positive projection of the semiconductor active layer on the substrate; wherein,

[0021] The positive projection of the gate on the substrate includes a first side and a second side arranged oppositely in the first direction, and a third side and a fourth side arranged oppositely in the second direction; the positive projection of the semiconductor active layer on the substrate includes a fifth side and a sixth side arranged oppositely in the first direction, and a seventh side and an eighth side arranged oppositely in the second direction;

[0022] The fourth side is connected to the positive projection of the gate line on the substrate;

[0023] The first side is opposite to the fifth side, and the distance therebetween is S1; the second side and the sixth side are arranged oppositely, and the distance therebetween is S2; the third side and the seventh side are arranged oppositely, and the distance therebetween is S3; at least one of S1, S2, and S3 is less than 3 μm. Wherein, the width of any one of the bosses in any direction is greater than the width of the common electrode line segment in the first direction; and the sizes of all the bosses are the same.

[0024] An embodiment of the present disclosure provides a display panel, which includes the above-mentioned display substrate.

[0025] Wherein, the display panel further includes a counter substrate arranged opposite to the display substrate, and spacers located between the display substrate and the counter substrate; the positive projection of one spacer on the substrate is located within the positive projection of one boss on the substrate.

[0026] Wherein, the spacers include a first spacer and a second spacer; the height of the first spacer is greater than the height of the second spacer; and both ends of the first spacer are respectively abutted against the display substrate and the counter substrate.

[0027] Among them, the first spacer and the second spacer are both evenly arranged in the display panel, and the ratio of the arrangement density of the first spacer to that of the second spacer is 1:30 to 1:70. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a cross-sectional view of an exemplary display panel.

[0029] Figure 2 is Figure 1 a top view of an array substrate in the display panel.

[0030] Figure 3 is Figure 2 the layout of the array substrate shown.

[0031] Figure 4 is Figure 2 an equivalent circuit diagram of a sub-pixel in the array substrate.

[0032] Figure 5 This is the layout of an array substrate according to an embodiment of the present disclosure.

[0033] Figure 6 This is a schematic diagram of a common electrode line in the array substrate according to an embodiment of the present disclosure.

[0034] Figure 7 is a schematic diagram of a display panel applying the array substrate according to an embodiment of the present disclosure.

[0035] Figure 8 This is a schematic diagram of a data line in the array substrate according to an embodiment of the present disclosure.

[0036] Figure 9 This is the layout of a second metal layer in the array substrate according to an embodiment of the present disclosure.

[0037] Figure 10 This is the layout of a semiconductor layer in the array substrate according to an embodiment of the present disclosure.

[0038] Figure 11 is the layout of forming a semiconductor layer on a substrate on which a first insulating layer is formed.

[0039] Figure 12 This is the layout of a first transparent conductive layer in the array substrate according to an embodiment of the present disclosure.

[0040] Figure 13 This is the layout of a first metal layer in the array substrate according to an embodiment of the present disclosure.

[0041] Figure 14 is the layout of forming a first metal layer on a substrate on which a first transparent conductive layer is formed.

[0042] Figure 15 The layout of the second transparent conductive layer in the array substrate according to the embodiment of the present disclosure.

[0043] Figure 16 The layout of the display panel according to the embodiment of the present disclosure. Detailed implementation manners

[0044] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "include" or "comprise" mean that the elements or objects appearing before the term cover the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0046] Figure 1 It is a cross-sectional view of an exemplary display panel; as Figure 1As shown, the display panel includes a display substrate and a counter substrate disposed opposite to each other, and a liquid crystal layer disposed between the display substrate and the counter substrate. The display substrate and the counter substrate are aligned (i.e., a liquid crystal cell is formed) by a sealant disposed in the peripheral region Q2, and the alignment of the liquid crystal cell is maintained by spacers PS disposed in the display region Q1. Among them, the display substrate may be an array substrate, and the counter substrate may be a color filter substrate; of course, the display substrate may also be a COA (Color On Array; the color filter layer is disposed on the array substrate) substrate. In this case, no color filter layer will be disposed on the counter substrate. In the disclosed embodiments, the display substrate is an array substrate and the counter substrate is a color filter substrate as an example for illustration. Among them, the array substrate includes a substrate 10, sub-pixels disposed on the substrate 10, and the sub-pixels include thin film transistors TFTs, pixel electrodes 12, and common electrodes 14. Among them, a first interlayer insulating layer 11 is disposed between the gate and the semiconductor active layer of the thin film transistor TFT, and a second interlayer insulating layer 12 is disposed between the layer where the source and drain of the thin film transistor TFT are located and the layer where the common electrode is located. The color filter substrate includes a substrate 10' and a color filter layer disposed on the substrate 10'. Among them, the color filter layer includes color filter films and a black matrix, and the black matrix BM is used for light shielding and is disposed corresponding to the positions of non-light-transmitting elements such as thin film transistors TFTs on the array substrate. The color filter films are used for color display and are disposed corresponding to the positions where the pixel electrodes 12 are located. Figure 1 Only the red color filter film R is schematically shown therein. In an actual display panel, green and blue color filter films may also be included to achieve color display of the display panel.

[0047] Figure 2 is Figure 1 a top view of the array substrate in the display panel; Figure 3 is Figure 2 the layout of the array substrate shown in; as Figure 2 and 3As shown, the array substrate is a dual - gate array substrate, which may include a substrate 10, a plurality of sub - pixels P disposed on the substrate 10; the sub - pixels P on the substrate 10 form a plurality of first pixel groups P10 arranged side by side in the first direction X and a plurality of second pixel groups P20 arranged side by side in the second direction Y; each first pixel group P10 includes a plurality of sub - pixels P arranged side by side in the second direction Y; each second pixel group P20 includes a plurality of sub - pixels P arranged side by side in the first direction X. A gate line GL is disposed on each side of each second sub - pixel P group in the second direction Y. For two adjacent sub - pixels P in any second pixel group P20, the gate line GL connected to one of them is located on one side of the two opposite sides of this sub - pixel P in the second direction Y, and the gate line GL connected to the other one is located on the other side of the two opposite sides of this sub - pixel P in the second direction Y; each sub - pixel P in each two adjacent first pixel groups P10 is connected to the same data line DL, and the sub - pixels P connected to the same data line DL are connected to different gate lines GL.

[0048] Figure 4 is Figure 2 the equivalent circuit diagram of a sub - pixel in the array substrate of; as Figure 3 shown, the equivalent circuit includes a thin - film transistor TFT, a storage capacitor Cst, and a liquid - crystal capacitor Clc; the first pole of the thin - film transistor TFT is connected to the data line DL, the second pole of the thin - film transistor TFT is connected to the first electrode plate of the storage capacitor Cst and the first electrode plate of the liquid - crystal capacitor Clc, and the control pole of the thin - film transistor TFT is connected to the gate line GL; the second electrode plate of the storage capacitor Cst is connected to the reference voltage terminal Vref; the second electrode plate of the liquid - crystal capacitor Clc is connected to the common voltage signal. When a working - level signal is written to the gate line GL, the thin - film transistor TFT is turned on, and the display of the corresponding gray level is achieved through the data - line DL voltage signal written on the data line DL.

[0049] In addition, the transistors adopted in the embodiments of the present disclosure may be thin film transistors (TFTs), field effect transistors, or other switching devices with the same characteristics. The thin film transistors (TFTs) may include oxide semiconductor thin film transistors (TFTs), amorphous silicon thin film transistors (TFTs), polycrystalline silicon thin film transistors (TFTs), etc. Each transistor includes a first pole, a second pole, and a control pole; wherein, the control pole serves as the gate of the transistor, and one of the first pole and the second pole serves as the source of the transistor, and the other serves as the drain of the transistor; and the source and drain of the transistor may be symmetric in structure, so there may be no difference in their physical structures. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate serving as the control pole, it is directly described that the first pole is the source and the second pole is the drain. Therefore, the sources and drains of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed.

[0050] Figure 3 For Figure 2 the layout of the array substrate shown; in combination with Figure 1 and 3 as shown, the array substrate includes a substrate 10, a second metal layer 20, a first interlayer insulating layer 11, a semiconductor layer 30, a first transparent conductive layer 40, a first metal layer 50, a second interlayer dielectric layer, and a second transparent conductive layer 60, which are sequentially disposed on the substrate 10. Among them, the second metal layer 20 includes gate lines GL and the gates of the thin film transistors (TFTs) in each sub-pixel P, and the gates of the thin film transistors (TFTs) in each sub-pixel P in the same second pixel and the connected gate lines GL are of an integrally formed structure. The semiconductor layer 30 includes the semiconductor active layers of the thin film transistors (TFTs) in each sub-pixel P, and the semiconductor active layer in each thin film transistor (TFT) and its gate at least partially overlap in the orthographic projection on the substrate 10. The first transparent electrode layer includes pixel electrodes 12 in each sub-pixel P. The second metal layer 20 includes data lines DL, common electrode lines CL, and the sources and drains of the thin film transistors (TFTs) in each sub-pixel P. Among them, the drain of each thin film transistor (TFT) is overlapped with the pixel electrode 12; the data line DL and the sources of the thin film transistors (TFTs) connected thereto are of an integral structure. The second transparent electrode layer includes common electrodes 14 in each sub-pixel P. Since the common electrode 14 is located on the side of the pixel electrode 12 away from the substrate 10, the common electrode 14 adopts a slit electrode.

[0051] Continuing to refer to FIG. 4, the thin film transistors (TFTs) in the sub-pixels P in the second pixel group P20 that are connected to the same data line DL and are arranged adjacent to each other are located between two gate lines GL that are between these two adjacent second pixel groups P20. When this array substrate is applied to a display panel, the position where the spacer is located exactly corresponds to the position of the thin film transistor (TFT), and the end of the slit of the slit electrode has a corner. When the number of pixels per inch (Pixels Per Inch; abbreviated as PPI) reaches 300 or more, that is, when the size of the sub-pixel P is less than or equal to 25.6 μm, according to Figure 4 the pixel layout design, compared with a conventional display panel, the aperture ratio will decrease by more than 6%.

[0052] Figure 5 is a layout of an array substrate according to an embodiment of the present disclosure; Figure 6 is a schematic diagram of a common electrode line in the array substrate according to an embodiment of the present disclosure; as Figure 5 and 6 shown, the embodiment of the present disclosure provides an array substrate that Figure 1 is similar to the array substrate shown in Figure 2As shown, a plurality of sub-pixels P form a plurality of first pixel groups P10 arranged side by side along a first direction X, and a plurality of second pixel groups P20 arranged side by side along a second direction Y. Each first pixel group P10 includes a plurality of sub-pixels P arranged side by side along the second direction Y; each second pixel group P20 includes a plurality of sub-pixels P arranged side by side along the first direction X. A gate line GL is provided on each side of each second pixel group P20 in the second direction Y. At this time, two gate lines GL are provided between any two adjacent second pixel groups P20. For two adjacent sub-pixels P in any second pixel group P20, one of the gate lines GL connected thereto is located on one side of the two opposite sides of the sub-pixel P in the second direction Y, and the other gate line GL connected thereto is located on the other side of the two opposite sides of the sub-pixel P in the second direction Y; each sub-pixel P in each two adjacent first pixel groups P10 is connected to the same data line DL, and the sub-pixels P connected to the same data line DL are connected to different gate lines GL; wherein, a first region Q11 is defined between any two adjacent first pixel groups P10, and a second region Q12 is defined between any two adjacent second pixel groups P20; a common electrode line CL is provided in at least part of the first region Q11, and the common electrode line CL and the data line DL are located in different first regions Q11; that is to say, if a data line DL is provided between two adjacent first pixel groups P10, no common electrode line CL is provided between these two adjacent first pixel groups P10. In the embodiment of the present disclosure, the common electrode line CL includes a plurality of common electrode segments 101 and a boss 102 connected between the two common electrode segments 101, and the width of at least one boss 102 in any direction is greater than the width of the common electrode segment 101 in the first direction X; the boss 102 is located in the second region Q12.

[0053] It should be noted that Figure 7 is a schematic diagram of a display panel using the array substrate of the embodiment of the present disclosure; as Figure 7 shown, the display panel includes an array substrate 200 and a color filter substrate 300 arranged oppositely, and spacers provided therebetween. The array substrate 200 is the array substrate in the embodiment of the present disclosure, Figure 7These are only exemplary drawings and do not illustrate the specific structures of each film layer. When the array substrate in the embodiments of the present disclosure is applied to a display panel, the spacer PS for maintaining the cell gap of the display panel and the boss whose width in any direction is greater than the width of the common electrode line segment 101 in the first direction X are correspondingly arranged. That is, the orthographic projection of a spacer on the substrate 10 is located within the orthographic projection of a boss 102 on the substrate 10. Generally, the spacers PS in the display panel are divided into a first spacer PS1 and a second spacer PS2. Among them, the first spacer PS1 is higher than the second spacer PS2, and the area of the orthographic projection of the first spacer PS1 on the substrate 10 is larger than the area of the orthographic projection of the second spacer PS2 on the substrate 10. At this time, the first spacer PS1 serves as the main spacer to maintain the cell gap of the display panel; the second spacer PS2 serves as the secondary spacer to play a buffering role when an external force acts on the display panel. In the embodiments of the present disclosure, by forming the boss 102 on the common electrode line CL and arranging the spacer at the corresponding position of the boss 102, the problem of uneven aperture ratio of each sub-pixel P caused by different spacer sizes can be effectively avoided.

[0054] In some examples, with continued reference to Figure 6 , the shape of the boss 102 can be any shape such as a polygon, a circle, an ellipse, etc., and the shape of the boss 102 is not limited in the embodiments of the present disclosure. Figure 6 Only the circular boss 102 is taken as an example for illustration in

[0055] In some examples, for all the bosses 102 on any common electrode line CL, the width in any direction is greater than the width of the common electrode line segment 101 in the first direction X. Further, all the bosses 102 have the same size. In this case, when the common electrode line CL uses a non-transparent material, that is, the boss 102 is a non-transparent region, the aperture ratio of the display substrate can be ensured to be consistent, thereby improving the display uniformity. In the embodiments of the present disclosure, the description is also made taking the sizes of the respective bosses 102 as being the same as an example, but this does not constitute a limitation on the protection scope of the embodiments of the present disclosure.

[0056] In some examples, with continued reference to Figure 5 , a thin film transistor TFT and a pixel electrode 12 are disposed in each sub-pixel P. The gate of the thin film transistor TFT is connected to the gate line GL, the source of the thin film transistor TFT is connected to the data line DL, and the drain of the thin film transistor TFT is connected to the pixel electrode 12. The pixel electrodes 12 of any of the sub-pixels P in the second pixel group P20 form a pixel electrode group, and the thin film transistors TFT in any two adjacent sub-pixels P in the same second pixel group P20 are respectively located on two opposite sides of the pixel electrode group in the second direction Y. For example: as Figure 5As shown, for any two adjacent thin film transistors (TFTs) in the same sub-pixel P within the second pixel group P20, one is located on the upper side of the pixel electrode group, and the other is located on the lower side. From Figure 5 it can be seen that each thin film transistor (TFT) within the sub-pixel P is located on the side of the gate line GL closer to the pixel electrode 12. Therefore, compared with Figure 2 the array substrate shown, the distance between two thin film transistors (TFTs) located within the adjacent second pixel groups P20 and connected to the same data line DL is increased. Thus, the risk of short circuit between the source and drain of these two thin film transistors (TFTs) can be effectively reduced.

[0057] Of course, each sub-pixel P not only includes the pixel electrode 12 but may also be provided with a common electrode 14. When the pixel electrode 12 is arranged closer to the substrate 10 than the common electrode 14, the pixel electrode 12 is a plate-shaped electrode and the common electrode 14 is a slit electrode; when the common electrode 14 is arranged closer to the substrate 10 than the pixel electrode 12, the common electrode 14 is a plate-shaped electrode and the pixel electrode 12 is a slit electrode. In the following description of the embodiments of the present disclosure, the case where the pixel electrode 12 is a plate-shaped electrode and the common electrode 14 is a slit electrode is taken as an example, but this does not limit the protection scope of the embodiments of the present disclosure. Further, the extending direction of the slit in each common electrode 14 is a single direction, that is, there are no corners at both ends of each slit. In this way, the aperture ratio of each sub-pixel P can be ensured to be uniform. For example: the extending direction of the slit is substantially the same as the extending direction of the common electrode line segment 101, or even completely the same. Herein, the extending direction of the slit being substantially the same as the extending direction of the common electrode line segment 101 means that the included angle between their extending directions and the first direction X differs by within 5°. Of course, each slit may not adopt a straight-line opening, but may also be a broken-line opening. The opening trend of the slit does not limit the protection scope of the embodiments of the present disclosure.

[0058] In some examples, continue to refer to Figure 5, in the array substrate, thin film transistors TFTs that are connected to the same data line DL and are within the sub-pixels P of two adjacent first pixel groups P10 are centrosymmetric. That is to say, for any two thin film transistors TFTs that are connected to the same data line and are within the sub-pixels P of two adjacent first pixel groups P10, the connection node of one of them to the data line DL is the first node a, and the connection node of the other to the data line DL is the second node b. Taking the midpoint c of the first node a and the second node b as the center of symmetry, the two thin film transistors TFTs are centrosymmetric. For example, two thin film transistors TFTs that are connected to the same data line DL and are in diagonal positions are centrosymmetric. Of course, not only are the thin film transistors TFTs that are connected to the same data line DL and are within the sub-pixels P of two adjacent first pixel groups P10 centrosymmetric, but also the pixel electrodes 12 and the common electrodes 14 are both centrosymmetric. Through this setting method, the consistency of the aperture ratio of each sub-pixel P is ensured.

[0059] In some examples, Figure 8 is a schematic diagram of the data line in the array substrate of the embodiment of the present disclosure; as Figure 8As shown, for any data line DL, it includes a plurality of data line segments 201, and connection line segments 202 connecting two adjacent data line segments 201. The connection line segment 202 includes a first sub-connection line segment 202a and two second sub-connection line segments 202b. Both ends of the first sub-connection line segment 202a are connected to a second sub-connection line segment 202b respectively, and the data line segment 201 is connected through the second sub-connection line segment 202b. Among them, the data line segment 201 is located in the first region Q11, the first sub-connection line segment 202a is located in the second region Q12, and the second sub-connection line segment 202b can be located in the first region Q11, or can be located in the second region Q12, or can be partially located in the first region Q11 and partially located in the second region Q12. The extension lines of the data line segments 201 located in an odd number coincide, the extension lines of the data line segments 201 located in an even number coincide, and the extension lines of the data line segments 201 located in an odd number and the extension lines of the data line segments 201 located in an even number are parallel. The source electrode of the thin film transistor TFT in each sub-pixel P is connected to the first sub-connection line segment 202a. The included angle between the extension direction of the data line segment 201 and the second direction Y is about 5° - 10°; the included angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is about 100° - 130°. For example: when the included angle between the extension direction of the data line segment 201 and the second direction Y is 10°, the included angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is 125°. Another example: when the included angle between the extension direction of the data line segment 201 and the second direction Y is 5°, the included angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is 130°. Another example: when the included angle between the extension direction of the data line segment 201 and the second direction Y is 7°, the included angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is 132°. That is to say, there is a corner at the position where the data line DL is connected to the thin film transistor TFT, and through this setting method, the aperture of each sub-pixel P can be increased. In the embodiment of the present disclosure, preferably, the included angle between the extension direction of the data line segment 201 and the second direction Y is 10°, and the included angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is 125°. Through experimental verification, when the included angle between the extension direction of the data line segment 201 and the second direction Y is 10°, and the included angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is 125°, compared with the case where the included angle between the extension direction of the data line segment 201 and the second direction Y is 5°, and the included angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is 130°, the pixel aperture ratio can be increased by 2.29%; compared with the case where the included angle between the extension direction of the data line segment 201 and the second direction Y is 7°, and the included angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is 130°, the pixel aperture ratio can be increased by 1.76%.

[0060] Further, the data lines DL and the common electrode lines CL are alternately arranged, and the extending directions of the data line segments 201 and the common electrode line segments 101 are the same. That is, among the adjacent first regions Q11, one is provided with the data line DL and the other is provided with the common electrode line CL. In this way, the arrangement rule of the sub-pixels P in the array substrate can be made, so that the transmittance of each sub-pixel P can be ensured to be uniform.

[0061] In some examples, the array substrate in the embodiments of the present disclosure may include a first metal layer 50, and the first metal layer 50 includes the common electrode line CL and the data line DL, as well as the source and drain electrodes of the thin film transistor TFT; that is, the common electrode line CL and the data line DL in the array substrate, as well as the source and drain electrodes of the thin film transistor TFT are arranged on the same layer and have the same material. In this case, the patterns including the common electrode line CL and the data line DL, as well as the source and drain electrodes of the thin film transistor TFT can be formed by one patterning process. Among them, since the source of each thin film transistor TFT needs to be connected to the data line DL, at this time, the source of the thin film transistor TFT and the data line DL connected thereto can be an integrally formed structure.

[0062] In some examples, the array substrate in the embodiments of the present disclosure may include a second metal layer 20, and the second metal layer 20 includes the gate lines GL and the gates of the respective thin film transistors TFT. In this case, the patterns including the gate lines GL and the gates of the respective thin film transistors TFT can be formed by one patterning process. Since the gate of each thin film transistor TFT needs to be connected to the gate line GL, at this time, the gate of the thin film transistor TFT and the gate line GL connected thereto can adopt an integrally formed structure.

[0063] To make the structure of the array substrate in the embodiments of the present disclosure clearer, the following combines Figure 5 , and Figure 5 The layout of each film layer of the shown array substrate is used to describe the array substrate in the embodiments of the present disclosure in detail.

[0064] As Figure 5 shown, the array substrate includes: a substrate 10, a plurality of sub-pixels P disposed on the substrate 10, a plurality of gate lines GL and a plurality of data lines DL. Among them, each sub-pixel P is internally provided with a thin film transistor TFT, a pixel electrode 12 and a common electrode 14. From the perspective of film layers, the array substrate includes a substrate 10, a second metal layer 20, a first interlayer insulating layer 11, a semiconductor layer 30, a first transparent conductive layer 40, a first metal layer 50, a second interlayer insulating layer 13 and a second transparent conductive layer 60 which are sequentially disposed on the substrate 10. Next, the structures of each film layer will be described.

[0065] Figure 9Layout of the second metal layer in the array substrate according to an embodiment of the present disclosure; as Figure 9 shown, the second metal layer 20 includes gate lines GL and gates of thin film transistors TFT in each sub-pixel P, and the gate lines GL and the gates 301 of the thin film transistors TFT connected thereto are integrally formed structures. In some examples, the material of the second metal layer 20 includes, but is not limited to, conductive materials such as molybdenum Mo, molybdenum niobium alloy, aluminum Al, aluminum neodymium alloy, titanium Ti, or copper Gu. The second metal layer 20 can be a single-layer structure or a multi-layer structure, such as a Ti / Al / Ti three-layer structure.

[0066] In some examples, the first interlayer insulating layer 11 serves as a gate insulating layer and is disposed between the gates of the thin film transistors TFT and the semiconductor active layer. The material of the first interlayer insulating layer 11 can be selected from materials with a lattice structure similar to that of Si, such as SixNy or SixOy: silicon nitride or silicon oxide. Specifically, it can be a single-layer structure of silicon nitride or silicon oxide, and of course, a composite film layer structure of silicon nitride or silicon oxide can also be used.

[0067] Figure 10 Layout of the semiconductor layer in the array substrate according to an embodiment of the present disclosure; as Figure 10 shown, the semiconductor layer 30 includes semiconductor active layers 302 of thin film transistors TFT in each sub-pixel P. Among them, the semiconductor active layer 302 includes an active layer pattern (channel region) and a doping region pattern (source-drain doping region) of the thin film transistors TFT in each sub-pixel P. For example, the semiconductor layer 30 can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above source region and drain region can be regions doped with n-type impurities or p-type impurities. Of course, the material of the semiconductor layer 30 can also include oxide semiconductors, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO). In the embodiment of the present disclosure, the material of the semiconductor layer 30 is low-temperature polycrystalline silicon as an example for illustration. Figure 11 Layout for forming a semiconductor layer on a substrate on which a first insulating layer is formed; as Figure 11As shown, the orthographic projection of a semiconductor active layer and a gate on a substrate 10 overlaps. In the embodiments of the present disclosure, the orthographic projection of the gate of the thin-film transistor on the substrate covers the orthographic projection of the active layer on the substrate; wherein, the orthographic projection of the gate on the substrate includes a first side (left) and a second side (right) oppositely arranged along a first direction, and a third side (top) and a fourth side (bottom) oppositely arranged along a second direction; the orthographic projection of the semiconductor active layer on the substrate includes a fifth side (left) and a sixth side (right) oppositely arranged along the first direction, and a seventh side (top) and an eighth side (bottom) oppositely arranged along the second direction; the fourth side (bottom) of the gate is connected to the orthographic projection of the gate line on the substrate (that is, the gate of the thin-film transistor and the gate line connected thereto are an integral structure); the first side of the gate is opposite to the fifth side of the semiconductor active layer, and the distance therebetween is S1; the second side of the gate and the sixth side of the semiconductor active layer are oppositely arranged, and the distance therebetween is S2; the third side of the gate and the seventh side of the semiconductor active layer are oppositely arranged, and the distance therebetween is S3; at least one of S1, S2, and S3 is less than 3 μm. In some examples, S1 = S2 = S3 = 2.75 μm. However, it should be understood that the values of S1, S2, and S3 can be specifically set according to the display panel size and pixel aperture ratio requirements. In the embodiments of the present disclosure, at least one of S1, S2, and S3 being less than 3 μm helps the display panel to achieve a high PPI design and can increase the pixel aperture ratio. When S1 = S2 = S3 = 2.75 μm, the pixel aperture ratio can increase by more than 6.5%.

[0068] Figure 12 is the layout of the first transparent conductive layer in the array substrate of the embodiments of the present disclosure; as Figure 10 shown, the first transparent conductive layer 40 includes pixel electrodes 12 in each sub-pixel P. In some examples, the material of the first transparent conductive layer 40 includes transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0069] Figure 13 is the layout of the first metal layer in the array substrate of the embodiments of the present disclosure; Figure 14 is the layout of forming the first metal layer on the substrate on which the first transparent conductive layer is formed; as Figure 13 and 14As shown, the first metal layer 50 includes data lines DL, common electrode lines CL, and the source and drain 303 of thin film transistors TFT within each sub-pixel P. Among them, the source of each thin film transistor TFT and the data line DL connected thereto are of an integrally formed structure. The source and drain 303 of the thin film transistor TFT are respectively connected to the source region and drain region of the semiconductor active layer. At the same time, the drain 303 of the thin film transistor TFT is also electrically connected to the pixel electrode 12. In some examples, the first metal layer 50 includes, but is not limited to, a single-layer or multi-layer metal structure formed by molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal layer stack, such as a three-layer metal stack of titanium, aluminum, and titanium (Al / Ti / Al), etc.

[0070] In some examples, the second interlayer insulating layer 13 is formed on the side of the first metal layer 50 facing away from the substrate 10. The second interlayer insulating layer 13 can be a passivation layer (PVX), and this passivation layer can be formed of materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0071] Figure 15 This is the layout of the second transparent conductive layer in the array substrate of the embodiment of the present disclosure; as Figure 5 and 15 shown, the second transparent conductive layer 60 includes common electrodes 14 within each sub-pixel P, and the second transparent conductive layer 60 is electrically connected to the common electrode line CL through vias penetrating the second interlayer insulating layer 13. In some examples, the material of the second transparent conductive layer 60 can be the same as that of the first transparent conductive layer 40. Thus, the introduction of the array substrate in the embodiment of the present disclosure is completed.

[0072] Figure 16 This is the layout of the display panel of the embodiment of the present disclosure; as Figure 16 shown, in the embodiment of the present disclosure, a display panel is also provided. The display panel includes the above-mentioned array substrate and a counter substrate disposed opposite to the array substrate. The counter substrate can be a color filter substrate, and in the embodiment of the present disclosure, the case where the counter substrate is a color filter substrate is taken as an example for description. Of course, the array substrate further includes a liquid crystal layer disposed between the array substrate and the color filter substrate, and spacers PS for maintaining the cell thickness. The orthographic projection of a spacer PS on the substrate 10 is located within the orthographic projection of a protrusion on the common electrode line CL on the substrate 10.

[0073] In some examples, it is also possible to refer to Figure 7, the spacers in the display panel are divided into a first spacer PS1 and a second spacer PS2. Among them, the height of the first spacer PS1 is higher than that of the second spacer PS2, and the area of the orthographic projection of the first spacer PS1 on the substrate 10 is larger than the area of the orthographic projection of the second spacer PS2 on the substrate 10. At this time, the first spacer PS1 serves as the main spacer to maintain the cell thickness of the display panel; the second spacer PS2 serves as the secondary spacer to play a buffering role when an external force acts on the display panel. In the embodiments of the present disclosure, by forming a boss 102 on the common electrode line CL and arranging the spacers at the corresponding positions of the boss 102, the problem of uneven aperture ratio of each sub-pixel P caused by different spacer sizes can be effectively avoided.

[0074] Further, the first spacer PS1 and the second spacer PS2 in the embodiments of the present disclosure can both be formed on the color filter substrate 300. In this case, there is a certain distance between the second spacer PS2 and the array substrate 200. Of course, the first spacer PS1 and the second spacer PS2 can also both be formed on the array substrate 200. In this case, there is a certain distance between the second spacer PS2 and the color filter substrate 200.

[0075] In some examples, the first spacer PS1 and the second spacer PS2 in the display panel are evenly arranged, and the ratio of the arrangement density of the first spacer PS1 to the arrangement density of the second spacer PS2 is about 1:30 to 1:70. For example: the arrangement density of the first spacer PS1 is 1 / 108, the arrangement density of the second spacer PS2 is 52 / 108, and the ratio of the arrangement density of the first spacer PS1 to the arrangement density of the second spacer PS2 is 1:52. Another example: the arrangement density of the first spacer PS1 is 1 / 72, the arrangement density of the second spacer PS2 is 34 / 72, and the ratio of the arrangement density of the first spacer PS1 to the arrangement density of the second spacer PS2 is 1:34. It should be noted that the arrangement density of the first spacer PS1 and the arrangement density of the second spacer PS2 depend on parameters such as the size of the display panel and the orthographic projection area of the first spacer PS1 and the second spacer PS2 on the substrate 10. The display panel in the embodiments of the present disclosure can achieve a PPI of more than 300 due to including the above-mentioned array substrate, and is particularly suitable for projector projects.

[0076] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A display substrate, which comprises: a substrate substrate, a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels disposed on the substrate substrate; the plurality of sub-pixels form a plurality of first pixel groups arranged side by side in a first direction and a plurality of second pixel groups arranged side by side in a second direction; each of the plurality of first pixel groups includes a plurality of the sub-pixels arranged side by side in the second direction; each of the plurality of second pixels includes a plurality of the sub-pixels arranged side by side in the first direction; one gate line is disposed on each of the two sides of each second pixel group in the second direction; for two adjacent sub-pixels in any one of the second pixel groups, the gate line connected to one of them is located on one of the opposite sides of the sub-pixel in the second direction, and the gate line connected to the other is located on the other of the opposite sides of the sub-pixel in the second direction; each of the sub-pixels in every two adjacent first pixel groups is connected to the same data line, and the sub-pixels connected to the same data line are connected to different gate lines; wherein, a first region is defined between any two adjacent first pixel groups, and a second region is defined between any two adjacent second pixel groups; a common electrode line is further disposed in at least part of the first region, and the common electrode line and the data line are located in different first regions; the common electrode line includes a plurality of common electrode segments, and bosses connected between the two common electrode segments, and the width of at least one of the bosses in any direction is greater than the width of the common electrode segment in the first direction; the bosses are located in the second region; the extending directions of the two common electrode segments connected to both sides of the same boss do not overlap.

2. The display substrate according to claim 1, wherein, a thin film transistor and a pixel electrode are disposed in the sub-pixel; the gate of the thin film transistor is connected to the gate line, the source is connected to the data line, and the drain is connected to the pixel electrode; the pixel electrodes in the same second pixel group form a pixel electrode group, and the thin film transistors in any two adjacent sub-pixels in the same second pixel group are respectively located on two opposite sides of the pixel electrode group in the second direction.

3. The display substrate according to claim 2, wherein, for any two thin film transistors in the sub-pixels that are connected to the same data line and are located in two adjacent first pixel groups, the connection node of one of them and the data line is the first node, and the connection node of the other and the data line is the second node. Taking the midpoint of the first node and the second node as the center of symmetry, the two thin film transistors are centrosymmetric.

4. The display substrate according to claim 3, wherein, the pixel electrode connecting the two thin film transistors is centrosymmetric with respect to the center of symmetry.

5. The display substrate according to claim 3, wherein, the common electrode connecting the two thin film transistors is centrosymmetric with respect to the center of symmetry.

6. The display substrate according to claim 2, wherein, The data line includes a plurality of data line segments, and connection line segments connecting two adjacent data line segments; the connection line segments include a first sub-connection line segment and a second sub-connection line segment, and the first sub-connection line segment is connected to the data line segment through the second sub-connection line segment; the first sub-connection line segment is located in the second region; the source electrode of the thin film transistor is connected to the first sub-connection line segment; the included angle between the extending direction of the data line segment and the second direction is 5° to 10°; the included angle formed by the second sub-connection line segment and the data line segment is 100° to 130°.

7. The display substrate according to claim 6, wherein, a common electrode is further provided in the sub-pixel; one of the pixel electrode and the common electrode is a slit electrode, and the other is a plate-shaped electrode; the extending direction of the slit of the slit electrode is the same as the extending direction of the data line segment.

8. The display substrate according to claim 7, wherein, the common electrode includes a first slit and a second slit, and in the direction perpendicular to the substrate, the first slit overlaps with the pixel electrode, and the second slit is located in the second region.

9. The display substrate according to claim 6, wherein, the extending direction of the common electrode line segment is the same as the extending direction of the data line segment.

10. The display substrate according to any one of claims 2-9, wherein, the display substrate includes a first metal layer provided on the substrate; the first metal layer includes the data line, the common electrode line, the source electrode and the drain electrode of the thin film transistor.

11. The display substrate according to any one of claims 2-9, wherein, the display substrate includes a second metal layer provided on the substrate; the second metal layer includes the gate line and the gate electrode of the thin film transistor.

12. The display substrate according to any one of claims 2-9, wherein, the display substrate includes a second metal layer, a first interlayer insulating layer, a semiconductor layer, a first transparent conductive layer, a first metal layer, a second interlayer insulating layer, and a second transparent conductive layer sequentially arranged in a direction away from the substrate; the first metal layer includes the data line, the common electrode line, the source electrode and the drain electrode of the thin film transistor; the second metal layer includes the gate line and the gate electrode of the thin film transistor; the first transparent conductive layer includes the pixel electrode; the second transparent conductive layer includes the common electrode.

13. The display substrate according to any one of claims 2-9, wherein, the data line and the common electrode line are alternately arranged in the first direction.

14. The display substrate according to any one of claims 2-9, wherein, the positive projection of the gate electrode of the thin film transistor on the substrate covers the positive projection of the semiconductor active layer on the substrate; wherein, The positive projection of the gate on the substrate includes a first side and a second side that are oppositely arranged along the first direction, and a third side and a fourth side that are oppositely arranged along the second direction; the positive projection of the semiconductor active layer on the substrate includes a fifth side and a sixth side that are oppositely arranged along the first direction, and a seventh side and an eighth side that are oppositely arranged along the second direction; The fourth side is connected to the positive projection of the gate line on the substrate; The first side is opposite to the fifth side, and the distance between them is S1; the second side and the sixth side are oppositely arranged, and the distance between them is S2; the third side and the seventh side are oppositely arranged, and the distance between them is S3; at least one of S1, S2, and S3 is less than 3 μm.

15. The display substrate according to claim 1, wherein, The width of any one of the bosses in any direction is greater than the width of the common electrode segment in the first direction; and the sizes of all the bosses are the same.

16. A display panel, which includes the display substrate according to any one of claims 1-15.

17. The display panel according to claim 16, wherein, It further includes a counter substrate disposed opposite to the display substrate, and spacers located between the display substrate and the counter substrate; the spacers are disposed at positions corresponding to the bosses.

18. The display panel according to claim 16, wherein, It further includes a counter substrate disposed opposite to the display substrate, and spacers located between the display substrate and the counter substrate; The positive projection of one of the spacers on the substrate is located within the positive projection of one of the bosses on the substrate.

19. The display panel according to claim 18, wherein, The spacers include a first spacer and a second spacer; the height of the first spacer is greater than the height of the second spacer; and both ends of the first spacer are in contact with the display substrate and the counter substrate respectively.

20. The display panel according to claim 19, wherein, Both the first spacer and the second spacer are evenly arranged in the display panel, and the density ratio of the arrangement of the first spacer to the arrangement of the second spacer is 1:30 to 1:

70.

21. The display panel according to claim 16, wherein, The projection of the boss on the substrate overlaps at least partially with the projections of two adjacent gate lines on the substrate.

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