Array substrate and display device

Abstract

The invention provides an array substrate and a display device. The array substrate comprises a substrate, and a first metal layer, a first insulating layer, a second insulating layer and a first electrode layer which are arranged on the surface of one side of the substrate, the first electrode layer comprises a first electrode pattern, and the first electrode pattern is electrically connected with the first metal layer through a first via hole and a second via hole; the orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the first via hole on the substrate; the ratio range of the overlapping area of the orthographic projection of the first electrode layer on the substrate and the orthographic projection of the second via hole on the substrate to the orthographic projection area of the second via hole on the substrate is larger than or equal to 0.85 and smaller than or equal to 0.99. The alignment liquid diffuses around the first electrode layer and the second via hole and is guided by the shape of the first electrode layer to diffuse into the resin hole, and uniform in-plane diffusion is achieved, so that small black spots are eliminated, uniform diffusion of the alignment liquid is facilitated, picture quality is improved, and picture unevenness is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to an array substrate and a display device. Background Art

[0002] In related technologies, as display devices are increasingly developing towards narrow borders, high refresh rates, high resolutions, and high pixels per inch (PPI), the display substrates used need to meet the requirements of increased pixel density and aperture ratio accordingly. The corresponding array substrates need to use active layer materials with high mobility, transistors with smaller sizes, and adopt small hole designs to improve the aperture ratio / transmittance, etc. Oxide materials have become a commonly used active layer material for transistors because of their certain transparency, relatively high mobility, and relatively simple preparation process. Usually, on the array substrate of a display panel, there are a gate metal layer, a source-drain metal layer, a semiconductor layer, an organic layer, an insulating layer, and two transparent conductive layers. The two transparent conductive layers are divided into a bottom transparent electrode and an upper transparent electrode. In display technology, it is necessary to drill holes in the organic layer (the organic layer can be a resin layer), and further etch an insulating layer hole in the middle to make the upper transparent conductive layer adjacent to the drain metal. However, it is necessary for the transparent electrode to effectively cover all the resin layer holes and insulating layer holes to prevent the etching solution from seeping in and corroding during the etching process. However, with a small high pixel density and small resin holes, when the transparent electrode completely covers the resin layer holes, it is not conducive to the alignment liquid to diffuse around the resin holes. Figure 1 It is a schematic diagram of the coating of the alignment liquid on the surface of the electrode plate. An APR (Asahi Photosensitive Resins) plate is hung on the plate ketone. The alignment liquid is carried on the APR. After being printed and pressed on the surface of the array substrate, it is transferred to the surface of the array substrate. The surface of the APR plate is densely dotted. Each dot is a convex platform, and the gap between the convex platforms carries the alignment liquid. When the transparent electrode effectively covers all the resin layer holes, the alignment liquid is not easy to diffuse evenly here, resulting in black dot defects on the grayscale display screen. Summary of the Invention

[0003] The main purpose of the present invention is to provide an array substrate and a display device, which solve the problem that in the existing array substrate, after being printed and pressed on the surface of the array substrate and transferred to the surface of the array substrate, the surface of the APR plate is densely dotted, each dot is a convex platform, and the gap between the convex platforms carries the alignment liquid. When the transparent electrode effectively covers all the resin layer holes, the alignment liquid is not easy to diffuse evenly here, resulting in black dot defects on the grayscale display screen.

[0004] In one aspect, an embodiment of the present invention provides an array substrate, including a substrate, and a first metal layer, a first insulating layer, a second insulating layer, and a first electrode layer provided on one surface of the substrate;

[0005] The first electrode layer includes a first electrode pattern, and the first electrode pattern is electrically connected to the first metal layer through a first via hole and a second via hole;

[0006] The first via hole is located in and penetrates the first insulating layer; the second via hole is located in and penetrates the second insulating layer;

[0007] The orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the first via hole on the substrate; the ratio of the overlapping area between the orthographic projection of the first electrode layer on the substrate and the orthographic projection of the second via hole on the substrate to the orthographic projection area of the second via hole on the substrate ranges from greater than or equal to 0.85 to less than or equal to 0.99.

[0008] Optionally, the first electrode layer has a plurality of separated opening structures, and at least one end of the opening structure orthographically projects on the substrate and partially overlaps with the orthographic projection of the second via hole on the substrate.

[0009] Optionally, the array substrate according to at least one embodiment of the present invention further includes a second electrode layer disposed between the second insulating layer and the first electrode layer;

[0010] The orthographic projection of the second electrode layer on the substrate does not overlap with the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate.

[0011] Optionally, the array substrate according to at least one embodiment of the present invention includes a plurality of rows of first signal lines, a plurality of columns of second signal lines disposed on the substrate, and a plurality of pixel units defined by the intersection of the first signal lines and the second signal lines;

[0012] Each pixel unit includes a first electrode pattern, a second electrode pattern, a first via hole, a second via hole, and a transistor; the transistor includes an active pattern;

[0013] The active pattern includes a first connection portion and a second connection portion;

[0014] The first connection portion is electrically connected to the second signal line through a third via hole; the second connection portion is electrically connected to the first electrode layer;

[0015] The third via hole and the first via hole are not in the same pixel unit.

[0016] Optionally, the array substrate according to at least one embodiment of the present invention includes a plurality of rows of first signal lines, a plurality of columns of second signal lines disposed on the substrate, and a plurality of pixel units defined by the intersection of the first signal lines and the second signal lines;

[0017] Each of the pixel units includes a first electrode pattern, a second electrode pattern, a first via hole, a second via hole, and a transistor; the transistor includes an active pattern.

[0018] Along the direction extending parallel to the first signal line, the maximum distance between the orthographic projection of the edge of the second via hole on the substrate and the orthographic projection of the edge of the first electrode pattern at the second via hole on the substrate is within a distance range.

[0019] Optionally, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other, and the pixel electrode groups include a plurality of pixel electrodes that are electrically connected to each other.

[0020] A first portion of the orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the first portion is close to the orthographic projection of the pixel electrode on the substrate.

[0021] A second portion of the orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the first portion and the second portion are disposed on opposite sides.

[0022] The second portion is close to the orthographic projection of the first signal line on the substrate.

[0023] Optionally, the edge of the orthographic projection of the second via hole on the substrate is an oblique rectangular, rectangular, or rounded rectangular shape.

[0024] The orthographic projection of the first signal line on the substrate is disposed on a first side of the orthographic projection of the second via hole on the substrate, and the orthographic projection of the pixel electrode on the substrate is disposed on a second side of the orthographic projection of the second via hole on the substrate; the first side and the second side are opposite sides.

[0025] The first portion is disposed at a corner of the orthographic projection of the second via hole on the substrate close to the pixel electrode and the active pattern, and the second portion is disposed at a corner of the orthographic projection of the second via hole on the substrate close to the first signal line and the first connection portion.

[0026] Optionally, a third portion of the orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the third portion is close to the orthographic projection of the first signal line on the substrate.

[0027] Optionally, the edge of the orthographic projection of the second via hole on the substrate is an oblique rectangular, rectangular, or rounded rectangular shape.

[0028] The third portion is disposed at a corner of the second via hole close to the first signal line and the active pattern.

[0029] Optionally, the second electrode pattern includes a common electrode and four auxiliary connection portions;

[0030] The common electrode included in one pixel unit is electrically connected to the common electrodes in four adjacent pixel units through the four auxiliary connection portions respectively;

[0031] The positive projections of two of the four auxiliary connection portions on the substrate partially overlap with the positive projections of the corresponding second signal lines on the substrate respectively;

[0032] The positive projections of the other two of the four auxiliary connection portions on the substrate partially overlap with the positive projections of the corresponding first signal lines on the substrate respectively.

[0033] Optionally, the distance range is greater than or equal to 0.8 μm and less than or equal to 1.2 μm; or,

[0034] The distance range is greater than or equal to a first distance threshold, and the first distance threshold is greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

[0035] Optionally, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes that are electrically connected to each other;

[0036] A fourth part of the positive projection of the second via on the substrate is not covered by the first electrode pattern, and the fourth part is close to the positive projection of the pixel electrode on the substrate.

[0037] Optionally, the edge of the positive projection of the second via on the substrate is an oblique rectangular, rectangular or rounded rectangular;

[0038] The fourth part is disposed at a corner of the positive projection of the second via on the substrate close to the pixel electrode and close to the active pattern.

[0039] Optionally, the distance range is greater than or equal to 1.8 μm and less than or equal to 2.2 μm; or,

[0040] The distance range is greater than or equal to a second distance threshold, and the second distance threshold is greater than or equal to 1.8 μm and less than or equal to 2.2 μm.

[0041] Optionally, the second electrode pattern includes a common electrode and a first auxiliary connection portion;

[0042] The common electrode included in one pixel unit is electrically connected to the common electrode in an adjacent pixel unit through the first auxiliary connection portion;

[0043] The orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with the orthographic projection of one of the second signal lines on the substrate.

[0044] Optionally, the edge of the orthographic projection of the second via hole on the substrate is an oblique rectangular, rectangular or rounded rectangular;

[0045] The fourth portion is disposed at a corner of the orthographic projection of the second via hole on the substrate close to the pixel electrode and far from the active pattern.

[0046] Optionally, the distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or,

[0047] The distance range is greater than or equal to a third distance threshold, and the third distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

[0048] Optionally, the second electrode pattern includes a common electrode, a first auxiliary connection portion and a second auxiliary connection portion;

[0049] The common electrode included in one pixel unit is electrically connected to the common electrode included in a pixel unit adjacent to and in the same row as this pixel unit through the first auxiliary connection portion; the orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate;

[0050] The common electrode included in one pixel unit is electrically connected to the common electrode included in a pixel unit adjacent to and in the same column as this pixel unit through the second auxiliary connection portion; the orthographic projection of the second auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate.

[0051] Optionally, the edge of the orthographic projection of the second via hole on the substrate is a polygon;

[0052] The fourth portion is disposed at a corner of the orthographic projection of the second via hole on the substrate far from the pixel electrode and the active pattern.

[0053] Optionally, the second electrode pattern includes a common electrode, a first auxiliary connection portion and a second auxiliary connection portion;

[0054] The common electrode included in one pixel unit is electrically connected to the common electrode included in a pixel unit adjacent to and in the same row as this pixel unit through the first auxiliary connection portion; the orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with the orthographic projection of one of the second signal lines on the substrate;

[0055] The common electrode included in one of the pixel units is electrically connected to the common electrode included in a pixel unit that is in the same column as and adjacent to this pixel unit through the second auxiliary connection portion, and the orthographic projection of the second auxiliary connection portion on the substrate partially overlaps with the orthographic projection of one of the first signal lines on the substrate.

[0056] Optionally, the edge of the orthographic projection of the second via on the substrate is an oblique rectangular, rectangular or rounded rectangular shape;

[0057] The first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes that are electrically connected to each other;

[0058] The orthographic projection of the pixel electrode on the substrate is located on the second side of the orthographic projection of the second via on the substrate;

[0059] The lower edge of the orthographic projection of the connection pattern on the substrate is partially consistent with the edge of the orthographic projection of the second via on the substrate; and / or, the upper edge of the orthographic projection of the connection pattern on the substrate is partially consistent with the edge of the orthographic projection of the second via on the substrate.

[0060] Optionally, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes that are electrically connected to each other;

[0061] The orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second via on the substrate.

[0062] Optionally, the distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or,

[0063] The distance range is greater than or equal to a fourth distance threshold, and the fourth distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

[0064] Optionally, the edge of the orthographic projection of the second via on the substrate is a polygon.

[0065] In a second aspect, an embodiment of the present invention provides a display device, including the above-mentioned array substrate.

[0066] An embodiment of the present invention provides an array substrate and a display device. The orthographic projection of the first electrode layer on the substrate partially covers the orthographic projection of the second via hole on the substrate, so that the alignment liquid diffuses around the first electrode layer and the second via hole under the guidance of the shape of the first electrode layer and diffuses into the resin holes, achieving uniform in-plane diffusion, thereby eliminating small black dots. For high-PPI (pixel density) display products and ultra-high PPI display products, the oxide process and the organic film process are beneficial to the uniform diffusion of the alignment liquid, improving the picture quality and reducing picture unevenness. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 is a schematic diagram of the coating of the alignment liquid on the substrate surface;

[0068] Figure 2 is a planar layout diagram of the array substrate according to at least one embodiment of the present invention;

[0069] Figure 3A and Figure 3B is Figure 2 a partially enlarged planar layout diagram in;

[0070] Figure 4 is Figure 3A a planar layout diagram of the gate metal layer in;

[0071] Figure 5 is Figure 3A a planar layout diagram of the semiconductor layer in;

[0072] Figure 6A and Figure 6B is a planar layout diagram of the source-drain metal layer in FIG. 3;

[0073] Figure 7A is Figure 3A a schematic diagram of the layout diagram of the orthographic projection of the second via hole H2 on the substrate in;

[0074] Figure 7B is Figure 3A a superposition schematic diagram of the second via hole and the first electrode layer in;

[0075] Figure 8A is Figure 3A a planar layout diagram of the second electrode layer in;

[0076] Figure 8B is Figure 3A a planar layout diagram of the stack of the second electrode layer, the gate metal layer and the source-drain metal layer in;

[0077] Figure 9A and Figure 9B is Figure 3A a planar layout diagram of the first electrode layer in;

[0078] Figure 10 is Figure 3A a stacked diagram of a first electrode layer, a second via, and a first via therein;

[0079] Figure 11 is a planar layout diagram of an array substrate according to at least one embodiment of the present invention;

[0080] Figure 12A and Figure 12B is Figure 11 a locally enlarged planar layout diagram therein;

[0081] Figure 13 is Figure 12A a planar layout diagram of a gate metal layer therein;

[0082] Figure 14 is Figure 12A a planar layout diagram of a semiconductor layer therein;

[0083] Figure 15 is Figure 12A a planar layout diagram of a source-drain metal layer therein;

[0084] Figure 16A is Figure 12A a layout diagram of a positive projection of a second via on a substrate therein;

[0085] Figure 16B is Figure 12A a stacked schematic diagram of a second via and a first electrode layer therein;

[0086] Figure 17A is Figure 12A a planar layout diagram of a second electrode layer therein;

[0087] Figure 17B is Figure 12A a stacked planar layout diagram of a second electrode layer, a gate metal layer, and a source-drain metal layer therein;

[0088] Figure 18A and Figure 18B is Figure 12A a planar layout diagram of a first electrode layer therein;

[0089] Figure 19 is Figure 12A a stacked schematic diagram of a first electrode layer, a second via, and a first via therein;

[0090] Figure 20 is a layout diagram of an array substrate according to at least one embodiment of the present invention;

[0091] Figure 21A and Figure 21B is Figure 20 a locally enlarged planar layout diagram therein;

[0092] Figure 22 is Figure 21A the planar layout diagram of the gate metal layer in

[0093] Figure 23 is Figure 21A the planar layout diagram of the semiconductor layer in

[0094] Figure 24 is Figure 21A the planar layout diagram of the source / drain metal layer in

[0095] Figure 25A is Figure 21A the layout diagram of the orthographic projection of the second via on the substrate in

[0096] Figure 25B is Figure 21A the stacked schematic diagram of the second via and the first electrode layer in

[0097] Figure 26A is Figure 21A the planar layout diagram of the second electrode layer in

[0098] Figure 26B is the stacked planar layout diagram of the second electrode layer and the source / drain metal layer in Figure 21;

[0099] Figure 27A and Figure 27B is Figure 21A the planar layout diagram of the first electrode layer in

[0100] Figure 28 is Figure 21A the stacked schematic diagram of the first electrode layer, the second via, and the first via in

[0101] Figure 29 is the planar layout diagram of the array substrate according to at least one embodiment of the present invention;

[0102] Figure 30A and Figure 30B is Figure 29 the locally enlarged planar layout diagram in

[0103] Figure 31 is Figure 30A the planar layout diagram of the gate metal layer in

[0104] Figure 32 is Figure 30A the planar layout diagram of the semiconductor layer in

[0105] Figure 33 is Figure 30A the planar layout diagram of the source / drain metal layer in

[0106] Figure 34A isFigure 30A The plan layout diagram of the orthographic projection of the second via hole in

[0107] Figure 34B on the substrate; Figure 30A The stack schematic diagram of the second via hole and the first electrode layer in

[0108] Figure 35A is Figure 30A The plan layout diagram of the second electrode layer in

[0109] Figure 35B is Figure 30A The plan layout diagram of the stack of the second electrode layer and the first electrode layer in

[0110] Figure 36A and Figure 36B is Figure 30A The plan layout diagram of the first electrode layer in

[0111] Figure 37 is Figure 30A The stack schematic diagram of the first electrode layer, the second via hole and the first via hole in

[0112] Figure 38A and Figure 38B is the plan layout diagram of the array substrate according to at least one embodiment of the present invention;

[0113] Figure 39 is Figure 38A The plan layout diagram of the gate metal layer in

[0114] Figure 40 is Figure 38A The plan layout diagram of the semiconductor layer in

[0115] Figure 41 is Figure 38A The plan layout diagram of the source-drain metal layer in

[0116] Figure 42A is Figure 38A The plan layout diagram of the second via hole in

[0117] Figure 42B is Figure 38A The stack schematic diagram of the second via hole and the first electrode layer in

[0118] Figure 43A is Figure 38A The plan layout diagram of the second electrode layer in

[0119] Figure 43B is Figure 38A The plan layout diagram of the stack between the second electrode layer and the source-drain metal layer in

[0120] Figure 44A andFigure 44B is Figure 38A the planar layout of the first electrode layer in

[0121] Figure 45 is Figure 38A the superimposed view of the first electrode layer and the second via in

[0122] Figure 46 In at least one embodiment of the present invention, it is the layout diagram of the second via H2;

[0123] Figure 47A and Figure 47B In at least one embodiment of the present invention, it is the planar layout diagram of the first electrode layer;

[0124] Figure 48 In at least one embodiment of the present invention, it is the superimposed view of the first electrode layer, the first via and the second via;

[0125] Figure 49 In at least one embodiment of the present invention, it is the layout diagram of the second via H2;

[0126] Figure 50A and Figure 50B In at least one embodiment of the present invention, it is the planar layout diagram of the first electrode layer;

[0127] Figure 51 In at least one embodiment of the present invention, it is the superimposed view of the first electrode layer, the first via and the second via. Detailed implementation manners

[0128] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0129] The transistors used in all embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two poles of the transistor other than the gate, one of the poles is called the first pole and the other pole is called the second pole.

[0130] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be the drain and the second pole can be the source; or, the first pole can be the source and the second pole can be the drain.

[0131] The array substrate according to the embodiment of the present invention includes a substrate, and a first metal layer, a first insulating layer, a second insulating layer, and a first electrode layer arranged in sequence along a direction away from the substrate;

[0132] The first electrode layer includes a first electrode pattern; the first electrode pattern is electrically connected to the first metal layer through a first via hole and a second via hole;

[0133] The first via hole is located in and penetrates the first insulating layer; the second via hole is located in and penetrates the second insulating layer;

[0134] The orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the first via hole on the substrate; the ratio of the overlapping area of the orthographic projection of the first electrode layer on the substrate and the orthographic projection of the second via hole on the substrate to the orthographic projection area of the second via hole on the substrate ranges from greater than or equal to 0.85 to less than or equal to 0.99.

[0135] The embodiment of the present invention provides an array substrate. The orthographic projection of the first electrode layer on the substrate partially covers the orthographic projection of the second via hole on the substrate, so that the alignment liquid diffuses around the first electrode layer and the second via hole under the guidance of the shape of the first electrode layer and diffuses into the resin holes, achieving uniform in-plane diffusion, thereby eliminating small black dots. For high-PPI (pixel density) display products and ultra-high PPI display products, oxide processes and organic film processes are beneficial to the uniform diffusion of the alignment liquid, improving the picture quality and reducing picture unevenness.

[0136] In specific implementation, the first electrode pattern may completely cover the first via hole.

[0137] In the related art, the sizes of the first via hole (the first via hole may be a via hole penetrating the insulating layer) and the second via hole (the second via hole may be a via hole penetrating the organic layer) on high-PPI display products are small, and the first electrode layer completely covers the via holes to prevent the etching solution from infiltrating, resulting in uneven printing of the alignment liquid and forming small black dots in the grayscale picture.

[0138] Optionally, the first insulating layer may be an organic layer, the first electrode layer may be a pixel electrode layer, and the second electrode layer may be a common electrode layer.

[0139] In at least one embodiment of the present invention, the first electrode layer has a plurality of separated opening structures, and at least one end of at least one of the opening structures overlaps with the orthographic projection of the second via hole on the substrate.

[0140] In Figures 2 - 51 a coordinate system of X-Y is drawn, wherein the X direction is the first direction and the Y direction is the second direction. For example, the first direction X may be the horizontal direction, and the second direction Y may be the vertical direction.

[0141] Figure 2 It is a layout diagram of the array substrate according to at least one embodiment of the present invention.

[0142] In Figure 2 Among them, the one labeled 21 is the first electrode layer, and the one labeled 22 is the second electrode layer; the one labeled H1 is the first via hole, and the one labeled H2 is the second via hole.

[0143] Figure 3A And Figure 3B is Figure 2 A planar layout diagram of a partial area in

[0144] In Figure 3A Among them, the one labeled 21 is the first electrode layer, the one labeled 22 is the second electrode layer, the one labeled 23 is the gate metal layer, the one labeled 24 is the source-drain metal layer, and the one labeled 20 is the semiconductor layer.

[0145] In Figure 3B Among them, the one labeled PXZ is the pixel electrode group, the one labeled VCOM is the common electrode, the one labeled H1 is the first via hole, the one labeled H2 is the second via hole, the one labeled DL1 is the first data line, the one labeled DL2 is the second data line, the one labeled GL is the gate line, and the one labeled H3 is the third via hole.

[0146] Figure 4 is Figure 3A A planar layout diagram of the gate metal layer in Figure 5 is Figure 3A A planar layout diagram of the semiconductor layer in Figure 6A And Figure 6B is Figure 3A A planar layout diagram of the source-drain metal layer in Figure 7A is Figure 3A A schematic diagram of the layout diagram of the orthographic projection of the second via hole H2 on the substrate in Figure 7B is Figure 3A An overlay schematic diagram of the second via hole and the first electrode layer in Figure 8A is Figure 3A A planar layout diagram of the second electrode layer in Figure 8B is Figure 3A A planar layout diagram of the stack of the second electrode layer, the gate metal layer and the source-drain metal layer in Figure 9A And Figure 9B is Figure 3A A planar layout diagram of the first electrode layer in Figure 10 is Figure 3A A stack diagram of the first electrode layer, the second via hole and the first via hole in

[0147] In at least one embodiment of the present invention, the second signal line may include a first part, a second part, and a third part that are interconnected; the first part is the part of the second signal line that overlaps with the first signal line, and the width of the first part in the horizontal direction may be greater than the width of the third part in the horizontal direction, or the width of the first part in the horizontal direction may be the same as the width of the third part in the horizontal direction;

[0148] The second part may be a connecting part extending leftward from the second signal line, and the second part is used to overlap with the second connecting part included in the active pattern.

[0149] Optionally, the first signal line may be a gate line, and the second signal line may be a data line.

[0150] In Figure 6A , the one labeled DL1 is the first data line, and the one labeled DL2 is the second data line.

[0151] In Figure 6B , the second data line includes a first part B1, a second part B2, a first third part B13, and a second third part B23;

[0152] The width of the first part B1 in the horizontal direction is greater than the width of B13 in the horizontal direction; the width of the first part B1 in the horizontal direction is greater than the width of B23 in the horizontal direction;

[0153] The second part B2 is disposed on the left side of B13;

[0154] B1, B2, B13, and B23 are interconnected.

[0155] In Figure 6B , three dashed lines are drawn to separate the first part B1, the second part B2, the first third part B13, and the second third part B23.

[0156] In Figure 7A , the one labeled H2W is the edge of the positive projection of H2 on the substrate.

[0157] In Figure 9A , the one labeled PXZ is the pixel electrode, and the one labeled X1 is the connecting pattern; the connecting pattern X1 is interconnected with the pixel electrode PXZ, and the first electrode pattern includes the connecting pattern X1 and the pixel electrode group PXZ that are electrically connected to each other.

[0158] As Figure 9B shown, the first electrode layer includes a first opening structure K1, a second opening structure K2, and a third opening structure K3;

[0159] The first opening structure K1, the second opening structure K2, and the third opening structure K3 are separated from each other;

[0160] As Figure 3A and Figure 3B shown, the orthographic projection of one end of the first opening structure K1 on the substrate overlaps with the orthographic projection of the second via hole H2 on the substrate. As Figure 9B shown, a pixel electrode group includes a first pixel electrode PX1, a second pixel electrode PX2, a third pixel electrode PX3, and a fourth pixel electrode PX4 that are electrically connected to each other;

[0161] K1 is disposed between PX1 and PX2, K2 is disposed between PX2 and PX3, and K3 is disposed between PX3 and PX4.

[0162] As Figure 9A and Figure 9B shown, the one labeled X1 is a connection pattern.

[0163] As Figure 9B shown, the first dotted line for dividing the connection pattern X1 is a dotted line extending in the horizontal direction, which is used to separate the connection pattern X1 from the second pixel electrode PX2;

[0164] The second dotted line for dividing the connection pattern X1 is a dotted line extending in the vertical direction, which is used to separate the connection pattern X1 from the third pixel electrode PX3 and to separate the connection pattern X1 from the fourth pixel electrode PX4.

[0165] In at least one embodiment of the present invention, the array substrate may further include a second electrode layer disposed between the second insulating layer and the first electrode layer;

[0166] The orthographic projection of the second electrode layer on the substrate does not overlap with the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate.

[0167] Optionally, the second electrode layer may be a common electrode layer, and the second electrode layer may include a common electrode and an auxiliary connection pattern.

[0168] In a specific implementation, the second electrode layer may not cover the first via hole.

[0169] In at least one embodiment of the present invention, the first electrode layer may be an upper transparent electrode, and the second electrode layer may be a lower transparent electrode. The upper transparent electrode completely covers the first via hole, and the upper transparent electrode partially covers the second via hole. Therefore, the alignment liquid diffuses around the upper transparent electrode and the resin hole and is guided by the shape of the transparent electrode to diffuse into the second via hole, achieving uniform in-plane diffusion, thereby eliminating small black dots.

[0170] The array substrate according to at least one embodiment of the present invention includes multiple rows of first signal lines, multiple columns of second signal lines disposed on the substrate, and multiple pixel units defined by the intersection of the first signal lines and the second signal lines;

[0171] Each of the pixel units includes a first electrode pattern, a second electrode pattern, a first via, a second via, and a transistor; the transistor includes an active pattern;

[0172] The active pattern includes a first connection portion and a second connection portion;

[0173] The first connection portion is electrically connected to the second signal line through a third via; the second connection portion is electrically connected to the first electrode layer;

[0174] The third via and the first via are not in the same pixel unit.

[0175] Optionally, the first signal line can be a gate line, the second signal line can be a data line, the gate line can extend in a first direction, the data line can extend in a second direction, and the first direction intersects the second direction;

[0176] The first direction can be a horizontal direction, and the second direction can be a vertical direction; or, the first direction can be a vertical direction, and the second direction can be a horizontal direction.

[0177] As Figure 5 shown, the one labeled A0 is the active pattern of the transistor, the one labeled A01 is the first connection portion L1 included in the active pattern, and the one labeled A02 is the second connection portion L2 included in the active pattern A0;

[0178] As Figures 3B - 9B shown, the second connection portion L2 is electrically connected to the data line DL through the third via H3;

[0179] The third via H3 and the first via H1 are not in the same pixel unit.

[0180] In Figure 3B it, the one labeled P1 is the first pixel unit, and the one labeled P2 is the second pixel unit;

[0181] The gate line GL is disposed between the first pixel unit P1 and the second pixel unit P2;

[0182] The first data line DL1 is disposed on the left side of the first pixel unit P1, and the second data line DL2 is disposed on the right side of the first pixel unit P1.

[0183] In at least one embodiment of the present invention, along the direction parallel to the extension of the first signal line, the maximum distance between the orthographic projection of the edge of the second via on the substrate and the orthographic projection of the edge of the first electrode pattern at the second via on the substrate is within a distance range.

[0184] In a specific implementation, the orthographic projection of the edge of the first electrode pattern at the second via on the substrate is disposed within the orthographic projection of the second via on the substrate.

[0185] In at least one embodiment of the present invention, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes that are electrically connected to each other;

[0186] A first portion of the orthographic projection of the second via on the substrate is not covered by the first electrode pattern, and the first portion is close to the orthographic projection of the pixel electrode on the substrate;

[0187] A second portion of the orthographic projection of the second via on the substrate is not covered by the first electrode pattern, and the first portion and the second portion are disposed on opposite sides;

[0188] The second portion is close to the orthographic projection of the first signal line on the substrate.

[0189] In a specific implementation, a portion of the orthographic projection of the second via on the substrate is not covered by the first electrode pattern, the first electrode is close to the pixel electrode, a second portion of the orthographic projection of the second via on the substrate is not covered by the first electrode pattern, and the first portion and the second portion are disposed on opposite sides.

[0190] In at least one embodiment of the present invention, the array substrate further includes a second metal layer (the second metal layer may be a gate metal layer) disposed between the substrate and the first metal layer (the first metal layer may be a source-drain metal layer), and the second metal pattern on the second metal layer includes a first signal line;

[0191] The second portion is close to the orthographic projection of the first signal line on the substrate.

[0192] In a specific implementation, the second portion of the orthographic projection of the second via on the substrate is close to the orthographic projection of the first signal line on the substrate.

[0193] Optionally, the first signal line may be a gate line.

[0194] Such as Figure 3A 、 Figure 3B and Figure 10As shown, the orthographic projection of the first electrode pattern on the substrate partially covers the second via hole H2, but does not completely cover the second via hole H2; the common electrode VCOM does not cover the second via hole H2, and the first electrode pattern completely covers the first via hole H1.

[0195] A first portion H21 of the second via hole H2 on the substrate and a second portion H22 of the second via hole H2 on the substrate are not covered by the first electrode pattern;

[0196] The first portion H21 is close to the pixel electrode, and the second portion H22 is close to the gate line GL.

[0197] In Figure 3A 、 Figure 3B In at least one embodiment of the array substrate shown, there are insulating layers with different thicknesses separating the gate metal layer and the semiconductor layer, the source-drain metal layer and the common electrode layer, and the common electrode layer and the pixel electrode layer.

[0198] A first insulating layer (the first insulating layer can be an organic layer, and the organic layer can be a resin layer), a second insulating layer, and a first electrode layer (the first electrode layer can be a pixel electrode layer) can be provided between the first metal layer (the first metal layer can be a source-drain metal layer) and the first electrode layer. There are etching holes in the organic layer and part of the insulating layer for conducting the electrodes. The first electrode layer and the second electrode layer can be transparent conductive layers, and the transparent conductive layer is obtained by depositing indium tin oxide. The thickness of the transparent conductive layer can be greater than or equal to 400 angstroms and less than or equal to 900 angstroms.

[0199] In at least one embodiment of the present invention, the edge of the orthographic projection of the second via hole on the substrate can be an oblique rectangular, rectangular, or rounded rectangular shape;

[0200] The orthographic projection of the first signal line on the substrate is disposed on a first side of the orthographic projection of the second via hole on the substrate, and the orthographic projection of the pixel electrode on the substrate is disposed on a second side of the orthographic projection of the second via hole on the substrate; the first side and the second side are opposite sides;

[0201] The first portion is disposed at a corner of the orthographic projection of the second via hole on the substrate close to the pixel electrode and the active pattern, and the second portion is disposed at a corner of the orthographic projection of the second via hole on the substrate close to the first signal line and the first connection portion.

[0202] Optionally, the first side can be the lower side, and the second side can be the upper side.

[0203] As Figure 7A shown, the first portion H21 is close to each pixel electrode and the active pattern A0, and the second portion H22 is close to the gate line GL and the active pattern A0;

[0204] H21 is disposed at the upper right corner of the second via hole, and H22 is disposed at the lower right corner of the second via hole.

[0205] As Figure 7B shown, the upper right corner of the second via hole H2 and the lower right corner of the second via hole H2 are not covered by the first electrode pattern.

[0206] In a specific implementation, the edge of the orthographic projection of the second via hole on the substrate may be an oblique rectangular, rectangular or rounded rectangular shape. The orthographic projection of the gate line on the substrate is below the orthographic projection of the second via hole on the substrate, and the orthographic projection of the pixel electrode on the substrate is disposed above the orthographic projection of the second via hole on the substrate. The first part may be disposed at the upper right corner of the orthographic projection of the second via hole on the substrate, and the second part may be disposed at the lower right corner of the orthographic projection of the second via hole on the substrate.

[0207] In at least one embodiment of the present invention, the distance range may be greater than or equal to 0.8 μm and less than or equal to 1.2 μm; or,

[0208] the distance range may be greater than or equal to a first distance threshold, and the first distance threshold may be greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

[0209] In Figures 2 - 10 the corresponding at least one embodiment, along the direction parallel to the extension of the gate line GL, the maximum distance between the orthographic projection of the edge of the second via hole H2 on the substrate and the orthographic projection of the edge of the first electrode pattern at the second via hole H2 on the substrate is within the distance range;

[0210] The distance range is greater than or equal to 0.8 μm and less than or equal to 1.2 μm; or,

[0211] the distance range is greater than or equal to a first distance threshold, and the first distance threshold is greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

[0212] In at least one embodiment of the present invention, the second electrode pattern may include a common electrode and four auxiliary connection portions;

[0213] The common electrode included in one pixel unit is electrically connected to the common electrodes in four adjacent pixel units through the four auxiliary connection portions respectively;

[0214] The orthographic projections of two of the four auxiliary connection portions on the substrate partially overlap with the orthographic projections of the corresponding second signal lines on the substrate;

[0215] The orthographic projections of the other two auxiliary connection parts among the four auxiliary connection parts on the substrate respectively partially overlap with the orthographic projections of the corresponding first signal lines on the substrate.

[0216] As Figure 8A shown, the one labeled FL1 is the first auxiliary connection part, the one labeled FL2 is the second auxiliary connection part, and the one labeled FL3 is the third auxiliary connection part;

[0217] The common electrode VCOM is electrically connected to the common electrode on the left through FL1, the common electrode VCOM is electrically connected to the common electrode on the right through FL2, and the common electrode VCOM is electrically connected to the common electrode on the lower side through FL3;

[0218] As Figure 8B shown, the orthographic projection of FL1 on the substrate partially overlaps with the orthographic projection of the first data line DL1 on the substrate, the orthographic projection of FL2 on the substrate partially overlaps with the orthographic projection of the second data line DL2 on the substrate, and the orthographic projection of FL3 on the substrate partially overlaps with the orthographic projection of the gate line GL on the substrate.

[0219] In Figures 2 - 10 at least one embodiment shown, the common electrode VCOM can also be electrically connected to the common electrode above through a fourth auxiliary electrode part, and the orthographic projection of the fourth auxiliary electrode part on the substrate can partially overlap with the orthographic projection of the gate line above on the substrate.

[0220] As Figure 8A 、 Figure 8B shown, FL1 and FL2 extend in the horizontal direction, and FL3 extends in the vertical direction.

[0221] In at least one embodiment of the present invention, the array substrate further includes a second metal layer disposed between the substrate and the first metal layer, and the second metal pattern on the second metal layer includes a first signal line;

[0222] The third part of the orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the third part is close to the orthographic projection of the first signal line on the substrate.

[0223] In specific implementation, the third part of the orthographic projection of the second via hole on the substrate close to the orthographic projection of the first signal line on the substrate is not covered by the first electrode pattern.

[0224] In at least one embodiment of the present invention, the edge of the orthographic projection of the second via hole on the substrate can be an oblique rectangular, rectangular or rounded rectangular; the third part can be disposed at a corner of the orthographic projection of the second via hole on the substrate close to the first signal line and the active pattern.

[0225] Figure 11 It is a top - view layout diagram of the array substrate according to at least one embodiment of the present invention.

[0226] In Figure 11 it, the one labeled 21 is the first electrode layer, the one labeled 22 is the second electrode layer; the one labeled H1 is the first via - hole, and the one labeled H2 is the second via - hole.

[0227] Figure 12A and Figure 12B is Figure 11 a top - view layout diagram of a partial area in

[0228] Figure 13 is Figure 12A a top - view layout diagram of the gate metal layer in Figure 14 is Figure 12A a top - view layout diagram of the semiconductor layer in Figure 15 is Figure 12A a top - view layout diagram of the source - drain metal layer in Figure 16A is Figure 12A a top - view layout diagram of the orthographic projection of the second via - hole on the substrate in Figure 16B is Figure 12A a schematic diagram of the stack of the second via - hole and the first electrode layer in Figure 17A is Figure 12A a top - view layout diagram of the second electrode layer in Figure 17B is Figure 12A a top - view layout diagram of the stack of the second electrode layer, the gate metal layer and the source - drain metal layer in Figure 18A and Figure 18B is Figure 12A a top - view layout diagram of the first electrode layer in Figure 19 is Figure 12A a schematic diagram of the superposition of the first electrode layer, the second via - hole and the first via - hole in

[0229] In Figure 12A it, the one labeled 21 is the first electrode layer, the one labeled 22 is the second electrode layer, the one labeled 23 is the gate metal layer, the one labeled 24 is the source - drain metal layer, and the one labeled 20 is the semiconductor layer.

[0230] In Figure 12B it, the one labeled PXZ is the pixel electrode group, the one labeled VCOM is the common electrode, the one labeled H1 is the first via - hole, the one labeled H2 is the second via - hole, the one labeled GL is the gate line, the one labeled H3 is the third via - hole, the one labeled DL1 is the first data line, and the one labeled DL2 is the second data line.

[0231] In Figure 13 it, the one labeled GL is the gate line.

[0232] In Figure 14Among them, the one labeled as A0 is the active pattern; the one labeled as L1 is the first connection part, and the one labeled as L2 is the second connection part; as Figures 12A - 19 shown, the second connection part L2 is electrically connected to the second data line DL2 through the third via hole H3;

[0233] In Figure 15 it, the one labeled as DL1 is the first data line, and the one labeled as DL2 is the second data line;

[0234] In Figure 16A it, the one labeled as H2W is the edge of H2; the one labeled as H23 is the third part included in the orthographic projection of the second via hole H2 on the substrate; the third part H23 is arranged at the lower right corner of the second via hole H2.

[0235] As Figure 16B shown, the lower right corner of the second via hole H2 is not covered by the first electrode pattern.

[0236] As Figure 12B 、 Figure 14 and Figure 16A shown, the third part H23 is close to the gate line GL, and the third part H23 is close to the active pattern A0, and the third part H23 is arranged at the lower right corner of the second via hole.

[0237] In Figure 17A and Figure 17B it, the one labeled as VCOM is the common electrode;

[0238] As Figure 17A shown, the one labeled as FL1 is the first auxiliary connection part, the one labeled as FL2 is the second auxiliary connection part, and the one labeled as FL3 is the third auxiliary connection part;

[0239] The common electrode VCOM is electrically connected to the common electrode on the left through FL1, the common electrode VCOM is electrically connected to the common electrode on the right through FL2, and the common electrode VCOM is electrically connected to the common electrode on the lower side through FL3;

[0240] As Figure 17B shown, the orthographic projection of FL1 on the substrate overlaps with the orthographic projection of the first data line DL1 on the substrate in part, the orthographic projection of FL2 on the substrate overlaps with the orthographic projection of the second data line DL2 on the substrate in part, and the orthographic projection of FL3 on the substrate overlaps with the orthographic projection of the gate line GL on the substrate in part.

[0241] In Figures 11 - 19 at least one embodiment shown, the common electrode VCOM can also be electrically connected to the common electrode above through the fourth auxiliary electrode part, and the orthographic projection of the fourth auxiliary electrode part on the substrate can overlap with the orthographic projection of the gate line above on the substrate in part.

[0242] As Figure 17A 、 Figure 17B shown, FL1 and FL2 extend in the horizontal direction, and FL3 extends in the vertical direction.

[0243] In Figure 18A , the one labeled PXZ is the pixel electrode, and the one labeled X1 is the connection pattern. The connection pattern X1 is connected to the pixel electrode PX.

[0244] In Figure 18B , the one labeled PX1 is the first pixel electrode, the one labeled PX2 is the second pixel electrode, the one labeled PX3 is the third pixel electrode, and the one labeled PX4 is the fourth pixel electrode;

[0245] A first opening structure K1 is provided between PX1 and PX2, a second opening structure K2 is provided between PX2 and PX3, and a third opening structure K3 is provided between PX3 and PX4.

[0246] As Figure 18B shown, the first dashed line for dividing the connection pattern X1 is a dashed line extending in the horizontal direction, which is used to separate the connection pattern X1 from the first pixel electrode PX1;

[0247] The second dashed line for dividing the connection pattern X1 is a dashed line extending in the vertical direction, which is used to separate the connection pattern X1 from the second pixel electrode PX2, separate the connection pattern X1 from the third pixel electrode PX3, and separate the connection pattern X1 from the fourth pixel electrode PX4.

[0248] As Figures 11 - 19 shown, the third part H23 of the orthographic projection of the second via hole H2 on the substrate is not covered by the first electrode pattern, and the third part H23 is close to the orthographic projection of the gate line GL on the substrate;

[0249] As Figures 11 - 19 shown, the first electrode pattern completely covers the orthographic projection of the first via hole H1 on the substrate, and the first electrode pattern partially covers the orthographic projection of the second via hole H2 on the substrate; the common electrode VCOM does not cover the second via hole H2, and the first electrode pattern completely covers the first via hole H1;

[0250] The part of the orthographic projection of the second via hole on the substrate that is not covered by the first electrode pattern is the third part H23, and the third part H23 is close to the orthographic projection of the gate line on the substrate.

[0251] Optionally, the edge of the orthographic projection of the second via hole on the substrate is an oblique rectangular, rectangular or rounded rectangular;

[0252] The orthographic projection of the gate line on the substrate is below the orthographic projection of the second via hole on the substrate;

[0253] The third part is disposed at the lower right corner of the orthographic projection of the second via hole on the substrate.

[0254] In a specific implementation, the edge of the orthographic projection of the second via hole on the substrate can be an oblique rectangular, rectangular or rounded rectangular; the orthographic projection of the gate line on the substrate can be below the orthographic projection of the second via hole on the substrate; the third part can be disposed at the lower right corner of the orthographic projection of the second via hole on the substrate.

[0255] In Figures 11 - 19 In at least one embodiment of the array substrate shown, along the direction parallel to the extension of the gate line GL, the maximum distance between the orthographic projection of the edge of the second via hole H2 on the substrate and the orthographic projection of the edge of the first electrode pattern at the second via hole H2 on the substrate is within a distance range;

[0256] The distance range is greater than or equal to 0.8 μm and less than or equal to 1.2 μm; or,

[0257] The distance range is greater than or equal to a first distance threshold, and the first distance threshold is greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

[0258] In at least one embodiment of the present invention, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes that are electrically connected to each other;

[0259] The fourth part of the orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the fourth part is close to the orthographic projection of the pixel electrode on the substrate.

[0260] In a specific implementation, the fourth part of the orthographic projection of the second via hole on the substrate that is not covered by the first electrode pattern is close to the orthographic projection of the pixel electrode on the substrate.

[0261] Figure 20 is a layout diagram of the array substrate according to at least one embodiment of the present invention.

[0262] In Figure 20 , the one labeled 21 is the first electrode layer, and the one labeled 22 is the second electrode layer; the one labeled H1 is the first via hole, and the one labeled H2 is the second via hole.

[0263] Figure 21A And Figure 21B is Figure 20 a planar layout diagram of a partial area in

[0264] Figure 22 is Figure 21A a planar layout diagram of the gate metal layer inFigure 23 is Figure 21A a plan view of the semiconductor layer in Figure 24 is Figure 21A a plan view of the source-drain metal layer in Figure 25A is Figure 21A a plan view of the positive projection of the second via hole on the substrate in Figure 25B is Figure 21A a schematic diagram of the stack of the second via hole and the first electrode layer in Figure 26A is a plan view of the second electrode layer in FIG. 21, Figure 26B is a plan view of the stack of the second electrode layer and the source-drain metal layer in FIG. 21; Figure 27A and Figure 27B is Figure 21A a plan view of the first electrode layer in Figure 28 is Figure 21A a schematic diagram of the stack of the first electrode layer, the second via hole, and the first via hole in

[0265] In Figure 21A the component labeled 21 is the first electrode layer, the component labeled 22 is the second electrode layer, the component labeled 23 is the gate metal layer, the component labeled 24 is the source-drain metal layer, and the component labeled 20 is the semiconductor layer.

[0266] In Figure 21B the component labeled PXZ is the pixel electrode group, the component labeled VCOM is the common electrode, the component labeled H1 is the first via hole, the component labeled H2 is the second via hole, the component labeled GL is the gate line, the component labeled DL1 is the first data line, and the component labeled DL2 is the second data line.

[0267] In Figure 22 the component labeled GL is the gate line.

[0268] In Figure 23 the component labeled A0 is the active pattern;

[0269] In Figure 24 the component labeled DL is the data line;

[0270] In Figure 25A the component labeled H2W is the edge of H2; the component labeled H24 is the fourth part included in the positive projection of the second via hole H2 on the substrate;

[0271] In Figure 26A and Figure 26B the component labeled VCOM is the common electrode.

[0272] In Figure 27A the component labeled PXZ is the pixel electrode group, the component labeled X1 is the connection pattern, and the connection pattern X1 is connected to the pixel electrode group PXZ.

[0273] As shown in Figure 27B FIG. 1, the pixel electrode labeled PX1 is the first pixel electrode, the pixel electrode labeled PX2 is the second pixel electrode, the pixel electrode labeled PX3 is the third pixel electrode, the pixel electrode labeled PX4 is the fourth pixel electrode, and the pixel electrode labeled PX5 is the fifth pixel electrode;

[0274] A first opening structure K1 is provided between PX1 and PX2, a second opening structure K2 is provided between PX2 and PX3, a third opening structure K3 is provided between PX3 and PX4, and a fourth opening structure K4 is provided between PX4 and PX5.

[0275] As shown in Figure 27B FIG. 2, the first dotted line for dividing the connection pattern X1 is a dotted line extending in the horizontal direction, which is used to separate the connection pattern X1 from the second pixel electrode PX2 and separate the connection pattern X1 from the third pixel electrode PX3;

[0276] The second dotted line for dividing the connection pattern X1 is a dotted line extending in the vertical direction, which is used to separate the connection pattern X1 from the fourth pixel electrode PX4 and separate the connection pattern X1 from the fifth pixel electrode PX5;

[0277] The third dotted line for dividing the connection pattern X3 is used to separate the connection pattern X1 from the first pixel electrode PX1.

[0278] As shown in FIG. 21- Figure 28 FIG. 22, the fourth part H24 of the orthographic projection of the second via hole H2 on the substrate is not covered by the first electrode pattern, and the fourth part H24 is close to the orthographic projection of each pixel electrode on the substrate;

[0279] As shown in FIG. 21- Figure 28 FIG. 22, the first electrode pattern completely covers the orthographic projection of the first via hole on the substrate, and the first electrode pattern partially covers the orthographic projection of the second via hole on the substrate; the common electrode VCOM does not cover the second via hole H2, and the first electrode pattern completely covers the first via hole H1.

[0280] Optionally, the edge of the orthographic projection of the second via hole on the substrate is an oblique rectangular, rectangular or rounded rectangular;

[0281] The fourth part is disposed at a corner of the orthographic projection of the second via hole on the substrate close to the pixel electrode and far from the active pattern.

[0282] As shown in FIG. 21- Figure 28As shown, the edge of the positive projection of the second via hole on the substrate may be an oblique rectangular shape. The fourth part H24 is disposed at the upper left corner of the positive projection of H2 on the substrate. The positive projections of the respective pixel electrodes on the substrate are disposed above the positive projection of the second via hole H2 on the substrate, and the positive projection of the active pattern A0 on the substrate is disposed to the left of the positive projection of the second via hole H2 on the substrate.

[0283] Optionally, the distance range is greater than or equal to 1.8 μm and less than or equal to 2.2 μm; or,

[0284] the distance range is greater than or equal to a third distance threshold, and the third distance threshold is greater than or equal to 1.8 μm and less than or equal to 2.2 μm.

[0285] In at least one embodiment shown in FIG. 21- Figure 28 along the direction extending parallel to the gate line GL, the maximum distance between the positive projection of the edge of the second via hole H2 on the substrate and the positive projection of the edge of the first electrode pattern at the second via hole H2 on the substrate is within the distance range;

[0286] the distance range is greater than or equal to 1.8 μm and less than or equal to 2.2 μm; or,

[0287] the distance range is greater than or equal to a second distance threshold, and the first distance threshold is greater than or equal to 1.8 μm and less than or equal to 2.2 μm.

[0288] In at least one embodiment of the present invention, the second electrode pattern includes a common electrode and a first auxiliary connection portion;

[0289] the common electrode included in one pixel unit is electrically connected to the common electrode in an adjacent pixel unit through the first auxiliary connection portion;

[0290] The positive projection of the first auxiliary connection portion on the substrate partially overlaps with the positive projection of one of the second signal lines on the substrate.

[0291] As Figure 26B shown, the second electrode pattern includes a common electrode VCOM and a first auxiliary connection portion FL1;

[0292] The common electrode VCOM is electrically connected to the common electrode on the right through the first auxiliary connection portion FL1;

[0293] The positive projection of the first auxiliary connection portion FL1 on the substrate partially overlaps with the positive projection of the second data line DL2 on the substrate.

[0294] In at least one embodiment of the present invention, the edge of the orthographic projection of the second via on the substrate is an oblique-angled rectangle, a rectangle, or a rounded rectangle;

[0295] The fourth part is disposed at a corner of the orthographic projection of the second via on the substrate, close to the pixel electrode and away from the active pattern.

[0296] Optionally, the orthographic projection of the pixel electrode on the substrate may be disposed on the right side of the orthographic projection of the second via on the substrate, and the orthographic projection of the active pattern on the substrate may be disposed above the orthographic projection of the second via on the substrate;

[0297] The fourth part may be disposed at the upper right corner of the orthographic projection of the second via on the substrate.

[0298] Figure 29 is a planar layout diagram of the array substrate according to at least one embodiment of the present invention.

[0299] In Figure 29 , the one labeled 21 is the first electrode layer, and the one labeled 22 is the second electrode layer; the one labeled H1 is the first via, and the one labeled H2 is the second via.

[0300] Figure 30A and Figure 30B is Figure 29 a planar layout diagram of a partial area in

[0301] Figure 31 is [[ID= a planar layout diagram of the gate metal layer in ​ is ​ a planar layout diagram of the semiconductor layer in ​ is ​ a planar layout diagram of the source-drain metal layer in ​ is ​ a planar layout diagram of the orthographic projection of the second via on the substrate in ​ is ​ a stacked schematic diagram of the second via and the first electrode layer in ​ is Figure 30A a planar layout diagram of the second electrode layer in Figure 35B is Figure 30A a stacked planar layout diagram of the second electrode layer and the first electrode layer;

[0302] Figure 36A and Figure 36B is Figure 30A a planar layout diagram of the first electrode layer in Figure 37 is Figure 30A a stacked schematic diagram of the first electrode layer, the second via, and the first via.

[0303] In Figure 30A among them, the one labeled 21 is the first electrode layer, the one labeled 22 is the second electrode layer, the one labeled 23 is the gate metal layer, the one labeled 24 is the source-drain metal layer, and the one labeled 20 is the semiconductor layer.

[0304] In Figure 30B among them, the one labeled H1 is the first via hole, the one labeled H2 is the second via hole, the one labeled PXZ is the pixel electrode group, the one labeled VCOM is the common electrode, the one labeled GL1 is the first gate line, the one labeled GL2 is the second gate line, the one labeled DL is the data line, and the one labeled A0 is the active pattern.

[0305] In Figure 31 among them, the one labeled GL1 is the first gate line, and the one labeled GL2 is the second gate line; the first gate line GL1 and the second gate line GL2 extend in the horizontal direction.

[0306] In Figure 32 among them, the one labeled A0 is the active pattern, the one labeled L1 is the first connection part, and the one labeled L2 is the second connection part.

[0307] In Figure 33 among them, the one labeled DL is the data line.

[0308] In FIG. 34, the one labeled H2W is the edge of H2; the one labeled H24 is the fourth part included in the orthographic projection of the second via hole H2 on the substrate.

[0309] In at least one embodiment of the present invention, the second electrode pattern may include a common electrode, a first auxiliary connection part, and a second auxiliary connection part;

[0310] The common electrode included in one pixel unit is electrically connected to the common electrode included in a pixel unit that is in the same row as and adjacent to this pixel unit through the first auxiliary connection part; the orthographic projection of the first auxiliary connection part on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate;

[0311] The common electrode included in one pixel unit is electrically connected to the common electrode included in a pixel unit that is in the same column as and adjacent to this pixel unit through the second auxiliary connection part; the orthographic projection of the second auxiliary connection part on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate.

[0312] In Figure 35A and Figure 35B among them, the one labeled VCOM is the common electrode, the one labeled FL1 is the first auxiliary connection part, and the one labeled FL2 is the second auxiliary connection part; FL1 extends in the horizontal direction, and FL2 extends in the vertical direction;

[0313] The common electrode VCOM is electrically connected to the common electrode on the left through the first auxiliary connection portion FL1;

[0314] The common electrode VCOM is electrically connected to the common electrode below through the second auxiliary connection portion FL2.

[0315] As Figure 35B shown, the positive projection of FL1 on the substrate partially overlaps with the positive projection of the pixel electrode group PXZ on the substrate;

[0316] The positive projection of FL2 on the substrate partially overlaps with the positive projection of the pixel electrode group PXZ on the substrate.

[0317] In Figure 36A , the one labeled PXZ is the pixel electrode group, and the one labeled X1 is the connection pattern, and the pixel electrode group PXZ is connected to the connection pattern X1.

[0318] As Figure 36B shown, the one labeled PX1 is the first pixel electrode, the one labeled PX2 is the second pixel electrode, the one labeled PX3 is the third pixel electrode, the one labeled PX4 is the fourth pixel electrode, and the one labeled PX5 is the fifth pixel electrode;

[0319] A first opening structure K1 is provided between PX1 and PX2, a second opening structure K2 is provided between PX2 and PX3, a third opening structure K3 is provided between PX3 and PX4, and a fifth opening structure K5 is provided between PX4 and PX5.

[0320] As Figure 36A and Figure 36B shown, the first dashed line for dividing the connection pattern X1 is a dashed line extending in the horizontal direction, which is used to separate the connection pattern X1 from the first pixel electrode PX1 and separate the connection pattern X1 from the second pixel electrode PX2;

[0321] The second dashed line for dividing the connection pattern X1 is used to separate the connection pattern X1 from the third pixel electrode PX4 and separate the connection pattern X1 from the third pixel electrode PX3;

[0322] The third dashed line for dividing the connection pattern X3 is a dashed line extending in the vertical direction, which is used to separate the connection pattern X1 from the fourth pixel electrode PX4;

[0323] The fourth dashed line for dividing the connection pattern X1 is a dashed line extending in the horizontal direction, which is used to separate the connection pattern X1 from the fifth pixel electrode PX5.

[0324] As Figures 29 - 37As shown, the fourth part H24 of the orthographic projection of the second via hole H2 on the substrate is not covered by the first electrode pattern, and the fourth part H24 is close to the orthographic projection of the pixel electrode PX on the substrate;

[0325] As Figures 29 - 37 shown, the first electrode pattern completely covers the orthographic projection of the first via hole on the substrate, and the first electrode pattern partially covers the orthographic projection of the second via hole on the substrate; the common electrode VCOM does not cover the second via hole H2, and the first electrode pattern completely covers the first via hole H1.

[0326] As Figures 29 - 37 shown, the orthographic projection of the pixel electrode PX on the substrate is disposed on the right side of the orthographic projection of the second via hole H2 on the substrate, and the fourth part H24 is disposed at the upper right corner of the orthographic projection of the second via hole H2 on the substrate.

[0327] Optionally, the distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or,

[0328] the distance range is greater than or equal to a third distance threshold, and the third distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm

[0329] In Figures 29 - 37 at least one corresponding embodiment, along the direction parallel to the extension of the gate line GL, the maximum distance between the orthographic projection of the edge of the second via hole H2 on the substrate and the orthographic projection of the edge of the first electrode pattern at the second via hole H2 on the substrate is within the distance range;

[0330] the distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or,

[0331] the distance range is greater than or equal to a third distance threshold, and the third distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

[0332] In at least one embodiment of the present invention, the edge of the orthographic projection of the second via hole on the substrate is a polygon;

[0333] The fourth part is disposed at a corner of the orthographic projection of the second via hole on the substrate away from the pixel electrode and the active pattern.

[0334] Figure 38A And Figure 38B is a plan layout diagram of the array substrate according to at least one embodiment of the present invention.

[0335] Figure 39 Is Figure 38A a plan layout diagram of the gate metal layer inFigure 40 is Figure 38A a plan view of the semiconductor layer in Figure 41 is Figure 38A a plan view of the source-drain metal layer in Figure 42A is Figure 38A a plan view of the second via in Figure 43A is Figure 38A a plan view of the second electrode layer in Figure 43B is Figure 38A a plan view of the stacked layer between the second electrode layer and the source-drain metal layer;

[0336] Figure 44A and Figure 44B is Figure 38A a plan view of the first electrode layer in Figure 45 is Figure 38A a schematic diagram of the superposition of the first electrode layer and the second via.

[0337] In Figure 38A the component labeled 21 is the first electrode layer, the component labeled 22 is the second electrode layer, the component labeled 23 is the gate metal layer, the component labeled 24 is the source-drain metal layer, and the component labeled 20 is the semiconductor layer.

[0338] In Figure 38B the component labeled PXZ is the pixel electrode group, the component labeled VCOM is the common electrode, the component labeled H1 is the first via, the component labeled H2 is the second via, the component labeled GL is the gate line, the component labeled DL1 is the first data line, the component labeled DL2 is the second data line, and the component labeled A0 is the active pattern.

[0339] In Figure 39 the component labeled GL is the gate line. In Figure 40 the component labeled A0 is the active pattern. In Figure 41 the component labeled DL1 is the first data line, and the component labeled DL2 is the second data line.

[0340] In at least one embodiment of the present invention, the second electrode pattern may include a common electrode, a first auxiliary connection portion, and a second auxiliary connection portion;

[0341] the common electrode included in one pixel unit is electrically connected to the common electrode included in a pixel unit adjacent to and in the same row as this pixel unit through the first auxiliary connection portion; the orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with the orthographic projection of one of the second signal lines on the substrate;

[0342] The common electrode included in one of the pixel units is electrically connected to the common electrode included in a pixel unit that is in the same column and adjacent to this pixel unit through the second auxiliary connection portion, and the orthographic projection of the second auxiliary connection portion on the substrate partially overlaps with the orthographic projection of one of the first signal lines on the substrate.

[0343] In Figure 43A and Figure 43B the one labeled VCOM is the common electrode, and the one labeled FL1 is the first auxiliary connection portion.

[0344] As Figure 43A shown, the common electrode VCOM is electrically connected to the common electrode on the left through the first auxiliary connection portion FL1, and FL1 extends in the horizontal direction.

[0345] In Figure 43A the corresponding embodiment, the common electrode VCOM can also be electrically connected to the common electrode below through the second auxiliary connection portion, and the second auxiliary connection portion extends in the vertical direction.

[0346] As Figure 43B shown, the orthographic projection of FL1 on the substrate partially overlaps with the orthographic projection of the first data line DL1 on the substrate.

[0347] In Figure 43A the auxiliary connection portion labeled FL0 is for electrically connecting the common electrode on the left of the common electrode VCOM and the connection portion for the common electrode disposed below this common electrode;

[0348] As Figure 43B shown, the orthographic projection of FL0 on the substrate partially overlaps with the orthographic projection of the gate line GL on the substrate.

[0349] In Figure 44A the one labeled PX is the pixel electrode, the one labeled X1 is the connection pattern, and the connection pattern X1 is in communication with the pixel electrode PX.

[0350] In Figure 44B the one labeled PX1 is the first pixel electrode, the one labeled PX2 is the second pixel electrode, the one labeled PX3 is the third pixel electrode, and the one labeled PX4 is the fourth pixel electrode;

[0351] A first opening structure K1 is provided between PX1 and PX2, a second opening structure K2 is provided between PX2 and PX3, and a third opening structure K3 is provided between PX3 and PX4.

[0352] As Figure 44BAs shown, the dashed lines for dividing the connection pattern X1 are used to separate the connection pattern X1 from the first pixel electrode PX1, separate the connection pattern X1 from the second pixel electrode PX2, separate the connection pattern X1 from the third pixel electrode PX3, and separate the connection pattern X1 from the fourth pixel electrode PX4.

[0353] In Figure 45 , those labeled PX are pixel electrodes, those labeled H2 are second vias, and those labeled H1 are first vias.

[0354] In Figure 42A , those labeled H2W are the edges of H2; those labeled H24 are the fourth part included in the orthographic projection of the second via H2 on the substrate.

[0355] As Figures 38A - 45 shown, the fourth part H24 of the orthographic projection of the second via H2 on the substrate is not covered by the first electrode pattern, and the fourth part H24 is close to the orthographic projection of the pixel electrode PX on the substrate;

[0356] As Figures 38A - 45 shown, the first electrode pattern completely covers the orthographic projection of the first via on the substrate, and the first electrode pattern partially covers the orthographic projection of the second via on the substrate; the common electrode VCOM does not cover the second via H2, and the first electrode pattern completely covers the first via H1.

[0357] As Figures 38A - 45 shown, the orthographic projection of the pixel electrode PX on the substrate is disposed on the right side of the orthographic projection of the second via H2 on the substrate, and the fourth part H24 is disposed at the lower left corner of the orthographic projection of the second via H2 on the substrate.

[0358] Figure 46 is the layout diagram of the second via H2 in at least one embodiment of the present invention; Figure 47A and Figure 47B is the planar layout diagram of the first electrode layer in at least one embodiment of the present invention; Figure 48 is the superimposed schematic diagram of the first electrode layer, the first via, and the second via in at least one embodiment of the present invention.

[0359] In Figure 46 , those labeled H2W are the edges of H2; as Figure 47A shown, those labeled PXZ are pixel electrode groups, and those labeled X1 are connection patterns.

[0360] As Figure 47B shown, those labeled PX1 are the first pixel electrodes, those labeled PX2 are the second pixel electrodes, those labeled PX3 are the third pixel electrodes, and those labeled PX4 are the fourth pixel electrodes;

[0361] A first opening structure K1 is provided between PX1 and PX2, a second opening structure K2 is provided between PX2 and PX3, and a third opening structure K3 is provided between PX3 and PX4.

[0362] As Figure 47B shown, a first dashed line for dividing the connection pattern X1 is used to separate the connection pattern X1 and the first pixel electrode PX1, and to separate the connection pattern X1 and the second pixel electrode PX2. The first dashed line is a dashed line extending in the horizontal direction;

[0363] A second dashed line for dividing the connection pattern X1 is used to separate the connection pattern X1 and the third pixel electrode PX3, and to separate the connection pattern X1 and the fourth pixel electrode PX4. The second dashed line is a dashed line extending in the vertical direction.

[0364] As Figure 48 shown, the lower right corner of the second via hole H2 is not covered by the first electrode pattern, and the first electrode pattern partially covers the second via hole H2;

[0365] As Figures 46 - 48 shown, the first electrode pattern completely covers the first via hole H1.

[0366] As Figures 46 - 48 shown, the overlapping area between the orthographic projection of the first electrode pattern on the substrate and the orthographic projection of the second via hole H2 on the substrate is a first area. The overlapping area of the first area and the orthographic projection of the second via hole H2 on the substrate can be greater than or equal to 0.85 and less than or equal to 0.99.

[0367] Optionally, the edge of the orthographic projection of the second via hole on the substrate is an oblique rectangular, rectangular or rounded rectangular;

[0368] The first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other. The pixel electrode group includes a plurality of pixel electrodes that are electrically connected to each other;

[0369] The orthographic projection of the pixel electrode on the substrate is located on the second side of the orthographic projection of the second via hole on the substrate;

[0370] The lower edge of the orthographic projection of the connection pattern on the substrate coincides with part of the edge of the orthographic projection of the second via hole on the substrate; and / or, the upper edge of the orthographic projection of the connection pattern on the substrate coincides with part of the edge of the orthographic projection of the second via hole on the substrate.

[0371] In a specific implementation, as Figure 48As shown, the lower edge of the orthographic projection of the connection pattern X1 on the substrate coincides with the edge portion of the orthographic projection of the second via hole H2 on the substrate, and the upper edge of the orthographic projection of the connection pattern X1 on the substrate coincides with the edge portion of the orthographic projection of the second via hole H2 on the substrate.

[0372] In at least one embodiment of the present invention, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other, and the pixel electrode groups include a plurality of pixel electrodes that are electrically connected to each other;

[0373] The orthographic projection of the first electrode pattern on the substrate at least partially overlaps with the orthographic projection of the second via hole on the substrate.

[0374] Figure 49 is a layout diagram of the second via hole H2 in at least one embodiment of the present invention; Figure 50A and Figure 50B is a planar layout diagram of the first electrode layer in at least one embodiment of the present invention; Figure 51 is a superimposed schematic diagram of the first electrode layer, the first via hole, and the second via hole in at least one embodiment of the present invention.

[0375] In Figure 50A , those labeled PX are pixel electrodes, and those labeled X1 are connection patterns, and PX and X1 are connected.

[0376] As Figure 50B shown, those labeled PX1 are the first pixel electrodes, those labeled PX2 are the second pixel electrodes, those labeled PX3 are the third pixel electrodes, those labeled PX4 are the fourth pixel electrodes, and those labeled PX5 are the fifth pixel electrodes;

[0377] A first opening structure K1 is provided between PX1 and PX2, a second opening structure K2 is provided between PX2 and PX3, a third opening structure K3 is provided between PX3 and PX4, and a fourth opening structure K4 is provided between PX4 and PX45.

[0378] As Figure 50B shown, the dashed lines for dividing the connection pattern X1 are used to separate the connection pattern X1 from the first pixel electrode PX1, separate the connection pattern X1 from the second pixel electrode PX2, separate the connection pattern X1 from the third pixel electrode PX3, separate the connection pattern X1 from the fourth pixel electrode PX4, and separate the connection pattern X1 from the fifth pixel electrode PX5.

[0379] As Figures 49 - 51 shown, the orthographic projection of the first electrode pattern on the substrate at least partially overlaps with the orthographic projection of the second via hole H2 on the substrate.

[0380] Optionally, the distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or,

[0381] the distance range is greater than or equal to a fourth distance threshold, and the fourth distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

[0382] Optionally, the edge of the orthographic projection of the second via hole on the substrate is a polygon.

[0383] The display device according to an embodiment of the present invention includes the above-mentioned array substrate.

[0384] The above is the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. An array substrate, characterized in that, it includes a substrate, and a first metal layer, a first insulating layer, a second insulating layer and a first electrode layer disposed on one surface of the substrate; the first electrode layer includes a first electrode pattern, and the first electrode pattern is electrically connected to the first metal layer through a first via hole and a second via hole; the first via hole is located in and penetrates the first insulating layer; the second via hole is located in and penetrates the second insulating layer; the orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the first via hole on the substrate; the ratio range of the overlapping area of the orthographic projection of the first electrode layer on the substrate and the orthographic projection of the second via hole on the substrate to the orthographic projection area of the second via hole on the substrate is greater than or equal to 0.85 and less than or equal to 0.

99.

2. The array substrate according to claim 1, characterized in that, the first electrode layer has a plurality of mutually separated opening structures, and at least one end of the opening structure orthographically projects on the substrate and partially overlaps with the orthographic projection of the second via hole on the substrate.

3. The array substrate according to claim 1, characterized in that, it further includes a second electrode layer disposed between the second insulating layer and the first electrode layer; the orthographic projection of the second electrode layer on the substrate does not overlap with the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate.

4. The array substrate according to claim 1, characterized in that, it includes a plurality of rows of first signal lines, a plurality of columns of second signal lines disposed on the substrate, and a plurality of pixel units defined by the intersection of the first signal lines and the second signal lines; each pixel unit includes a first electrode pattern, a second electrode pattern, a first via hole, a second via hole and a transistor; the transistor includes an active pattern; the active pattern includes a first connection portion and a second connection portion; the first connection portion is electrically connected to the second signal line through a third via hole; the second connection portion is electrically connected to the first electrode layer; the third via hole and the first via hole are not in the same pixel unit.

5. The array substrate according to claim 1, characterized in that, it includes a plurality of rows of first signal lines, a plurality of columns of second signal lines disposed on the substrate, and a plurality of pixel units defined by the intersection of the first signal lines and the second signal lines; each pixel unit includes a first electrode pattern, a second electrode pattern, a first via hole, a second via hole and a transistor; the transistor includes an active pattern; along the direction parallel to the extension of the first signal line, the maximum distance between the orthographic projection of the edge of the second via hole on the substrate and the orthographic projection of the edge of the first electrode pattern at the second via hole on the substrate is within a distance range.

6. The array substrate according to claim 5, characterized in that, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes that are electrically connected to each other. A first part of a positive projection of the second via hole on the substrate is not covered by the first electrode pattern, and the first part is close to a positive projection of the pixel electrode on the substrate; A second part of a positive projection of the second via hole on the substrate is not covered by the first electrode pattern, and the first part and the second part are disposed on opposite sides; The second part is close to a positive projection of the first signal line on the substrate.

7. The array substrate according to claim 6, wherein, an edge of a positive projection of the second via hole on the substrate is an oblique rectangular, rectangular or rounded rectangular; a positive projection of the first signal line on the substrate is disposed on a first side of a positive projection of the second via hole on the substrate, and a positive projection of the pixel electrode on the substrate is disposed on a second side of a positive projection of the second via hole on the substrate; the first side and the second side are opposite sides; The first part is disposed at a corner of the positive projection of the second via hole on the substrate close to the pixel electrode and the active pattern, and the second part is disposed at a corner of the positive projection of the second via hole on the substrate close to the first signal line and the first connection part.

8. The array substrate according to claim 5, wherein, a third part of a positive projection of the second via hole on the substrate is not covered by the first electrode pattern, and the third part is close to a positive projection of the first signal line on the substrate.

9. The array substrate according to claim 8, wherein, an edge of a positive projection of the second via hole on the substrate is an oblique rectangular, rectangular or rounded rectangular; The third part is disposed at a corner of the second via hole close to the first signal line and the active pattern.

10. The array substrate according to claim 7 or 9, wherein, the second electrode pattern includes a common electrode and four auxiliary connection parts; the common electrodes included in one pixel unit are respectively electrically connected to the common electrodes in four adjacent pixel units through the four auxiliary connection parts; positive projections on the substrate of two of the four auxiliary connection parts respectively partially overlap with positive projections on the substrate of corresponding second signal lines; positive projections on the substrate of the other two of the four auxiliary connection parts respectively partially overlap with positive projections on the substrate of corresponding first signal lines.

11. The array substrate according to any one of claims 6 to 9, wherein, the distance range is greater than or equal to 0.8 μm and less than or equal to 1.2 μm; or, the distance range is greater than or equal to a first distance threshold, and the first distance threshold is greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

12. The array substrate according to claim 5, wherein, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other, and the pixel electrode groups include a plurality of pixel electrodes that are electrically connected to each other; A fourth part of the orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the fourth part is close to the orthographic projection of the pixel electrode on the substrate.

13. The array substrate according to claim 12, wherein, the edge of the orthographic projection of the second via hole on the substrate is an oblique-angled rectangle, a rectangle or a rounded rectangle; the fourth part is disposed at a corner of the orthographic projection of the second via hole on the substrate close to the pixel electrode and close to the active pattern.

14. The array substrate according to claim 12 or 13, wherein, the distance range is greater than or equal to 1.8 μm and less than or equal to 2.2 μm; or, the distance range is greater than or equal to a second distance threshold, and the second distance threshold is greater than or equal to 1.8 μm and less than or equal to 2.2 μm.

15. The array substrate according to any one of claims 12 to 14, wherein, the second electrode pattern includes a common electrode and a first auxiliary connection portion; the common electrode included in one pixel unit is electrically connected to the common electrode in an adjacent pixel unit through the first auxiliary connection portion; the orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with the orthographic projection of one of the second signal lines on the substrate.

16. The array substrate according to claim 12, wherein, the edge of the orthographic projection of the second via hole on the substrate is an oblique-angled rectangle, a rectangle or a rounded rectangle; the fourth part is disposed at a corner of the orthographic projection of the second via hole on the substrate close to the pixel electrode and far from the active pattern.

17. The array substrate according to claim 16, wherein, the distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or, the distance range is greater than or equal to a third distance threshold, and the third distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

18. The array substrate according to claim 16 or 17, wherein, the second electrode pattern includes a common electrode, a first auxiliary connection portion and a second auxiliary connection portion; the common electrode included in one pixel unit is electrically connected to the common electrode included in an adjacent pixel unit in the same row through the first auxiliary connection portion; the orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate; the common electrode included in one pixel unit is electrically connected to the common electrode included in an adjacent pixel unit in the same column through the second auxiliary connection portion; the orthographic projection of the second auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate.

19. The array substrate according to claim 12, wherein, the edge of the orthographic projection of the second via hole on the substrate is a polygon; the fourth part is disposed at a corner of the orthographic projection of the second via hole on the substrate far from the pixel electrode and the active pattern.

20. The array substrate according to claim 19, wherein, The second electrode pattern includes a common electrode, a first auxiliary connection portion, and a second auxiliary connection portion; The common electrode included in one pixel unit is electrically connected to the common electrode included in a pixel unit adjacent thereto and in the same row through the first auxiliary connection portion; a positive projection of the first auxiliary connection portion on the substrate partially overlaps a positive projection of one of the second signal lines on the substrate; The common electrode included in one pixel unit is electrically connected to the common electrode included in a pixel unit adjacent thereto and in the same column through the second auxiliary connection portion; a positive projection of the second auxiliary connection portion on the substrate partially overlaps a positive projection of one of the first signal lines on the substrate.

21. The array substrate according to claim 1, wherein, An edge of a positive projection of the second via hole on the substrate is an oblique rectangular, rectangular or rounded rectangular; The first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes that are electrically connected to each other; A positive projection of the pixel electrode on the substrate is located on a second side of a positive projection of the second via hole on the substrate; A lower edge of a positive projection of the connection pattern on the substrate is partially consistent with an edge of a positive projection of the second via hole on the substrate; And / or, an upper edge of a positive projection of the connection pattern on the substrate is partially consistent with an edge of a positive projection of the second via hole on the substrate.

22. The array substrate according to claim 5, wherein, The first electrode pattern includes a connection pattern and a plurality of pixel electrode groups that are electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes that are electrically connected to each other; A positive projection of the pixel electrode on the substrate at least partially overlaps a positive projection of the second via hole on the substrate.

23. The array substrate according to claim 22, wherein, The distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or, The distance range is greater than or equal to a fourth distance threshold, and the fourth distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

24. The array substrate according to claim 22, wherein, An edge of a positive projection of the second via hole on the substrate is a polygon.

25. A display device, wherein, It includes the array substrate according to any one of claims 1 to 24.

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