Display device

Abstract

The purpose of the present invention is to suppress deterioration in display quality. A display device (11) is provided with: a switching element (24); a first electrode (25) connected to the switching element (24); a first wiring (27) located on the lower layer side than the first electrode (25); a second electrode (38), which is positioned on the upper layer side of the first wiring (27), and which has a reflective layer (38B) that reflects light and has an uneven surface (38S); a third electrode (37) which is positioned on the lower layer side than the first electrode (25) and on the upper layer side than the first wiring (27), is disposed so as to overlap at least the first electrode (25) and the first wiring (27), and has a common potential; a first insulating film (35) interposed between the first electrode (25) and the third electrode (37); and a second insulating film (34) which is located on the upper layer side of the first wiring (27), is disposed on the lower layer side of the third electrode (37), and has a film thickness larger than that of the first insulating film (35).

Description

Technical Field

[0001] The technology disclosed in this specification relates to a display device. Background Art

[0002] Conventionally, as an example of a display device, a device described in Patent Document 1 below is known. In Patent Document 1, a reflective liquid crystal display element is described as a display device. The reflective liquid crystal display element described in Patent Document 1 includes: a reflector; a counter substrate opposed to the reflector; and a liquid crystal layer sandwiched between the reflector and the counter substrate. The reflector is provided on a glass substrate, and the surface layer portion has a photosensitive resin layer having a plurality of uneven surfaces inclined in a fixed direction and a reflective film provided on the photosensitive resin layer.

[0003] Prior Art Documents Patent Documents Patent Document 1: Japanese Patent Laid-Open No. 2000-105370 Summary of the Invention Technical Problem to be Solved by the Invention In the reflective liquid crystal display element described in Patent Document 1 above, the reflective film having uneven surfaces functions as a pixel electrode, but does not have a configuration for maintaining the potential of the reflective film charged by driving the TFT. In order to maintain the potential of the reflective film, a method of, for example, providing a common electrode overlapping the reflective film with an insulating film interposed therebetween and forming a holding capacitor between the reflective film and the common electrode is sometimes employed. However, in the reflective liquid crystal display element described in Patent Document 1 above, if a configuration of providing a common electrode overlapping the reflective film having uneven surfaces with an insulating film interposed therebetween is adopted, the common electrode becomes uneven in shape following the reflective film. Therefore, there is a problem that it is difficult to keep the interval between the common electrode and the reflective film fixed over the entire region. When a deviation occurs in the interval between the common electrode and the reflective film, the holding capacitor becomes unstable and the display quality may deteriorate.

[0004] The technology described in this specification has been completed based on the above circumstances, and its object is to suppress deterioration of display quality.

[0005] Solution to the Problem (1) A display device related to the technology described in this specification includes: a switching element; a first electrode connected to the switching element; a first wiring connected to the switching element and located on a lower layer side than the first electrode, for transmitting an image signal supplied to the first electrode; a second electrode located on an upper layer side than the first wiring and having a reflective layer for reflecting light, the reflective layer having an uneven surface; a third electrode located on a lower layer side than the first electrode and on an upper layer side than the first wiring, and the third electrode is disposed to overlap at least the first electrode and the first wiring respectively and is set to a common potential; a first insulating film interposed between the first electrode and the third electrode; and a second insulating film located on an upper layer side than the first wiring and disposed on a lower layer side with respect to the third electrode, the film thickness of the second insulating film being larger than the film thickness of the first insulating film.

[0006] (2) Additionally, based on the above (1), in the above display device, the second electrode may be configured to be located on an upper layer side than the first electrode, and the display device includes a third insulating film interposed between the second electrode and the first electrode, the film thickness of the third insulating film being larger than the film thickness of the first insulating film.

[0007] (3) Additionally, based on the above (2), in the above display device, the display device includes: a fourth electrode disposed opposite to the second electrode with a gap therebetween and set to a common potential; and a liquid crystal layer interposed between the second electrode and the fourth electrode, the second electrode being configured to overlap with the first electrode, and a first contact hole for connecting the second electrode and the first electrode is provided at an opening in a position of the third insulating film that overlaps both the second electrode and the first electrode.

[0008] (4) Additionally, based on the above (1), in the above display device, the second electrode is disposed on a lower layer side with respect to the second insulating film, and the display device includes a fourth insulating film located on an upper layer side than the first wiring and disposed on a lower layer side with respect to the second electrode, the film thickness of the fourth insulating film being larger than the film thickness of the first insulating film.

[0009] (5) Additionally, based on the above (4), in the above display device, the second electrode is set to the common potential.

[0010] (6) Additionally, based on the above (5), in the above display device, a plurality of the first electrodes are arranged at intervals, and the second electrode is disposed within a range spanning the plurality of first electrodes.

[0011] (7) Additionally, based on any one of the above (4) to (6), the display device may include a fifth electrode. The fifth electrode is disposed on the lower layer side with respect to the second insulating film and on the upper layer side with respect to the fourth insulating film. The second electrode has a transparent electrode film disposed on the lower layer side with respect to the reflective layer. The fifth electrode is formed by a part of the transparent electrode film, overlaps with a part of the switching element, and overlaps with a part of the first electrode. A second contact hole is formed at an opening position in the fourth insulating film where both the switching element and the fifth electrode overlap. The second contact hole connects the fifth electrode to the switching element. A third contact hole is formed at an opening position in the second insulating film where both the first electrode and the fifth electrode overlap. The third contact hole connects the first electrode and the fifth electrode.

[0012] (8) Additionally, based on the above (7), the display device may include: a sixth electrode that is disposed opposite to the first electrode with a gap therebetween and is set to a common potential; and a liquid crystal layer that is interposed between the first electrode and the sixth electrode.

[0013] (9) Additionally, based on any one of the above (1) to (8), the display device may include: a second wiring that is connected to the switching element, crosses the first wiring, and transmits a scanning signal; a fifth insulating film that is disposed on the upper layer side with respect to the first wiring and on the lower layer side with respect to the second wiring; and a third wiring that is disposed on the lower layer side with respect to the fifth insulating film and is disposed overlapping the second wiring. A fourth contact hole is formed at an opening position in the fifth insulating film where both the second wiring and the third wiring overlap. The fourth contact hole connects the second wiring and the third wiring.

[0014] Advantages of the Invention According to the technology described in this specification, it is possible to suppress a reduction in display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic cross-sectional view showing a liquid crystal panel, a driver, and a flexible substrate constituting a liquid crystal display device according to Embodiment 1.

[0016] Figure 2 is a top view showing the pixel arrangement in the display area of the liquid crystal panel according to Embodiment 1.

[0017] Figure 3 is a magnified top view showing the pixel arrangement in the display area of the liquid crystal panel according to Embodiment 1.

[0018] Figure 4 is a cross-sectional view along the iv-iv line in the liquid crystal panel according to Embodiment 1. Figure 3

[0019] Figure 5 is a cross-sectional view along the Figure 3 v-v line in the liquid crystal panel according to Embodiment 1.

[0020] Figure 6 is a top view showing the pixel arrangement in the display area of the liquid crystal panel according to Embodiment 1, and is a top view showing the first metal film and the second metal film in different dot patterns.

[0021] Figure 7 is a top view showing the pixel arrangement in the display area of the liquid crystal panel according to Embodiment 1, and is a top view showing the second transparent electrode film in a dot pattern.

[0022] Figure 8 is a cross-sectional view along the Figure 3 viii-viii line in the liquid crystal panel according to Embodiment 1.

[0023] Figure 9 is a top view showing the pixel arrangement in the display area of the liquid crystal panel according to Embodiment 1, and is a top view showing the first transparent electrode film in a dot pattern.

[0024] Figure 10 is a top view showing the pixel arrangement in the display area of the liquid crystal panel according to Embodiment 1, and is a top view showing the third transparent electrode film and the third metal film in different dot patterns.

[0025] Figure 11 A cross-sectional view along the Figure 3 xi-xi line in the liquid crystal panel according to Embodiment 1.

[0026] Figure 12 is a top view showing the pixel arrangement in the display area of the liquid crystal panel according to Embodiment 2.

[0027] Figure 13 is a cross-sectional view along the Figure 12 xiii-xiii line in the liquid crystal panel according to Embodiment 2.

[0028] Figure 14 is a cross-sectional view along the Figure 12 xiv-xiv line in the liquid crystal panel according to Embodiment 2.

[0029] Figure 15FIG. 0 is a plan view showing in an enlarged manner the pixel arrangement in the display area of the liquid crystal panel according to Embodiment 2, and is a plan view showing the first transparent electrode film and the third metal film in different dot patterns.

[0030] Figure 16 FIG. 4 is a cross-sectional view taken along line xvi-xvi of the liquid crystal panel according to Embodiment 2. Figure 12 of the liquid crystal panel according to Embodiment 2.

[0031] Figure 17 FIG. 10 is a plan view showing in an enlarged manner the pixel arrangement in the display area of the liquid crystal panel according to Embodiment 2, and is a plan view showing the third transparent electrode film in a dot pattern.

[0032] Figure 18 FIG. 14 is a plan view showing in an enlarged manner the pixel arrangement in the display area of the liquid crystal panel according to Embodiment 2, and is a plan view showing the second transparent electrode film in a dot pattern.

[0033] Figure 19 FIG. 18 is a cross-sectional view taken along line xix-xix of the liquid crystal panel according to Embodiment 2. Figure 12 of the liquid crystal panel according to Embodiment 2. DETAILED DESCRIPTION

[0034] <Embodiment 1> According to Figures 1 to 11 Embodiment 1 will be described. In the present embodiment, a transflective liquid crystal display device 10 is exemplified. In addition, the X-axis, Y-axis, and Z-axis are shown in a part of each drawing, and the directions of the respective axes are depicted as the directions shown in each drawing. Further, the upper sides of Figure 1 , Figure 4 , Figure 5 , Figure 8 and Figure 11 are set as the front side, and the lower side of the drawing is set as the back side.

[0035] As Figure 1 shown, the transflective liquid crystal display device 10 includes: a transflective liquid crystal panel (display device) 11 that displays an image, and a backlight device (lighting device) that irradiates light onto the liquid crystal panel 11. The transflective liquid crystal panel 11 is capable of performing both reflective display and transmissive display. In reflective display, external light (ambient light, environmental light) is reflected for display, and in transmissive display, light irradiated from the backlight device (backlight light) is transmitted for display. The external light used in reflective display includes sunlight, indoor lighting, etc. In the liquid crystal panel 11, the central side portion of the screen is the display area for displaying an image, and the peripheral side portion in a frame shape surrounding the display area in the screen is the non-display area where no image is displayed. In addition, the backlight device has a light source (e.g., an LED, etc.), optical members, etc., and the light source is disposed on the back side with respect to the liquid crystal panel 11 ( Figure 1on the lower side shown, and emits white light (white light), and the optical member converts it into planar light by imparting an optical effect to the light from the light source.

[0036] As Figure 1 shown, the liquid crystal panel 11 is formed by laminating a pair of substrates 20 and 21. The surface side (front side) of the pair of substrates 20 and 21 is set as the counter substrate (second substrate, CF substrate) 20, and the inner side (back side) is set as the array substrate (first substrate) 21. The counter substrate 20 and the array substrate 21 are both formed by laminating various films on the inner surface side of glass substrates (substrates) 20GS and 21GS made of glass material. As the glass material for each of the glass substrates 20GS and 21GS, for example, alkali-free glass or the like is used. A predetermined interval is provided between the pair of substrates 20 and 21, and a liquid crystal layer 22 is provided therein. The liquid crystal layer 22 contains liquid crystal molecules, which are substances whose optical properties change with the application of an electric field. A sealing portion 23 for sealing the liquid crystal layer 22 is provided between the outer peripheral ends of the pair of substrates 20 and 21. The sealing portion 23 is made of a photocurable resin material, a thermosetting resin material, etc., and is formed in a frame shape (endless ring shape) so as to surround the liquid crystal layer 22. In addition, polarizing plates 21 and 14 are respectively attached to the outer surface sides of the two substrates 20 and 21.

[0037] As Figure 1 shown, the size of the counter substrate 20 in the Y-axis direction is shorter than the size of the array substrate 21 in the Y-axis direction. The counter substrate 20 is attached in such a form that one end portion in the Y-axis direction is aligned with the array substrate 21. Therefore, the other end portion of the array substrate 21 in the Y-axis direction is set as an exposed portion 21A that protrudes laterally and is exposed with respect to the counter substrate 20. A driver (signal supply unit) 12 for supplying various signals related to the following display functions and a flexible substrate 13 are mounted on the exposed portion 21A.

[0038] The driver 12 is composed of an LSI chip having a drive circuit inside. As Figure 1 shown, the driver 12 is COG (Chip On Glass) mounted on the exposed portion 21A of the array substrate 21. The driver 12 processes various signals transmitted by the flexible substrate 13. The flexible substrate 13 is configured to have a plurality of wiring patterns formed on a base material made of a synthetic resin material (such as a polyimide-based resin, etc.) having insulation and flexibility. One end side of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end side is connected to an external circuit board (control board, etc.). The driver 12 and the flexible substrate 13 supply various signals (such as a scan signal, an image signal, etc.) to the backplane circuit (gate wiring 26, source wiring 27, etc.) provided in the liquid crystal panel 11.

[0039] Use Figure 2 andFigure 3 The configuration of the display area of the array substrate 21 will be outlined. As Figure 2 and Figure 3 shown, on the inner surface side of the display area of the array substrate 21, at least a TFT (transistor, switching element) 24 and a pixel electrode (first electrode) 25 are provided. A plurality of TFTs 24 and a plurality of pixel electrodes 25 are arranged in a matrix (row-column pattern) at intervals along the X-axis direction and the Y-axis direction. Around these TFTs 24 and pixel electrodes 25, gate wirings (second wirings, scanning wirings) 26 and source wirings (first wirings, image wirings, signal wirings) 27 that are orthogonal (cross) to each other are disposed. The gate wiring 26 extends along the X-axis direction, and a plurality of them are arranged at intervals in the Y-axis direction. The gate wiring 26 transmits a scanning signal for driving the TFT 24. The source wiring 27 extends along the Y-axis direction, and a plurality of them are arranged at intervals in the X-axis direction. The source wiring 27 transmits an image signal for charging the pixel electrode 25. The pixel electrode 25 and the following color filter 28 together constitute a pixel as a display unit. The TFT 24, the gate wiring 26, and the source wiring 27 constitute a backplane circuit for driving the pixel.

[0040] Use Figure 4 to outline the configuration of the display area of the counter substrate 20. As Figure 4 shown, on the inner surface side of the display area A of the counter substrate 20, color filters 28 of three colors, blue (B), green (G), and red (R), are provided. A plurality of color filters 28 presenting different colors are arranged adjacent to each other in the X-axis direction. A plurality of color filters 28 presenting different colors extend along the Y-axis direction. In this way, a plurality of color filters 28 presenting different colors are arranged in a longitudinal stripe pattern as a whole. These color filters 28 are arranged to overlap with the respective pixel electrodes 25 on the array substrate 21 side in a top view. The overlapping color filter 28 and pixel electrode 25 constitute a pixel as a display unit. A plurality of color filters 28 presenting different colors are arranged such that their boundaries (color boundaries) overlap with the source wiring 27. On the upper layer side (liquid crystal layer 22 side) of the color filter 28, an overcoat film 29 is provided for flattening. The overcoat film 29 is arranged in a planar shape over substantially the entire area of the counter substrate 20.

[0041] As Figure 4As shown, a counter electrode (fourth electrode) 30 is provided on the upper layer side of the outer coating film 29. The counter electrode 30 is formed in a full-surface shape in the same manner as the outer coating film 29, and is provided at least over the entire display area. The counter electrode 30 is made of a transparent electrode material. A common potential is supplied to the counter electrode 30. Therefore, an electric field is generated between the counter electrode 30 and the pixel electrode 25 charged by the TFT 24, and the alignment state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled by this electric field. The display mode of the liquid crystal panel 11 according to the present embodiment is a VA (Vertical Alignment) mode. The VA mode is a display mode in which liquid crystal molecules are vertically aligned with respect to the main surface of the glass substrate, and the alignment state of the liquid crystal molecules is switched by a vertical electric field. Further, a spacer 31 (see Figure 2 ) that protrudes toward the array substrate 21 side is provided on the upper layer side of the counter electrode 30. The protruding front end surface of the spacer 31 can contact the inner surface of the array substrate 21, whereby the interval between the pair of substrates 20 and 21, that is, the cell gap (the thickness of the liquid crystal layer 22) can be maintained. In addition, alignment films for aligning the liquid crystal molecules contained in the liquid crystal layer 22 are respectively formed on the innermost surfaces (uppermost layers) of the two substrates 20 and 21 that are in contact with the liquid crystal layer 22.

[0042] Next, with reference to Figure 4 and Figure 5 , various films laminated and formed on the inner surface side of the array substrate 21 will be described. As shown in Figure 4 and Figure 5 , on the array substrate 21, a first metal film (first conductive film), a gate insulating film (fifth insulating film) 32, a semiconductor film, a second metal film (second conductive film), an interlayer insulating film 33, a first planarization film (second insulating film, first organic insulating film) 34, a first transparent electrode film (third conductive film), an inter-electrode insulating film (first insulating film) 35, a second transparent electrode film (fourth conductive film), a second planarization film (third insulating film, second organic insulating film) 36, a third transparent electrode film (fifth conductive film), a third metal film (sixth conductive film), and an alignment film are laminated and formed in this order from the lower layer side (glass substrate 21GS side).

[0043] The first metal film, the second metal film, and the third metal film respectively have conductivity, light reflectivity, and light shielding properties by being formed as a single-layer film made of a single metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a stacked film or alloy made of different types of metal materials. The first metal film forms the gate wiring 26, the gate electrode 24A of the TFT 24, etc. The second metal film forms the source wiring 27, the source electrode 24B and the drain electrode 24C of the TFT 24, etc. The third metal film forms a part of the reflection electrode 38 described later, etc. The semiconductor film is formed of a thin film using a semiconductor material such as an oxide semiconductor as a material, and forms the semiconductor part 24D, etc. in the TFT 24. The first transparent electrode film, the second transparent electrode film, and the third transparent electrode film are formed of a transparent electrode material (such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), etc.). The first transparent electrode film forms the common electrode 37 described later, etc. The second transparent electrode film forms the pixel electrode 25, etc. The third transparent electrode film forms a part of the reflection electrode 38 described later, etc.

[0044] The gate insulating film 32, the interlayer insulating film 33, and the inter-electrode insulating film 35 are respectively made of inorganic insulating materials such as silicon nitride (SiN x ), silicon oxide (SiO 2 ), etc. The first planarization film 34 and the second planarization film 36 are made of an organic insulating material such as PMMA (acrylic resin), for example. The film thicknesses of the first planarization film 34 and the second planarization film 36 are larger than the film thicknesses of the gate insulating film 32, the interlayer insulating film 33, and the inter-electrode insulating film 35 made of inorganic insulating materials, and are about 1 μm to 3 μm, for example. Through the first planarization film 34, the structure (common electrode 37) formed of the first transparent electrode film on its upper layer side is planarized. Through the second planarization film 36, the degree of freedom of the cross-sectional shape of the structure (reflection electrode 38) formed of the first transparent electrode film on its upper layer side is provided. The gate insulating film 32 insulates the first metal film on the lower layer side, and the semiconductor film and the second metal film on the upper layer side. The interlayer insulating film 33 and the first planarization film 34 insulate the semiconductor film and the second metal film on the lower layer side, and the first transparent electrode film on the upper layer side. The inter-electrode insulating film 35 insulates the first transparent electrode film on the lower layer side, and the second transparent electrode film on the upper layer side. The second planarization film 36 insulates the second transparent electrode film on the lower layer side, and the third transparent electrode film on the upper layer side.

[0045] Use Figure 5 And Figure 6 The structure of the TFT 24 will be described in detail. In Figure 6 It shows the pixel arrangement in the same range as Figure 3 And in Figure 6In [description], the first metal film and the second metal film included in the array substrate 21 are shown in different dot patterns. As Figure 5 and Figure 6 shown, the TFT 24 has a gate electrode 24A formed of the first metal film. The gate electrode 24A branches from the gate wiring 26. Specifically, the gate electrode 24A is formed by extending a part of the gate wiring 26 along the Y-axis direction toward the pixel electrode 25 to be connected, and is substantially rectangular in a plan view. The gate electrode 24A is supplied with a scan signal transmitted to the gate wiring 26. The TFT 24 has a source electrode 24B formed of the second metal film. The source electrode 24B branches from the source wiring 27. Specifically, the source electrode 24B is formed by extending a part of the source wiring 27 along the X-axis direction toward the pixel electrode 25 to be connected, then bending toward the gate wiring 26 side and extending along the Y-axis direction, and is substantially L-shaped in a plan view. The extending front end side portion ( Figure 6 the right side portion) extending from the source wiring 27 of the source electrode 24B is connected to the following semiconductor portion 24D and is disposed overlapping the gate electrode 24A.

[0046] As Figure 5 and Figure 6 shown, the TFT 24 has a drain electrode 24C formed of the second metal film. The drain electrode 24C is integrally formed in a substantially island shape extending along the Y-axis direction, and one side ( Figure 6 the lower side) end portion thereof is connected to the following semiconductor portion 24D at a position spaced apart from the source electrode 24B in the X-axis direction and is disposed overlapping the gate electrode 24A. The other side ( Figure 6 the upper side) end portion of the drain electrode 24C is horizontally long and rectangular, and is connected to the pixel electrode 25 here. In addition, the drain electrode 24C is disposed overlapping the pixel electrode 25 over its entire region. A pixel contact hole CH1 is formed by opening at a position overlapping both the other side end portion of the drain electrode 24C and a part of the pixel electrode 25 in the interlayer insulating film 33 and the first planarizing film 34. The pixel electrode 25 is connected to the drain electrode 24C through the pixel contact hole CH1.

[0047] As Figure 5 and Figure 6 shown, the TFT 24 has a semiconductor portion 24D formed of a semiconductor film. The semiconductor portion 24D is substantially square in a plan view. One side ( Figure 6 the left side) end portion of the semiconductor portion 24D in the X-axis direction is connected to the source electrode 24B, and the other side ( Figure 6The (right) end portion thereof is connected to the drain electrode 24C. The semiconductor portion 24D is disposed overlapping the gate electrode 24A with the gate insulating film 32 therebetween. Then, when the TFT 24 becomes conductive based on the scan signal supplied to the gate electrode 24A, the image signal supplied to the source electrode 24B from the source wiring 27 is supplied to the drain electrode 24C via the semiconductor portion 24D. As a result, the pixel electrode 25 is charged to the potential based on the image signal.

[0048] Use Figure 4 , Figure 7 and Figure 8 to describe the configuration of the pixel electrode 25 in detail. In Figure 7 , the pixel arrangement in the same range as Figure 3 is shown, and in Figure 7 , the second transparent electrode film included in the array substrate 21 is shown in a dot pattern. As Figure 7 shown, the pixel electrode 25 is disposed in the region surrounded by the gate wiring 26 and the source wiring 27, and has a substantially rectangular planar shape that is longitudinally long. The pixel electrode 25 is disposed to overlap substantially the entire region of the TFT 24. The pixel electrode 25 is formed of the second transparent electrode film, and as Figure 4 and Figure 8 shown, is located on the upper layer side compared to either the gate wiring 26 or the source wiring 27. As Figure 7 and Figure 8 shown, the size of the pixel electrode 25 in the Y-axis direction is slightly larger than the arrangement pitch of the gate wiring 26. Therefore, the pixel electrode 25 partially overlaps the gate wiring 26, and the outer edge portion along the X-axis direction is located closer to the center in the line width direction (Y-axis direction) of the gate wiring 26 than the side edge portion of the gate wiring 26. As Figure 4 and Figure 7 shown, the size of the pixel electrode 25 in the X-axis direction is substantially equal to the arrangement pitch of the source wiring 27. Therefore, the pixel electrode 25 is disposed such that the outer edge portion along the Y-axis direction overlaps the side edge portion of the source wiring 27.

[0049] As Figure 4 and Figure 8 shown, a common electrode (third electrode, holding capacitance electrode) 37 for forming a holding capacitance with the pixel electrode 25 is provided on the array substrate 21. Hereinafter, use Figure 4 , Figure 5 , Figure 8 and Figure 9 to describe the configuration of the common electrode 37 in detail. In Figure 9 , the pixel arrangement in the same range as Figure 3 is shown, and in Figure 9 , the first transparent electrode film included in the array substrate 21 is shown in a dot pattern. As Figure 4 ,Figure 8 and Figure 9 As shown, the common electrode 37 is arranged in a full-surface shape over substantially the entire display area. The common electrode 37 is formed of a first transparent electrode film and is arranged to overlap with all the pixel electrodes 25 disposed in the display area with an inter-electrode insulating film 35 therebetween, overlapping the lower layer. The common electrode 37 formed of the first transparent electrode film is located on a more upper layer side than either the gate wiring 26 or the source wiring 27. Since the common electrode 37 also exists in the area (inter-pixel area) between the pixel electrodes 25 adjacent to each other in the X-axis direction and the Y-axis direction, the common electrode 37 is arranged to overlap with the gate wiring 26 and the source wiring 27. A common potential signal serving as a common potential (reference potential) is supplied from the backplane circuit to the common electrode 37. The common electrode 37 set to the common potential is arranged to overlap with the pixel electrode 25 charged by the TFT 24 with the inter-electrode insulating film 35 therebetween. Therefore, a holding capacitor is formed between the pixel electrode 25 and the common electrode 37. By using this holding capacitor, the potential of the charged pixel electrode 25 can be held well. In addition, as Figure 5 shown, a first opening 37A for allowing the pixel electrode 25 to pass through is provided at a position of the common electrode 37 overlapping with the pixel contact hole CH1. Short circuit between the pixel electrode 25 and the common electrode 37 is avoided by the first opening 37A.

[0050] Thus, in the present embodiment, as Figure 4 and Figure 5 shown, at a position on a more upper layer side than the source wiring 27 and on a more lower layer side than the pixel electrode 25, since the common electrode 37 set to the common potential is arranged, parasitic capacitance generated between the source wiring 27 and the pixel electrode 25 can be suppressed. Moreover, the film thickness of the first planarization film 34 located on a more upper layer side than the source wiring 27 and on a lower layer side with respect to the common electrode 37 is larger than the film thickness of the inter-electrode insulating film 35. Therefore, the flatness of the common electrode 37 located on a more upper layer side than the first planarization film 34 is sufficiently ensured. By ensuring the flatness of the common electrode 37, the flatness of the pixel electrode 25 arranged on an upper layer side with the inter-electrode insulating film 35 therebetween with respect to the common electrode 37 can also be ensured. Therefore, compared with the case where a common electrode overlapping with a reflective layer having an uneven surface with an insulating film interposed therebetween is provided as in the prior art, it is difficult for a deviation to occur in the interval between the pixel electrode 25 and the common electrode 37. As a result, the holding capacitor formed between the pixel electrode 25 and the common electrode 37 is stabilized, and thus the display quality is not easily deteriorated.

[0051] As Figure 4 and Figure 8 shown, a reflective electrode (second electrode) 38 for performing reflective display using external light is provided on the array substrate 21. Hereinafter, use Figure 4 、Figure 5 , Figure 8 and Figure 10 Describe in detail the structure of the reflective electrode 38. In Figure 10 , a pixel arrangement in the same range as Figure 3 is shown, and in Figure 10 , the third transparent electrode film and the third metal film included in the array substrate 21 are shown in different dot patterns. As Figure 5 shows, the reflective electrode 38 has a stacked structure composed of a transparent electrode layer 38A and a reflective layer 38B laminated on the upper side of the transparent electrode layer 38A. The transparent electrode layer 38A is composed of the third transparent electrode film and can effectively transmit light. The reflective layer 38B is composed of the third metal film and can effectively reflect light. In this way, the reflective electrode 38 is located on a position more upper side than the pixel electrode 25 composed of the second transparent electrode film. The cross-sectional shape of the reflective electrode 38 is a concavo-convex shape, and the reflective layer 38B disposed on its surface layer has a concavo-convex surface 38S. The concavo-convex surface 38S includes a plurality of convex portions 38S1 and concave portions 38S2, and these convex portions 38S1 and concave portions 38S2 are formed by alternately repeating arrangements within the concavo-convex surface 38S. Such a cross-sectional shape of the reflective electrode 38 reflects the cross-sectional shape of the second planarization film 36 that is the base of the reflective electrode 38. In order to make the cross-sectional shape of the second planarization film 36 a concavo-convex shape, for example, the material of the second planarization film 36 is a photosensitive organic insulating material, and the second planarization film 36 of the formed film is exposed and developed through a halftone mask or a gray tone mask, and the halftone mask or the gray tone mask has a pattern reflecting the concavo-convex shape. In this way, since the reflective layer 38B of the reflective electrode 38 has a concavo-convex surface 38S, it can diffusely reflect external light, and thus a display close to paper white can be achieved. In addition, the cross-sectional shape of the alignment film disposed on the upper side with respect to the reflective electrode 38 becomes a concavo-convex shape imitating the reflective electrode 38.

[0052] As Figure 10 shows, the reflective electrode 38 is disposed in a region surrounded by the gate wiring 26 and the source wiring 27, and the planar shape is a longitudinally long approximate square. The size of the reflective electrode 38 in the Y-axis direction is slightly larger than the arrangement interval of the gate wiring 26, and the size in the X-axis direction is approximately equal to the arrangement interval of the source wiring 27. That is, the size of the reflective electrode 38 in a top view is substantially the same as that of the pixel electrode 25, and it is disposed so as to overlap the pixel electrode 25 in a top view over substantially the entire region. And, as Figure 5As shown, the reflective electrode 38 is connected to the pixel electrode 25. An inter-electrode contact hole (first contact hole) CH2 is formed by opening in the second planarization film 36 between the transparent electrode layer 38A constituting the reflective electrode 38 and the pixel electrode 25. The inter-electrode contact hole CH2 is disposed at a position in the second planarization film 36 that overlaps both the transparent electrode layer 38A and the pixel electrode 25 (specifically, to the Figure 5 right side of the pixel contact hole CH1). The reflective electrode 38 is connected to the pixel electrode 25 by passing the transparent electrode layer 38A through the inter-electrode contact hole CH2, thereby having the same potential as the pixel electrode 25. Therefore, when the pixel electrode 25 is charged as the TFT 24 is driven, the reflective electrode 38 is also charged to the same potential as the pixel electrode 25, and a holding capacitor is formed between the pixel electrode 25 and the common electrode 37, so that the potential of the reflective electrode 38 is also well maintained. Since the reflective electrode 38 is disposed on the array substrate 21 close to the liquid crystal layer 22 after the alignment film, an electric field with sufficient intensity is generated between the reflective electrode 38 and the counter electrode 30 facing the liquid crystal layer 22 with the liquid crystal layer 22 interposed therebetween. By controlling the alignment state of the liquid crystal molecules contained in the liquid crystal layer 22 with this electric field, the amount of light emitted toward the surface side of the liquid crystal panel 11 is controlled for each pixel, and a predetermined image can be displayed in the display area. In addition, an opening 30A is provided at a position in the counter electrode 30 provided in the counter substrate 20 that overlaps the inter-electrode contact hole CH2 as a structure for restricting the alignment of the liquid crystal molecules contained in the liquid crystal layer 22.

[0053] As Figure 4 , Figure 8 and Figure 10 shown, the reflective electrode 38 has a transmissive opening 38C by partially cutting away the reflective layer 38B. The transmissive opening 38C is provided in the reflective layer 38B of the reflective electrode 38, but not formed in the transparent electrode layer 38A. The transmissive opening 38C is located near the center of the reflective electrode 38 in the X-axis direction and is disposed at a position that sandwiches the inter-electrode contact hole CH2 with the pixel-to-pixel contact hole CH1 in the Y-axis direction. The planar shape of the transmissive opening 38C is substantially square, and the four corners are cut obliquely. The light irradiated from the backlight device to the liquid crystal panel 11 passes through the transparent electrode layer 38A and can be emitted to the surface side through the transmissive opening 38C in the reflective layer 38B. Thus, in addition to the reflective display using external light, transmissive display can also be performed using the light from the backlight device.

[0054] Thus, in the present embodiment, as Figure 4 , Figure 5 and Figure 8As shown in FIG. 1 , since the reflective electrode 38 is arranged at a position on the upper layer side than the pixel electrode 25, the reflected light generated by the reflective layer 38B of the reflective electrode 38 does not pass through the pixel electrode 25. Therefore, the light can be reflected by the reflective layer 38B of the reflective electrode 38 with low loss to be used for displaying an image. The film thickness of the second planarizing film 36 arranged on the lower layer side relative to the reflective electrode 38 is greater than the film thickness of the inter-electrode insulating film 35, so the reliability of the cross-sectional shape of the second planarizing film 36 being formed as designed is improved. Therefore, the reproducibility related to the shape of the concave-convex surface 38S of the reflective layer 38B of the reflective electrode 38 is improved.

[0055] like Figure 4 and Figure 11 As shown, a redundant wiring (third wiring) 39 connected to the source wiring 27 is provided on the array substrate 21. Figure 4 , Figure 6 and Figure 11 , the structure of redundant wiring 39 is described in detail. Figure 4 and Figure 11 As shown in FIG. 1 , the redundant wiring 39 is formed of a first metal film and is arranged to overlap with the source wiring 27 to be connected. Figure 6 As shown, the redundant wiring 39 extends in the Y-axis direction in parallel with the source wiring 27. The line width of the redundant wiring 39 is larger than the line width of the source wiring 27, for example, about 3 times. The redundant wiring 39 is arranged concentrically with the source wiring 27 in the line width direction (X-axis direction), and has a central portion overlapping with the source wiring 27 and a pair of side portions sandwiching the central portion. Therefore, the redundant wiring 39 is in a relationship in which the pair of side portions sandwiching the central portion do not overlap with the source wiring 27 but overlap with the pixel electrode 25 and the reflective electrode 38. The redundant wiring 39 has a portion closer to the source electrode 24B than the source wiring 27 branching off. Figure 6 The position shown above extends from the upper side to the portion closer to the intersection with the gate wiring 26. Figure 6 The length to the lower position shown.

[0056] like Figure 11As shown, in the gate insulating film 32 between the redundant wiring 39 formed of the first metal film and the source wiring 27 formed of the second metal film, an inter-wiring contact hole (fourth contact hole) CH3 is formed by opening. The inter-wiring contact hole CH3 is disposed at a position overlapping both the redundant wiring 39 and the source wiring 27 in the gate insulating film 32. Two inter-wiring contact holes CH3 are provided at positions respectively overlapping the two end portions in the length direction (Y-axis direction) of the redundant wiring 39. The source wiring 27 is connected to the two end portions in the length direction of the redundant wiring 39 through the two inter-wiring contact holes CH3. Therefore, for example, even when a disconnection occurs in the portion between the two inter-wiring contact holes CH3 in the source wiring 27, the image signal transmitted from the side closer to the signal supply source (driver 12 side) than the disconnection portion in the source wiring 27 can be transmitted to the side closer to the signal supply destination (the side opposite to the driver 12 side) than the disconnection portion through the redundant wiring 39. Thereby, the redundancy of the source wiring 27 can be ensured. In addition, since the redundant wiring 39 is wider than the source wiring 27, it can shield the light traveling between the pixels adjacent in the X-axis direction during transmissive display. Thereby, the color mixing generated between the pixels presenting different colors can be suppressed.

[0057] Thus, in the present embodiment, as Figure 4 shown, the holding capacitor is formed by the pixel electrode 25 and the common electrode 37 located in layers different from the redundant wiring 39. Therefore, regardless of the presence of the redundant wiring 39, the formation ranges of the pixel electrode 25 and the common electrode 37 can be freely set. Therefore, assuming a case where an electrode having the same potential as the pixel electrode 25 is provided in the same layer (second metal film) as the source wiring 27 and an electrode having the same potential as the gate wiring 26 and provided in the same layer (first metal film) is provided so as to overlap with this electrode to form a holding capacitor, the overlapping area of the pixel electrode 25 and the common electrode 37 can be increased. Thereby, the holding capacitor formed between the pixel electrode 25 and the common electrode 37 can be increased, so that the potential of the pixel electrode 25 can be held more stably.

[0058] In addition, as Figure 8 shown, an exhaust hole 40 for discharging the gas generated from the first planarization film 34 is provided on the array substrate 21. Hereinafter, using Figures 7 to 9, a detailed description of the structure of the vent hole 40 will be given. The vent hole 40 is provided on the common electrode 37, the inter-electrode insulating film 35, and the pixel electrode 25 between the first planarization film 34 and the second planarization film 36. Specifically, the vent hole 40 is formed by the second opening 37B provided in the common electrode 37, the third opening 35A provided in the inter-electrode insulating film 35, and the fourth opening 25A provided in the pixel electrode 25 communicating with each other. The second opening 37B and the fourth opening 25A are provided with substantially the same opening area. In contrast, the opening area of the third opening 35A is smaller than the opening areas of the second opening 37B and the fourth opening 25A. As Figure 7 and Figure 9 shown, the vent hole 40 is arranged at a position adjacent to the drain electrode 24C and the semiconductor portion 24D of the TFT 24 in a top view. That is, the vent hole 40 is arranged at a position that does not overlap with the source wiring 27 at least, and the second opening 37B of the common electrode 37 is also arranged so as not to overlap with the source wiring 27 at least. Thus, the electric field generated from the source wiring 27 can be sufficiently shielded by the common electrode 37. Here, when the organic insulating materials of the first planarization film 34 and the second planarization film 36 are, for example, acrylic resin materials, after film formation, gases such as ethylene gas and propane gas can be released from the first planarization film 34 and the second planarization film 36 over time. When gas is generated from the first planarization film 34, the gas can be released to the second planarization film 36 side through the second opening 37B, the third opening 35A, and the fourth opening 25A that constitute the above-mentioned vent hole 40. The gas generated from the first planarization film 34 and the second planarization film 36 can be released to the liquid crystal layer 22 side from the portion of the second planarization film 36 not covered by the reflective electrode 38. Thus, the gas generated from the first planarization film 34 and the second planarization film 36 can be released.

[0059] As described above, the liquid crystal panel (display device) 11 of the present embodiment includes: a TFT (switching element) 24; a pixel electrode (first electrode) 25 connected to the TFT 24; a source wiring (first wiring) 27 connected to the TFT 24, located on a lower layer side than the pixel electrode 25, and transmitting an image signal supplied to the pixel electrode 25; a reflection electrode (second electrode) 38 located on an upper layer side than the source wiring 27, having a reflection layer 38B that reflects light, and the reflection layer 38B has an uneven surface 38S; a common electrode (third electrode) 37 located on a lower layer side than the pixel electrode 25 and on an upper layer side than the source wiring 27, arranged to overlap at least the pixel electrode 25 and the source wiring 27 respectively, and set to a common potential; an inter-electrode insulating film (insulating film) 35 interposed between the pixel electrode 25 and the common electrode 37; a first planarization film (second insulating film) 34 located on an upper layer side than the source wiring 27 and arranged on a lower layer side with respect to the common electrode 37, and having a film thickness larger than that of the inter-electrode insulating film 35.

[0060] When the TFT 24 is driven, the pixel electrode 25 is charged to a potential based on the image signal transmitted by the source wiring 27. The pixel electrode 25 is arranged to overlap the common electrode 37 set to a common potential with the inter-electrode insulating film 35 therebetween, so a holding capacitor is formed between the pixel electrode 25 and the common electrode 37. By using this holding capacitor, the potential of the charged pixel electrode 25 can be held well. On the other hand, by reflecting light with the reflection layer 38B of the reflection electrode 38, image display using external light can be performed. Since the reflection layer 38B of the reflection electrode 38 has an uneven surface 38S, external light can be diffusely reflected, and thus a display close to paper white can be achieved.

[0061] At a position on an upper layer side than the source wiring 27 and on a lower layer side than the pixel electrode 25, since the common electrode 37 set to a common potential is arranged, the parasitic capacitance generated between the source wiring 27 and the pixel electrode 25 can be suppressed. Moreover, the film thickness of the first planarization film 34 located on an upper layer side than the source wiring 27 and arranged on a lower layer side with respect to the common electrode 37 for displaying an image is larger than that of the inter-electrode insulating film 35, so the flatness of the common electrode 37 located on an upper layer side than the first planarization film 34 is sufficiently ensured. By ensuring the flatness of the common electrode 37, the flatness of the pixel electrode 25 can also be ensured, and the pixel electrode 25 is arranged on an upper layer side with the inter-electrode insulating film 35 therebetween with respect to the common electrode 37. Therefore, compared with the case of arranging a common electrode that overlaps a reflection layer having an uneven surface with an insulating film therebetween as in the past, it is difficult for a deviation to occur in the interval between the pixel electrode 25 and the common electrode 37. As a result, the holding capacitor formed between the pixel electrode 25 and the common electrode 37 is stabilized, and thus the display quality is not easily reduced.

[0062] In addition, in the array substrate 21, the reflective electrode 38 is located on the upper layer side relative to the pixel electrode 25, and the array substrate 21 includes a second planarization film (third insulating film) 36 interposed between the reflective electrode 38 and the pixel electrode 25 and having a film thickness larger than that of the inter-electrode insulating film 35. Since the reflective electrode 38 is arranged to be located on the upper layer side relative to the pixel electrode 25, the reflected light generated by the reflective layer 38B of the reflective electrode 38 does not transmit through the pixel electrode 25. Therefore, light can be reflected by the reflective layer 38B of the reflective electrode 38 with low loss for image display. Since the film thickness of the second planarization film 36 arranged on the lower layer side relative to the reflective electrode 38 is larger than that of the inter-electrode insulating film 35, the reproducibility related to the shape of the uneven surface 38S of the reflective layer 38B of the reflective electrode 38 is improved.

[0063] In addition, the liquid crystal panel 11 includes a counter electrode (fourth electrode) 30 and a liquid crystal layer 22. The counter electrode (fourth electrode) 30 is arranged to face the reflective electrode 38 with a gap therebetween and is set to a common potential. The liquid crystal layer 22 is interposed between the reflective electrode 38 and the counter electrode 30. The reflective electrode 38 is arranged to overlap with the pixel electrode 25. An inter-electrode contact hole (first contact hole) CH2 is formed at an opening at a position in the second planarization film 36 that overlaps both the reflective electrode 38 and the pixel electrode 25. The inter-electrode contact hole (first contact hole) CH2 connects the reflective electrode 38 to the pixel electrode 25. Through the inter-electrode contact hole CH2 of the second planarization film 36, the reflective electrode 38 is connected to the pixel electrode 25. Since the reflective electrode 38 and the pixel electrode 25 are at the same potential, an electric field with sufficient intensity is generated between the reflective electrode 38 and the counter electrode 30. Thereby, the alignment state of the liquid crystal molecules included in the liquid crystal layer 22 can be well controlled by the electric field generated between the reflective electrode 38 and the counter electrode 30.

[0064] In addition, the array substrate 21 includes: a gate wiring (second wiring) 26 that is connected to the TFT 24, crosses the source wiring 27, and transmits a scan signal; a gate insulating film (fifth insulating film) 32 that is disposed on the upper layer side with respect to the source wiring 27 and on the lower layer side with respect to the gate wiring 26; and a redundant wiring (third wiring) 39 that is disposed on the lower layer side and overlaps the gate wiring 26 with respect to the gate insulating film 32. A via hole between wirings (fourth via hole) CH3 is formed at a position where the gate insulating film 32 overlaps both the gate wiring 26 and the redundant wiring 39, and the via hole between wirings (fourth via hole) CH3 connects the gate wiring 26 and the redundant wiring 39. The scan signal transmitted to the gate wiring 26 is supplied to the TFT 24 for transmission, thereby driving the TFT 24. The source wiring 27 is connected to the redundant wiring 39 through the via hole CH3 in the gate insulating film 32. Assuming that a disconnection occurs in the source wiring 27, the image signal can be transmitted through the redundant wiring 39. Thus, the redundancy of the source wiring 27 can be ensured. In addition, a holding capacitor is formed by the pixel electrode 25 and the common electrode 37 that are located in different layers from the redundant wiring 39. Therefore, regardless of the presence of the redundant wiring 39, the formation ranges of the pixel electrode 25 and the common electrode 37 can be freely set. Therefore, compared with the case where an electrode having the same potential as the pixel electrode 25 is provided on the same layer as the source wiring 27 and an electrode having the same layer as the gate wiring 26 and having a common potential is provided so as to overlap with the electrode to form a holding capacitor, the overlapping area of the pixel electrode 25 and the common electrode 37 can be increased. Thus, the holding capacitor formed between the pixel electrode 25 and the common electrode 37 can be increased.

[0065] <Embodiment 2> According to Figures 12 to 19 Embodiment 2 will be described. In this Embodiment 2, a case is shown in which the stacking order of the respective films on the inner surface side of the array substrate 121 is changed, and the configurations of the pixel electrode 125, the common electrode 137, the reflective electrode 138, etc. are changed. In addition, redundant descriptions of the same structures, operations, and effects as those in the above-described First Embodiment are omitted.

[0066] Refer to Figure 13 and Figure 14 , various films laminated and formed on the inner surface side of the array substrate 121 constituting the liquid crystal panel 111 according to the present embodiment will be described. As Figure 13 and Figure 14As shown, on the array substrate 121, a first metal film, a gate insulating film (fifth insulating film) 132, a semiconductor film, a second metal film, an interlayer insulating film 133, a first planarization film (fourth insulating film) 134, a first transparent electrode film, a third metal film, a second planarization film (second insulating film) 136, a second transparent electrode film, an inter-electrode insulating film (first insulating film) 135, a third transparent electrode film, and an alignment film are sequentially stacked from the lower layer side.

[0067] As Figure 12 and Figure 13 shown, the reflective electrode 138 according to the present embodiment is provided on a lower layer side than the pixel electrode 125 and the common electrode 137. Specifically, the reflective electrode 138 is disposed on the upper layer side with respect to the first planarization film 134 and on the lower layer side with respect to the second planarization film 136. As Figure 13 , Figure 15 and Figure 16 shown, the reflective electrode 138 is composed of a transparent electrode layer 138A formed of the first transparent electrode film and a reflective layer 138B formed of the third metal film. In the present embodiment, a common potential signal having a common potential set by the bottom plate circuit is supplied to the reflective electrode 138. Along with this, the reflective electrode 138 is disposed in a substantially entire surface shape in substantially the entire display area. The reflective electrode 138 is located on a position upper than either the gate wiring 126 or the source wiring 127. Since the reflective electrode 138 also exists in a region (inter-pixel region) between pixel electrodes 125 adjacent to each other in the X-axis direction and the Y-axis direction, the reflective electrode 138 is disposed to overlap with the gate wiring 126 and the source wiring 127. The cross-sectional shape of the reflective electrode 138 is a concavo-convex shape, and the reflective layer 138B disposed on its surface layer has a concavo-convex surface 138S. Such a cross-sectional shape of the reflective electrode 138 reflects the cross-sectional shape of the first planarization film 134 serving as a base of the reflective electrode 138. In order to make the cross-sectional shape of the first planarization film 134 a concavo-convex shape, for example, the material of the first planarization film 134 is made an organic insulating material having photosensitivity, and the formed first planarization film 134 is exposed and developed through a halftone mask or a gray tone mask having a pattern reflecting the concavo-convex shape. In addition, as Figure 13 shown, the reflective electrode 138 has a transmissive opening 138C by locally cutting off the transparent electrode layer 138A on the basis of the reflective layer 138B. The transmissive opening 138C is composed of non-formed portions of the transparent electrode layer 138A and the reflective layer 138B constituting the reflective electrode 138.

[0068] As Figure 13 , Figure 14 and Figure 17As shown, the pixel electrode 125 according to this embodiment is formed of a third transparent electrode film. Thus, the pixel electrode 125 is disposed on the array substrate 121 so as to be closer to the liquid crystal layer 122 after the alignment film, and thus an electric field having sufficient strength is generated between the pixel electrode 125 and the counter electrode 130 facing each other with the liquid crystal layer 122 interposed therebetween. The alignment state of the liquid crystal molecules included in the liquid crystal layer 122 is controlled by this electric field, so that the amount of light emitted toward the surface side of the liquid crystal panel 111 is controlled for each pixel, and a predetermined image can be displayed in the display area.

[0069] As Figures 13 to 15 shown, the pixel electrode 125 formed of the third transparent electrode film is connected to the drain electrode 124C formed of the second metal film via an intermediate electrode (fifth electrode) 41 located in the middle in the stacking direction (Z-axis direction). The intermediate electrode 41 is formed of a part of the first transparent electrode film. That is, the intermediate electrode 41 is located in the same layer as the transparent electrode layer 138A constituting the reflection electrode 138. In addition, since the intermediate electrode 41 formed of a part of the first transparent electrode film does not include the third metal film constituting the reflection electrode 138, light can be transmitted, and a situation in which a short circuit occurs with the reflection electrode 138 due to film residue of the third metal film (reflection layer 138B) can be avoided. As Figure 15 shown, the intermediate electrode 41 is disposed within the transmissive opening 138C of the reflection electrode 138 and has an island shape surrounded by the opening edge of the transmissive opening 138C. The intermediate electrode 41 has a substantially rectangular shape that is longitudinally long in a plan view and is disposed so as to overlap both the drain electrode 124C and the pixel electrode 125, which are connection targets. In other words, the drain electrode 124C is provided so that a part thereof enters the transmissive opening 138C. Specifically, one end side portion of the intermediate electrode 41 in the Y-axis direction ( Figure 15 lower side portion) overlaps the drain electrode 124C and the pixel electrode 125, and the other end side portion of the intermediate electrode 41 in the Y-axis direction ( Figure 15 upper side portion) is disposed so as to overlap the pixel electrode 125 without overlapping the drain electrode 124C.

[0070] As Figure 13 and Figure 14As shown, in the interlayer insulating film 133 and the first planarization film 134 between the intermediate electrode 41 and the drain electrode 124C, a first pixel contact hole (second contact hole) CH4 is formed to open in a communicating manner. The first pixel contact hole CH4 is disposed at a position in the interlayer insulating film 133 and the first planarization film 134 that overlaps both the intermediate electrode 41 and the drain electrode 124C. The intermediate electrode 41 is connected to the drain electrode 124C through the first pixel contact hole CH4. In the second planarization film 136 and the inter-electrode insulating film 135 between the pixel electrode 125 and the intermediate electrode 41, a second pixel contact hole (third contact hole) CH5 is formed to open in a communicating manner. The second pixel contact hole CH5 is disposed at a position in the second planarization film 136 and the inter-electrode insulating film 135 that does not overlap with the drain electrode 124C but overlaps both the pixel electrode 125 and the intermediate electrode 41 (specifically, to the right of the first pixel contact hole CH4). The pixel electrode 125 is connected to the intermediate electrode 41 through the second pixel contact hole CH5. In this way, the pixel electrode 125 is connected to the drain electrode 124C of the TFT124 via the intermediate electrode 41. In addition, the cross-sectional shape of the second pixel contact hole CH5 in the second planarization film 136 and the inter-electrode insulating film 135 is a shape gentler than the cross-sectional shape of the first pixel contact hole CH4 in the interlayer insulating film 133 and the first planarization film 134. Thus, during manufacturing, when the material of the alignment film is coated on the innermost surface of the array substrate 121, the material of the alignment film easily flows into the second pixel contact hole CH5, so the reliability of uniformly coating the alignment film becomes higher. In addition, the opening 130A of the counter electrode (sixth electrode) 130 provided in the counter substrate 120 is disposed at a position overlapping with the first pixel contact hole CH4. Figure 14 On the right side).

[0071] As Figure 13 , Figure 16 and Figure 18 shown, the common electrode 137 according to the present embodiment is formed of a second transparent electrode film. The common electrode 137 formed of the second transparent electrode film is disposed on the lower layer side so as to overlap with a plurality of pixel electrodes 125 with the inter-electrode insulating film 135 therebetween. Thus, a holding capacitor is formed between the common electrode 137 set to a common potential and the pixel electrode 125 charged by the TFT124, so that the potential of the charged pixel electrode 125 can be held well. In addition, as Figure 13 and Figure 16 shown, at a position in the common electrode 137 that overlaps with the second pixel contact hole CH5, a first opening 137A for allowing the pixel electrode 125 to pass through is provided.

[0072] As Figure 13 and Figure 16As shown, these pixel electrodes 125 and common electrodes 137 are located on the upper layer side of the second planarization film 136 and are planarized by the second planarization film 136 having a film thickness larger than that of the inter-electrode insulating film 135. Therefore, in the cross-sectional shapes of the pixel electrodes 125 and the common electrodes 137, it is possible to avoid reflecting the uneven surface 138S of the reflective layer 138B constituting the reflective electrode 138. In this way, since the flatness of the pixel electrodes 125 and the common electrodes 137 is sufficiently ensured, compared with the case of the conventional common electrode arranged to overlap the reflective layer having an uneven surface with an insulating film interposed therebetween, it is difficult to generate a deviation in the interval between the pixel electrode 125 and the common electrode 137. As a result, the holding capacitance formed between the pixel electrode 125 and the common electrode 137 is stabilized, and thus the display quality is not easily deteriorated. In particular, in the present embodiment, on the uppermost layer of the array substrate 121, the pixel electrode 125 is arranged after the alignment film, and the uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is prevented from being exposed on the uppermost layer after the alignment film. Therefore, it is preferable for suppressing the volume change of the liquid crystal layer 122.

[0073] Moreover, in the present embodiment, as Figure 13 and Figure 16 shown, at a position on the upper layer side of the source wiring 127 and on the lower layer side of the pixel electrode 125, on the basis of the common electrode 137 set to a common potential, a reflective electrode 138 set to a common potential is further arranged. Therefore, the electric field generated from the source wiring 127 can be shielded doubly by the common electrode 137 and the reflective electrode 138. As a result, the parasitic capacitance generated between the source wiring 127 and the pixel electrode 125 can be further suppressed.

[0074] In addition, as Figure 19 shown, the exhaust hole 140 according to the present embodiment is provided in the common electrode 137 and the inter-electrode insulating film 135 located on the upper layer side of the second planarization film 136. Specifically, the exhaust hole 140 is formed by the second opening 137B provided in the common electrode 137 and the third opening 135A provided in the inter-electrode insulating film 135 communicating with each other. As Figure 17 and Figure 18As shown, the exhaust holes 140 are arranged at positions that overlap with the gate wiring 126 in a plan view, that is, at positions between two adjacent pixel electrodes 125 in the Y-axis direction. A plurality of exhaust holes 140 are arranged at intervals along the X-axis direction on the gate wiring 126, and the arrangement interval is about half of the arrangement interval of the source wiring 127. Specifically, the exhaust holes 140 are arranged at positions that overlap with the intersections of the gate wiring 126 and the source wiring 127 and at the intermediate positions between two adjacent source wirings 127 in the X-axis direction. Thus, since the exhaust holes 140 according to the present embodiment are arranged between two adjacent pixel electrodes 125 in the Y-axis direction, display defects caused by the exhaust holes 140 are hardly visible. Here, as Figure 13 and Figure 14 shown, the gas generated from the first planarization film 134 is released to the second planarization film 136 side through the transmission opening 138C of the reflective electrode 138. The gas generated from the first planarization film 134 and the second planarization film 136, as Figure 19 shown, passes through the second opening 137B and the third opening 135A that form the exhaust holes 140 in the second planarization film 136, and at the same time passes between two adjacent pixel electrodes 125 in the Y-axis direction and is released to the liquid crystal layer 122 side. Thereby, the gas generated from the first planarization film 134 and the second planarization film 136 can be discharged.

[0075] As described above, the liquid crystal panel 111 of the present embodiment includes: a TFT 124; a pixel electrode 125 connected to the TFT 124; a source wiring 127 connected to the TFT 124, located on a lower layer side than the pixel electrode 125, and transmitting an image signal supplied to the pixel electrode 125; a reflective electrode 138 located on an upper layer side than the source wiring 127, having a reflective layer 138B for reflecting light and the reflective layer 138B having a concavo-convex surface 138S; a common electrode 137 located on a lower layer side than the pixel electrode 125 and on an upper layer side than the source wiring 127, arranged to overlap at least the pixel electrode 125 and the source wiring 127 respectively, and set to a common potential; an inter-electrode insulating film 135 interposed between the pixel electrode 125 and the common electrode 137; a second planarization film (second insulating film) 136 located on an upper layer side than the source wiring 127, and arranged on the lower layer side of the common electrode 137, and having a film thickness larger than that of the inter-electrode insulating film 135.

[0076] When the TFT 124 is driven, the pixel electrode 125 is charged to a potential based on an image signal transmitted through the source wiring 127. The pixel electrode 125 is disposed to overlap with the common electrode 137 set to a common potential with an inter-electrode insulating film 135 therebetween, so that a holding capacitor is formed between the pixel electrode 125 and the common electrode 137. By using this holding capacitor, the potential of the charged pixel electrode 125 can be held well. On the other hand, by reflecting light with the reflective layer 138B of the reflective electrode 138, image display using external light can be performed. The reflective layer 138B of the reflective electrode 138 has a concavo-convex surface 138S, so that external light can be diffusely reflected, and thus a display close to the paper white can be achieved.

[0077] Since the common electrode 137 set to a common potential is disposed at a position above the source wiring 127 and below the pixel electrode 125, parasitic capacitance generated between the source wiring 127 and the pixel electrode 125 can be suppressed. Further, the second planarization film 136 that is located above the source wiring 127 and below the common electrode 137 and displays an image has a greater thickness than the inter-electrode insulating film 135, so that the flatness of the common electrode 137 located above the second planarization film 136 is sufficiently ensured. By ensuring the flatness of the common electrode 137, the flatness of the pixel electrode 125, which is disposed above the common electrode 137 with the inter-electrode insulating film 135 therebetween, can also be ensured. Therefore, compared with the case where a common electrode is provided to overlap with a reflective layer having a concavo-convex surface with an insulating film therebetween as in the past, it is difficult for a deviation to occur in the interval between the pixel electrode 125 and the common electrode 137. As a result, the holding capacitor formed between the pixel electrode 125 and the common electrode 137 is stabilized, and thus the display quality is not easily degraded.

[0078] In addition, in the array substrate 121, the reflective electrode 138 is disposed on the lower layer side with respect to the second planarization film 136 and is located on the upper layer side of the source wiring 127. The array substrate 121 includes a first planarization film (fourth insulating film) 134, which is disposed on the lower layer side with respect to the reflective electrode 138 and has a film thickness larger than that of the inter-electrode insulating film 135. Since the reflective electrode 138 is disposed on the lower layer side with respect to the second planarization film 136, the uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is planarized by the second planarization film 136. Compared with the case where the reflective electrode is disposed on the upper layer side of the pixel electrode 125, the uneven surface 138S of the reflective layer 138B can be prevented from being exposed to the uppermost layer. In addition, since the film thickness of the first planarization film 134 disposed on the lower layer side with respect to the reflective electrode 138 is larger than the film thickness of the inter-electrode insulating film 135, the reproducibility related to the shape of the uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is improved.

[0079] In addition, the reflective electrode 138 is set to a common potential. Since the reflective electrode 138 and the common electrode 137, both of which are set to the common potential, are disposed at a position on the upper layer side of the source wiring 127 and on the lower layer side of the pixel electrode 125, the parasitic capacitance generated between the source wiring 127 and the pixel electrode 125 can be further suppressed.

[0080] In addition, a plurality of pixel electrodes 125 are arranged at intervals. The reflective electrode 138 is disposed within a range spanning the plurality of pixel electrodes 125. The reflective electrode 138 is disposed to overlap the plurality of pixel electrodes 125 and is also disposed in the region between two adjacent pixel electrodes 125. In this way, compared with the case where a plurality of reflective electrodes are provided in a manner of separately overlapping the plurality of pixel electrodes 125, since the amount of reflected light based on the reflective layer 138B increases, it is preferable for improving the brightness related to the displayed image.

[0081] In addition, the array substrate 121 includes an intermediate electrode (fifth electrode) 41. The intermediate electrode (fifth electrode) 41 is disposed on the lower layer side with respect to the second planarization film 136 and on the upper layer side with respect to the first planarization film 134. The reflective electrode 138 has a transparent electrode layer 138A disposed on the lower layer side with respect to the reflective layer 138B. The intermediate electrode 41 is formed by a part of the transparent electrode layer 138A, and is disposed to overlap with a part of the TFT 124 and a part of the pixel electrode 125. In the first planarization film 134, a first pixel contact hole (second contact hole) CH4 that connects the intermediate electrode 41 to the TFT 124 is formed by opening at a position overlapping both the TFT 124 and the intermediate electrode 41. In the second planarization film 136, a second pixel contact hole (third contact hole) CH5 that connects the pixel electrode 125 to the intermediate electrode 41 is formed by opening at a position overlapping both the pixel electrode 125 and the intermediate electrode 41. The intermediate electrode 41 is connected to a part of the TFT 124 through the first pixel contact hole CH4 of the first planarization film 134, and a part of the pixel electrode 125 is connected to the intermediate electrode 41 through the second pixel contact hole CH5 of the second planarization film 136. Since the intermediate electrode 41 disposed to overlap with the pixel electrode 125 is formed by a part of the transparent electrode layer 138A, light can be transmitted. In addition, since the intermediate electrode 41 does not have the reflective layer 138B, a situation where a short circuit occurs with the reflective electrode 138 due to film residue of the reflective layer 138B can be avoided.

[0082] In addition, the liquid crystal panel 111 further includes a counter electrode (sixth electrode) 130 that is disposed to face the pixel electrode 125 with a gap therebetween and is set to a common potential, and a liquid crystal layer 122 interposed between the pixel electrode 125 and the counter electrode 130. An electric field with sufficient intensity can be generated between the pixel electrode 125 connected to the TFT 124 via the intermediate electrode 41 and the counter electrode 130. Thus, the alignment state of liquid crystal molecules included in the liquid crystal layer 122 can be favorably controlled by the electric field generated between the pixel electrode 125 and the counter electrode 130. Since the uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is prevented from being exposed to the outermost layer, it is preferable for suppressing volume change of the liquid crystal layer 122.

[0083] <Other Embodiments> The technology disclosed in this specification is not limited to the embodiments described according to the above description and drawings. For example, the following embodiments are also included in the technical scope.

[0084] (1) The specific planar shape of the pixel electrodes 25 and 125, the size observed in plan view, etc. may be appropriately changed in addition to those shown in the drawings.

[0085] (2) The specific configuration, number of settings, planar shape, size as viewed from above, etc. of the transmission openings 38C and 138C in the reflective electrodes 38 and 138 can be appropriately changed in addition to those shown in the drawings.

[0086] (3) The configuration, size as viewed from above, etc. of each electrode 24A, 24B, 24C, 124C and the semiconductor portion 24D constituting the TFTs 24 and 124 can be appropriately changed in addition to those shown in the drawings.

[0087] (4) The specific configuration, number of settings, planar shape, size as viewed from above, etc. of the exhaust holes 40 and 140 can be appropriately changed in addition to those shown in the drawings. For example, in the configuration described in Embodiment 1, the exhaust hole 40 can be disposed at a position overlapping with the gate wiring 26. For example, in the configuration described in Embodiment 2, all the exhaust holes 140 can be disposed at a position overlapping with the gate wiring 126 but not overlapping with the source wiring 127.

[0088] (5) The exhaust holes 40 and 140 can also be omitted.

[0089] (6) The specific line width, length dimension, etc. of the redundant wiring 39 can be appropriately changed in addition to those shown in the drawings. For example, the line width of the redundant wiring 39 can be substantially the same as that of the source wirings 27 and 127.

[0090] (7) The redundant wiring 39 can also be omitted.

[0091] (8) The liquid crystal panels 11 and 111 can be reflective in addition to the transflective type. When the liquid crystal panels 11 and 111 are reflective, the backlight device can be omitted.

[0092] (9) As described in (8) above, when the liquid crystal panels 11 and 111 are reflective, the transparent electrode layers 38A and 138A in the reflective electrodes 38 and 138 can be omitted, and the reflective electrodes 38 and 138 can be constituted only by the reflective layers 38B and 138B. In the configuration described in Embodiment 2, when the first transparent electrode film constituting the transparent electrode layer 138A is omitted, the intermediate electrode 41 may be constituted by a part of the third metal film.

[0093] (10) As described in (8) above, when the liquid crystal panels 11 and 111 are reflective, the pixel electrodes 25 and 125 and the common electrodes 37 and 137 can be constituted by a metal film instead of a transparent electrode film.

[0094] (11) As described in (8) above, when the liquid crystal panel 11 is reflective, in the configuration described in Embodiment 1, the transmission opening 38C in the reflective electrode 38 can be omitted.

[0095] The semiconductor film material constituting the semiconductor section 24D may also be amorphous silicon, polycrystalline silicon (low-temperature polycrystalline silicon), or the like.

[0096] (13)The color filter 28 may be omitted from the counter substrates 20 and 120, and the transflective liquid crystal panels 11 and 111 for monochromatic display may be adopted. Alternatively, the color filter 28 of the counter substrates 20 and 120 may not be omitted, but the specific color types and quantities in the color filter 28 may be changed.

[0097] (14)The color filter 28 may be provided on the array substrates 21 and 121 instead of the counter substrates 20 and 120.

[0098] (15)The operation mode of the liquid crystal panels 11 and 111 may also be an IPS (In-Plane Switching) mode or the like.

[0099] Description of Reference Numerals 11, 111... liquid crystal panel (display device), 22, 122... liquid crystal layer, 24, 124... TFT (switching element), 25, 125... pixel electrode (first electrode), 26, 126... gate wiring (second wiring), 27, 127... source wiring (first wiring), 30... counter electrode (fourth electrode), 32, 132... gate insulating film (fifth insulating film), 34... first planarization film (second insulating film), 35, 135... inter-electrode insulating film (first insulating film), 36... second planarization film (third insulating film), 37, 137... common electrode (third electrode), 38, 138... reflective electrode (second electrode), 38B, 138B... reflective layer, 38S, 138S... uneven surface, 39... redundant wiring (third wiring), 41... intermediate electrode (fifth electrode), 130... counter electrode (sixth electrode), 134... first planarization film (fourth insulating film), 136... second planarization film (second insulating film), 138A... transparent electrode layer, CH2... inter-electrode contact hole (first contact hole), CH3... inter-wiring contact hole (fourth contact hole), CH4... first pixel contact hole (second contact hole), CH5... second pixel contact hole (third contact hole).

Claims

1. A display device, characterized in that: include: Switching elements; A first electrode connected to the switch element; a first wiring connected to the switching element and located at a lower layer side than the first electrode, and transmitting an image signal supplied to the first electrode; a second electrode located at an upper layer side than the first wiring and having a reflective layer for reflecting light, the reflective layer having a concavoconvex surface; a third electrode located below the first electrode and above the first wiring, wherein the third electrode is arranged to overlap at least the first electrode and the first wiring, and is set to a common potential; a first insulating film disposed between the first electrode and the third electrode; as well as The second insulating film is located on the upper layer side than the first wiring and is arranged on the lower layer side with respect to the third electrode, and the film thickness of the second insulating film is larger than the film thickness of the first insulating film.

2. The display device according to claim 1, characterized in that The second electrode is arranged to be located on the upper layer side than the first electrode, The display device includes a third insulating film interposed between the second electrode and the first electrode, and a film thickness of the third insulating film is greater than a film thickness of the first insulating film.

3. The display device according to claim 2, characterized in that: The display device comprises: a fourth electrode disposed opposite to the second electrode with a gap therebetween and having a common potential; and a liquid crystal layer, which is between the second electrode and the fourth electrode, The second electrode is configured to overlap with the first electrode, A first contact hole for connecting the second electrode and the first electrode is opened in the third insulating film at a position overlapping with both the second electrode and the first electrode.

4. The display device according to claim 1, characterized in that The second electrode is arranged on the lower side with respect to the second insulating film, The display device includes a fourth insulating film located above the first wiring and below the second electrode, and having a thickness greater than that of the first insulating film.

5. The display device according to claim 4, characterized in that: The second electrode is set to the common potential.

6. The display device according to claim 5, characterized in that: A plurality of first electrodes are arranged in a spaced-apart manner. The second electrode is arranged in a range spanning a plurality of the first electrodes.

7. The display device according to any one of claims 4 to 6, characterized in that: The display device includes a fifth electrode, the fifth electrode being arranged on a lower layer side relative to the second insulating film and on an upper layer side relative to the fourth insulating film, The second electrode includes a transparent electrode film disposed on a lower layer side relative to the reflective layer. The fifth electrode is formed of a portion of the transparent electrode film, overlaps a portion of the switching element and overlaps a portion of the first electrode. A second contact hole is opened in the fourth insulating film at a position overlapping with both the switching element and the fifth electrode, and the second contact hole connects the fifth electrode to the switching element. A third contact hole is opened in the second insulating film at a position overlapping with both the first electrode and the fifth electrode, and the third contact hole connects the first electrode and the fifth electrode.

8. The display device according to claim 7, characterized in that: include: a sixth electrode disposed opposite to the first electrode with a gap therebetween and set to a common potential; as well as The liquid crystal layer is between the first electrode and the sixth electrode.

9. The display device according to any one of claims 1 to 6, characterized in that: include: a second wiring connected to the switch element and crossing the first wiring to transmit a scan signal; a fifth insulating film arranged on an upper layer side with respect to the first wiring and arranged on a lower layer side with respect to the second wiring; as well as a third wiring arranged on a lower layer side with respect to the fifth insulating film and arranged to overlap with the second wiring, A fourth contact hole is opened in the fifth insulating film at a position overlapping with both the second wiring and the third wiring, and the fourth contact hole connects the second wiring and the third wiring.

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