Power supply related thresholds for over-current protection

Abstract

The invention relates to a power supply related threshold for over-current protection. A reference signal generation circuit (260) includes a voltage to current V2I converter (610) having a terminal. The first current mirror (620) has a first terminal and a second terminal. The first terminal is coupled to the terminal of the V2I converter (610). The second current mirror (640) has a first terminal, a second terminal, and a third terminal. The first terminal of the second current mirror (640) is coupled to the second terminal of the first current mirror (620). A third current mirror (660) has a first terminal coupled to the second terminal of the first current mirror (620). The third current mirror (660) is coupled to the third terminal of the second current mirror (640).

Description

Technical Field

[0001] This application relates to power supply related thresholds for overcurrent protection. Background Art

[0002] Many electrical applications include overcurrent protection (OCP). In many OCP techniques, a current is compared to a threshold level. If the current exceeds the threshold level, an overcurrent signal is asserted. Logic can respond to the assertion of the overcurrent signal by, for example, turning off a switch (e.g., a transistor), thereby turning off the current. Summary of the Invention

[0003] In an example, a reference signal generation circuit includes a voltage-to-current (V2I) converter having terminals. A first current mirror has a first terminal and a second terminal. The first terminal is coupled to the terminal of the V2I converter. A second current mirror has a first terminal, a second terminal, and a third terminal. The first terminal of the second current mirror is coupled to the second terminal of the first current mirror. A third current mirror has a first terminal coupled to the second terminal of the first current mirror. The third current mirror is coupled to the third terminal of the second current mirror. Brief Description of the Drawings

[0004] Figure 1 is a block diagram of a system including an overcurrent protection circuit in an example.

[0005] Figure 2 is a circuit schematic of an overcurrent protection circuit including an example of a current sensing circuit.

[0006] Figure 3 is a circuit schematic of an overcurrent protection circuit including another example of a current sensing circuit.

[0007] Figure 4 is a diagram illustrating a fixed overcurrent protection threshold in an example.

[0008] Figure 5 is a diagram illustrating a piecewise linear overcurrent protection threshold in another example.

[0009] Figure 6 is available for Figure 1-3 a circuit schematic of an example of a reference signal generation circuit in an overcurrent protection circuit.

[0010] Figure 7 is available for Figure 1-3 a circuit schematic of another example of a reference signal generation circuit in an overcurrent protection circuit.

[0011] Figure 8 is a flowchart of a method for detecting an overcurrent condition in an example. Detailed implementation manners

[0012] The same reference numerals or other reference indicators are used in the figures to denote the same or similar features (functionally and / or structurally).

[0013] Figure 1 is a block diagram of the system 90 in the example. The system 90 includes a driver 100 and a load 180. The driver 100 includes driver terminals 101, 102, 103, and 104. Terminals 102 and 103 are coupled to the power supply voltage Vin and ground, respectively. Terminal 101 is the input terminal of the driver 100, and terminal 104 is the output terminal coupled to the load 180. In one example, the load 180 can be a motor, such as a stepper motor, a direct current (DC) motor, a polyphase (e.g., three-phase) motor, etc. In another example, the load 180 can be the power stage of a power converter, such as a buck converter, a boost converter, etc. As a power converter, the load 180 can include one or more inductors and capacitors.

[0014] The driver 100 includes a controller 110, one or more half-bridges 130, and a pair of over-current protection (OCP) circuits 150a and 150b coupled to each half-bridge 130. The driver 100 may also include additional components. The controller 110 includes controller terminals 111, 112, 113, 114, and 115. The OCP circuit 150a includes terminals 151a, 152a, 153a, and 154a. The OCP circuit 150b includes terminals 151b, 152b, 153b, and 154b. The driver terminal 101 is coupled to the controller terminal 115. Each half-bridge 130 includes gate drivers 132 and 136 and transistors 134 and 138. The controller terminal 111 is coupled to the input of the gate driver 132, and the controller terminal 112 is coupled to the input of the gate driver 136. The terminal 151a of the OCP circuit 150a is coupled to the transistor 134, and the terminal 151b of the OCP circuit 150b is coupled to the transistor 138. The dashed lines connecting the terminals 151a and 151b to their respective transistors 134 and 138 indicate different ways in which the current sensing circuits within the OCP circuits 150a and 150b can be coupled to the transistors 134 and 138 (described below). The terminals 152a and 154a of the OCP circuit 150a are coupled to the driver terminals 102 and 103, respectively. Similarly, the terminals 152b and 154b of the OCP circuit 150b are coupled to the driver terminals 102 and 103, respectively. The terminal 153a of the OCP circuit 150a is coupled to the controller terminal 113, and the terminal 153b of the OCP circuit 150b is coupled to the controller terminal 114.

[0015] Within each half-bridge, the transistors 134 and 138 can be Figure 1The n-channel field effect transistor (NFET) shown in the example of, or either or both of transistors 134 and 138, can be implemented as another type of transistor. In Figure 1 the example of, the drain terminal of transistor 134 is coupled to driver terminal 102, and the source terminal of transistor 138 is coupled to driver terminal 103. The source terminal of transistor 134 is coupled to the drain terminal of transistor 138 at switch terminal 139. Switch terminal 139 is coupled to driver terminal 104. Load 180 is coupled to driver terminal 104. The output of gate driver 132 is coupled to the gate terminal of transistor 134, and the output of gate driver 136 is coupled to the gate terminal of transistor 138.

[0016] In one example, driver 100 including controller 110, half-bridge 130, and OCP circuits 150a and 150b can be fabricated on the same semiconductor die (integrated circuit (“IC”)). Load 180 can be a component separate from the semiconductor die of the component containing driver 100. In another example, driver 100 and load 180 can be fabricated as separate semiconductor dies but packaged together as a single packaged device.

[0017] In response to a signal at driver terminal 101, in one example, controller 110 generates a pulse width modulation (PWM) signal (e.g., inside controller 110) to control the on and off states of transistors 134 and 138 within a given half-bridge 130. Based on the PWM signal, controller 110 controls the duty cycle of the timing of transistors 134 and 138. Controller 110 generates a control signal at terminal 111 to turn on and off transistor 134. Controller 110 also generates a control signal at terminal 112 to turn on and off transistor 138. In response to the control signals from terminals 111 and 112, gate drivers 132 and 136 generate appropriate voltages to turn on and off corresponding transistors 134 and 138.

[0018] In response to transistor 134 being turned on, current flows from driver terminal 102 through transistor 134 to load 180. In response to transistor 138 being turned on, current flows from driver terminal 103 through transistor 138 to load 180. In one example, load 180 is an inductive load (e.g., a motor, an inductor, etc.). When transistor 134 is turned on, due to the inductance of the load, the current Iload through the transistor to the load ramps up as shown by reference numeral 175. When transistor 138 is turned on, the current to the load continues to flow through transistor 138 but ramps down as indicated by reference numeral 176. OCP circuits 150a and 150b are operable to detect short - circuit conditions associated with transistors 134, 138 to which each OCP circuit is coupled. As described below, each of OCP circuits 150a and 150b generates a threshold current based on the magnitude of voltage Vin and compares the current sensed from its corresponding transistor 134, 138 with the threshold current to determine whether an over - current condition has occurred. If OCP circuit 150a does not detect an over - current condition, OCP circuit 150a forces the signal OCP_OUTH 158a at its terminal 153a to a first logic state (e.g., logic high). Similarly, if OCP circuit 150b does not detect an over - current condition, OCP circuit 150b forces the signal OCP_OUTL 158b at its terminal 153b to a first logic state.

[0019] Any one of a plurality of short - circuit conditions can be detected by either OCP circuit 150a or 150b. For example, if driver terminal 104 is inadvertently shorted to ground, an over - current condition will occur when controller 110 turns on transistor 134. OCP circuit 150a detects the over - current condition associated with transistor 134 and asserts the signal OCP_OUTH 158a at terminal 153a connected to controller terminal 113 to a second logic state (e.g., logic low). Controller 110 can respond to the asserted signal at terminal 113 by turning off transistor 134. Similarly, if driver terminal 104 is inadvertently shorted to voltage Vin, an over - current condition will occur when controller 110 turns on transistor 138. OCP circuit 150b detects the over - current condition associated with transistor 138 and asserts the signal OCP_OUTL 158b at terminal 153b connected to controller terminal 114 to a second logic state. Controller 110 can respond to the asserted signal at terminal 114 by, for example, turning off transistor 138.

[0020] Figure 2 is a schematic diagram of example OCP circuit 150b. OCP circuit 150a can be used Figure 2implemented by the same circuit shown herein. In this example, the OCP circuit 150b includes a current sensing circuit 220a, a comparator 240, and a reference signal generation circuit 260. The reference signal generation circuit 260 has terminals 261 and 262. The current sensing circuit 220a has terminals 221, 222, 223, and 224. The comparator 240 has terminals 241, 242, and 243. In Figure 2 the example, terminal 241 is the positive (+) terminal of the comparator 240, and terminal 242 is the negative (-) terminal of the comparator 240. Terminal 243 is the output of the comparator 240.

[0021] In Figure 2 the example, terminal 221 of the current sensing circuit 220a is coupled to the gate of the transistor 138, and terminal 223 is coupled to the drain of the transistor 138. Terminals 221 and 223 represent terminals 151b of the overcurrent protection circuit 150b. Terminal 224 of the current sensing circuit 220a is coupled to terminal 154b of the overcurrent protection circuit 150b. Terminal 222 of the current sensing circuit 220a is coupled to terminal 242 of the comparator 240. Terminal 261 of the reference signal generation circuit 260 is coupled to terminal 152b of the OCP circuit 150b. Terminal 262 of the reference signal generation circuit 260 is coupled to the positive terminal (terminal 241) of the comparator 240. Terminal 243 of the comparator is coupled to terminal 153b of the OCP circuit 150b.

[0022] Figure 2 The current sensing circuit 220a in the example includes a transistor 227 and a resistor R1. The transistor 227 can be an NFET as shown or a different type of transistor. The gate terminal and the drain terminal of the transistor 227 are coupled to terminals 221 and 223, respectively, and thus are coupled to the gate terminal and the drain terminal of the transistor 138, respectively. The resistor R1 is coupled between the source terminal of the transistor 227 and terminal 154b of the OCP circuit 150b.

[0023] The size of a field effect transistor (FET) refers to the ratio of the width (W) of its channel to the length (L) of its channel. In an example, transistor 227 is smaller than transistor 138. The current Isns passing through transistor 227 is proportional to the current I_138 passing through transistor 138. The ratio of the magnitude of the current Isns to the magnitude of the current I_138 is the ratio of the effective impedance of transistor 227 plus the resistance of resistor R1 to the impedance of transistor 138. For example, if the size of transistor 227 is one percent of the size of transistor 138, then for a resistor R1 whose resistance is much smaller than the impedance of transistor 227, the magnitude of the current Isns will be approximately one percent of the magnitude of the current I_138. The current Isns flows through resistor R1 and generates a voltage Vsns across resistor R1, i.e., Isns * R1. Therefore, the voltage Vsns is proportional to the current I_138 and is thus a proxy for the current I_138.

[0024] The reference signal generation circuit 260 receives a voltage Vin at its terminal 261. As described below, the reference signal generation circuit 260 generates a threshold current based on the voltage Vin and converts the threshold current into a threshold voltage OCP_TH, which can be a proxy for the threshold current. The threshold voltage OCP_TH is provided to the positive terminal (terminal 241) of the comparator 240. The comparator 240 compares the current I_138 with the threshold current to determine whether an overcurrent situation exists by comparing the threshold voltage OCP_TH with the voltage Vsns. Using the threshold voltage OCP_TH provided at the positive terminal of the comparator 240 and the voltage Vsns provided at the negative terminal (terminal 242) of the comparator 240, if Vsns is less than the threshold voltage OCP_TH and thus the current Isns is less than the threshold current generated inside the reference signal generation circuit 260, the comparator 240 makes its output signal OCP_OUTL logic high. Otherwise, if Vsns is greater than the threshold voltage OCP_TH, the comparator 240 makes its output signal OCP_OUTL logic low.

[0025] Figure 3 has a current sensing circuit 220b instead of Figure 2Schematic diagram of an example OCP protection circuit 150b for the current sensing circuit 220a in []. The current sensing circuit 220b includes terminals 321 and 322. The terminals 321 and 322 are coupled to the terminals 151b and 154b of the OCP protection circuit 150b, respectively. The current sensing circuit 220b includes a resistive device 320 coupled between the terminals 321 and 322. In one example, the resistive device 320 includes a resistor. In other examples, the resistive device 320 is coupled between the drain of the transistor 138 and the load 180 or between the drain of the transistor 134 and the driver terminal 102. The resistance of the resistive device 320 is relatively low, for example, 100 milliohms. The current I_138 flows through the transistor 138 and also through the resistive device 320, thereby generating a voltage Vsns proportional to the current I_138 across the resistive device 320. Figure 3 The comparator 240 and the reference signal generation circuit 260 in [] are largely the same as Figure 2 those in [].

[0026] Figure 4 is a graph in which, for a given gate-to-source voltage (Vgs), the y-axis represents the transistor drain current (Id) and the x-axis represents the transistor drain-source voltage (Vds). The curve 402 is an example of the relationship between the drain current of the transistors 134 and 138 and the Vds of the transistors. The curve 402 shows the magnitude of the current passing through the transistors for a given value of Vds of the transistors 134 and 138. During normal operation (without a short circuit), the Vds of the transistors 134 and 138 is less than the voltage Vin. For example, Vin can be 4V, but the Vds applied to the transistors 134 and 138 can be 3V. According to the curve 402, for a Vds of 3V, the drain current of the transistor will be approximately 2.4A. However, if the switch terminal 139 is inadvertently shorted to the driver terminal 102 (which has the voltage Vin) when the controller 110 turns on, for example, the transistor 138, then the Vds of the transistor 138 will be equal to 4V instead of 3V, and the drain current passing through the transistor 138 will be equal to 2.7A instead of 2.4A. In this example where Vin is equal to 4V, the short circuit will generate a current of 2.7A.

[0027] Generally, for a short circuit condition (the switch terminal is shorted to ground or Vin), the current passing through the transistors 134 and 138 is a function of Vin. The voltage Vin can be any voltage in the range from Vin41 to a higher operating voltage (e.g., 12.5V). In Figure 4 the example of [], Vin41 is 2.5V and Vin42 is 4.5V. Therefore, depending on the magnitude of Vin, the short circuit current passing through the transistors 134 and 138 can be in the range of approximately 2.2A to 3.3A.

[0028] In one example, OCP circuits 150a and 150b can be configured to have a fixed OCP current threshold 406 that corresponds to the maximum value of the transistor current when Vin equals 4.5V during a short circuit condition. In Figure 4 the example, the fixed OCP current threshold 406 is 2.9A. The OCP circuits 150a and 150b compare the magnitude of the current through respective transistors 134 or 148 of the OCP circuits with the fixed OCP current threshold 406 by comparing corresponding voltage representatives Vsns and OCP_TH, for example. In one example, the fixed OCP current threshold 406 implemented by the OCP circuits 150a and 150b is set at a level approximately equal to the sensed current Isns corresponding to the fixed OCP current threshold 406. In response to the OCP circuits 150a, 150b detecting that the current of the corresponding transistors 134, 138 has reached or exceeded the fixed OCP current threshold 406, the OCP circuits 150a, 150b assert corresponding output signals OCP_OUTH 158a or OCP_OUTL 158b to indicate an overcurrent condition.

[0029] However, if the voltage Vin is provided at a level less than voltage Vin42 (e.g., at 4V instead of 4.5V), the drain current through transistors 134, 138 during a short circuit condition will be 2.7A which is less than the fixed OCP current threshold 406 of 2.9A, and a short circuit with a Vin value greater than 4V will be undetectable (a false negative). On the other hand, if the fixed OCP current threshold 406 is set to a lower value, e.g., 2.7A, the OCP circuits 150a, 150b will erroneously detect a drain current higher than the fixed OCP current threshold 2.7A as a short circuit condition only due to using a Vin large enough to make the Vds of transistors 134, 138 greater than 4V (a false positive).

[0030] In examples implementing a fixed OCP current threshold, the half-bridge 130 can include a temperature sensor for sensing the temperature of transistor 134 and another temperature sensor for sensing the temperature of transistor 138. The output signals from such temperature sensors can be monitored by the controller 110. The controller 110 can use the signals from the temperature sensors to determine whether an overcurrent condition has occurred for a voltage VM within a range 435. For a voltage VM at or above voltage Vin42, the controller 110 can use the output signals 158a and 158b from the OCP circuits 150a and 150b, respectively.

[0031] Figure 5A graph in which the y-axis represents current and the x-axis represents the voltage Vin. Curve 502 represents the current through transistors 134, 138 relative to the voltage Vin for the short-circuit cases where the switch terminal 139 is shorted to ground or Vin. In either case, the Vds of the transistor is Vin. Compared with the fixed OCP current threshold 406, Figure 5 The graph of Figure 5 includes a piecewise-linear reference current Iref relative to the voltage Vin. The piecewise-linear graph of the current Iref includes a linear segment 531 corresponding to a first range 521 of the voltage Vin between Vin51 and Vin52. The linear segment 531 of the current Iref causes the current Iref to be proportional to the voltage Vin. In a second range 522 of the voltage Vin above Vin52, the current Iref is substantially constant, e.g., independent of the voltage Vin. In an example, each OCP circuit 150a and 150b generates the reference current Iref according to Figure 5 The piecewise-linear graph of Figure 5 . For the linear segment 531, the reference current Iref scales relative to Vin and thus scales relative to Vin for the short-circuit cases. Therefore, compared with using Figure 4 The fixed OCP current threshold 406 in Figure 4 , the risk of false positives and false negatives in short-circuit detection is reduced. Thus, a system whose OCP circuit implements a piecewise-linear reference current may advantageously also not include the temperature sensor described above.

[0032] Figure 6 FIG. is a circuit schematic diagram of an example reference signal generation circuit 260 that can be used in either or both of the OCP circuits 150a or 150b. In this example, the reference signal generation circuit 260 includes a voltage-to-current (V2I) converter 610, current mirrors 620, 640, 660, and 680, a current source circuit 630, and a resistor 690. The V2I converter 610 has terminals 611 and 612. The current mirror 620 has terminals 621 and 622. The current mirror 640 has terminals 641, 642, and 643. The current mirror 660 has terminals 661, 662, and 663. The current mirror 680 has terminals 681 and 682. The current source circuit 630 has a terminal 631.

[0033] Terminal 611 of the V2I converter 610 is coupled to terminal 261 of the reference signal generation circuit 260. Terminal 612 of the V2I converter 610 is coupled to terminal 621 of the current mirror 620. Terminal 622 of the current mirror 620 is coupled to terminal 642 of the current mirror 640. Terminal 631 of the current source circuit 630 is coupled to terminal 641 of the current mirror 640. Terminal 662 of the current mirror 660 is coupled to terminal 643 of the current mirror 640. Terminal 681 of the current mirror 680 is coupled to terminal 661 of the current mirror 660. Terminal 682 of the current mirror 680 is coupled to the positive terminal (terminal 241) of the resistor 690 and the comparator 240. The resistor 690 is coupled between terminal 682 and ground (e.g., terminal 154a or 154b in the corresponding OCP circuits 150a, 150b).

[0034] In Figure 6 the example of, the V2I converter 610 includes resistors 613, 614 and 617, an operational amplifier (OP-AMP) 615 and a transistor 616. The transistor 616 is an NNFET in this example, but may be a different type of transistor in other examples. Resistors 613 and 614 are serially coupled between terminal 611 and 154a (154b) and form a voltage divider. In one example, the resistance of resistor 614 is R', and the resistance of resistor 613 is (k - 1)*R', where R' is any suitable resistance (e.g., 100 kiloohms), and k is an integer greater than 1. The connection 619 between resistors 613 and 614 is coupled to the positive terminal of the OP-AMP 615. The output 618 of the OP-AMP is coupled to the gate of the transistor 616. The source of the transistor 616 is coupled to the resistor 617 and to the negative input of the OP-AMP 615. The resistor 617 is coupled between the source of the transistor 617 and ground (e.g., terminal 154a / 154b). The drain of the transistor 616 is coupled to terminal 612.

[0035] The current mirror 620 includes transistors 624 and 626. The transistors 624 and 626 are p-channel field effect transistors (PFETs) in this example, but may be implemented as other types of transistors in other examples. The gates of the transistors 624 and 626 are coupled together and coupled to the drain of the transistor 624 and terminal 621. The sources of the transistors 624 and 626 are coupled together and coupled to the power supply voltage terminal 609, which may be equal to Vin or an internally generated voltage, e.g., a voltage less than Vin. The drain of the transistor 626 is coupled to terminal 622. The drain current through the transistor 624 is mirrored by the transistor 626. In one example, the current mirror ratio between the transistors 624 and 626 is 1:1, but may not be 1:1 in other examples.

[0036] The current mirror 640 includes transistors 644, 646, and 648. In this example, transistors 664, 646, and 648 are NFETs, but in other examples, they may be implemented as other types of transistors. The gates of transistors 644, 646, and 648 are coupled together and coupled to the drain of transistor 644 and terminal 641. The sources of transistors 644, 646, and 648 are coupled together and coupled to terminals 154a or 154b of the respective OCP circuits 150a, 150b. The drain of transistor 646 is coupled to terminal 642, and the drain of transistor 648 is coupled to terminal 643. The drain current through transistor 644 is mirrored through transistors 646 and 648. In one example, the current mirror ratio between transistors 644 and 646 is 1:1, but in other examples, it may not be 1:1. Additionally, the current mirror ratio between transistors 644 and 648 is 1:n. The value of n can be, for example, 5.

[0037] The current mirror 660 includes transistors 664 and 666. In this example, transistors 664 and 666 are NFETs, but in other examples, they may be implemented as other types of transistors. The gates of transistors 664 and 666 are coupled together and coupled to the drain of transistor 664 and terminal 661. The sources of transistors 664 and 666 are coupled together and coupled to terminal 662. The drain of transistor 666 is coupled to terminal 663. The drain current through transistor 664 is mirrored through transistor 666. In one example, the current mirror ratio between transistors 684 and 686 is 1:m. The value of m can be, for example, 4.

[0038] The current mirror 680 includes transistors 684 and 686. In this example, transistors 684 and 686 are PFETs, but in other examples, they may be implemented as other types of transistors. The gates of transistors 684 and 686 are coupled together and coupled to the drain of transistor 684 and terminal 681. The sources of transistors 684 and 686 are coupled together and coupled to the power supply voltage terminal 609. The drain of transistor 686 is coupled to terminal 682. The drain current through transistor 684 is mirrored through transistor 686. In one example, the current mirror ratio between transistors 684 and 686 is 1:1, but in other examples, it may not be 1:1.

[0039] The current flowing through transistors 624 and 616 and resistor 617 is current I1. The current flowing through transistor 626 is current I2. Current source circuit 630 generates a current Ib flowing through transistor 644. The current flowing through transistor 664 is current I3. The current flowing through transistor 646 is current I4. The current flowing through transistor 648 is current I4. The current flowing through transistors 684 and 666 is current I5. The current flowing through transistor 648 is current I6. Reference current Iref flows through transistor 686 and resistor 690. The voltage across resistor 690 generated by the reference current Iref flowing through resistor 690 is the threshold voltage OCP_TH.

[0040] The voltage divider formed by resistors 613 and 614 provides a voltage 605 proportional to voltage Vin to the positive input terminal of OP-AMP 615. The voltage 605 is:

[0041]

[0042] Since the voltage on the negative input terminal of the operational amplifier is equal to the voltage on the positive input terminal of the operational amplifier, the voltage on the negative input terminal of the operational amplifier and thus the voltage across resistor 617 are also:

[0043]

[0044] Current I1 is the voltage across resistor 617 divided by its resistance. In an example where the resistance of resistor 617 is R', current I1 is:

[0045]

[0046] Therefore, V2I converter 610 converts voltage Vin into current I1, and current I1 is proportional to voltage Vin.

[0047] The following description describes the operation of reference signal generation circuit 260 when current I2 is greater than current Ib. Voltage Vin51 represents the voltage level of voltage Vin that generates a current I1 greater than current Ib. Current mirror 620 mirrors current I1 into current I2. Since current I1 is proportional to voltage Vin, current I2 is also proportional to voltage Vin. In an example where the current mirror ratio of current mirror 620 is 1:1 Figure 6 current I2 will be equal to current I1. Therefore, when current I1 is greater than current Ib, current I2 will be greater than current Ib. In an example where the current mirror ratio between transistors 644 and 646 is 1:1, current I4 will be equal to current Ib. When current I2 is greater than current Ib, current I3 is the difference between current I2 and I4, i.e.:

[0048] I3 = I2 - I4 (Equation 4)

[0049] Therefore, when current I2 is greater than current Ib, current I3 is proportional to voltage Vin.

[0050] In an example where the current mirror ratio of current mirror 660 is 1:m, Figure 6 current I5 is m*I3. Since current I3 is proportional to voltage Vin, current I4 is also proportional to voltage Vin. For the 1:1 current mirror ratio of current mirror 680, reference current Iref is equal to current I5, and thus, current Iref is proportional to current I5. Reference current Iref flows through resistor 690, and thus, reference voltage OCP_TH is proportional to voltage Vin, as Figure 5 indicated by region 521 in. In region 421, the relationship between reference voltage Vin and reference current Iref is:

[0051]

[0052] The slope of reference current Iref in region 521 is m / (k*R'). Therefore, the current mirror ratio m of current mirror 660 sets the slope of reference current Iref with respect to voltage Vin.

[0053] For a voltage Vin equal to 0V, current I1 will be 0 amperes. If current I1 is 0 amperes, then current I2 will also be 0 amperes. If current I2 is 0 amperes, then currents I3 and I4 will also be 0 amperes. If current I3 is 0 amperes, then current I5 will be 0 amperes, and thus, reference current Iref will be 0 amperes. If reference current Iref is 0 amperes, then reference voltage OCP_TH will be 0V. This situation where both voltage Vin and reference voltage OCP_TH are at 0V is Figure 5 identified by point 551 in.

[0054] For levels of voltage Vin that are greater than 0V but less than Vin51, current I1 is greater than 0 amperes but less than current Ib. If current I1 is less than current Ib, then currents I3, I4, and I5, as well as reference current Iref, are all 0 amperes, and reference voltage OCP_TH is also 0V, as Figure 5 shown in region 523 in.

[0055] As described above, for levels of the voltage Vin above Vin51, the reference current Iref increases linearly with respect to the voltage Vin, as shown in region 521. The sum of currents I3 and I5 is not greater than current I6. Current I6 is equal to n*Ib. Current I6 represents the upper limit of the sum of currents I3 and I5. The level Vin52 of the voltage Vin represents the voltage Vin at which currents I3 and I5 are equal to I6. For levels of the voltage Vin greater than Vin52, due to the upper limit of the sum of I3 and I5 imposed by current I6 through transistor 648, current I5 and thus the reference current Iref will not increase above Imax. Thus, for levels of the voltage Vin above Vin52, the reference current Iref is a constant level Imax. The current Imax is

[0056]

[0057] Because the reference voltage OCP_TH is proportional to the reference current Iref, for levels of the voltage Vin above Vin52, the reference voltage OCP_TH is also constant. In region 522, the reference voltage OCP_TH, which is the product of the reference current Iref and the resistance of resistor 690, is:

[0058]

[0059] where R_690 is the resistance of resistor 690.

[0060] Figure 7 is a schematic diagram of the reference signal generation circuit 260 in the OCP protection circuit 150a for transistor 134 ( Figure 1 ). Figure 7 The reference signal generation circuit 260 in the instance of Figure 6 is generally the same as the reference signal generation circuit of Figure 6 , but includes an additional current mirror 750 coupled to terminal 682 of current mirror 680. Current mirror 750 includes transistors 752 and 754. Resistor 790 is coupled between terminal 261 and the source of transistor 754. The current through resistor 790 generates the reference voltage OCP_TH.

[0061] Figure 8 is a flowchart of a method 800 for detecting an overcurrent condition. Figure 8 The operations shown in the instance of Figure 8 can be performed by the OCP circuit (e.g., OCP circuits 150a and / or 150b) described above. Method 800 may include operations 802, 804, 806, 808, 810, 812, and 814. Operation 802 includes generating a reference signal that is proportional to an input voltage (e.g., Vin) within a first voltage range and constant for an input voltage within a second voltage range. In one instance, the first voltage range may beFigure 5 The voltage range in [reference] is 521, and the second voltage range may be voltage range 522.

[0062] For operation 804, the method includes sensing a current through a transistor. The transistor can be any one of the transistors in, for example, half-bridge 130, which can be part of a motor driver, a power converter, or other applications that include a half-bridge. The current can be sensed as described above, for example, as described in the examples of [references] Figure 2 and 3 to sense the current.

[0063] For operation 806, the sensed current is compared with a reference signal. In decision operation 808, the method determines whether the sensed current is greater than the reference signal. If the sensed current is greater than the reference signal ("Y" branch), then at operation 810, the method includes setting an overcurrent signal to a first logic state, such as logic high. For example, the overcurrent signal can be output signal OCP_OUTH 158a from OCP circuit 150a or output signal OCP_OUTL 158b from OCP circuit 150b. In operation 812, in response to the first logic state of the overcurrent signal, a controller (e.g., controller 110) can take corrective action. For example, the controller can turn off the transistor whose current is determined to be too high or turn off the entire half-bridge that includes the transistor. However, if the sensed current does not exceed the reference signal, then at operation 814, the overcurrent signal is set to a second logic state, such as logic low, thereby indicating that no overcurrent condition has been detected, and the control loop returns to operation 806.

[0064] In this description, the term "coupled" can encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B through a direct connection; or (b) in a second example, device A is coupled to device B through an intermediate component C, provided that intermediate component C does not change the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

[0065] Additionally, in this specification, the recitation "based on" means "at least partially based on". Thus, if X is based on Y, then X can depend on Y and any number of other factors.

[0066] A device “configured to” perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or can be user-configurable (or reconfigurable) after manufacture to perform the function and / or other additional or alternative functions. The configuration can be performed by firmware and / or software programming of the device, by the construction and / or layout of hardware components and the interconnection of the device, or a combination thereof.

[0067] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” may be used interchangeably. Unless specifically stated to the contrary, these terms generally are used to mean an interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components or their ends.

[0068] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements (e.g., semiconductor die and / or integrated circuit (IC) packages) within a single physical device, and may be adapted to be coupled to at least some of the passive elements and / or sources at the time of manufacture or after manufacture, e.g., by an end user and / or a third party, to form the described structure.

[0069] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may alternatively be used with little change to the rest of the circuitry. For example, a field effect transistor (“FET”) (e.g., an n-channel FET (NFET) or a p-channel FET (PFET)), a bipolar junction transistor (BJT - e.g., an NPN transistor or a PNP transistor), an insulated gate bipolar transistor (IGBT), and / or a junction field effect transistor (JFET) may be used instead of or in combination with the devices described herein. The transistor may be a depletion device, a drain extension device, an enhancement device, a natural transistor, or other types of device structure transistors. Additionally, the device may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0070] The terminals of a transistor may be referred to in the claims. In the context of an FET, the terminals are the gate, drain, and source. In the context of a BJT, the terminals are the base, collector, and emitter.

[0071] The circuits described herein can be reconfigured to include additional or different components to provide at least partially a functionality similar to that available prior to component replacement. Unless otherwise specified, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0072] Although some elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features can be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit can be included in the integrated circuit, and / or some of the features described as internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) are incorporated in / above a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0073] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "substantially", or "essentially" in front of a parameter means within + / - 10% of the parameter, or, if the parameter is zero, within a reasonable value range that is approximately zero.

[0074] Modifications of the described examples are possible within the scope of the claims, and other examples are possible.

Claims

1. A reference signal generating circuit, comprising: A voltage to current V2I converter having terminals; a first current mirror having a first terminal and a second terminal, the first terminal being coupled to the terminal of the V2I converter; a second current mirror having a first terminal, a second terminal and a third terminal, the first terminal of the second current mirror being coupled to the second terminal of the first current mirror; as well as A third current mirror has a first terminal coupled to the second terminal of the first current mirror, and the third current mirror is coupled to the third terminal of the second current mirror.

2. The reference signal generating circuit of claim 1, wherein the third current mirror has a second terminal, and the reference signal generating circuit further comprises a fourth current mirror having a first terminal coupled to the second terminal of the third current mirror.

3. The reference signal generating circuit according to claim 2, wherein the third current mirror has a first field effect transistor FET and a second FET, the first FET has a source terminal, the second FET has a source terminal, and the source terminals of the first and second FETs are coupled together and coupled to the third terminal of the second current mirror.

4. The reference signal generating circuit according to claim 1, wherein The second current mirror has a current mirror ratio of 1:n between the first terminal of the second current mirror and the third terminal of the second current mirror; The third current mirror has a second terminal and has a current mirror ratio of 1:m between the first terminal of the third current mirror and the second terminal of the third current mirror; and Where m is different from n. 5 . The reference signal generating circuit of claim 1 , further comprising a current source circuit having a terminal coupled to the first terminal of the second current mirror.

6. The reference signal generating circuit of claim 1, wherein the third current mirror has a second terminal, and the reference signal generating circuit comprises a fourth current mirror having a terminal coupled to the second terminal of the third current mirror.

7. The reference signal generating circuit of claim 6, wherein the terminal of the fourth current mirror is a first terminal, the fourth current mirror has a second terminal, and the reference signal generating circuit comprises a resistor coupled to the second terminal of the fourth current mirror.

8. An integrated circuit IC, comprising: a first transistor; a current sensing circuit having a first terminal and a second terminal, the first terminal being coupled to the first transistor; a comparator having a first comparator terminal and a second comparator terminal, the second comparator terminal coupled to the second terminal of the current sensing circuit; as well as A reference signal generating circuit, comprising: A voltage to current V2I converter having terminals; a first current mirror having a first terminal and a second terminal, the first terminal being coupled to the terminal of the V2I converter; a second current mirror having a first terminal, a second terminal and a third terminal, the first terminal of the second current mirror being coupled to the second terminal of the first current mirror; as well as a third current mirror having a first terminal and a second terminal, the first terminal of the third current mirror being coupled to the second terminal of the first current mirror, the third current mirror being coupled to the third terminal of the second current mirror, and the second terminal of the third current mirror being coupled to the first comparator terminal of the comparator.

9. The IC of claim 8, wherein the third current mirror has a first field effect transistor (FET) and a second FET, the first FET having a source terminal, the second FET having a source terminal, and the source terminals of the first and second FETs are coupled together and coupled to the third terminal of the second current mirror.

10. The IC of claim 8, wherein: The second current mirror has a current mirror ratio of 1:n between the first terminal of the second current mirror and the third terminal of the second current mirror; The third current mirror has a second terminal and has a current mirror ratio of 1:m between the first terminal of the third current mirror and the second terminal of the third current mirror; and Where m is different from n.

11. The IC of claim 8, further comprising a current source circuit having a terminal coupled to the first terminal of the second current mirror.

12. An integrated circuit IC, comprising: a first transistor; a current sensing circuit having a first terminal and a second terminal, the first terminal being coupled to the first transistor; a reference signal generating circuit having a first terminal and a second terminal, the reference signal generating circuit being configured to generate a signal at the second terminal that is a function of a voltage at the first terminal of the reference signal generating circuit within a first voltage range; as well as A comparator having a first terminal and a second terminal, the first terminal of the comparator being coupled to the second terminal of the reference signal generating circuit, and the second terminal of the comparator being coupled to the second terminal of the current sensing circuit.

13. The IC of claim 12, wherein the reference signal generating circuit is configured to generate the signal at the second terminal, the signal being substantially constant within a second voltage range. The IC of claim 13 , wherein the second voltage range is higher than the first voltage range.

15. The IC of claim 12, wherein the reference signal generating circuit comprises: a first current mirror having a first terminal and a second terminal; a current source circuit having terminals; a second current mirror having a first terminal, a second terminal and a third terminal, the first terminal of the second current mirror being coupled to the terminal of the current source circuit and the second terminal of the second current mirror being coupled to the second terminal of the first current mirror; as well as A third current mirror has a first terminal and a second terminal, the first terminal of the third current mirror being coupled to the second terminal of the first current mirror, and the second terminal of the third current mirror being coupled to the third terminal of the second current mirror.

16. The IC of claim 15, further comprising a voltage-to-current (V2I) converter having a first terminal and a second terminal, the first terminal of the V2I converter being coupled to the first terminal of the reference signal generating circuit, and the second terminal of the V2I converter being coupled to the first terminal of the first current mirror.

17. The IC of claim 15, wherein the third current mirror has a third terminal, and the driver further comprises a fourth current mirror having a first terminal coupled to the third terminal of the third current mirror.

18. The IC of claim 17, wherein the third current mirror has a first field effect transistor (FET) and a second FET, the first FET having a source terminal, the second FET having a source terminal, and the source terminals of the first and second FETs are coupled together and coupled to the third terminal of the third current mirror.

19. The IC of claim 15, wherein The second current mirror has a current mirror ratio of 1:n between the first terminal and the third terminal of the second current mirror; The third current mirror has a third terminal, and a current mirror ratio of 1:m is provided between the first terminal and the third terminal of the third current mirror; and Where m is different from n.

20. The IC of claim 12, wherein the first transistor has a control terminal and the comparator has an output, and the IC includes a controller having a first terminal coupled to the control terminal, the controller also having a second terminal coupled to the output of the comparator.

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