Band-gap reference circuit for low power consumption

Abstract

The invention discloses a band-gap reference circuit for low power consumption, and relates to the technical field of integrated circuits. Comprising an oscillator module, a double-phase non-overlapping clock module and a voltage multiplication module which are connected in sequence, the band gap voltage generation module is connected with the switched capacitor network module; the oscillator module generates a first clock signal and outputs the first clock signal to the double-phase non-overlapping clock module to obtain a first conversion signal and a second conversion signal; the first conversion signal and the second conversion signal enter the voltage multiplication module to obtain a first amplification voltage and a second amplification voltage and control switches in the band gap voltage generation module and the switched capacitor network module; the band gap voltage generation module generates a first CTAT voltage and a second CTAT voltage according to the switch and outputs the first CTAT voltage and the second CTAT voltage to the switched capacitor network module to obtain a target band gap voltage. No resistor is used in the circuit, so that the whole circuit is small in chip area and low in power consumption, no curvature compensation circuit is added, and the chip area and the power consumption of the circuit are further reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a bandgap reference circuit for low power consumption. Background Art

[0002] An ultra-low power consumption bandgap reference can provide a stable voltage reference circuit under very low power consumption conditions, which is crucial in many application scenarios, especially in scenarios with strict power consumption limitations, such as wearable devices, Internet of Things, and implantable biomedical devices. In the existing technology, mostly the negative temperature coefficient voltage (V EB ) between the base and emitter of a bipolar transistor and the positive temperature coefficient voltage (ΔV EB ) generated by two bipolar transistors operating at different current densities are added together to obtain a reference independent of temperature.

[0003] In the existing technology, mostly a combination of resistors and transistors is used to generate a reference voltage independent of temperature, so it is difficult to achieve a small area. At the same time, in the existing technology, in order to obtain a reference with a low temperature coefficient, a curvature compensation circuit is often added in the circuit design, thus further increasing the chip area and power consumption.

[0004] CN110347203B discloses a broadband low-power consumption bandgap reference circuit, including a bandgap core circuit, a feedback circuit, and a start-up circuit; the bandgap core circuit includes a current mirror; the input end of the current mirror is connected to the VDD end, the first current branch of the current mirror is connected to the first end of the first resistor through the first triode, the second current branch is connected to the first end of the second resistor through the second triode, and the connection point of the second end of the first resistor and the second end of the second resistor is grounded through the third resistor; the feedback circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a third triode, and a first capacitor; the start-up circuit includes a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and a fourth triode; this solution can effectively reduce the power consumption and layout area by adopting a bandgap core structure without an operational amplifier. However, there are still resistors, and the chip area is still too large. Summary of the Invention

[0005] The object of the present invention is to solve the above problems and propose a bandgap reference circuit for low power consumption.

[0006] In the embodiment of the present invention, a bandgap reference circuit for low power consumption is proposed. The circuit includes an oscillator module, a two-phase non-overlapping clock module, a voltage multiplier module, a bandgap voltage generation module, and a switched capacitor network module: The oscillator module, the two-phase non-overlapping clock module, and the voltage multiplier module are connected in sequence; The bandgap voltage generation module is connected to the switched capacitor network module; The oscillator module is used to generate a first clock signal and output the first clock signal to the non-overlapping clock module for clock signal conversion to obtain a first conversion signal and a second conversion signal; the first conversion signal and the second conversion signal are non-overlapping clock signals; The first conversion signal and the second conversion signal enter the voltage multiplier module to multiply the input voltage and output a first amplified voltage and a second amplified voltage; The voltage multiplier module controls the switches in the bandgap voltage generation module and the switched capacitor network module through the first amplified voltage and the second amplified voltage; The bandgap voltage generation module is used to generate a first CTAT voltage and a second CTAT voltage according to the switches; and output the first CTAT voltage and the second CTAT voltage to the switched capacitor network module to obtain a target bandgap voltage.

[0007] Optionally, the oscillator module includes transistor one, transistor two, transistor three, transistor four, transistor five, transistor six, transistor seven, transistor eight, transistor nine, transistor ten, transistor eleven, transistor twelve, a first power supply voltage, and a first capacitor: The source of transistor one is connected to the first power supply voltage, the drain of transistor one is connected to the source of transistor two, the drain of transistor two is connected to the drain of transistor three, the source of transistor three is connected to the drain of transistor four, and the source of transistor four is grounded; The source of transistor five is connected to the power supply voltage, the drain of transistor five is connected to the source of transistor six, the drain of transistor six is connected to the drain of transistor seven, the source of transistor seven is connected to the drain of transistor eight, and the source of transistor eight is grounded; The gates of transistor five, transistor six, transistor seven, and transistor eight are connected to the drains of transistor two and transistor three; The source of transistor nine is connected to the first power supply voltage, the drain of transistor nine is connected to the source of transistor ten, the drain of transistor ten is connected to the drain of transistor eleven, the source of transistor eleven is connected to the drain of transistor twelve, and the source of transistor twelve is grounded; The gates of transistor nine, transistor ten, transistor eleven, and transistor twelve are connected to the drains of transistor six and transistor seven; The gates of transistor one, transistor two, transistor three, and transistor four are connected to the drains of transistor ten and transistor eleven; The upper plate of the first capacitor is connected to the drains of transistor ten and transistor eleven, and the lower plate of the first capacitor is connected to the ground; The connection points of the upper plate of the first capacitor, the gates of transistor one, transistor two, transistor three, transistor four, and the drains of transistor ten and transistor eleven serve as the output terminals of the oscillator module for outputting the first clock signal.

[0008] Optionally, the two-phase non-overlapping clock module includes a first inverter, a second inverter, and a third inverter: The first inverter and the second inverter are connected in series; The input terminals of the first inverter and the third inverter are connected to the output terminal of the oscillator module, and the input terminals of the first inverter and the third inverter are used to receive the first clock signal; The output terminal of the first inverter is connected to the input terminal of the second inverter; The output terminal of the second inverter is used to output the first conversion signal, and the output terminal of the third inverter is used to output the second conversion signal.

[0009] Optionally, the voltage multiplier module includes a second capacitor, a third capacitor, transistor thirteen, transistor fourteen, and a second power supply voltage; The drains of transistor thirteen and transistor fourteen are connected to the second power supply voltage; The gate of transistor thirteen, the source of transistor fourteen, and the upper plate of the third capacitor are connected; The gate of transistor fourteen, the source of transistor thirteen, and the upper plate of the second capacitor are connected; The lower plate of the second capacitor is connected to the output terminal of the second inverter, and the lower plate of the third capacitor is connected to the output terminal of the third inverter.

[0010] Optionally, the bandgap voltage generation module includes a first V EB generation circuit and a second V EB generation circuit; The first V EB generation circuit and the second V EB generation circuit have the same structure; the first V EB generation circuit generates a first bandgap voltage; the second V EB generation circuit generates a second bandgap voltage; The first V EB generation circuit includes a first clock switch A, a second clock switch A, a first clock switch B, a second clock switch B, a fourth capacitor, transistor fifteen, a fifth capacitor, and a third power supply voltage; The upper plate of the fourth capacitor is respectively connected to one end of the first clock switch A and one end of the second clock switch B; the lower plate of the fourth capacitor is respectively connected to one end of the second clock switch A and one end of the first clock switch B; The other ends of the first clock switch A and the first clock switch B are respectively connected to the positive pole of the third power supply voltage; the negative pole of the third power supply voltage is grounded; After the base and the collector of the fifteenth transistor are connected, they are respectively connected to the other end of the second clock switch A and the lower plate of the fifth capacitor and then grounded; The source of the fifteenth transistor is respectively connected to the other end of the second clock switch B and the upper plate of the fifth capacitor.

[0011] Optionally, the second V EB The generation circuit includes a third clock switch A, a fourth clock switch A, a third clock switch B, a fourth clock switch B, a sixth capacitor, a sixteenth transistor, a seventh capacitor and a fourth power supply voltage; The upper plate of the sixth capacitor is respectively connected to one end of the third clock switch A and one end of the fourth clock switch B; the lower plate of the sixth capacitor is respectively connected to one end of the fourth clock switch A and one end of the third clock switch B; The other ends of the third clock switch A and the third clock switch B are respectively connected to the positive pole of the fourth power supply voltage; the negative pole of the fourth power supply voltage is grounded; After the base and the collector of the sixteenth transistor are connected, they are respectively connected to the other end of the fourth clock switch A and the lower plate of the seventh capacitor and then grounded; The source of the sixteenth transistor is respectively connected to the other end of the fourth clock switch B and the upper plate of the seventh capacitor.

[0012] Optionally, the first V EB The generation circuit is connected to the switched-capacitor network module through a fifth clock switch B; the second V EB The generation circuit is connected to the switched-capacitor network module through a sixth clock switch B.

[0013] Optionally, the switched-capacitor network module includes a fifth clock switch A, a sixth clock switch A, a seventh clock switch A, an eighth clock switch A, a ninth clock switch A, a tenth clock switch A, a seventh clock switch B, an eighth clock switch B, a ninth clock switch B, a tenth clock switch B, an eleventh clock switch B, a twelfth clock switch B, a thirteenth clock switch B, a fourteenth clock switch B, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor; The upper plate of the eighth capacitor, one end of the fifth clock switch A and one end of the seventh clock switch B are connected to each other; the lower plate of the eighth capacitor, the other end of the seventh clock switch B and the lower plate of the ninth capacitor are connected to each other and grounded; The other end of the fifth clock switch A, one end of the fifth clock switch B, the upper plate of the ninth capacitor, one end of the sixth clock switch A and one end of the eighth clock switch B are connected to each other; The other end of the eighth clock switch B, one end of the ninth clock switch B, one end of the seventh clock switch A, and the upper plate of the tenth capacitor are interconnected; the other end of the sixth clock switch A, the lower plate of the tenth capacitor, one end of the tenth clock switch B, and one end of the sixth clock switch B are interconnected; The other end of the ninth clock switch B, one end of the eleventh clock switch B, one end of the eighth clock switch A, and the upper plate of the eleventh capacitor are interconnected; the other end of the seventh clock switch A, the lower plate of the eleventh capacitor, the other end of the tenth clock switch B, and one end of the twelfth clock switch B are interconnected; The other end of the eleventh clock switch B, one end of the thirteenth clock switch B, one end of the ninth clock switch A, and the upper plate of the twelfth capacitor are interconnected; the other end of the eighth clock switch A, the lower plate of the twelfth capacitor, the other end of the twelfth clock switch B, and one end of the tenth clock switch B are interconnected; The other end of the thirteenth clock switch B, one end of the tenth clock switch A, and the upper plate of the thirteenth capacitor are interconnected; the other end of the ninth clock switch A, the other end of the fourteenth clock switch B, and the lower plate of the thirteenth capacitor are interconnected; The other end of the tenth clock switch A is connected to the upper plate of the fourteenth capacitor, and the lower plate of the fourteenth capacitor is grounded.

[0014] Advantages of the present invention: 1. A bandgap reference circuit for low power consumption provided by the present invention does not use resistors, making the overall circuit chip area small and the power consumption low; 2. A bandgap reference circuit for low power consumption provided by the present invention does not add a curvature compensation circuit, further reducing the circuit chip area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention will be further described below with reference to the accompanying drawings.

[0016] Figure 1 It is a block diagram of a bandgap reference circuit for low power consumption provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of a corresponding circuit of an oscillator module provided by an embodiment of the present invention; Figure 3 It is a schematic diagram of a corresponding circuit of a two-phase non-overlapping clock module provided by an embodiment of the present invention; Figure 4 It is a schematic diagram of a corresponding circuit of a voltage multiplier module provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of a total circuit for generating an amplified voltage provided by an embodiment of the present invention; Figure 6The schematic diagram of the corresponding circuit of the first V EB generation circuit in the bandgap voltage generation module provided by the embodiment of the present invention; Figure 7 The schematic diagram of the corresponding circuit of the second V EB generation circuit in the bandgap voltage generation module provided by the embodiment of the present invention; Figure 8 The schematic diagram of the corresponding circuit of the switched capacitor network module provided by the embodiment of the present invention; Figure 9 The schematic diagram of the overall circuit for generating the bandgap voltage provided by the embodiment of the present invention; In the figure: 1. Oscillator module, 2. Biphase non-overlapping clock module, 3. Voltage multiplier module, 4. Bandgap voltage generation module, 401. First V EB generation circuit, 402. Second V EB generation circuit, 5. Switched capacitor network module. Detailed implementation manners

[0017] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The term "and / or" in this article is only a description of the associated relationship of the associated objects, indicating that there can be three relationships. For example, A and B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the descriptions such as "first" and "second" in the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that those skilled in the art can implement it. When the combination of the technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of the technical solutions does not exist and is not within the protection scope required by the present invention.

[0018] All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the protection scope of the present invention.

[0019] The embodiment of the present invention provides a bandgap reference circuit for low power consumption. Refer to Figure 1 , Figure 1 The circuit diagram of a bandgap reference circuit for low power consumption provided by the embodiment of the present invention. The circuit includes an oscillator module 1, a biphase non-overlapping clock module 2, a voltage multiplier module 3, a bandgap voltage generation module 4, and a switched capacitor network module 5: The oscillator module 1, the dual-phase non-overlapping clock module 2, and the voltage multiplier module 3 are connected in sequence; The bandgap voltage generation module 4 and the switched-capacitor network module 5 are connected; The oscillator module 1 is used to generate a first clock signal and output the first clock signal to the dual-phase non-overlapping clock module 2 for clock signal conversion to obtain a first conversion signal and a second conversion signal; the first conversion signal and the second conversion signal are non-overlapping clock signals; The first conversion signal and the second conversion signal enter the voltage multiplier module 3 to multiply the input voltage and output a first amplified voltage and a second amplified voltage; The voltage multiplier module 3 controls the switches in the bandgap voltage generation module 4 and the switched-capacitor network module 5 through the first amplified voltage and the second amplified voltage; The bandgap voltage generation module 4 is used to generate a first CTAT voltage and a second CTAT voltage according to the switches; and output the first CTAT voltage and the second CTAT voltage to the switched-capacitor network module 5 to obtain a target bandgap voltage.

[0020] In one implementation, the oscillator module 1 is an oscillator used to generate a clock signal with a PTAT frequency (the first clock signal). After passing through the dual-phase non-overlapping clock module 2, the first conversion signal and the second conversion signal obtained by the dual-phase non-overlapping clock module 2 are non-overlapping clock signals, which can avoid the switches from conducting simultaneously. Then, the first conversion signal and the second conversion signal enter the voltage multiplier module 3. The voltage multiplier module 3 is used to double the amplitudes of the first conversion signal and the second conversion signal, so that the amplitude of the first amplified voltage 2 is twice that of the first conversion signal, and the amplitude of the second amplified voltage 2 is twice that of the second conversion signal.

[0021] In one implementation, refer to Figure 4 , at X1 is the first amplified voltage, which is used to control the switch of the clock switch A (the switch φ starting with 1), and at X2 is the second amplified voltage, which is used to control the switch of the clock switch B (the switch φ starting with 2).

[0022] In one embodiment, refer to Figure 2 , Figure 2 is a schematic diagram of a corresponding circuit of an oscillator module provided by an embodiment of the present invention, including transistor one M1, transistor two M2, transistor three M3, transistor four M4, transistor five M5, transistor six M6, transistor seven M7, transistor eight M8, transistor nine M9, transistor ten M10, transistor eleven M11, transistor twelve M12, the first power supply voltage VDD1, and the first capacitor C21: The source of transistor M1 is connected to the first power supply voltage VDD1, the drain of transistor M1 is connected to the source of transistor M2, the drain of transistor M2 is connected to the drain of transistor M3, the source of transistor M3 is connected to the drain of transistor M4, and the source of transistor M4 is grounded; The source of transistor M5 is connected to the power supply voltage, the drain of transistor M5 is connected to the source of transistor M6, the drain of transistor M6 is connected to the drain of transistor M7, the source of transistor M7 is connected to the drain of transistor M8, and the source of transistor M8 is grounded; The gates of transistors M5, M6, M7, and M8 are connected to the drains of transistors M2 and M3; The source of transistor M9 is connected to the first power supply voltage VDD1, the drain of transistor M9 is connected to the source of transistor M10, the drain of transistor M10 is connected to the drain of transistor M11, the source of transistor M11 is connected to the drain of transistor M12, and the source of transistor M12 is grounded; The gates of transistors M9, M10, M11, and M12 are connected to the drains of transistors M6 and M7; The gates of transistors M1, M2, M3, and M4 are connected to the drains of transistors M10 and M11; The upper plate of the first capacitor C21 is connected to the drains of transistors M10 and M11, and the lower plate of the first capacitor C21 is connected to ground; The connection point A1 between the upper plate of the first capacitor C21, the gates of transistors M1, M2, M3, M4, and the drains of transistors M10 and M11 serves as the output terminal of the oscillator module 1 for outputting the first clock signal.

[0023] In one implementation, the circuit adopts a symmetric connection of M1 - M4 and M5 - M8, M9 - M12, which helps to improve the stability and anti-interference ability of the circuit and reduce the influence of process deviation at the same time.

[0024] In one implementation, refer to Figure 2 point A1 in. The output at point A1 is the first clock signal, which is provided to the inputs of the first inverter INV1 and the third inverter INV3 in the non-overlapping clock module.

[0025] In one implementation, by connecting the gates of M5 - M8 and M9 - M12 to the drains of M2 - M3 and M6 - M7, a negative feedback is formed, which helps to stabilize the operating point and reduce the influence of temperature or power supply fluctuations; the capacitor C21 is used to couple signals, filter out the DC components, ensure the purity of the output signal, and at the same time, as part of the output node, help to stabilize the oscillation frequency.

[0026] In one implementation, through the cascading of multi - stage transistors M1 - M4, M5 - M8, and M9 - M12, multi - stage amplification of signals is achieved, enhancing the gain and driving ability, ensuring the strength of the output signal. The output terminal A1 is connected to the ground through the capacitor C21 to filter out high - frequency noise and improve the stability of the output signal.

[0027] In one embodiment, refer to Figure 3 , Figure 3 The schematic diagram of a corresponding circuit of a two - phase non - overlapping clock module provided by an embodiment of the present invention includes a first inverter INV1, a second inverter INV2, and a third inverter INV3: The first inverter INV1 and the second inverter INV2 are connected in series; The input terminals of the first inverter INV1 and the third inverter INV3 are connected to the output terminal of the oscillator module 1. The input terminals of the first inverter INV1 and the third inverter INV3 are used to receive the first clock signal; The output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2; The output terminal of the second inverter INV2 is used to output the first conversion signal, and the output terminal of the third inverter INV3 is used to output the second conversion signal.

[0028] In one implementation, refer to Figure 3 , receive the first clock signal through point A1, send the first conversion signal to the lower plate of the second capacitor C1 through point A2, and send the second conversion signal to the lower plate of the third capacitor C22 through point A3.

[0029] In one implementation, by connecting the first inverter INV1 and the second inverter INV2 in series, the first conversion signal is generated; at the same time, the second conversion signal is directly generated by the third inverter INV3, which can achieve the phase separation of two signals and meet the requirements of different circuits for signal phases.

[0030] In one embodiment, refer to Figure 4 , Figure 4 The schematic diagram of a corresponding circuit of a voltage multiplication module provided by an embodiment of the present invention includes a second capacitor C1, a third capacitor C22, a transistor thirteen M13, a transistor fourteen M14, and a second power supply voltage VDD2; The drains of transistor thirteen M13 and transistor fourteen M14 are connected to the second power supply voltage VDD2; The gate of transistor thirteen M13, the source of transistor fourteen M14, and the upper plate of the third capacitor C22 are connected; The gate of transistor fourteen M14, the source of transistor thirteen M13, and the upper plate of the second capacitor C1 are connected; The lower plate of the second capacitor C1 is connected to the output terminal of the second inverter INV2, and the lower plate of the third capacitor C22 is connected to the output terminal of the third inverter INV3.

[0031] In one implementation, see Figure 4 , the lower plate of the second capacitor C1 receives the first conversion signal through point A2, and the lower plate of the third capacitor C22 receives the second conversion signal through point A3.

[0032] In one implementation, the second amplified voltage is output at the connection of the gate of transistor thirteen M13, the source of transistor fourteen M14, and the upper plate of the third capacitor C22; the first amplified voltage is output at the connection of the gate of transistor fourteen M14, the source of transistor thirteen M13, and the upper plate of the second capacitor C1.

[0033] In one implementation, by connecting the second capacitor C1 and the third capacitor C22 to the output terminals of two inverters respectively, the phase relationship of the two signals can be ensured to meet the application scenarios with high requirements for signal synchronization.

[0034] In one implementation, see Figure 5 , it consists of a ring oscillator, a low-power single / double-phase clock converter, and a clock multiplier circuit. This design is powered by a low power supply voltage to generate a low-frequency PTAT clock signal to bias the core BGR to reduce the stability error problem and the error caused by leakage. The proposed ring oscillator architecture utilizes the CTAT resistance of MOSFETs biased in the subthreshold region to generate the PTAT frequency; the oscillation frequency can be expressed as where N is the number of stages, and △t is the propagation delay of the inverter, which is equal to the RC delay provided by the inverter.

[0035] In one implementation, see Figure 5 , Figure 5Schematic diagram of the overall circuit for generating amplified voltage provided by an embodiment of the present invention. The oscillator module 1 generates a first clock signal with a PTAT frequency clock signal, which is transmitted through node A1 to the input terminals of the first inverter INV1 and the third inverter INV3 in the two-phase non-overlapping clock module 2. The first clock signal passes through the first inverter INV1 and the second inverter INV2 successively to obtain a first conversion signal; the first clock signal also passes through the third inverter INV3 to obtain a second conversion signal; the first conversion signal reaches the lower plate of the second capacitor C1 through point A2, and the second conversion signal reaches the lower plate of the third capacitor C22 through point A3. Finally, the first conversion signal and the second conversion signal pass through the voltage multiplication module to obtain a first amplified voltage and a second amplified voltage; the first amplified voltage is output at node X1, and the second amplified voltage is output at node X2; the first amplified voltage and the second amplified voltage are used to control the switches of clock switch A and clock switch B in the bandgap voltage generation module and the switched capacitor network module.

[0036] In one embodiment, refer to Figure 6 , Figure 6 Schematic diagram of the corresponding circuit of the first V EB generation circuit in the bandgap voltage generation module provided by an embodiment of the present invention The bandgap voltage generation module 4 includes a first V EB generation circuit 401 and a second V EB generation circuit 402; The first V EB generation circuit 401 and the second V EB generation circuit 402 have the same structure; the first V EB generation circuit 401 generates a first bandgap voltage; the second V EB generation circuit 402 generates a second bandgap voltage; The first V EB generation circuit 401 includes a first clock switch A φ11, a second clock switch A φ12, a first clock switch B φ21, a second clock switch B φ22, a fourth capacitor Cf1, a transistor fifteen Q1, a fifth capacitor CL1, and a third power supply voltage VDD3; The upper plate of the fourth capacitor Cf1 is respectively connected to one end of the first clock switch A φ11 and one end of the second clock switch B φ22; the lower plate of the fourth capacitor Cf1 is respectively connected to one end of the second clock switch A φ12 and one end of the first clock switch B φ21; The other ends of the first clock switch A φ11 and the first clock switch B φ21 are respectively connected to the positive pole of the third power supply voltage VDD3; the negative pole of the third power supply voltage VDD3 is grounded; After the base and collector of transistor fifteen Q1 are connected, they are respectively connected to the other end of the second clock switch Aφ12 and the lower plate of the fifth capacitor CL1, and then grounded; The source of transistor fifteen Q1 is respectively connected to the other end of the second clock switch Bφ22 and the upper plate of the fifth capacitor CL1.

[0037] In one implementation, the source of transistor fifteen Q1 is respectively connected to the other end of the second clock switch Bφ22 and the upper plate of the fifth capacitor CL1 to output the first bandgap voltage.

[0038] In one embodiment, refer to Figure 7 , Figure 7 This is a schematic diagram of the corresponding circuit of the second V EB generation circuit in the bandgap voltage generation module provided by the embodiment of the present invention; the second V EB generation circuit 402 includes a third clock switch Aφ13, a fourth clock switch Aφ14, a third clock switch Bφ23, a fourth clock switch Bφ24, a sixth capacitor Cf2, a transistor sixteen Q2, a seventh capacitor CL2, and a fourth power supply voltage VDD4; The upper plate of the sixth capacitor Cf2 is respectively connected to one end of the third clock switch Aφ13 and one end of the fourth clock switch Bφ24; the lower plate of the sixth capacitor Cf2 is respectively connected to one end of the fourth clock switch Aφ14 and one end of the third clock switch Bφ23; The other ends of the third clock switch Aφ13 and the third clock switch Bφ23 are respectively connected to the positive pole of the fourth power supply voltage VDD4; the negative pole of the fourth power supply voltage VDD4 is grounded; After the base and collector of transistor sixteen Q2 are connected, they are respectively connected to the other end of the fourth clock switch Aφ14 and the lower plate of the seventh capacitor CL2, and then grounded; The source of transistor sixteen Q2 is respectively connected to the other end of the fourth clock switch Bφ24 and the upper plate of the seventh capacitor CL2.

[0039] In one implementation, the second bandgap voltage is output at the connection between the source of transistor sixteen Q2 and the other end of the fourth clock switch Bφ24 and the upper plate of the seventh capacitor CL2.

[0040] In one embodiment, the first V EB generation circuit 401 is connected to the switched-capacitor network module through the fifth clock switch Bφ25; the second V EB generation circuit 402 is connected to the switched-capacitor network module through the sixth clock switch Bφ26.

[0041] In one embodiment, refer to Figure 8 , Figure 8Schematic diagram of a circuit corresponding to a switched capacitor network module provided by an embodiment of the present invention; The switched capacitor network module includes a fifth clock switch Aφ15, a sixth clock switch Aφ16, a seventh clock switch Aφ17, an eighth clock switch Aφ18, a ninth clock switch Aφ19, a tenth clock switch Aφ110, a seventh clock switch Bφ27, an eighth clock switch Bφ28, a ninth clock switch Bφ29, a tenth clock switch Bφ210, an eleventh clock switch Bφ211, a twelfth clock switch Bφ212, a thirteenth clock switch Bφ213, a fourteenth clock switch Bφ214, an eighth capacitor Ca1, a ninth capacitor Ca2, a tenth capacitor C3, an eleventh capacitor C4, a twelfth capacitor C5, a thirteenth capacitor C6, and a fourteenth capacitor Cref; The upper plate of the eighth capacitor Ca1, one end of the fifth clock switch Aφ15, and one end of the seventh clock switch Bφ27 are connected to each other; the lower plate of the eighth capacitor Ca1, the other end of the seventh clock switch Bφ27, and the lower plate of the ninth capacitor Ca2 are connected to each other and grounded; The other end of the fifth clock switch Aφ15, one end of the fifth clock switch Bφ25, the upper plate of the ninth capacitor Ca2, one end of the sixth clock switch Aφ16, and one end of the eighth clock switch Bφ28 are connected to each other; The other end of the eighth clock switch Bφ28, one end of the ninth clock switch Bφ29, one end of the seventh clock switch Aφ17, and the upper plate of the tenth capacitor C3 are connected to each other; the other end of the sixth clock switch Aφ16, the lower plate of the tenth capacitor C3, one end of the tenth clock switch Bφ210, and one end of the sixth clock switch Bφ26 are connected to each other; The other end of the ninth clock switch Bφ29, one end of the eleventh clock switch Bφ211, one end of the eighth clock switch Aφ18, and the upper plate of the eleventh capacitor C4 are connected to each other; the other end of the seventh clock switch Aφ17, the lower plate of the eleventh capacitor C4, the other end of the tenth clock switch Bφ210, and one end of the twelfth clock switch Bφ212 are connected to each other; The other end of the eleventh clock switch Bφ211, one end of the thirteenth clock switch Bφ213, one end of the ninth clock switch Aφ19, and the upper plate of the twelfth capacitor C5 are connected to each other; the other end of the eighth clock switch Aφ18, the lower plate of the twelfth capacitor C5, the other end of the twelfth clock switch Bφ212, and one end of the tenth clock switch Bφ210 are connected to each other; The other end of the thirteenth clock switch Bφ213, one end of the tenth clock switch Aφ110, and the upper plate of the thirteenth capacitor C6 are connected to each other; the other end of the ninth clock switch Aφ19, the other end of the fourteenth clock switch Bφ214, and the lower plate of the thirteenth capacitor C6 are connected to each other; The other end of the tenth clock switch Aφ110 is connected to the upper plate of the fourteenth capacitor Cref, and the lower plate of the fourteenth capacitor Cref is grounded.

[0042] In one implementation, the switched-capacitor circuit uses capacitors and switches to implement signal processing functions, which can save chip area compared with the traditional resistor-capacitor (RC) network.

[0043] In one embodiment, refer to Figure 9 , Figure 9 which is the schematic diagram of the overall circuit for generating the bandgap voltage provided by the embodiment of the present invention. Among them, the first amplified voltage and the second amplified voltage of the PTAT clock signal are used to drive the clock switch A and the clock switch B in the first V EB generation circuit and the second V EB generation circuit, so that the first V EB generation circuit generates a CTAT voltage V EB1 (the first bandgap voltage) on the fifth capacitor CL1 and generates a CTAT voltage V EB2 (the second bandgap voltage) on the seventh capacitor CL2. Similarly, the PTAT clock signal is also used to control the clock switch A and the clock switch B in the switched-capacitor network module, and the switched-capacitor network module is controlled to generate a CTAT coefficient α for the bandgap voltage V EB and scale the PTAT voltage .

[0044] In one implementation, during the connection stage of the clock switch B, the switched-capacitor network module is controlled to sample V EB1 and V EB2 , and store the difference on the capacitors C3 - C6; during the connection stage of the clock switch A, the voltage at node A is α times V EB1 , where α is determined by the ratio of the eighth capacitor Ca1 to the ninth capacitor Ca2, that is, α = Ca1 / (Ca1 + Ca2).

[0045] In one implementation, in the entire low-power bandgap reference circuit, all capacitors are MIM capacitors; all transistor models are the same; all clock switch A and clock switch B models are the same, and they are all MOS transistors. The gates of all clock switch A MOS transistors are connected to X1 in the voltage multiplier module 3 and are controlled by the first amplified voltage. When the first amplified voltage is 0, all clock switch A MOS transistors are in the off state, and when the first amplified voltage is 2, all clock switch A MOS transistors are in the connected state. The gates of all clock switch B MOS transistors are connected to X2 in the voltage multiplier module 3 and are controlled by the second amplified voltage. When the second amplified voltage is 0, all clock switch B MOS transistors are in the off state, and when the second amplified voltage is 2, all clock switch B MOS transistors are in the connected state.

[0046] In one implementation, the voltage difference V stored in C3 - C6 EB1 -V EB2 is added to the voltage at node B to form a temperature - independent reference voltage, which is stored across the reference capacitor, the fourteenth capacitor Cref, as shown in the formula:

[0047] ; when the first CTAT voltage and the second CTAT voltage enter the switched - capacitor network module 5, a first PTAT voltage ( ) is generated. The first PTAT voltage and the first CTAT voltage after being affected are added together across the fourteenth capacitor Cref to obtain the target bandgap voltage.

[0048] In one implementation, a slow PTAT clock signal is used to drive the bandgap reference core circuit, thereby reducing power consumption. The proposed design uses MOS capacitors, reducing the circuit area. The capacitance value is selected such that VREF is temperature - independent. The switches in the switched - capacitor network module are designed with a minimum width to reduce leakage current, which also helps to reduce power consumption.

[0049] The above has described a detailed embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered as limiting the scope of implementation of the present invention. All equivalent changes and improvements made according to the scope of the present invention application should still fall within the patent coverage scope of the present invention.

Claims

1. A bandgap reference circuit for low power consumption, characterized in that: The circuit comprises an oscillator module (1), a two-phase non-overlapping clock module (2), a voltage multiplication module (3), a bandgap voltage generation module (4), and a switched capacitor network module (5): The oscillator module (1), the two-phase non-overlapping clock module (2) and the voltage multiplication module (3) are connected in sequence; The bandgap voltage generating module (4) is connected to the switched capacitor network module (5); The oscillator module (1) is used to generate a first clock signal, and output the first clock signal to the two-phase non-overlapping clock module (2) for clock signal conversion to obtain a first conversion signal and a second conversion signal; the first conversion signal and the second conversion signal are non-overlapping clock signals; The first conversion signal and the second conversion signal enter the voltage multiplication module (3) to multiply the input voltage and output a first amplified voltage and a second amplified voltage; The voltage multiplication module (3) controls switches in the bandgap voltage generation module (4) and the switch capacitor network module (5) through the first amplified voltage and the second amplified voltage; The bandgap voltage generating module (4) is used to generate a first CTAT voltage and a second CTAT voltage according to the switch; and output the first CTAT voltage and the second CTAT voltage to the switch capacitor network module (5) to obtain a target bandgap voltage.

2. A bandgap reference circuit for low power consumption according to claim 1, characterized in that: The oscillator module (1) comprises a transistor 1 (M1), a transistor 2 (M2), a transistor 3 (M3), a transistor 4 (M4), a transistor 5 (M5), a transistor 6 (M6), a transistor 7 (M7), a transistor 8 (M8), a transistor 9 (M9), a transistor 10 (M10), a transistor 11 (M11), a transistor 12 (M12), a first power supply voltage (VDD1) and a first capacitor (C21): The source of transistor 1 (M1) is connected to the first power supply voltage (VDD1), the drain of transistor 1 (M1) is connected to the source of transistor 2 (M2), the drain of transistor 2 (M2) is connected to the drain of transistor 3 (M3), the source of transistor 3 (M3) is connected to the drain of transistor 4 (M4), and the source of transistor 4 (M4) is grounded; The source of transistor five (M5) is connected to the power supply voltage, the drain of transistor five (M5) is connected to the source of transistor six (M6), the drain of transistor six (M6) is connected to the drain of transistor seven (M7), the source of transistor seven (M7) is connected to the drain of transistor eight (M8), and the source of transistor eight (M8) is grounded; The gates of transistor five (M5), transistor six (M6), transistor seven (M7) and transistor eight (M8) are connected to the drains of transistor two (M2) and transistor three (M3); The source of transistor nine (M9) is connected to the first power supply voltage (VDD1), the drain of transistor nine (M9) is connected to the source of transistor ten (M10), the drain of transistor ten (M10) is connected to the drain of transistor eleven (M11), the source of transistor eleven (M11) is connected to the drain of transistor twelve (M12), and the source of transistor twelve (M12) is grounded; The gates of transistor nine (M9), transistor ten (M10), transistor eleven (M11), and transistor twelve (M12) are connected to the drains of transistor six (M6) and transistor seven (M7); The gates of transistor one (M1), transistor two (M2), transistor three (M3), and transistor four (M4) are connected to the drains of transistor ten (M10) and transistor eleven (M11); The upper plate of the first capacitor (C21) is connected to the drain of the transistor ten (M10) and the transistor eleven (M11), and the lower plate of the first capacitor (C21) is connected to the ground; The connection point (A1) of the upper plate of the first capacitor (C21), the gates of transistors one (M1), two (M2), three (M3), and four (M4) and the drains of transistors ten (M10) and eleven (M11) serves as the output end of the oscillator module (1) for outputting the first clock signal.

3. A bandgap reference circuit for low power consumption according to claim 2, characterized in that: The two-phase non-overlapping clock module includes a first inverter (INV1), a second inverter (INV2) and a third inverter (INV3): The first inverter (INV1) and the second inverter (INV2) are connected in series; The input ends of the first inverter (INV1) and the third inverter (INV3) are connected to the output end of the oscillator module (1), and the input ends of the first inverter (INV1) and the third inverter (INV3) are used to receive the first clock signal; The output end of the first inverter (INV1) is connected to the input end of the second inverter (INV2); The output end of the second inverter (INV2) is used to output the first conversion signal, and the output end of the third inverter (INV3) is used to output the second conversion signal.

4. A bandgap reference circuit for low power consumption according to claim 3, characterized in that: The voltage multiplication module (3) comprises a second capacitor (C1), a third capacitor (C22), a transistor thirteen (M13), a transistor fourteen (M14), and a second power supply voltage (VDD2); The drains of transistor thirteen (M13) and transistor fourteen (M14) are connected to the second power supply voltage (VDD2); The gate of transistor thirteen (M13), the source of transistor fourteen (M14) and the upper plate of the third capacitor (C22) are connected; The gate of transistor fourteen (M14), the source of transistor thirteen (M13) and the upper plate of the second capacitor (C1) are connected; The lower plate of the second capacitor (C1) is connected to the output end of the second inverter (INV2), and the lower plate of the third capacitor (C22) is connected to the output end of the third inverter (INV3).

5. A bandgap reference circuit for low power consumption according to claim 4, characterized in that: The bandgap voltage generating module (4) comprises a first V EB Generating circuit (401) and second V EB Generating circuit (402); The first V EB generating circuit (401) and the second V EB The generating circuit (402) has the same structure; the first V EB The generating circuit (401) generates a first bandgap voltage; the second V EB The generating circuit (402) generates a second bandgap voltage; The first V EB The generating circuit (401) includes a first clock switch A (φ11), a second clock switch A (φ12), a first clock switch B (φ21), a second clock switch B (φ22), a fourth capacitor (Cf1), a transistor fifteen (Q1), a fifth capacitor (CL1) and a third power supply voltage (VDD3); The upper plate of the fourth capacitor (Cf1) is respectively connected to one end of the first clock switch A (φ11) and one end of the second clock switch B (φ22); the lower plate of the fourth capacitor (Cf1) is respectively connected to one end of the second clock switch A (φ12) and one end of the first clock switch B (φ21); The other end of the first clock switch A (φ11) and the other end of the first clock switch B (φ21) are respectively connected to the positive electrode of the third power supply voltage (VDD3); the negative electrode of the third power supply voltage (VDD3) is grounded; After the base and collector of transistor 15 (Q1) are connected, they are respectively connected to the other end of the second clock switch A (φ12) and the lower plate of the fifth capacitor (CL1) and then grounded; The source of transistor fifteen (Q1) is connected to the other end of the second clock switch B (φ22) and the upper plate of the fifth capacitor (CL1) respectively.

6. A bandgap reference circuit for low power consumption according to claim 5, characterized in that: The second V EB The generating circuit (402) comprises a third clock switch A (φ13), a fourth clock switch A (φ14), a third clock switch B (φ23), a fourth clock switch B (φ24), a sixth capacitor (Cf2), a transistor sixteen (Q2), a seventh capacitor (CL2) and a fourth power supply voltage (VDD4); The upper plate of the sixth capacitor (Cf2) is respectively connected to one end of the third clock switch A (φ13) and one end of the fourth clock switch B (φ24); the lower plate of the sixth capacitor (Cf2) is respectively connected to one end of the fourth clock switch A (φ14) and one end of the third clock switch B (φ23); The other end of the third clock switch A (φ13) and the other end of the third clock switch B (φ23) are respectively connected to the positive electrode of the fourth power supply voltage (VDD4); the negative electrode of the fourth power supply voltage (VDD4) is grounded; After the base and collector of transistor 16 (Q2) are connected, they are respectively connected to the other end of the fourth clock switch A (φ14) and the lower plate of the seventh capacitor (CL2) and then grounded; The source of transistor sixteen (Q2) is connected to the other end of the fourth clock switch B (φ24) and the upper plate of the seventh capacitor (CL2) respectively.

7. A bandgap reference circuit for low power consumption according to claim 5, characterized in that: The first V EB The generating circuit (401) is connected to the switch capacitor network module via a fifth clock switch B (φ25); the second V EB The generating circuit (402) is connected to the switch capacitor network module via a sixth clock switch B (φ26).

8. A bandgap reference circuit for low power consumption according to claim 7, characterized in that: The switch capacitor network module includes a fifth clock switch A (φ15), a sixth clock switch A (φ16), a seventh clock switch A (φ17), an eighth clock switch A (φ18), a ninth clock switch A (φ19), a tenth clock switch A (φ110), a seventh clock switch B (φ27), an eighth clock switch B (φ28), a ninth clock switch B (φ29), a tenth clock switch B (φ210), an eleventh clock switch B (φ211), a twelfth clock switch B (φ212), a thirteenth clock switch B (φ213), a fourteenth clock switch B (φ214), an eighth capacitor (Ca1), a ninth capacitor (Ca2), a tenth capacitor (C3), an eleventh capacitor (C4), a twelfth capacitor (C5), a thirteenth capacitor (C6), and a fourteenth capacitor (Cref); The upper plate of the eighth capacitor (Ca1), one end of the fifth clock switch A (φ15) and one end of the seventh clock switch B (φ27) are connected to each other; the lower plate of the eighth capacitor (Ca1), the other end of the seventh clock switch B (φ27) and the lower plate of the ninth capacitor (Ca2) are connected to each other and grounded; The other end of the fifth clock switch A (φ15), one end of the fifth clock switch B (φ25), the upper plate of the ninth capacitor (Ca2), one end of the sixth clock switch A (φ16) and one end of the eighth clock switch B (φ28) are connected to each other; The other end of the eighth clock switch B (φ28), one end of the ninth clock switch B (φ29), one end of the seventh clock switch A (φ17) and the upper plate of the tenth capacitor (C3) are connected to each other; the other end of the sixth clock switch A (φ16), the lower plate of the tenth capacitor (C3), one end of the tenth clock switch B (φ210), and one end of the sixth clock switch B (φ26) are connected to each other; The other end of the ninth clock switch B (φ29), one end of the eleventh clock switch B (φ211), one end of the eighth clock switch A (φ18) and the upper plate of the eleventh capacitor (C4) are connected to each other; the other end of the seventh clock switch A (φ17), the lower plate of the eleventh capacitor (C4), the other end of the tenth clock switch B (φ210), and one end of the twelfth clock switch B (φ212) are connected to each other; The other end of the eleventh clock switch B (φ211), one end of the thirteenth clock switch B (φ213), one end of the ninth clock switch A (φ19) and the upper plate of the twelfth capacitor (C5) are connected to each other; the other end of the eighth clock switch A (φ18), the lower plate of the twelfth capacitor (C5), the other end of the twelfth clock switch B (φ212), and one end of the tenth clock switch B (φ210) are connected to each other; The other end of the thirteenth clock switch B (φ213), one end of the tenth clock switch A (φ110) and the upper plate of the thirteenth capacitor (C6) are connected to each other; the other end of the ninth clock switch A (φ19), the other end of the fourteenth clock switch B (φ214) and the lower plate of the thirteenth capacitor (C6) are connected to each other; The other end of the tenth clock switch A (φ110) is connected to the upper plate of the fourteenth capacitor (Cref), and the lower plate of the fourteenth capacitor (Cref) is grounded.

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