Voltage regulation method, electronic equipment and storage medium

Abstract

The invention provides a voltage regulation method, electronic equipment and a storage medium, and relates to the technical field of power consumption management. The problem that an existing electronic equipment storage system is high in power consumption is solved. The method comprises the following steps: acquiring a current working state of the storage system, and reducing voltage provided for the storage system in response to the current working state being a light-load working state.

Description

Technical Field

[0001] The present disclosure relates to the technical field of power consumption management, and particularly to a voltage regulation method, an electronic device, and a storage medium. Background Art

[0002] Currently, electronic devices have become an indispensable part of modern life. With the rapid development of mobile technologies, the industry has been paying increasing attention to the energy-saving performance of electronic devices. High energy consumption not only has an adverse impact on the environment, but also has an adverse impact on the user experience and usage cost. Summary of the Invention

[0003] Embodiments of the present disclosure provide a voltage regulation method, an electronic device, and a storage medium.

[0004] In a first aspect, a voltage regulation method is provided, which is applied to an electronic device including a storage system. The voltage regulation method includes: obtaining a current working state of the storage system, where the working state includes a light-load working state and a heavy-load working state, and in response to the current working state being the light-load working state, reducing the voltage provided to the storage system.

[0005] In the voltage regulation method provided by the present disclosure, the processor actively detects the working state of the storage system, and dynamically regulates the voltage provided to the storage system according to the working state of the storage system. For example, when the storage system is in a light-load working state, the power consumption of the storage system can be reduced by reducing the voltage provided to the storage system, thereby achieving the effect of dynamically reducing the overall power consumption of the electronic device.

[0006] In some embodiments, the electronic device further includes a power management chip. Reducing the voltage provided to the storage system includes: sending a first voltage adjustment instruction to the power management chip, and the power management chip, in response to the first voltage adjustment instruction, reduces the voltage provided to the storage system from the standard working voltage to the lower-limit working voltage.

[0007] In some embodiments, the storage system includes a storage controller and a memory. The voltage provided to the storage system includes a first power supply voltage provided to the storage controller and a second power supply voltage provided to the memory; reducing the voltage provided to the storage system from the standard working voltage to the lower-limit working voltage includes: the power management chip reduces the first power supply voltage provided to the storage controller from the standard working voltage of the first power supply voltage to the lower-limit working voltage of the first power supply voltage, and reduces the second power supply voltage provided to the memory from the standard working voltage of the second power supply voltage to the lower-limit working voltage of the second power supply voltage. Since the first power supply voltage and the second power supply voltage supply power to the storage controller and the memory of the storage system, reducing the first power supply voltage and the second power supply voltage can reduce the voltage provided to the storage system, thereby reducing the power consumption of the storage system.

[0008] In some embodiments, reducing the voltage supplied to the storage system from the standard operating voltage to the lower limit operating voltage further includes: the power management chip reducing the second power supply voltage supplied to the memory from the standard operating voltage of the second power supply voltage to zero, and reducing the first power supply voltage supplied to the storage controller from the standard operating voltage of the first power supply voltage to the lower limit operating voltage of the first power supply voltage. In some special operating states of the light load operating state, the second power supply voltage supplied to the memory can be cut off. Therefore, in the special operating state of the light load operating state, by reducing the first power supply voltage, the voltage supplied to the storage system can be reduced, thereby reducing the power consumption of the storage system.

[0009] In some embodiments, before obtaining the current operating state of the storage system, the method further includes: in response to not sending an operation instruction to the storage system for exceeding a preset time threshold, obtaining the current operating state of the storage system, where the operation instruction is used to instruct the storage system to enter a heavy load operating state.

[0010] In some embodiments, obtaining the current operating state of the storage system includes: sending a status information acquisition instruction to the storage system, and obtaining the status information fed back by the storage system, and determining the operating state of the storage system according to the status information.

[0011] In some embodiments, after reducing the voltage supplied to the storage system, the method further includes: in response to the operation instruction sent to the storage system and / or the status information fed back by the storage system being a heavy load state, sending a second voltage adjustment instruction to the power management chip, and the power management chip, in response to the second voltage adjustment instruction, adjusting the voltage supplied to the storage system from the lower limit operating voltage to the standard operating voltage.

[0012] In some embodiments, the light load operating state includes multiple sub-operating states, and the sub-operating states include: standby state, sleep state, idle state, sleep state, deep sleep state, where the lower limit operating voltages corresponding to different sub-operating states are different.

[0013] In a second aspect, an electronic device is provided, including: a storage system; and at least one processor, where the at least one processor is coupled to the storage system, and the at least one processor is configured to: obtain the current operating state of the storage system, where the operating state includes a light load operating state and a heavy load operating state, and in response to the current operating state being a light load operating state, reduce the voltage supplied to the storage system.

[0014] In some embodiments, the electronic device further includes a power management chip, and at least one processor is coupled to the power management chip. The at least one processor is configured to: send a first voltage adjustment instruction to the power management chip, and the power management chip is configured to: in response to the first voltage adjustment instruction, reduce the voltage provided to the storage system from the standard operating voltage to the lower limit operating voltage.

[0015] In some embodiments, the voltage provided to the storage system includes a first power supply voltage provided to the storage controller and a second power supply voltage provided to the memory. The power management chip is configured to: reduce the first power supply voltage provided to the storage controller from the standard operating voltage of the first power supply voltage to the lower limit operating voltage of the first power supply voltage, and reduce the second power supply voltage provided to the memory from the standard operating voltage of the second power supply voltage to the lower limit operating voltage of the second power supply voltage.

[0016] In some embodiments, the power management chip is further configured to: reduce the second power supply voltage provided to the memory from the standard operating voltage of the second power supply voltage to zero, and reduce the first power supply voltage provided to the storage controller from the standard operating voltage of the first power supply voltage to the lower limit operating voltage of the first power supply voltage.

[0017] In some embodiments, the at least one processor is further configured to: in response to not sending an operation instruction to the storage system for exceeding a preset time threshold, obtain the current working state of the storage system, where the operation instruction is used to instruct the storage system to enter a heavy load working state.

[0018] In some embodiments, the at least one processor is configured to: send a status information acquisition instruction to the storage system, acquire the status information fed back by the storage system, and determine the working state of the storage system according to the status information.

[0019] In some embodiments, the at least one processor is further configured to: in response to the operation instruction sent to the storage system and / or the status information fed back by the storage system being in a heavy load state, send a second voltage adjustment instruction to the power management chip, where the second voltage adjustment instruction is used to instruct the power management chip to adjust the voltage provided to the storage system from the lower limit operating voltage to the standard operating voltage.

[0020] In some embodiments, the light load working state includes multiple sub-working states, and the sub-working states include: standby state, sleep state, idle state, sleep state, deep sleep state, where the lower limit operating voltages corresponding to different sub-working states are different.

[0021] In a third aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, any one of the methods in the first aspect above can be implemented.

[0022] Understandably, for the technical effects of the second to third aspects, reference may be made to the technical effects of the first aspect and any of its embodiments, and they will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Block diagram of an electronic device provided by an embodiment of the present disclosure;

[0024] Figure 2 Block diagram of a storage system provided by an embodiment of the present disclosure;

[0025] Figure 3 Schematic flowchart of a voltage regulation method provided by an embodiment of the present disclosure;

[0026] Figure 4 Schematic flowchart of another voltage regulation method provided by an embodiment of the present disclosure;

[0027] Figure 5 Schematic flowchart of another voltage regulation method provided by an embodiment of the present disclosure;

[0028] Figure 6 Power supply schematic diagram of an electronic device provided by an embodiment of the present disclosure;

[0029] Figure 7 Schematic diagram of a voltage waveform regulation provided by an embodiment of the present disclosure;

[0030] Figure 8 Schematic diagram of another voltage waveform regulation provided by an embodiment of the present disclosure;

[0031] Figure 9 Schematic block diagram of a voltage regulation method provided by an embodiment of the present disclosure;

[0032] Figure 10 Schematic block diagram of another voltage regulation method provided by an embodiment of the present disclosure;

[0033] Figure 11 Schematic block diagram of another voltage regulation method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0035] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0036] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more.

[0037] When describing some embodiments, the expression "coupled" and its derivatives may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical contact or electrical contact. In this case, "coupled" may also be described as "connected". In addition, the term "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0038] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0039] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B. The use of "suitable for" or "configured to" herein means open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps. Additionally, the use of "based on" means open and inclusive because a process, step, calculation, or other action "based on" one or more conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0040] The use of "configured to" herein means open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps.

[0041] Embodiments of the present disclosure provide an electronic device, which may be any one of, for example, a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, and the like. Refer to Figure 1 , the electronic device 10 includes a processor 1001, a power management chip 1002 (power management ic, PMIC), and a storage system 110. The processor 1001 is coupled to the storage system 110, and the processor 1001 is coupled to the power management chip 1002.

[0042] In the above embodiment, the processor and the power management chip may be disposed on the same main board (physical space or physical carrier), and the storage system is disposed on another main board. It should be noted that there are various possibilities for the relative positional relationship among the processor, the power management chip, and the storage system. For example, the processor, the power management chip, and the storage system may also be all disposed on the same main board. The present disclosure does not specifically limit the relative positional relationship among the host, the processor, the power management chip, and the storage system.

[0043] Exemplarily, refer to Figure 2 , Figure 2 shows a schematic diagram of the storage system 110 provided by the embodiments of the present disclosure. The storage system 110 includes a storage controller 111 and a memory 112. The storage controller 111 is coupled to the memory 112 to control the memory 112 to store data. The memory 112 may be a two-dimensional (2-dimension, 2D) memory or a three-dimensional (3-dimension, 3D) memory.

[0044] The storage system 110 may be integrated into various types of storage devices. For example, it may be included in the same package (such as a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package). That is to say, the storage system 110 may be applied to and packaged into different types of mobile electronic products, such as a mobile phone (such as a cell phone), a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage.

[0045] In some embodiments, the storage system 110 includes a storage controller 111 and a memory 112, and the storage system 110 can be integrated into a memory card. The memory card includes any one of a personal computer memory card international association (PCMCIA) card (abbreviated as PC card), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multi media card (MMC), a secure digital memory card (SD) card, and a UFS.

[0046] Currently, electronic devices have become an indispensable part of modern life. To improve the battery life, it is necessary to reduce the power consumption of electronic devices. By reducing the power consumption of conventional systems such as the display system and the communication system, the overall power consumption of the electronic device can be reduced. The storage system has multiple operating states. In some operating states, the storage system needs to perform data processing operations, so a normal operating voltage needs to be maintained. In other operating states, the storage system does not need to perform data processing operations, so a high voltage is not required. However, these states do not regulate the power supply, resulting in a relatively high power consumption of the storage system in these states and a high overall power consumption of the electronic device. Therefore, when the storage system does not perform data processing operations, it is necessary to reduce the power consumption of the storage system, thereby reducing the overall power consumption of the electronic device.

[0047] To solve the above problems, embodiments of the present disclosure provide a solution: dynamically adjust the voltage supplied to the storage system according to the operating state of the storage system, so as to reduce the overall power consumption of the electronic device by reducing the power consumption of the storage system in the electronic device when the storage system is in a light load operating state.

[0048] The storage system in an electronic device can include multiple types. In the present disclosure, two types, namely EMMC and UFS, are used for illustration. EMMC and UFS are mainly used to store the operating system, application programs, media files, and other data of the electronic device.

[0049] The main features of EMMC are low power consumption, small size, and low cost, but the data transfer speed is relatively slow, and it is mainly used in low-end electronic devices. UFS is a more advanced storage technology that provides higher data transfer speeds and lower latency.

[0050] By optimizing the power management of the storage system, not only can a longer battery life be provided, but also the risk of overheating of the device during high-load use can be reduced. This is of great significance for meeting the daily needs of users, improving the usability of electronic devices, and providing a better user experience. Therefore, in the process of designing and manufacturing electronic devices, paying attention to the power consumption of the storage system is crucial, which can reflect obvious performance and efficiency advantages in actual use.

[0051] The multiple working states of the storage system can include two major categories: the heavy-load working state and the light-load working state. The heavy-load working state can include one of the following: the storage system is performing operations corresponding to read instructions, write instructions, and erase instructions issued by the processor respectively, and the storage system is performing garbage collection (GC) operations. The light-load working state indicates that the storage system is operating under a relatively low load and is not performing data read, write, and erase operations.

[0052] In some examples, the heavy-load working state is also called the active working state, and the light-load working state is also called the inactive working state; of course, the present disclosure only provides some examples of naming the two working states, and it should be understood that in other examples, it is not limited to these two, but the coverage range should be determined according to the definitions of the two working states.

[0053] The light-load working state includes multiple sub-working states. For example, the standby state, the sleep state, the idle state, the sleep state, and the deep sleep state. And the specific executable operations in each sub-working state are different, so the corresponding lower limit working voltage is different, that is, the power consumption reduced in each sub-working state is different. Each sub-working state in the light-load working state will be described below.

[0054] Exemplarily, taking the storage system as UFS for illustration, the light-load working state can include the following states:

[0055] Hibernate state: When there is no data being transmitted between the processor and the storage system, the working states of the data links of the processor and the storage system are both in the light-load working state, and this is the hibernate state at this time.

[0056] Idle state: When the UFS is idle, that is, there are neither commands sent from the processor nor background tasks to be processed by itself, the UFS is in the idle state.

[0057] Sleep state: Compared with the idle state, the power consumption in the sleep state needs to be further reduced, and the UFS turns off most of its peripherals and clocks.

[0058] Deep Sleep state: Compared with the Sleep state, the power consumption in the Deep Sleep state needs to be further reduced. In both the Sleep state and the Deep Sleep state, only the restart command and the sleep wake-up command are responded to. All other commands are ignored.

[0059] Exemplarily, taking the storage system as an EMMC for illustration, its light-load working states may include the StandBy state and the Sleep state.

[0060] Specifically, when the above-mentioned electronic device 10 is working, it executes the Figure 3 voltage regulation method shown, and this voltage regulation method includes steps S200 - S202.

[0061] The process by which the processor determines whether the storage system is in the light-load working state includes two judgment conditions. The first judgment condition is: determining whether the processor has not sent a working instruction to the storage system for a long time. The second judgment condition is: determining whether the processor has received the status information corresponding to the light-load working state feedback from the storage system.

[0062] Refer to Figure 3 , the voltage regulation method provided by the embodiments of the present disclosure includes:

[0063] S200: Determine whether an operation instruction has not been sent to the storage system for more than a preset time threshold.

[0064] When the processor issues an operation instruction to the storage system, the operation instruction may include a read instruction, a write instruction, an erase instruction, etc. The read instruction, the write instruction, and the erase instruction are used to instruct the storage system to perform corresponding data reading operations, data writing operations, and data erasing operations, etc., that is, the operation instruction is used to instruct the storage system to enter the heavy-load working state. When the processor does not issue an operation instruction to the storage system for more than the preset time, it means that the storage system will not perform operations such as data writing operations, data erasing operations, and data reading operations. After meeting the above conditions, the processor will actively obtain the current working state of the storage system to determine the current working state of the storage system.

[0065] S201: Obtain the current working state of the storage system.

[0066] To effectively optimize the power consumption of the storage system, the processor needs to obtain the current working state of the storage system and make corresponding voltage adjustment strategies according to the working state of the storage system. The working state of the storage system includes a light-load working state and a heavy-load working state. The light-load working state represents that the storage system operates under relatively low load. In the light-load working state, the resource utilization rate of the storage system is relatively low, and few or no data read / write and erase operations are performed. The heavy-load working state represents that the storage system operates under high load. In the heavy-load working state, the resource utilization rate of the storage system is high, and the storage system may face a large number of data access requests or application activities, so a large number of data read / write and erase operations will be performed.

[0067] Even if the processor does not send an operation instruction to the storage system for more than a preset time threshold, the storage system may still be executing the operation instruction sent by the processor before, but the processor does not know whether the storage system has completed the operation instruction issued by the processor. Therefore, the processor needs to actively interact with the storage system to further determine the current working state of the storage system.

[0068] Refer to Figure 4 , in a possible implementation, when obtaining the current working state of the storage system, it specifically includes:

[0069] S2011: Send a status information acquisition instruction to the storage system and obtain the status information fed back by the storage system.

[0070] The processor is communicatively connected to the storage system through a preset data channel. The processor first sends a status information acquisition instruction to the storage system. The purpose of this instruction is to obtain the register information representing the detailed current state of the storage system. The status information of the storage system is stored in the status register. Here, obtaining the status information of the storage system is actually achieved by obtaining the status information stored in the status register.

[0071] S2012: Determine the working state of the storage system according to the status information.

[0072] After receiving the information acquisition instruction, the controller of the storage system feeds back the corresponding status register information according to the actual current state of the storage system. After the processor obtains the status register information, it can determine the working state of the storage system by parsing the digital code information corresponding to the status register information.

[0073] Exemplarily, if the status information fed back by the storage system is the first information, the first status information is used to indicate that the working status of the storage system is an overload working status; if the status information fed back by the storage system is the second information, the working status of the storage system is a sleep status in the light load working status, and if the status information fed back by the storage system is the third information, the working status of the storage system is an idle status in the light load working status...

[0074] S202: In response to the current working status being the light load working status, reduce the voltage provided to the storage system.

[0075] In different working statuses, in order to meet the working requirements of the storage system, the voltages required for the storage system to work are different. Therefore, the voltages provided to the storage system can be different in different working statuses. For example, when the working status of the storage system is the light load working status, the load is low, and the required voltage is lower than the standard working voltage. Therefore, when the storage system is in the light load working status, reducing the voltage provided to the storage system will not affect the normal data processing operation of the storage system, but can reduce the power consumption of the storage system.

[0076] Exemplarily, when the storage system is in the overload working status, the required voltage is V1, and when the storage system is in the light load working status, the required voltage is V2, where V2 < V1. The solution provided by the present disclosure can reduce the voltage provided to the storage system when the storage system is in the light load working status. Under the condition of a certain current, the magnitude of the power consumption is proportional to the magnitude of the voltage. Therefore, the power consumption of the storage system in the light load working status can be less than that in the overload working status.

[0077] The voltage control of the storage system by the processor is implemented through a power management chip. Refer to Figure 5 , in a possible implementation manner, reducing the voltage provided to the storage system includes:

[0078] S2021: Send a first voltage adjustment instruction to the power management chip.

[0079] The processor issues the first voltage adjustment instruction to the power management chip through a preset communication link. The first voltage adjustment instruction is used to instruct the power management chip to reduce the voltage provided to the storage system from the standard working voltage to the lower limit working voltage.

[0080] S2022: In response to the first voltage adjustment instruction, the power management chip reduces the voltage provided to the storage system from the standard working voltage to the lower limit working voltage.

[0081] Exemplarily, the processor sends a first voltage adjustment instruction to the power management chip. After receiving the first voltage adjustment instruction, the power management chip reduces the voltage supplied to the storage system from the standard operating voltage V3 to the lower limit operating voltage V4. In the light load operating state, the performance requirements of the system are relatively low. Therefore, even if the input voltage drops from voltage V3 to voltage V4, it will not have an adverse impact on the normal operation of the storage system. Because in the light load operating state, the resource utilization rate of the system is relatively low, and there are no large amounts of computing tasks or data processing requirements. Therefore, through appropriate voltage reduction, the system can operate with higher energy efficiency while still meeting its operating requirements.

[0082] For different storage systems, due to differences in their power supply structures, the voltage supplied to them can be multiple paths, but at least includes a first power supply voltage for powering the storage controller and a second power supply voltage for powering the memory.

[0083] In one possible implementation manner, reducing the voltage supplied to the storage system from the standard operating voltage to the lower limit operating voltage specifically includes:

[0084] S20221: The power management chip reduces the first power supply voltage supplied to the storage controller from the standard operating voltage of the first power supply voltage to the lower limit operating voltage of the first power supply voltage, and reduces the second power supply voltage supplied to the memory from the standard operating voltage of the second power supply voltage to the lower limit operating voltage of the second power supply voltage.

[0085] The power supply of the storage system includes at least two-way power supply. One-way power supply is used to provide the required power for the storage controller, while the other-way power supply is used to provide power for the memory.

[0086] Exemplarily, refer to Figure 6 , taking the storage system as UFS for illustration, the voltage supplied to the storage system includes the first power supply voltage supplied to the storage controller and the second power supply voltage supplied to the memory. For example, the first power supply voltage can be VCCQ, and the second power supply voltage can be VCC.

[0087] It should be noted that in different sub-operating states of the light load operating state, the lower limit operating voltages corresponding to VCCQ and VCC are different.

[0088] Exemplarily, in the idle state, the lower limit operating voltages of VCCQ and VCC can be 1.19V and 2.48V respectively; in the sleep state, the lower limit operating voltages of VCCQ and VCC can be 1.17V and 2.45V respectively; in the sleep state, the lower limit operating voltages of VCCQ and VCC can be 1.15V and 2.43V respectively; in the deep sleep state, the lower limit operating voltages of VCCQ and VCC can be 1.14V and 2.40V respectively.

[0089] Refer to Figure 7 and Figure 8 , the voltage adjustment processes of VCCQ and VCC will be mainly described below.

[0090] Refer to Figure 7 , during the time period T1, when the operating state of the storage system is a heavy load operating state, the VCCQ and VCC provided by the power management chip to the storage system are both standard operating voltages. For example, VCCQ is 1.20V and VCC is 2.50V.

[0091] During the time period T2, when the operating state of the storage system is an idle state under a light load operating state, the VCCQ and VCC provided by the power management chip to the storage system are both the lower limit operating voltages of the idle state. For example, the lower limit operating voltage corresponding to VCCQ in the idle state is 1.19V, and the lower limit operating voltage corresponding to VCC in the sleep state is 2.48V.

[0092] During the time period T3, when the operating state of the storage system resumes to a heavy load operating state, the VCCQ and VCC provided by the power management chip to the storage system are both standard operating voltages. For example, VCCQ is 1.20V and VCC is 2.50V.

[0093] In some cases, some electronic devices can cut off the power supply to the memory in some light load operating states. For example, in the sleep state and the hibernation state, only the power supply to the storage controller is retained. That is, in this case, the lower limit operating voltage of the second power supply voltage can be 0. And if you want to further reduce the power consumption of the storage system in the light load operating state, you can also achieve it by reducing the power supply voltage provided to the storage controller.

[0094] In a possible implementation manner, reducing the voltage provided to the storage system from the standard operating voltage to the lower limit operating voltage further includes:

[0095] S20222: The power management chip reduces the second power supply voltage provided to the memory from the standard operating voltage of the second power supply voltage to zero, and reduces the first power supply voltage provided to the storage controller from the standard operating voltage of the first power supply voltage to the lower limit operating voltage of the first power supply voltage.

[0096] Exemplarily, continuing to take the storage system as UFS for illustration, refer to Figure 8, the voltages supplied to the UFS include two voltages, VCC and VCCQ. During the T1 time period, when the operating state of the storage system is a heavy-load operating state, the voltages supplied by VCCQ and VCC are both standard operating voltages, which are 1.20V and 2.50V respectively. During the T2 time period, when the operating state of the storage system is the deep sleep state in the light-load operating state, VCC is 0V, and VCCQ is the lower-limit operating voltage corresponding to the sleep state, that is, 1.14V.

[0097] When the storage system is in the light-load operating state, the power consumption of the storage system can be reduced by reducing the voltage supplied to the storage system. However, once the processor sends an operation instruction to the storage system, this low-power state is broken, or when the storage system needs to perform a garbage collection operation internally and the storage system feeds back the status register information representing the execution of the garbage collection operation to the processor, the storage system needs to change from the light-load operating state to the heavy-load operating state. Therefore, the voltage supplied to the storage system needs to be restored to the standard operating voltage.

[0098] In a possible implementation manner, after reducing the voltage supplied to the storage system, the method further includes:

[0099] In response to the operation instruction sent to the storage system and / or the status information fed back by the storage system being the heavy-load state, send a second voltage adjustment instruction to the power management chip, where the second voltage adjustment instruction is used to instruct the power management chip to adjust the voltage supplied to the storage system from the lower-limit operating voltage to the standard operating voltage.

[0100] Exemplarily, continuing to illustrate with the storage system being UFS, the voltages supplied to the UFS include two voltages, VCCQ and VCC. When the operating state of the storage system is the deep sleep state in the light-load operating state, the voltages supplied by VCCQ and VCC are both the lower-limit operating voltages corresponding to the deep sleep state, which can be 1.14V and 2.40V respectively. After the power management chip receives the second voltage adjustment instruction, it needs to adjust the voltage supplied to the storage system from the lower-limit operating voltage to the standard operating voltage, that is, increase the voltages supplied to VCCQ and VCC to 1.20V and 2.50V.

[0101] Based on the above adjustment process, by detecting whether there is a periodic change in the magnitude of the voltage supplied to the storage system, it can be determined whether the relevant solution adopts the voltage dynamic adjustment solution of the present disclosure.

[0102] Therefore, in practical applications, it is necessary to balance between energy conservation and performance. The storage system can switch between a low-power state and a high-performance state as needed to ensure a balance between energy efficiency and performance requirements under different workloads. Exemplarily, the lower working voltage provided to the storage system in a light-load working state can be 95% of the standard working voltage provided to the storage system in a heavy-load working state, thus bringing a 5% power consumption saving to the storage system.

[0103] The following will be combined with Figure 9 , to illustrate the voltage dynamic adjustment process of the present disclosure. The processor continuously judges the working state of the storage system. When the storage system is performing read / write and erase operations on data, the storage system is in a heavy-load working state, and the voltage provided to the storage system is the standard working voltage. When the processor judges that the storage system enters the light-load working state, the judgment process is as Figure 10 shown. When no operation instruction is sent to the storage system for more than a preset time and the working state characterized by the register information is the light-load working state, the voltage provided to the storage system is changed from the standard working voltage to the lower limit working voltage. At this time, the entire storage system is in the light-load working state. The judgment process for the storage system to exit the light-load working state is as Figure 11 shown. Once the processor sends an operation instruction to the storage system, or the processor monitors that the storage system needs to perform a garbage collection operation, the storage system needs to perform corresponding read / write and erase operations on data. Therefore, the storage system needs to exit the light-load working state, and the voltage provided to the storage system is changed from the lower limit working voltage to the standard working voltage.

[0104] For the voltage regulation method provided by the present disclosure, the processor actively detects the working state of the storage system and dynamically adjusts the voltage provided to the storage system according to the working state of the storage system. Therefore, when the storage system is in the light-load working state, the power consumption of the storage system can be reduced by reducing the voltage provided to the storage system, thereby achieving the effect of dynamically reducing the overall power consumption of the electronic device. And by detecting the change of the voltage provided to the storage system, it can be judged whether the power consumption of the storage system is reduced by dynamically adjusting the voltage provided to the storage system.

[0105] The embodiments of the present disclosure also provide an electronic device, which can be, for example, the electronic device 10 shown in Figure 1 , including a storage system 110 and at least one processor 1001. The at least one processor 1001 is coupled to the storage system 110, and the at least one processor 1001 is configured to: obtain the current working state of the storage system, where the working state includes a light-load working state and a heavy-load working state, and in response to the current working state being the light-load working state, reduce the voltage provided to the storage system.

[0106] In some embodiments, the electronic device 10 further includes a power management chip 1002. At least one processor 1001 is coupled to the power management chip 1002. The at least one processor 1001 is specifically configured to: send a first voltage adjustment instruction to the power management chip, where the first voltage adjustment instruction is used to instruct the power management chip to reduce the voltage provided to the storage system from the standard operating voltage to the lower limit operating voltage.

[0107] In some embodiments, the electronic device further includes a power management chip 1002. At least one processor 1001 is coupled to the power management chip 1002. The at least one processor 1001 is specifically configured to: send a first voltage adjustment instruction to the power management chip. The power management chip 1002 is configured to: in response to the first voltage adjustment instruction, reduce the voltage provided to the storage system from the standard operating voltage to the lower limit operating voltage.

[0108] In some embodiments, the voltage provided to the storage system includes a first power supply voltage provided to the storage controller and a second power supply voltage provided to the memory. The power management chip 1002 is configured to: reduce the first power supply voltage provided to the storage controller from the standard operating voltage of the first power supply voltage to the lower limit operating voltage of the first power supply voltage, and reduce the second power supply voltage provided to the memory from the standard operating voltage of the second power supply voltage to the lower limit operating voltage of the second power supply voltage.

[0109] In some embodiments, the power management chip 1002 is configured to: reduce the second power supply voltage provided to the memory from the standard operating voltage of the second power supply voltage to zero, and reduce the first power supply voltage provided to the storage controller from the standard operating voltage of the first power supply voltage to the lower limit operating voltage of the first power supply voltage.

[0110] In some embodiments, the at least one processor 1001 is further configured to: in response to not sending an operation instruction to the storage system for exceeding a preset time threshold, obtain the current working state of the storage system, where the operation instruction is used to instruct the storage system to enter a heavy load working state.

[0111] In some embodiments, the at least one processor 1001 is configured to: send a status information acquisition instruction to the storage system, obtain the status information fed back by the storage system, and determine the working state of the storage system according to the status information.

[0112] In some embodiments, the at least one processor 1001 is further configured to: in response to the operation instruction sent to the storage system and / or the status information fed back by the storage system being in a heavy load state, send a second voltage adjustment instruction to the power management chip, where the second voltage adjustment instruction is used to instruct the power management chip to adjust the voltage provided to the storage system from the lower limit operating voltage to the standard operating voltage.

[0113] In some embodiments, the light load operating state includes a plurality of sub - operating states, and the sub - operating states include: standby state, sleep state, idle state, sleep state, deep sleep state, wherein the lower limit operating voltages corresponding to different sub - operating states are different.

[0114] Those skilled in the art can clearly understand that for the convenience and conciseness of description, in the above - mentioned embodiments, the descriptions of each embodiment have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the corresponding processes in the foregoing method embodiments, and details will not be repeated here.

[0115] In several embodiments provided by the present disclosure, it should be understood that the provided programming method and memory can be implemented in other ways. For example, the division of a certain module is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0116] Those of ordinary skill in the art can realize that the modules and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present disclosure.

[0117] The above are only the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present disclosure should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A voltage regulation method, characterized in that, applied to an electronic device including a storage system, the voltage regulation method includes: obtaining the current working state of the storage system, wherein the working state includes a light load working state and a heavy load working state; responding to the current working state being the light load working state, reducing the voltage provided to the storage system.

2. The method according to claim 1, characterized in that, the electronic device further includes a power management chip, and the reducing the voltage provided to the storage system includes: sending a first voltage adjustment instruction to the power management chip; the power management chip responds to the first voltage adjustment instruction and reduces the voltage provided to the storage system from the standard working voltage to the lower limit working voltage.

3. The method according to claim 2, characterized in that, the storage system includes a storage controller and a memory, and the voltage provided to the storage system includes a first power supply voltage provided to the storage controller and a second power supply voltage provided to the memory; the reducing the voltage provided to the storage system from the standard working voltage to the lower limit working voltage includes: the power management chip reduces the first power supply voltage provided to the storage controller from the standard working voltage of the first power supply voltage to the lower limit working voltage of the first power supply voltage, and reduces the second power supply voltage provided to the memory from the standard working voltage of the second power supply voltage to the lower limit working voltage of the second power supply voltage.

4. The method according to claim 3, characterized in that, the reducing the voltage provided to the storage system from the standard working voltage to the lower limit working voltage further includes: the power management chip reduces the second power supply voltage provided to the memory from the standard working voltage of the second power supply voltage to zero, and reduces the first power supply voltage provided to the storage controller from the standard working voltage of the first power supply voltage to the lower limit working voltage of the first power supply voltage.

5. The method according to claim 1, characterized in that, before obtaining the current working state of the storage system, the method further includes: responding to not sending an operation instruction to the storage system for exceeding a preset time threshold, and obtaining the current working state of the storage system, wherein the operation instruction is used to instruct the storage system to enter the heavy load working state.

6. The method according to claim 1, characterized in that, the obtaining the current working state of the storage system includes: sending a status information obtaining instruction to the storage system and obtaining the status information fed back by the storage system; determining the working state of the storage system according to the status information.

7. The method according to claim 6, characterized in that, after reducing the voltage provided to the storage system, the method further includes: responding to the operation instruction sent to the storage system and / or the status information fed back by the storage system being the heavy load state, sending a second voltage adjustment instruction to the power management chip; In response to the second voltage adjustment instruction, the power management chip adjusts the voltage supplied to the storage system from the lower limit operating voltage to the standard operating voltage.

8. The method according to any one of claims 1-7, wherein, the light load operating state includes a plurality of sub-operating states, and the sub-operating states include: standby state, sleep state, idle state, sleep state, deep sleep state, wherein the lower limit operating voltages corresponding to different sub-operating states are different.

9. An electronic device, wherein, comprising: a storage system; and at least one processor, the at least one processor being coupled to the storage system, and the at least one processor being configured to: acquire the current operating state of the storage system, wherein the operating state includes a light load operating state and a heavy load operating state; and in response to the current operating state being the light load operating state, reduce the voltage supplied to the storage system.

10. The electronic device according to claim 9, wherein, the electronic device further includes a power management chip, the at least one processor being coupled to the power management chip, and the at least one processor being configured to: send a first voltage adjustment instruction to the power management chip; the power management chip being configured to: in response to the first voltage adjustment instruction, reduce the voltage supplied to the storage system from the standard operating voltage to the lower limit operating voltage.

11. The electronic device according to claim 10, wherein, the voltage supplied to the storage system includes a first power supply voltage supplied to a storage controller and a second power supply voltage supplied to a memory, and the power management chip is configured to: reduce the first power supply voltage supplied to the storage controller from the standard operating voltage of the first power supply voltage to the lower limit operating voltage of the first power supply voltage, and reduce the second power supply voltage supplied to the memory from the standard operating voltage of the second power supply voltage to the lower limit operating voltage of the second power supply voltage.

12. The electronic device according to claim 11, wherein, the power management chip is further configured to: reduce the second power supply voltage supplied to the memory from the standard operating voltage of the second power supply voltage to zero, and reduce the first power supply voltage supplied to the storage controller from the standard operating voltage of the first power supply voltage to the lower limit operating voltage of the first power supply voltage.

13. The electronic device according to claim 9, wherein, the at least one processor is further configured to: in response to not sending an operation instruction to the storage system for exceeding a preset time threshold, acquire the current operating state of the storage system, wherein the operation instruction is used to instruct the storage system to enter a heavy load operating state.

14. The electronic device according to claim 9, wherein, the at least one processor is configured to: send a status information acquisition instruction to the storage system and acquire the status information fed back by the storage system; determine the operating state of the storage system according to the status information.

15. The electronic device according to claim 14, Characterized in that, the at least one processor is further configured to: in response to the operation instruction sent to the storage system and / or the status information fed back by the storage system being the overload status, send a second voltage adjustment instruction to the power management chip; the power management chip is further configured to: in response to the second voltage adjustment instruction, adjust the voltage supplied to the storage system from the lower limit operating voltage to the standard operating voltage.

16. The electronic device according to any one of claims 9-15, characterized in that, the light load operating state includes a plurality of sub-operating states, and the sub-operating states include: standby state, sleep state, idle state, sleep state, deep sleep state, wherein the lower limit operating voltages corresponding to different sub-operating states are different.

17. A readable storage medium, characterized in that, the readable storage medium includes a stored program, wherein when the program runs, it controls the device where the readable storage medium is located to execute the method according to any one of claims 1 to 8.

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