Iterative error correction with adjustable parameters after threshold number of iterations

Abstract

The invention relates to iterative error correction with adjustable parameters after a threshold number of iterations. A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity equations on a corresponding subset of the sense word to determine a plurality of parity equation results. The processing device determines a syndrome of the sense word using the plurality of parity check equation results, determines whether the syndrome of the sense word satisfies a codeword criterion, and in response to the syndrome of the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after performing a threshold number of iterations.

Description

[0001] Divisional application information

[0002] This application is a divisional application of the patent application with the application date of March 2, 2021, the application number of 202110231132.5, and the invention title of "Iterative Error Correction Using Adjustable Parameters after a Threshold Number of Iterations". Technical Field

[0003] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly to iterative error correction using adjustable parameters after a threshold number of iterations in a memory subsystem. Background Art

[0004] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at and retrieve data from the memory devices. Summary of the Invention

[0005] One embodiment of the present disclosure provides a system including: a memory device; and a processing device operatively coupled to the memory device to perform operations including: reading a sensed word from the memory device; performing a plurality of parity check equations on a corresponding subset of the sensed word to determine a plurality of parity check equation results; using the plurality of parity check equation results to determine a syndrome of the sensed word; determining whether the syndrome of the sensed word satisfies a codeword criterion; and in response to the syndrome of the sensed word not satisfying the codeword criterion, performing an iterative low-density parity-check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after performing a threshold number of iterations.

[0006] Another embodiment of the present disclosure provides a method including: reading a sensed word; performing a plurality of parity check equations on a corresponding subset of the sensed word to determine a plurality of parity check equation results; using the plurality of parity check equation results to determine a syndrome of the sensed word; determining whether the syndrome of the sensed word satisfies a codeword criterion; and in response to the syndrome of the sensed word not satisfying the codeword criterion, performing an iterative low-density parity-check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after performing a threshold number of iterations.

[0007] Another embodiment of the present disclosure provides a non - transitory computer - readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform operations including: reading a sensed word from a memory device; performing a plurality of parity check equations on a corresponding subset of the sensed word to determine a plurality of parity check equation results; determining whether the plurality of parity check equation results indicate an error in the sensed word; and in response to the parity check equation results indicating an error in the sensed word: performing a first iteration of an error correction process; performing a threshold number of iterations of the error correction process, where the threshold number of iterations includes flipping any bit in the sensed word in which the number of unsatisfied parity check equation results is greater than or equal to the maximum number of unsatisfied parity check equation results for any bit in the sensed word from the previous iteration minus one; and performing one or more subsequent iterations of the error correction process after the threshold number of iterations, where the one or more subsequent iterations include flipping any bit in the sensed word in which the number of unsatisfied parity check equation results is equal to the maximum number of unsatisfied parity check equation results for any bit in the sensed word from the previous iteration. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure.

[0009] Figure 1 An example computing system including a memory subsystem is shown in accordance with some embodiments of the present disclosure.

[0010] Figure 2 is a flowchart of an example method of configuring iterative error correction parameters using criteria from a previous iteration in accordance with some embodiments of the present disclosure.

[0011] Figure 3 is a diagram showing a sensed - word correction sub - matrix for configuring iterative error correction parameters in accordance with some embodiments of the present disclosure.

[0012] Figure 4 is a flowchart of an example method of an iterative error correction process in which one or more parameters are configured using criteria from a previous iteration in accordance with some embodiments of the present disclosure.

[0013] Figure 5 is a diagram showing an updated sensed - word correction sub - matrix for configuring iterative error correction parameters after one or more iterations in accordance with some embodiments of the present disclosure.

[0014] Figure 6A flowchart of an example method of iterative error correction that utilizes adjustable parameters after a threshold number of iterations in accordance with some embodiments of the present disclosure.

[0015] Figure 7 A flowchart of an example method of an iterative error correction process that adjusts one or more parameters after a threshold number of iterations in accordance with some embodiments of the present disclosure.

[0016] Figure 8 A diagram showing an updated sense word correction submatrix for configuring iterative error correction parameters after one or more iterations in accordance with some embodiments of the present disclosure.

[0017] Figure 9 A block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0018] Aspects of the present disclosure are directed to iterative error correction that utilizes adjustable parameters after a threshold number of iterations in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with Figure 1 Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system may provide data to be stored at the memory subsystem and may request retrieval of data from the memory subsystem.

[0019] An example of a memory subsystem is a solid state drive (SSD) that includes one or more non-volatile memory devices and a memory subsystem controller that manages the non-volatile memory devices. The memory subsystem controller may encode data into a format that can be stored at the memory device. For example, a type of error detection and correction code (ECC), such as a low density parity check (LDPC) code, may be used to encode data. LDPC codes are capacity-approaching codes, which means that there are practical constructions that allow the error threshold to be set very close to the theoretical maximum. This error threshold defines an upper limit on data errors, whereby the probability of lost information can be made as small as possible. LDPC codes are reliable and efficient, which makes them suitable for bandwidth-constrained applications. For example, the encoded data written to the physical memory cells of a memory device may be referred to as a codeword. The data read from the cells, which may contain errors and be different from the codeword, may be referred to as a sense word. The sense word may include one or more of user data, an error correction code, metadata, or other information.

[0020] When performing error correction code operations, as part of a read operation, encoded data stored on a storage device can be transmitted from the memory device to the memory subsystem controller. The memory subsystem controller can perform a decoding operation to decode the encoded data into the original bit sequence that was encoded to be stored on the memory device. The number of bits of the decoded data received by the memory subsystem controller can be flipped due to noise, interference, distortion, bit synchronization errors, or errors from the medium itself (both intrinsic and extrinsic). For example, a bit that was initially stored as 0 can be flipped to 1, or vice versa, a bit that was initially stored as 1 can be flipped to 0.

[0021] Conventional memory subsystems perform error correction code operations that attempt to correct bit flip errors in the sensed words read from the memory device. For example, a conventional memory subsystem can perform error correction code operations on stored data to detect and correct errors in the encoded data. In many cases, an iterative process is used to decode the data. Fragments of the data array can be decoded to produce a string of corresponding bits (e.g., sensed words).

[0022] Generally, the error correction code capabilities of conventional memory subsystems are time and resource-intensive processes. The error correction process utilizes a number of parity equations, each parity equation applying to a subset of the bits of the sensed word, and the parity equations are used together to identify bit flip errors in the sensed word. In each iteration of the conventional error correction process, each bit of the sensed word can be processed at least twice (e.g., two or more passes are used on the entire sensed word). For example, during a first pass, the memory subsystem controller can identify the energy associated with each bit of the sensed word and identify the maximum energy associated with any bit of the sensed word. In one embodiment, the energy associated with a given bit (also referred to herein as the energy level) can be represented by a number of unsatisfied parity equations associated with the bit. In another embodiment, the energy can be the number of unsatisfied parity equations plus the XOR of the current bit value and its original value. A second pass of each bit of the sensed word is then required to compare the energy of each bit with the identified maximum energy. The conventional error correction process can then include flipping the bits that have an energy matching the maximum energy and moving to the next iteration of the process. The need to process each bit of the sensed word twice to identify the bits that should be flipped in a given iteration adds additional time and complexity to the conventional error correction process.

[0023] Aspects of the present disclosure address the above and other deficiencies by configuring iterative error correction parameters using criteria from previous iterations or partial iterations in a memory subsystem. In one embodiment, a parity component of a memory subsystem controller reads sensed words from memory devices of the memory subsystem and performs a number of parity equations on corresponding subsets of the sensed words. In one embodiment, each of the parity equations corresponds to a different subset of bits of the sensed word, although different subsets may share one or more bits. Each parity equation generates a parity equation result indicating whether the number of bits set to value '1' in the corresponding subset of the sensed word is even or odd. In one embodiment, if the number of bits set to value '1' in the corresponding subset is even, the parity equation result is said to be in a satisfied state (i.e., a state indicating no error in the corresponding subset of the sensed word), and if the number of bits set to value '1' in the corresponding subset is odd, the parity equation result is said to be in an unsatisfied state (i.e., a state indicating an error in the corresponding subset of the sensed word). Since any bit of the sensed word can be part of multiple different subsets, the bit can contribute to or be associated with multiple parity equation results. In one embodiment, the parity component logically combines all the parity equation results to determine the syndrome of the sensed word. If the syndrome of the sensed word does not satisfy the codeword criteria (e.g., does not indicate that all the parity equation results are in a satisfied state), the parity component determines that there is one or more errors in the sensed word and initiates an iterative LDPC correction process. Once the parity component starts flipping bits in the sensed word, the bit sequence may be referred to as a corrected word. In one embodiment, each iteration after the first iteration or at least one iteration after the first iteration uses a certain criterion that is at least partially based on the previous iteration of the LDPC correction process. The criterion is used to determine which bits of the corrected word to flip (i.e., change from '1' to '0' or from '0' to '1') and may include, for example, the maximum energy of any bit of the corrected word from the previous iteration (i.e., the iteration immediately preceding the current iteration). The parity component may perform multiple iterations of the LDPC correction process until the syndrome of the corrected word satisfies the codeword criteria, or until a threshold number of iterations is reached.

[0024] Other aspects of the present disclosure address the above and other deficiencies by performing iterative error correction using an adjustable parameter after a threshold number of iterations. In one embodiment, a parity component of a memory subsystem controller reads sense words from memory devices of the memory subsystem and performs a number of parity equations on a corresponding subset of the sense words. Each parity equation generates a parity equation result indicating whether the number of bits set to a value of '1' in the corresponding subset of the sense words is even or odd. If the syndrome of a sense word does not satisfy the codeword criterion (e.g., does not indicate that all parity equation results are in a satisfied state), the parity component determines that one or more errors exist in the sense word and initiates an iterative LDPC correction process using an adjustable parameter after a threshold number of iterations. In one embodiment, a first threshold number of iterations are initially performed using a first criterion that is at least partially based on a previous iteration of the LDPC correction process (e.g., one less than the maximum number of parity equation results for which any bit of the sense word or corrected word from the previous iteration is in an unsatisfied state). For any iteration performed after the first threshold number of iterations have been reached, the LDPC correction process may use a second criterion that is also at least partially based on a previous iteration of the LDPC correction process but may be different from the first criterion. For example, the second criterion may include the maximum number of parity equation results for which any bit of the corrected word from the previous iteration is in an unsatisfied state. The parity component may perform multiple iterations of the LDPC correction process until the syndrome of the corrected word satisfies the codeword criterion or until a second threshold number of iterations is reached. Additional details of the parity component and the iterative LDPC correction process are described below.

[0025] By using criteria from a previous iteration or an adjustable parameter after a threshold number of iterations to configure iterative error correction parameters, the number of times each bit of a sensed word is processed (i.e., the number of passes over each bit of the sensed word) can be reduced from two or more times to just once during the error correction process. For example, during a single pass, the memory subsystem controller can identify the number of unmet parity equation results associated with each bit of the sensed word and identify that the number of unmet parity equations is equal to the maximum number of parity equation results for any bit of the sensed word that was in an unmet state for the sensed word from the previous iteration. In one embodiment, the memory subsystem controller flips those bits and moves to the next iteration of the process without having to perform a second pass over the sensed word. This reduces the time and complexity of the parity and error correction process, thereby freeing up resources of the memory subsystem controller to perform other operations. Additionally, the techniques described herein can enable error correction to be completed in fewer iterations and reduce uncorrectable errors. Further, although the iterative error correction techniques are described herein in the context of reading data stored in a memory subsystem, it should be understood that these same techniques also apply to other implementations. For example, in an optical communication system, it may be necessary to verify whether the received data matches the transmitted data. If an error is identified in the received data, the iterative error correction techniques described herein can be applied to correct those errors. Advantages similar to those described above can be achieved in any number of different implementations of these techniques.

[0026] Figure 1 FIG. 1 shows an example computing system 100 that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. The memory subsystem 110 can include media such as one or more volatile memory devices (e.g., storage device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such memory devices.

[0027] The memory subsystem 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMCs), universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, an industrial device, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0029] The computing system 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of the host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0030] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0031] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include (but are not limited to) a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface that supports Double Data Rate (DDR)), etc. The physical host interface can be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize a Non-Volatile Memory Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1Memory subsystem 110 is shown as an example. In general, host system 120 may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0032] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) can be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. The cross-point array of non-volatile memory can perform bit storage based on the change of bulk resistance in combination with a stackable cross-gridded data access array. Additionally, compared with many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND type flash memory includes (for example) two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of memory devices 130 may include one or more memory cell arrays. One type of memory cell, e.g., single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), can store multiple bits per cell. In some embodiments, each of memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such memory cell arrays. In some embodiments, a particular memory device may include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of memory device 130 can be grouped into pages, which may refer to the logical units of the memory device for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0035] Although non-volatile memory components such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0036] Memory subsystem controller 115 (controller 115 for simplicity) can communicate with memory device 130 to perform operations such as reading data, writing data, or erasing data at memory device 130 and other such operations. Memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or combinations thereof. The hardware can include digital circuitry with dedicated (i.e., hard-wired) logic to perform the operations described herein. Memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] Memory subsystem controller 115 can include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, local memory 119 of memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of memory subsystem 110, including handling communications between memory subsystem 110 and host system 120.

[0038] In some embodiments, local memory 119 can include memory registers that store memory pointers, fetched data, etc. Local memory 119 can also include read-only memory (ROM) for storing microcode. Although Figure 1 the illustrated memory subsystem 110 has been shown to include memory subsystem controller 115, in another embodiment of the present disclosure, memory subsystem 110 does not include memory subsystem controller 115 and instead can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Typically, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (such as logical block addresses (LBAs), namespaces) associated with the memory device 130 and physical addresses (e.g., physical block addresses). The memory subsystem controller 115 can further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions for accessing the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 can also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0041] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] In one embodiment, the memory subsystem 110 includes a parity component 113 that may configure iterative error correction parameters using criteria from previous iterations or partial iterations in the memory subsystem 110. In one embodiment, in response to a syndrome of a sensed word read from one of the memory devices 130 or 140 not satisfying a codeword criterion (e.g., one or more of the parity equation results are in a non-satisfied state), the parity component may perform an iterative LDPC correction process. In one embodiment, the parity component 113 determines the number of parity equation results that are in a non-satisfied state for each bit of the sensed word and determines the maximum number of parity equation results that are in a non-satisfied state for any bit of the sensed word. If the current iteration is the first iteration of the iterative LDPC correction process, the parity component 113 may flip any bit in the sensed word where the energy level (e.g., the threshold number of parity equation results in a non-satisfied state) meets an energy threshold condition (e.g., is greater than or equal to a threshold energy level), and flip each of the parity equation results associated with those bits. In one embodiment, the threshold energy level is equal to the maximum energy of any bit of the sensed word (e.g., the maximum number of parity equation results in a non-satisfied state). If the current iteration is not the first iteration, the parity component 113 may flip any bit in the sensed word having an energy equal to the maximum energy of any bit of the corrected word from the previous iteration, and flip each of the parity equation results associated with those bits. The parity component 113 further determines whether the number of iterations performed in the iterative LDPC correction process meets an iteration criterion (e.g., is less than a threshold number of iterations), and if so, continues the LDPC correction process by moving to the next iteration. In response to the number of iterations performed not meeting the iteration criterion (e.g., meeting or exceeding a threshold number of iterations), the parity component 113 may end the LDPC correction process. Thus, in at least one iteration after the first iteration (e.g., each iteration after the first iteration), the parity component 113 uses criteria that are at least partially based on the previous iteration or partial iteration of the LDPC correction process. For example, the second iteration may use criteria based on the first iteration, the third iteration may use criteria based on the second iteration, and so on. Depending on the embodiment, the energy of a given bit may represent the number of unsatisfied parity equations associated with the bit or number of bits for which the parity equation is not satisfied plus the XOR of the current bit value with its original value (e.g., before the first iteration).

[0043] In another embodiment, the parity check component 113 determines the number of parity check equation results in an unsatisfied state for each bit of the sensed word, and determines the maximum number of parity check equation results in an unsatisfied state for any bit of the sensed word. If the current iteration is one of the threshold number of iterations after the first iteration of the iterative LDPC correction process (e.g., one of the first 3 or 4 iterations after the first iteration), then the parity check component 113 may flip any bit in the sensed word or the corrected word in which the number of parity check equation results in an unsatisfied state is greater than or equal to the maximum number of parity check equation results in an unsatisfied state for any bit of the sensed word or the corrected word from the previous iteration minus one, and flip each of the parity check equation results associated with those bits. If the current iteration is an iteration after the threshold number of iterations (e.g., not one of the first 3 or 4 iterations after the first iteration), then the parity check component 113 may flip any bit in the corrected word in which the number of parity check equation results in an unsatisfied state is equal to the maximum number of parity check equation results in an unsatisfied state for any bit of the corrected word from the previous iteration, and flip each of the parity check equation results associated with those bits. The parity check component 113 further determines whether the number of iterations performed in the iterative LDPC correction process satisfies an iteration criterion (e.g., less than the threshold number of iterations), and if so, continues the LDPC correction process by moving to the next iteration. In response to the number of iterations performed not satisfying the iteration criterion (e.g., satisfying or exceeding the threshold number of iterations), the parity check component 113 may end the LDPC correction process. Thus, after the threshold number of iterations, the parity check component 113 may adjust the criterion for determining whether to flip a given bit of the corrected word based at least in part on the previous iteration of the LDPC correction process. Other details regarding the operation of the parity check component 113 are described below.

[0044] Figure 2 is a flow chart of an example method of configuring iterative error correction parameters using criteria from a previous iteration in accordance with some embodiments of the present disclosure. Method 200 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 200 is performed by Figure 1is performed by the parity check component 113. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more of the processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0045] At operation 205, the processing logic receives a request to read data from a memory device, such as memory device 130, from a requesting party. In one embodiment, the memory subsystem controller 115 receives the request from the host system 120 or from some other component connected to or within the memory subsystem 110. The request may identify the data to be read from the memory device 130 of the memory subsystem 110.

[0046] At operation 210, the processing logic reads a sensed word from the memory device 130. In one embodiment, the sensed word comprises a sequence of bits representing the data requested at operation 205. In one embodiment, the parity check component 113 identifies the physical address in the memory device 130 storing the requested data, reads the sensed word from the memory device 130, and temporarily stores the sensed word in a buffer or other storage location while a parity check and / or error correction process may be performed. In Figure 3 An example sensed word 310 is shown. The sensed word 310 is shown as comprising a sequence of eight sensed word bits (i.e., SWB0 - SWB7), but it should be understood that this is merely an example for illustrative purposes. In other embodiments, the sensed word may comprise any number of bits, such as thousands of bits (e.g., 36k bits).

[0047] At operation 215, the processing logic performs a number of parity equations on a corresponding subset of the sensed word. In one embodiment, each of the parity equations corresponds to a different subset of bits of the sensed word, although different subsets may share one or more bits. For example, in one embodiment, a subset may include 40 bits out of 36k bits in the sensed word. There may be thousands (e.g., 3k) of parity equations, each configured to operate on a different subset of the 40 bits, for example. Each parity equation generates a parity equation result indicating whether the number of bits set to value '1' in the corresponding subset of the sensed word is even or odd. In one embodiment, if the number of bits set to value '1' in the corresponding subset is even, the parity equation result is said to be in a satisfied state, and if the number of bits set to value '1' in the corresponding subset is odd, the parity equation result is said to be in an unsatisfied state. In another embodiment, these values (i.e., logical states) may be reversed. Since any bit of the sensed word can be part of multiple different subsets, the bit may contribute to or be associated with multiple parity equation results. In one embodiment, each bit of the sensed word is part of the same number of subsets (e.g., 4 subsets) used by the parity equations.

[0048] At operation 220, the processing logic determines a syndrome of the sensed word using the determined parity equation results. In one embodiment, the parity component 113 logically combines the parity equation results to determine the syndrome, for example, by appending or concatenating the parity equation results. An example syndrome 320 is shown Figure 3 in FIG. The syndrome 320 is shown as including a sequence of eight syndrome bits (i.e., SB0 - SB7), but it should be understood that this is only an example for illustrative purposes. In other embodiments, the syndrome may include any number of bits, such as thousands of bits (e.g., 3k bits).

[0049] Figure 3FIG. 0 is a block diagram illustrating a syndrome correction submatrix 300 for configuring iterative error correction parameters according to some embodiments of the present disclosure. As described above, a sense word 310 includes a number of bits read from a memory device, and a syndrome 320 includes a number of bits representing the results of parity equations. In the illustrated example, there are eight parity equations, each parity equation corresponding to a different subset of the bits of the sense word 310. For example, a first subset represented by SB0 includes SWB0, SWB1, SWB2, and SWB4. A second subset represented by SB1 includes SWB0, SWB1, SWB2, and SWB5. A third subset represented by SB2 includes SWB0, SWB1, SWB2, and SWB6. There are additional subsets represented by each bit of the syndrome 320. In matrix 300, a value of '1' may indicate that a given bit of the sense word 310 is part of the subset represented by the bit of the syndrome 320, while a value of '0' may indicate that the bit of the sense word 310 is not part of the subset.

[0050] In one embodiment, each parity equation identifies the logical states of the bits of the sense word 310 that are part of each corresponding subset, adds those bits together, and determines whether the result is even or odd. In other words, each parity equation determines whether the number of bits of the sense word 310 that are part of the corresponding subset and have a particular logical state is even or odd. For example, the parity component 113 may determine whether the number of bits set to the logical value '1' in the corresponding subset of the sense word 310 is even or odd. In one embodiment, if the number of bits set to the logical value '1' in the corresponding subset of the sense word 310 is even, the parity equation result may be '0', indicating that the parity equation is satisfied. If the number of bits set to the logical value '1' in the corresponding subset of the sense word 310 is odd, the parity equation result may be '1', indicating that the parity equation is not satisfied. Each bit of the syndrome 320 represents one of these parity equation results. Thus, for SB0, since SWB0 is set to the value '1', SWB1 is set to the value '0', SWB2 is set to the value '1', and SWB4 is set to the value '0', there are two bits of the sense word 310 that are set to the value '1' in the corresponding subset. Two bits is an even number, so the parity equation result represented by SB0 is '0', indicating that the corresponding parity equation is satisfied. For example, for SB2, since SWB0 is set to the value '1', SWB1 is set to the value '0', SWB2 is set to the value '1', and SWB6 is set to the value '1', there are three bits of the sense word 310 that are set to the value '1' in the corresponding subset. Three bits is an odd number, so the parity equation result represented by SB0 is '1', indicating that the corresponding parity equation is not satisfied.

[0051] Referring back again toFigure 2 , at operation 225, the processing logic determines whether the syndrome of the sensed word satisfies the LDPC check criterion. In one embodiment, the parity check component 113 determines whether all of the parity check equation results in the syndrome are in a satisfied state (e.g., having a value of '0'). In one embodiment, if all of the parity check equation results in the syndrome are in a satisfied state, the parity check component 113 determines that the syndrome satisfies the LDPC check criterion. Conversely, if not all of the parity check equation results in the syndrome are in a satisfied state (e.g., one or more having a value of '1'), the parity check component 113 determines that the syndrome does not satisfy the LDPC check criterion. If the syndrome of the sensed word does satisfy the codeword criterion, the parity check component 113 determines that there are no errors in the sensed word and, at operation 230, transmits the sensed word as the requested data back to the requester.

[0052] However, if the syndrome of the sensed word does not satisfy the codeword criterion, the parity check component 113 determines that there is one or more errors in the sensed word and, at operation 235, performs an iterative LDPC correction process. In one embodiment, at least one iteration after the first iteration uses criteria that are at least partially based on a previous iteration or a partial iteration of the LDPC correction process. The criteria are used to determine which bits of the corrected word to flip (i.e., change from '1' to '0' or from '0' to '1') and may include, for example, the maximum number of parity check equation results for which a bit in the corrected word from a previous complete iteration (i.e., the iteration immediately preceding the current iteration) is in an unsatisfied state. In another embodiment, the criteria may be based on a partial iteration. For example, if a complete iteration involves checking 2000 bits, the maximum number (or maximum energy) of parity check equation results may be determined from only 1000 of those bits (i.e., one-half of the iteration) or some other fraction (e.g., one-third, one-quarter, etc.). If, in the current iteration, the parity check component 113 has examined a certain fraction of the bits that make up a complete iteration, the bits from this partial iteration of the current iteration may be used for the criteria. The parity check component 113 may perform multiple iterations of the LDPC correction process until the syndrome of the corrected word satisfies the codeword criterion at operation 225, or until a threshold number of iterations is reached. Additional details of the iterative LDPC correction process are described below with respect to Figure 4 describe additional details of the iterative LDPC correction process.

[0053] Figure 4is a flowchart of an example method of an iterative error correction process that configures one or more parameters using criteria from a previous iteration, according to some embodiments of the present disclosure. Method 400 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 400 is performed by the parity check component 113 of Figure 1 . Although shown in a particular sequence or order, the order of the process may be modified unless otherwise specified. Accordingly, it should be understood that the illustrated embodiments are merely examples, and the illustrated process may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible. Figure 1 At operation 405, the processing logic determines whether the syndrome of the sensed word satisfies the LDPC check criteria. If the syndrome of the sensed word does satisfy the codeword criteria, then at operation 410, the processing logic determines that there are no errors in the sensed word. However, if the syndrome of the sensed word does not satisfy the codeword criteria, then the parity check component 113 determines that there are one or more errors in the sensed word and initiates an iterative LDPC correction process. The iterative LDPC correction process may include a number of iterations, starting with a first iteration and continuing to one or more subsequent iterations.

[0054] At operation 415, the processing logic determines the number of parity check equation results that are in an unsatisfied state for each bit of the sensed word. Using the above and Figure 3

[0055] Figure 3In the example shown, SWB0 of sense word 310 is a portion that is a subset of SB0, SB1, SB2, and SB3 of syndrome 320, and SWB1 of sense word 310 is a portion that is a subset of SB0, SB1, SB2, and SB4 of syndrome 320, and SWB7 of sense word 310 is a portion that is a subset of SB3, SB5, SB6, and SB7 of syndrome 320. The additional bits of sense word 310 are portions of different subsets represented by each bit of syndrome 320. For SWB0, since SB0 is set to the value '0', SB1 is set to the value '0', SB2 is set to the value '1', and SB3 is set to the value '1', there are two bits of syndrome 320 that are set to the value '1', indicating that the corresponding parity check equation result is in an unsatisfied state. For SWB1, since SB0 is set to the value '0', SB1 is set to the value '0', SB2 is set to the value '1', and SB4 is set to the value '0', there is one bit of syndrome 320 that is set to the value '1', indicating that the corresponding parity check equation result is in an unsatisfied state. For SWB7, since SB3 is set to the value '1', SB5 is set to the value '1', SB6 is set to the value '0', and SB7 is set to the value '1', there are three bits of syndrome 320 that are set to the value '1', indicating that the corresponding parity check equation result is in an unsatisfied state. In another embodiment, the processing logic determines the energy for each bit of the sense word. Depending on the embodiment, the energy of a given bit can represent the number of unsatisfied parity check equations associated with the number of bits or the XOR of the current bit value with its original value.

[0056] At operation 420, the processing logic determines the maximum number of parity check equation results that are in an unsatisfied state for any bit of the sense word. Since SWB0 has two unsatisfied parity check equations, SWB1 has one unsatisfied parity check equation, and SWB7 has three unsatisfied parity check equations, the parity check component 113 can determine that the maximum number in the current iteration is three unsatisfied parity check equations. The parity check component 113 can store (e.g., in local memory 119 or elsewhere in memory subsystem 110) an indication of this maximum number for use in subsequent iterations. In another embodiment, the processing logic determines the maximum energy for any bit of the sense word.

[0057] At operation 425, the processing logic determines whether the current iteration of the LDPC correction process is the first iteration. If the current iteration is the first iteration, then at operation 430, the processing logic flips any bit in the sensed word in which the number (or level) of parity equation results in an unsatisfied state satisfies an energy threshold condition, and flips each of the parity equation results associated with those bits. In one embodiment, the energy threshold condition is satisfied when the level is greater than or equal to the threshold level. In one embodiment, the threshold level is equal to the maximum number of parity equation results in an unsatisfied state for any bit of the sensed word, as determined at operation 425. Thus, in the above example, the parity check component 113 may flip the value of SWB7 of the sensed word 310 from '0' to '1', and flip the values of SB3, SB5, SB6, and SB7 of the syndrome 320. The resulting matrix 500 is shown in Figure 5 . As shown, SWB7 of the sensed word 510 has a value of '1', SB3 of the syndrome 520 has a value of '0', SB5 has a value of '0', SB6 has a value of '1', and SB7 has a value of '0'. After flipping the bits at operation 430, the processing logic returns to operation 405 and determines whether the updated syndrome satisfies the codeword criterion.

[0058] However, if the processing logic determines at operation 425 that the current iteration is not the first iteration, then at operation 435, the processing logic flips any bit in the corrected word in which the number (or energy) of parity equation results in an unsatisfied state is greater than or equal to the maximum number (or maximum energy) of parity equation results in an unsatisfied state for any bit of the corrected word from the previous iteration, and flips each of the parity equation results associated with those bits. In one embodiment, the parity check component 113 checks the number of unsatisfied parity equation results from the updated syndrome 520 for each bit of the corrected word 510, and compares them with the maximum number of unsatisfied parity equation results from the previous iteration (e.g., 3), as determined at operation 420. The parity check component 113 may flip any identified bit in the corrected word 510. If there are no such identified bits in the corrected word 510, then no bits are flipped in the current iteration.

[0059] At operation 440, the processing logic determines whether the number of iterations performed in the iterative LDPC correction process meets an iteration criterion (e.g., less than a threshold number of iterations). In one embodiment, the parity check component 113 maintains a counter that is incremented after each iteration is performed. The parity check component 113 may compare the value of the counter to a threshold (e.g., 30) to determine whether the iteration criterion is met. If the number of iterations does meet the iteration criterion, the processing logic continues the LDPC correction process by determining whether the updated syndrome meets the codeword criterion and moving to the next iteration. However, if the number of iterations performed does not meet the iteration criterion (e.g., the number of iterations meets or exceeds the threshold number of iterations), the parity check component 113 may determine at operation 445 that the corrected word cannot be fully corrected and end the LDPC correction process.

[0060] Figure 6 is a flowchart of an example method of iterative error correction using an adjustable parameter after a threshold number of iterations in accordance with some embodiments of the present disclosure. Method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 600 is performed by the Figure 1 parity check component 113. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0061] At operation 605, the processing logic receives from a requester a request to read data from a memory device, such as memory device 130. In one embodiment, the memory subsystem controller 115 receives the request from the host system 120 or from some other component connected to or within the memory subsystem 110. The request may identify the data to be read from the memory device 130 of the memory subsystem 110.

[0062] At operation 610, the processing logic reads a sensed word from the memory device 130. In one embodiment, the sensed word includes a sequence of bits representing the data requested at operation 205. In one embodiment, the parity check component 113 identifies the physical address in the memory device 130 storing the requested data, reads the sensed word from the memory device 130, and temporarily stores the sensed word in a buffer or other storage location while the parity check and / or error correction process may be performed. In Figure 3An example sense word 310 is shown. The sense word 310 is shown as including a sequence of eight sense word bits (i.e., SWB0 - SWB7), but it should be understood that this is merely an example for illustrative purposes. In other embodiments, the sense word may include any number of bits, such as thousands of bits (e.g., 36k bits).

[0063] At operation 615, the processing logic performs a number of parity equations on corresponding subsets of the sense word. In one embodiment, each of the parity equations corresponds to a different subset of bits of the sense word, although different subsets may share one or more bits. For example, in one embodiment, a subset may include 40 bits out of 36k bits in the sense word. There may be, for example, thousands (e.g., 3k) of parity equations each configured to operate on a different subset of 40 bits. Each parity equation generates a parity equation result indicating whether the number of bits set to the value '1' in the corresponding subset of the sense word is even or odd. In one embodiment, if the number of bits set to the value '1' in the corresponding subset is even, the parity equation result is said to be in a satisfied state, and if the number of bits set to the value '1' in the corresponding subset is odd, the parity equation result is said to be in an unsatisfied state. In another embodiment, these values (i.e., logical states) may be reversed. Since any bit of the sense word can be part of multiple different subsets, the bit may contribute to or be associated with multiple parity equation results. In one embodiment, each bit of the sense word is part of the same number of subsets (e.g., 4 subsets) used by the parity equations.

[0064] At operation 620, the processing logic determines the syndrome of the sense word using the determined parity equation results. In one embodiment, the parity component 113 logically combines the parity equation results to determine the syndrome, such as by concatenating or stringing together the parity equation results. In Figure 3 An example syndrome 320 is shown. The syndrome 320 is shown as including a sequence of eight syndrome bits (i.e., SB0 - SB7), but it should be understood that this is merely an example for illustrative purposes. In other embodiments, the syndrome may include any number of bits, such as thousands of bits (e.g., 3k bits).

[0065] At operation 625, the processing logic determines whether the syndrome of the sensed word satisfies the LDPC check criterion. In one embodiment, the parity check component 113 determines whether the parity check equation results in the syndrome are all in a satisfied state (e.g., having a value of '0'). In one embodiment, if the parity check equation results in the syndrome are all in a satisfied state, the parity check component 113 determines that the syndrome satisfies the LDPC check criterion. Conversely, if the parity check equation results in the syndrome are not all in a satisfied state (e.g., one or more having a value of '1'), the parity check component 113 determines that the syndrome does not satisfy the LDPC check criterion. If the syndrome of the sensed word does satisfy the codeword criterion, the parity check component 113 determines that there are no errors in the sensed word and, at operation 630, transmits the sensed word as the requested data back to the requester.

[0066] However, if the syndrome of the sensed word does not satisfy the codeword criterion, the parity check component 113 determines that there are one or more errors in the sensed word and, at operation 635, performs an iterative LDPC correction process. In one embodiment, each of the first threshold number of iterations after the first iteration uses a first criterion that is at least partially based on the previous iteration of the LDPC correction process. The criterion is used to determine which bits of the corrected word to flip (i.e., change from '1' to '0' or from '0' to '1') and may include, for example, a number less than the maximum number of parity check equation results for which any bit of the corrected word from the previous iteration (i.e., the iteration immediately preceding the current iteration) is in an unsatisfied state. For any iteration performed after the first threshold number of iterations have been reached, the LDPC correction process may use a second criterion that is also at least partially based on the previous iteration of the LDPC correction process but may be different from the first criterion. For example, the second criterion may include the maximum number of parity check equation results for which any bit of the corrected word from the previous iteration is in an unsatisfied state.

[0067] The parity check component 113 may perform multiple iterations of the LDPC correction process until the syndrome of the corrected word satisfies the codeword criterion at operation 225 or until a second threshold number of iterations is reached. Additional details regarding Figure 7 the iterative LDPC correction process are described below.

[0068] Figure 7is a flowchart of an example method of an iterative error correction process that adjusts one or more parameters after a threshold number of iterations in accordance with some embodiments of the present disclosure. Method 700 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 700 is performed by the parity check component 113 of Figure 1 . Although shown in a particular sequence or order, the order of the process may be modified unless otherwise specified. Accordingly, it should be understood that the illustrated embodiments are merely examples and that the illustrated process may be performed in a different order and that some processes may be performed in parallel. Additionally, one or more of the processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible. Figure 1 At operation 705, the processing logic determines whether the syndrome of the sensed word satisfies the LDPC check criterion. If the syndrome of the sensed word does satisfy the codeword criterion, then at operation 410, the processing logic determines that there are no errors in the sensed word. However, if the syndrome of the sensed word does not satisfy the codeword criterion, then the parity check component 113 determines that there are one or more errors in the sensed word and initiates an iterative LDPC correction process. The iterative LDPC correction process may include a number of iterations, starting with a first iteration and continuing to one or more subsequent iterations.

[0069] At operation 715, the processing logic determines the number of parity check equation results that are in an unsatisfied state for each bit of the sensed word. Using the above and Figure 3

[0070] Figure 3In the example shown, SWB0 of the sense word 310 is part of a subset of SB0, SB1, SB2, and SB3 corresponding to the syndrome 320, and SWB1 of the sense word 310 is part of a subset of SB0, SB1, SB2, and SB4 corresponding to the syndrome 320, and SWB7 of the sense word 310 is part of a subset of SB3, SB5, SB6, and SB7 corresponding to the syndrome 320. The additional bits of the sense word 310 are parts of different subsets represented by each bit of the syndrome 320. For SWB0, since SB0 is set to the value '0', SB1 is set to the value '0', SB2 is set to the value '1', and SB3 is set to the value '1', there are two bits of the syndrome 320 that are set to the value '1', indicating that the corresponding parity check equation result is in an unsatisfied state. For SWB1, since SB0 is set to the value '0', SB1 is set to the value '0', SB2 is set to the value '1', and SB4 is set to the value '0', there is one bit of the syndrome 320 that is set to the value '1', indicating that the corresponding parity check equation result is in an unsatisfied state. For SWB7, since SB3 is set to the value '1', SB5 is set to the value '1', SB6 is set to the value '0', and SB7 is set to the value '1', there are three bits of the syndrome 320 that are set to the value '1', indicating that the corresponding parity check equation result is in an unsatisfied state. In another embodiment, the processing logic determines the energy for each bit of the sense word. Depending on the embodiment, the energy of a given bit may represent the number of unsatisfied parity check equations associated with the number of bits or the XOR of the current bit value with its original value.

[0071] At operation 720, the processing logic determines the maximum number of parity check equation results in an unsatisfied state for any bit of the sense word. Since SWB0 has two unsatisfied parity check equations, SWB1 has one unsatisfied parity check equation, and SWB7 has three unsatisfied parity check equations, the parity check component 113 can determine that the maximum number in the current iteration is three unsatisfied parity check equations. The parity check component 113 can store (e.g., in the local memory 119 or elsewhere in the memory subsystem 110) an indication of this maximum number for use in subsequent iterations. In another embodiment, the processing logic determines the maximum energy for any bit of the sense word.

[0072] At operation 725, the processing logic determines whether the current iteration of the LDPC correction process is the first iteration. If the current iteration is the first iteration, then at operation 730, the processing logic flips any bit in the sensed word in which the number (or level) of parity equation results in an unmet state meets the energy threshold condition, and flips each of the parity equation results associated with those bits. In one embodiment, the energy threshold condition is met when the level is greater than or equal to the threshold level. In one embodiment, the threshold level is equal to the maximum number of parity equation results for which any bit of the sensed word is in an unmet state, as determined at operation 425. Thus, in the above example, the parity check component 113 may flip the value of SWB7 of the sensed word 310 from '0' to '1', and flip the values of SB3, SB5, SB6, and SB7 of the syndrome 320. The resulting matrix 500 is shown in Figure 5 as shown. As shown, SWB7 of the sensed word 510 has the value '1', SB3 of the syndrome 520 has the value '0', SB5 has the value '0', SB6 has the value '1', and SB7 has the value '0'. After flipping the bits at operation 730, the processing logic returns to operation 705 and determines whether the updated syndrome meets the codeword criteria.

[0073] However, if the processing logic determines at operation 725 that the current iteration is not the first iteration, then at operation 735, the processing logic determines whether the number of iterations performed in the iterative LDPC correction process meets an adjustment threshold criterion (e.g., less than an adjustment threshold number of iterations). In one embodiment, the parity check component 113 maintains a counter that increments after each iteration is performed. The parity check component 113 may compare the value of the counter to an adjustment threshold (e.g., 3 or 4) to determine whether the adjustment threshold criterion is met.

[0074] If the number of iterations does meet the adjustment threshold criterion, then at operation 740, the processing logic flips any bit in the sensed word in which the number of parity equation results in an unmet state is greater than or equal to one less than the maximum number (or threshold level) of parity equation results for which any bit of the sensed word from the previous iteration was in an unmet state, and flips each of the parity equation results associated with those bits. Since the maximum number of unmet parity equations from the previous iteration determined at operation 720 was three, the parity check component may look for any bit of the sensed word 510 that has an equal number of unmet checks (i.e., = 3 - 1) of two. Thus, in the above example, the parity check component 113 may flip the value of SWB6 of the sensed word 510 from '0' to '1', and flip the values of SB2, SB3, SB4, and SB6 of the syndrome 520. The resulting matrix 800 is shown in Figure 8is shown. As shown, the SWB6 of the corrected word 810 has a value of '0', the SB2 of the syndrome 820 has a value of '0', the SB3 has a value of '1', the SB4 has a value of '1', and the SB6 has a value of '0'. In other embodiments, some other criterion may be used, such as two less, three less, etc. than the maximum number of unsatisfied parity equations from the previous iteration. After flipping the bits at operation 740, the processing logic returns to operation 705 and determines whether the updated syndrome satisfies the codeword criterion.

[0075] However, if the number of iterations performed does not satisfy the adjustment threshold criterion (e.g., the number of iterations meets or exceeds the adjustment threshold number of iterations), then at operation 745, the processing logic flips any bit in the corrected word in which the number (or energy) of parity equation results in an unsatisfied state is greater than or equal to the maximum number (or maximum energy) of parity equation results in an unsatisfied state for any bit of the corrected word from the previous iteration, and flips each of the parity equation results associated with those bits.

[0076] At operation 750, the processing logic determines whether the number of iterations performed in the iterative LDPC correction process satisfies the iteration criterion (e.g., less than the threshold number of iterations). In one embodiment, the parity check component 113 maintains a counter that is incremented after each iteration is performed. The parity check component 113 may compare the value of the counter to a threshold (e.g., 30) to determine whether the iteration criterion is satisfied. If the number of iterations does satisfy the iteration criterion, the processing logic continues the LDPC correction process by determining whether the updated syndrome satisfies the codeword criterion and moving to the next iteration. However, if the number of iterations performed does not satisfy the iteration criterion (e.g., the number of iterations meets or exceeds the threshold number of iterations), then the parity check component 113 may determine at operation 755 that the corrected word cannot be fully corrected and end the LDPC correction process.

[0077] Figure 9 An example machine of a computer system 900 is shown, within which an instruction set executable to cause the machine to perform any one or more of the methods discussed herein may be executed. In some embodiments, the computer system 900 may correspond to a host system (e.g., Figure 1 host system 120), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or may be used to perform the operations of a controller (e.g., execute an operating system to perform operations corresponding to Figure 1(operation of the parity check component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment.

[0078] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by that machine. Additionally, although a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0079] Example computer system 900 includes a processing device 902, a main memory 904 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 906 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 918, which communicate with each other via a bus 930.

[0080] Processing device 902 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, etc. More particularly, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. Computer system 900 may further include a network interface device 908 to communicate over a network 920.

[0081] The data storage system 918 may include a machine-readable storage medium 924 (also referred to as a computer-readable medium) having stored thereon one or more instruction sets 926 or software embodying any one or more of the methods or functions described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and / or within the processing device 902 during execution thereof by the computer system 900, which main memory 904 and processing device 902 also constitute machine-readable storage media. The machine-readable storage medium 924, the data storage system 918, and / or the main memory 904 may correspond to Figure 1 the memory subsystem 110.

[0082] In one embodiment, the instructions 926 include instructions that implement the functionality of a parity check component 113 corresponding to Figure 1 Although the machine-readable storage medium 924 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding an instruction set for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should accordingly be understood to include (but not be limited to) solid-state memory, optical media, and magnetic media.

[0083] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and so forth.

[0084] However, it should be borne in mind that all of these and similar terms are to be associated with appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage systems.

[0085] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to the computer system bus.

[0086] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. The structure of various of these systems will be presented as will be set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0087] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that may be used to program a computer system (or other electronic devices) to perform a process in accordance with the present disclosure. The machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, and the like.

[0088] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system, which comprises: a memory device; and a processing device operatively coupled to the memory device to perform operations including: receiving a request to read data from the memory device; and in response to receiving the request, performing an iterative error correction process on the data, wherein the iterative error correction process uses a first criterion for a first set of a threshold number of iterations and uses a second criterion at least partially based on a previous iteration for a second set of iterations after performing the threshold number of iterations.

2. The system according to claim 1, wherein performing the iterative error correction process comprises: determining an energy level associated with each bit of the data; determining a maximum energy level associated with any bit of the data; determining whether the current iteration of the error correction process is the first iteration; and in response to the current iteration being the first iteration, flipping any bit in the data whose energy level satisfies an energy threshold condition.

3. The system according to claim 2, wherein performing the iterative error correction process further comprises: in response to the current iteration not being the first iteration, determining whether the current iteration is one of the threshold number of iterations; and in response to the current iteration being one of the threshold number of iterations, flipping any bit in the data whose associated energy level is greater than or equal to the maximum energy level associated with any bit of the data from the previous iteration minus one.

4. The system according to claim 3, wherein the energy level associated with a given bit of the data represents the number of parity equation results for which the bit is in an unsatisfied state plus the XOR of the current value of the bit and the original value of the bit.

5. The system according to claim 3, wherein performing the iterative error correction process further comprises: in response to the current iteration not being one of the threshold number of iterations, flipping any bit in the data whose associated energy level is greater than or equal to the maximum energy level associated with any bit of the data from the previous iteration.

6. The system according to claim 1, wherein the processing device is configured to perform further operations including: performing a plurality of parity equations on a corresponding subset of the data to determine a plurality of parity equation results; using the plurality of parity equation results to determine a syndrome of the data; determining whether the syndrome of the data satisfies a codeword criterion; and in response to the syndrome of the data satisfying the codeword criterion, returning the data to the requester.

7. The system according to claim 6, wherein each of the plurality of parity equations corresponds to a different subset of the data, and wherein each of the plurality of parity equation results indicates whether the number of bits set to the value '1' in the corresponding subset of the data is even or odd, wherein determining the syndrome of the data comprises logically combining the plurality of parity equation results, and wherein determining whether the syndrome of the data satisfies the codeword criterion comprises determining whether all of the plurality of parity equation results in the syndrome are in a satisfied state.

8. The system according to claim 1, wherein the processing device is configured to perform further operations including: determining whether the number of iterations performed in the iterative error correction process satisfies an iteration criterion; in response to the number of iterations performed satisfying the iteration criterion, continuing the iterative error correction process; and in response to the number of iterations performed not satisfying the iteration criterion, ending the iterative error correction process.

9. A method, which comprises: receiving a request to read data from a memory device; and in response to receiving the request, performing an iterative error correction process on the data, wherein the iterative error correction process uses a first criterion for a first set of a threshold number of iterations and a second criterion at least partially based on a previous iteration for a second set of iterations after performing the threshold number of iterations.

10. The method according to claim 9, wherein performing the iterative error correction process comprises: determining the energy level associated with each bit of the data; determining the maximum energy level associated with any bit of the data; determining whether the current iteration of the iterative error correction process is the first iteration; and in response to the current iteration being the first iteration, flipping any bit in the data whose energy level satisfies an energy threshold condition.

11. The method according to claim 10, wherein performing the iterative error correction process further comprises: in response to the current iteration not being the first iteration, determining whether the current iteration is one of the threshold number of iterations; and in response to the current iteration being one of the threshold number of iterations, flipping any bit in the data whose associated energy level is greater than or equal to the maximum energy level associated with any bit of the data from the previous iteration minus one.

12. The method according to claim 11, wherein the energy level associated with a given bit of the data represents the number of parity equation results in an unsatisfied state for the bit plus the XOR of the current value of the bit and the original value of the bit.

13. The method according to claim 11, wherein performing the iterative error correction process further comprises: in response to the current iteration not being one of the threshold number of iterations, flipping any bit in the data whose associated energy level is greater than or equal to the maximum energy level associated with any bit of the data from the previous iteration.

14. The method according to claim 9, which further comprises: Perform a plurality of parity equations on corresponding subsets of the data to determine a plurality of parity equation results; Use the plurality of parity equation results to determine a syndrome of the data; Determine whether the syndrome of the data satisfies a codeword criterion; And In response to the syndrome of the data satisfying the codeword criterion, return the data to the requester.

15. The method according to claim 14, wherein each of the plurality of parity equations corresponds to a different subset of the data, and wherein each of the plurality of parity equation results indicates whether the number of bits set to value '1' in the corresponding subset of the data is even or odd, wherein determining the syndrome of the data includes logically combining the plurality of parity equation results, and wherein determining whether the syndrome of the data satisfies the codeword criterion includes determining whether all of the plurality of parity equation results in the syndrome are in a satisfied state.

16. The method according to claim 9, further comprising: Determine whether the number of iterations performed in the iterative error correction process satisfies an iteration criterion; In response to the number of iterations performed satisfying the iteration criterion, continue the iterative error correction process; And In response to the number of iterations performed not satisfying the iteration criterion, end the iterative error correction process.

17. A non-transitory computer-readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform operations including the following: Receive a request to read data from a memory device; and In response to receiving the request, perform an iterative error correction process on the data, wherein the iterative error correction process uses a first criterion for a first set of a threshold number of iterations and a second criterion that is at least partially based on a previous iteration for a second set of iterations after performing the threshold number of iterations.

18. The non-transitory computer-readable storage medium according to claim 17, wherein performing the iterative error correction process comprises: Determine an energy level associated with each bit of the data; Determine a maximum energy level associated with any bit of the data; Determine whether the current iteration of the error correction process is the first iteration; And In response to the current iteration being the first iteration, flip any bit in the data whose energy level satisfies an energy threshold condition.

19. The non-transitory computer-readable storage medium according to claim 18, wherein performing the iterative error correction process further comprises: In response to the current iteration not being the first iteration, determine whether the current iteration is one of the threshold number of iterations; And In response to the current iteration being one of the threshold number of iterations, flip any bit in the data whose associated energy level is greater than or equal to the maximum energy level associated with any bit of the data from the previous iteration minus one.

20. The non-transitory computer-readable storage medium according to claim 19, wherein the energy level associated with a given bit of the data represents the number of parity equation results for which the bit is in an unsatisfied state plus the XOR of the current value of the bit and the original value of the bit, and wherein performing the iterative error correction process further comprises: in response to the current iteration not being one of the threshold number of iterations, flipping any bit in the sense word data for which the associated energy level is greater than or equal to the maximum energy level associated with any bit of the sense word data from the previous iteration.

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