Storage controller, storage device and storage system

Abstract

The invention provides a storage controller, a storage device and a storage system. The memory controller includes: a processor configured to process a command for data from outside; a data storage configured to store the data as cache data; a tag memory configured to store a priority on replacement of the cache data; and a cache controller configured to determine a priority based on a type of the command for the data stored as cached data and a sequence of types.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0167881, filed with the Korean Intellectual Property Office on November 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a storage controller, a storage device, and a storage system. Background Art

[0003] A cache memory has a fast input / output speed but a small capacity. Since a programmer cannot directly manipulate the cache, the hit rate is an indicator of the cache memory performance, and since the capacity of the cache memory is also small, the cache replacement policy is directly related to the performance of the cache memory.

[0004] Generally, the least recently used (LRU) or most recently used (MRU) policy is used as a cache replacement policy, and these policies operate regardless of the operating environment of the system, resulting in inefficient management of the cache memory. There is a need to flexibly manage the cache memory according to the operating conditions of the system. Summary of the Invention

[0005] One or more embodiments of the present disclosure provide a storage controller including a cache memory that can improve the flexibility and hit rate of a cache replacement policy by considering the state of cache data.

[0006] In addition, one or more embodiments of the present disclosure provide a storage controller including a cache memory that can improve the cache hit rate by variably setting priorities according to the system state.

[0007] According to an aspect of an example embodiment, a storage controller includes: a processor configured to input and output commands for data to and from the outside; a data memory configured to store the data as cache data; a tag memory configured to store priorities for replacement of the cache data; and a cache controller configured to determine priorities based on the type and sequence of types of the commands for the data stored as cache data.

[0008] According to an aspect of an example embodiment, a storage device includes: a non-volatile memory device configured to store data; and a storage controller including a cache memory configured to store cache data for the data and priorities for replacement of the cache data, and to change at least a part of a priority table based on an application executed by an external host device, the priority table determining priorities for the cache data.

[0009] According to one aspect of an example embodiment, a storage system includes: a host device configured to execute an application and provide input / output commands for data based on the execution of the application; and a storage device including a non-volatile memory device and a cache memory, the non-volatile memory device being configured to store the data according to the input / output commands, the cache memory being configured to store the data as cache data, store priorities for replacement of the cache data, and determine priorities based on the application, a type of the input / output command for the data stored as cache data, and a sequence of the types. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the drawings.

[0011] Figure 1 is a block diagram showing a storage device according to an embodiment.

[0012] Figure 2 is showing Figure 1 a block diagram of a flash translation layer (FTL) of

[0013] Figure 3 is a block diagram showing a cache memory according to an embodiment.

[0014] Figure 4 is a diagram for explaining a priority table according to an embodiment.

[0015] Figure 5 is a diagram for explaining a priority bitmap according to an embodiment.

[0016] Figure 6 is a diagram for explaining a resistor array according to an embodiment.

[0017] Figure 7 is a block diagram showing a non-volatile storage device according to an embodiment.

[0018] Figure 8 is a diagram for explaining a three-dimensional structure of a memory cell array according to an embodiment.

[0019] Figure 9 and Figure 10 is a diagram for explaining an operation of a storage system according to an embodiment.

[0020] Figures 11 to 13 is a diagram for explaining an operation of a storage system according to an embodiment.

[0021] Figure 14 is a diagram for explaining an operation of a storage system according to an embodiment.

[0022] Figure 15 and Figure 16 is a diagram for explaining the operation of a storage system according to an embodiment.

[0023] Figure 17 is a diagram for explaining a priority bitmap according to an embodiment.

[0024] Figure 18 is a diagram for explaining a resistor array according to an embodiment.

[0025] Figure 19 and Figure 20 is a diagram for explaining the operation of a storage system according to an embodiment.

[0026] Figure 21 is a block diagram showing an SSD system to which a storage device according to an embodiment is applied.

[0027] Figure 22 is a block diagram showing a data center to which a storage device according to an embodiment is applied.

[0028] Figure 23 is a block diagram showing an electronic system to which a storage device according to an embodiment is applied. Detailed Description

[0029] Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. As those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0030] The accompanying drawings and the description are to be regarded as illustrative rather than restrictive. Throughout the specification, the same reference numerals represent the same elements.

[0031] For better understanding and convenience of description, the size and thickness of each component in the accompanying drawings are arbitrarily shown, and the following embodiments are not limited thereto.

[0032] In addition, unless explicitly stated to the contrary, the word "comprising" and its variations will be understood to mean including the stated elements but not excluding any other elements.

[0033] Figure 1 is a block diagram showing a storage device according to an embodiment. Figure 2 is showing Figure 1 a block diagram of the flash translation layer (FTL) of

[0034] Referring to Figures 1 to 2, the storage system 1 may include a host device 10 and a storage device 20. The host device 10 may include a host processor 11 and a host memory 12. The storage device 20 may include a storage controller 21 and a non-volatile memory device (NVM) 22.

[0035] The storage system 1 may include at least one of various information processing devices (such as, a personal computer, a laptop computer, a server, a workstation, a smart phone, a tablet PC). According to an embodiment, the storage system 1 may include communication equipment and may perform signal transmission and reception according to information processing with other devices external to the storage system 1.

[0036] According to an embodiment, the host processor 11 may operate as a processor to execute (process) a first application APP1, and the host memory 12 may operate as an operating memory such that the first application APP1 may be loaded onto the host memory 12 and executed. According to an embodiment, the first application APP1 may be a video playback program, a document editing / viewer program, etc. processed by the host device 10, but is not limited thereto.

[0037] According to an embodiment, the host processor 11 may execute and process commands, codes, files, image data, etc. while processing the first application APP1, and may control the host device 10 to provide a command CMD and a logical address LADDR related to the input / output of data DATA to the storage device 20 for data processing. The command CMD may include a data write command, a data read command, etc. According to an embodiment, the logical address LADDR may be provided to the storage device 20 in the form of a logical block address LBA.

[0038] According to an embodiment, the host processor 11 may manage operations of storing data (e.g., write data) in a buffer memory in the non-volatile memory device 22 or storing data (e.g., read data) of the non-volatile memory device 22 in the buffer memory. In the storage operation management of the host processor 11, according to an embodiment, the host memory 12 may be used as a buffer memory for temporarily storing data to be sent to the storage device 20 or data sent from the storage device 20.

[0039] According to an embodiment, the host processor 11 and the host memory 12 may be implemented as separate semiconductor chips. In addition, in one embodiment, the host processor 11 and the host memory 12 may be integrated in the same semiconductor chip. As an example, the host processor 11 may be one of multiple modules provided in an application processor, and the application processor may be implemented as a system on a chip (SOC). In addition, the host memory 12 may be an embedded memory provided within the application processor, or may be a non-volatile memory or a memory module provided outside the application processor.

[0040] The storage device 20 may include a storage medium for storing data according to a command CMD from the host device 10. For example, the storage device 20 may include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. If the storage device 20 is an SSD, the storage device 20 may be, for example, a device compliant with the Non-Volatile Memory Express (NVMe) standard.

[0041] If the storage device 20 is an embedded memory or an external memory, the storage device 20 may be a device compliant with the Universal Flash Storage (UFS) standard or the Embedded Multi-Media Card (eMMC) standard. The host device 10 and the storage device 20 may each generate and transmit a packet according to an adopted standard protocol.

[0042] When the non-volatile memory device 22 of the storage device 20 includes a flash memory, such a flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 20 may include various other types of non-volatile memories. For example, the storage device 20 may include a magnetic RAM (MRAM), a spin transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM, and various other types of memories.

[0043] The storage controller 21 may control the overall operation of the non-volatile memory device 22, and provide the command CMD to the non-volatile memory device 22 to control the data read operation and the data write operation of the non-volatile memory device 22. The storage controller 21 may include a host interface (I / F) 211 and a memory interface 212. In addition, the storage controller 21 may include a processor (e.g., a CPU) 213, a Flash Translation Layer (FTL) 214, a packet manager 215, a buffer memory 216, an Error Correction Code (ECC) engine 217, an Advanced Encryption Standard (AES) engine 218, etc.

[0044] The storage controller 21 may further include an operation memory, and an operating system or firmware executed by the processor 213 is loaded into the operation memory. According to an embodiment, the buffer memory 216 may operate as the operation memory of the processor 213, but is not limited thereto.

[0045] The host interface 211 can send packets to the host device 10 and receive packets from the host device 10. Packets sent from the host device 10 to the host interface 211 can include a command CMD or data DATA to be written to the non-volatile memory device 22, etc., and packets sent from the host interface 211 to the host device 10 can include a response to the command CMD or data DATA read from the non-volatile memory device 22, etc.

[0046] The memory interface 212 can send data DATA to be written to the non-volatile memory device 22 to the non-volatile memory device 22, or can receive data DATA read from the non-volatile memory device 22. The memory interface 212 can be implemented to conform to a standard protocol (such as Toggle or Open NAND Flash Interface (ONFI)).

[0047] The processor 213 can control the overall operation of the various components of the storage controller 21. The processor 213 can execute a firmware program or an operating system embedded in the storage device 20, and can process the command CMD (for example, can operate to provide the command CMD to the non-volatile memory device 22). The non-volatile memory device 220 can perform a data write operation and a data read operation on the data DATA through the provided command CMD.

[0048] According to an embodiment, the processor 213 can provide a priority value PV to Figure 3 multiple priority special function registers (SFR) PSFR within the cache controller 2145_1 of. As an example, the processor 213 can change the priority value PV stored in the multiple priority SFR PSFR according to a change in the application processed in the host device 10 (such as process execution, pre / post process switching, etc.).

[0049] According to an embodiment, the processor 213 can be implemented as various processing units (such as a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), etc. or a combination thereof).

[0050] The FTL 214 can include a mapping table management module 2141, a memory 2142 including a mapping table MT, a wear leveling module 2144, a garbage collection module 2143, and a cache memory 2145. The FTL 214 can perform various functions (such as address mapping, wear leveling, garbage collection) through the above configuration.

[0051] According to an embodiment, the FTL 214 can be implemented as hardware, firmware, software, and / or a combination thereof, and can be implemented as a dedicated circuit for performing the foregoing functions, but is not limited thereto.

[0052] The mapping table management module 2141 can perform an address mapping operation based on the mapping table MT. The address mapping operation is an operation of changing the logical address LADDR received from the host device 10 to the physical address PADDR for actually storing the data DATA in the non-volatile memory device 22.

[0053] The mapping table management module 2141 can modify the mapping table MT loaded in the memory 2142 by reflecting the wear leveling operation and the garbage collection operation for the non-volatile memory device 22. The mapping table MT can be implemented in the form of a lookup table or the like, and according to an embodiment, the mapping table MT may include an index, the logical address LADDR including the logical block address, and physical address PADDR information, etc. According to an embodiment, the mapping table MT may include the erase count or valid block information of the block according to the operation result of the FTL 214.

[0054] According to an embodiment, the mapping table MT can be stored in the non-volatile memory embedded in the FTL 214 or the non-volatile memory embedded in the host device 10. The stored mapping table MT can be loaded into the memory 2142 by the mapping table management module 2141.

[0055] In the memory 2142, the mapping table MT can be loaded during the address mapping operation of the mapping table management module 2141. The memory 2142 may include at least one of various types of memory devices (such as DRAM, SRAM, resistors, double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, non-volatile DIMM (NVDIMM), and combinations thereof).

[0056] Figure 2 It is shown that the memory 2142 is included in the FTL 214, but the embodiment is not limited thereto. According to an embodiment, Figure 1 the host memory 12 and the buffer memory 216 can perform the operation of the memory 2142.

[0057] The garbage collection module 2143 can perform a garbage collection operation for the non-volatile memory device 22. Garbage collection is a technique for ensuring the available capacity within the non-volatile memory device 22 by the method of copying the valid data of the original block to a new block and then erasing the original block.

[0058] The wear leveling module 2144 can perform a wear leveling operation for the non-volatile memory device 22. The wear leveling operation is a technique for preventing excessive deterioration of a specific block by ensuring uniform use of the blocks in the non-volatile memory device 22, and can be implemented by a firmware technique for balancing the erase count of the physical blocks.

[0059] The cache memory 2145 can operate as a buffer memory of the storage device 20, and can be used as a buffer memory for temporarily storing data DATA, command CMD, address LADDR to be sent from the host device 10 to the storage device 20, or data DATA sent from the storage device 20. The specific configuration of the cache memory 2145 will be described later with reference to Figures 3 to 6 describe the specific configuration of the cache memory 2145.

[0060] The packet manager 215 can generate packets according to the protocol negotiated with the host device 10 of the interface, or parse various information from the packets received from the host device 10.

[0061] The buffer memory 216 can temporarily store data DATA to be written into the non-volatile memory device 22 or data DATA to be read from the non-volatile memory device 22. The buffer memory 216 can be provided inside the storage controller 21, but according to an embodiment, the buffer memory 216 can be provided outside the storage controller 21.

[0062] The ECC engine 217 can perform an error detection and correction function on the read data DATA read from the non-volatile memory device 22. For example, the ECC engine 217 can generate parity bits for the write data to be written into the non-volatile memory device 22, and the parity bits so generated can be stored in the non-volatile memory device 22 together with the write data DATA. When reading data from the non-volatile memory device 22, the ECC engine 217 can use the parity bits read from the non-volatile memory device 22 together with the read data DATA to correct the error of the read data DATA, and can output the read data DATA with the error corrected.

[0063] The AES engine 218 can perform at least one of an encryption operation and a decryption operation on the data DATA input to the storage controller 21 by using a symmetric key algorithm.

[0064] Figure 3 is a block diagram showing a cache memory according to an embodiment. Figure 4 is a diagram for explaining a priority table according to an embodiment. Figure 5 is a diagram for explaining a priority bit map according to an embodiment. Figure 6 is a diagram of a resistor array according to an embodiment.

[0065] Referring to Figures 1 to 6 , the cache memory 2145 can include a cache controller 2145_1, a tag memory 2145_2, and a data memory 2145_3.

[0066] The cache memory 2145 can store each of the cache data CD0 to CDy and the tag information corresponding to the respective cache data among the cache data CD0 to CDy in the form of entries through the data memory 2145_3 and the tag memory 2145_2. According to an embodiment, the cache data CD0 to CDy can be data grouped in the form of cache blocks and cache lines in the data memory 2145_3, or can be data stored in units of pages.

[0067] The tag information can be stored in the tag memory 2145_2 and can be used for a search operation to determine whether the requested data DATA exists in the cache memory 2145. That is, the tag information can be information for confirming whether the cache data CD0 to CDy are hit. According to an embodiment, the tag information can correspond to an address, and the address can include a physical address, a logical address, etc., but is not limited thereto.

[0068] The cache controller 2145_1 can control the overall operation of the components of the cache memory 2145. The cache controller 2145_1 can perform a search operation for determining whether the data DATA requested from the host device 10 exists in the cache memory 2145, a replacement operation for some cache data entries to store new cache data when the data memory 2145_3 storing the cache data CD0 to CDy is full, an operation for determining the priority of each entry for the replacement operation, etc. The cache controller 2145_1 can include a configuration for processing operations.

[0069] The cache controller 2145_1 can include a priority manager PM and a victim cache selector VS. The priority manager PM can set and update the priority P for the replacement of the cache data CD0 to CDy stored in the data memory 2145_3.

[0070] The cache memory 2145 can store the cache data CD0 to CDy by a fully - associative method and can perform a replacement operation based on the priority P for all entries within the cache memory 2145, but the embodiment is not limited thereto. According to an embodiment, the cache memory 2145 can store the cache data CD0 to CDy by a set - associative method and can perform a replacement operation based on the priority P for partial entries corresponding to a group of entries among all entries within the cache memory 2145.

[0071] In the present disclosure, the priority P may be a state regarding the hit rate of cache data in the cache memory 2145. According to an embodiment, a high priority may be set to cache data having a high hit rate. According to an embodiment, for efficient resource management of the cache memory 2145, cache data with a low priority may be replaced first.

[0072] The priority manager PM may include a priority table PT and a plurality of priority SFRs PSFR. The priority manager PM may determine the priority P of each cache data based on the priority table PT and the plurality of priority SFRs PSFR, and may perform setting and updating operations for the priority of each cache data.

[0073] Referring to Figure 4 , the priority table PT may include a plurality of priority setting lists PSL1 to PSLM (M is an integer of 2 or greater), and the plurality of priority setting lists PSL1 to PSLM are distinguished based on the type of command for the cache data and the sequence of the type of command. Each of the priority setting lists PSL1 to PSLM may include a corresponding setting index PSL_I, the type of the previous command for the cache data, the type of the subsequent command for the cache data, and a priority value PV corresponding to the type of the previous command and the type of the subsequent command. In the present disclosure, the subsequent command may represent a command subsequently executed for "the cache data cached by the previous command". That is, the subsequent command may represent a command when the cache data is hit, and the previous command may represent a command before the cache data is hit.

[0074] According to an embodiment, the priority value PV corresponding to the type of the previous command and the type of the subsequent command may be changed according to the operating conditions of the host device 10. As an example, the priority table PT may be changed according to a change in the application processed in the host device 10 (for example, process execution, front / back process switching, etc.). Figure 4 The priority table PT of

[0075] shows an example of the priority value corresponding to the type of the previous command and the type of the subsequent command when the host device 10 executes the first application APP1.

[0076] According to an embodiment, the previous command and the subsequent command may include a command CMD provided from the host device 10, a command CMD generated based on the command CMD provided from the host device 10, or a command CMD generated within the storage controller 21 and provided to the non-volatile memory device 22, etc.

[0077] As an example, when the host device 10 provides a data write command or a data read command, the storage controller 21 may perform a data input / output operation based on the data write command or the data read command, and store the data that is the target of the input / output operation as cache data. In addition, when the host device 10 provides a data read command for sequentially stored data, the storage controller 21 may provide a prefetch command for data expected to be read internally to the non-volatile memory device 22, and may prefetch the data expected to be read as cache data.

[0078] According to an embodiment, the type of the previous command and the type of the subsequent command may each be one of a read command, a write command, and a prefetch command, but the type of the previous command and the type of the subsequent command may include a partial read command, a partial write command, etc. The type of the previous command and the type of the subsequent command are commands that trigger a cache operation of the cache memory 2145, and may be any command for accessing data stored in the storage device 20. The technical spirit and scope of the present disclosure are not limited to the examples of commands.

[0079] In addition, according to an embodiment, the type of the previous command may include a null command. In the present disclosure, the case where the previous command is a null command may indicate a case where data that was not previously cached is registered as cache data in the cache memory 2145.

[0080] For Figure 4 example, the priority table PT may include a first priority setting list PSL1 to an Mth priority setting list PSLM. The first priority setting list PSL1 may include a prefetch command as the type of the previous command, a read command as the type of the subsequent command, and 0 as the priority value PV corresponding to "prefetch command - read command".

[0081] The second priority setting list PSL2 may include a null command as the type of the previous command, a prefetch command as the type of the subsequent command, and 3 as the priority value PV corresponding to "null command - prefetch command". The prefetch command as the type of the subsequent command of the second priority setting list PSL2 may have the same type as the prefetch command as the type of the previous command of the first priority setting list PSL1. For Figure 4For example, for cache data whose priority is set based on the second priority setting list PSL2, operations caused by a read command can be executed subsequently. In the above example, the priority of cache data whose priority is predetermined based on the second priority setting list PSL2 can be updated by the first priority setting list PSL1.

[0082] The third priority setting list PSL3 may include a null command as the type of the previous command, a write command as the type of the subsequent command, and 2 as the priority value PV corresponding to "null command - write command".

[0083] The fourth priority setting list PSL4 may include a null command as the type of the previous command, a read command as the type of the subsequent command, and 2 as the priority value PV corresponding to "null command - read command".

[0084] The Mth priority setting list PSLM may include a read command as the type of the previous command, a read command as the type of the subsequent command, and 1 as the priority value PV corresponding to "read command - read command". In the same way, a read command as the type of the subsequent command of the fourth priority setting list PSL4 may have the same type as a read command as the type of the previous command of the Mth priority setting list PSLM. Figure 4 For example, for cache data whose priority is set based on the fourth priority setting list PSL4, operations caused by a read command can be executed subsequently. In the above example, the priority of cache data whose priority is predetermined based on the fourth priority setting list PSL4 can be updated by the Mth priority setting list PSLM.

[0085] In addition, based on the priority value PV stored in the multiple priority SFRs PSFR, the priority value PV in the priority setting lists PSL1 to PSLM in the priority table PT can be set and changed. According to a change in the application processed in the host device 10 (e.g., process execution, front / back process switching, etc.), the processor 213 according to an embodiment can provide the priority value PV to the multiple priority SFRs PSFR, and at least a part of the priority table PT can be set or changed by reflecting the priority value PV stored in the multiple priority SFRs PSFR.

[0086] According to an embodiment, the number of multiple priority SFRs PSFRs may correspond to M, where M is the number of priority setting lists PSL1 to PSLM within the priority table PT. The multiple priority SFRs PSFRs may include a first priority SFR to an nth priority SFR corresponding to the first priority setting list PSL1 to the Mth priority setting list PSLM, where n is a positive integer. According to an embodiment, one priority SFR may correspond to a priority value PV in one priority setting list, but the embodiment is not limited thereto.

[0087] The sacrifice cache selector VS may select cache data to be subject to a replacement operation. When the data memory 2145_3 is full, the sacrifice cache selector VS may select and remove entries of cache data in an order starting from the cache data with the lowest priority P.

[0088] For example, as Figure 5 shown, when there are priorities P in states P0 to P3, where the P0 state is the lowest priority and the P3 state is the highest priority, the sacrifice cache selector VS may first select and remove the first cache data CD1 and the first priority entry ET1 in the P0 state.

[0089] According to an embodiment, the sacrifice cache selector VS may remove cache data of the same priority in the order of the entries of the cache data (i.e., in a polling method).

[0090] The tag memory 2145_2 may include a priority bitmap PB. For example, the priority bitmap PB may be in a bitmap format. The priority bitmap PB may include multiple priority entries ET0 to ETy. The multiple priority entries ET0 to ETy may correspond to the entries of multiple cache data CD0 to CDy.

[0091] According to an embodiment, the number of priority entries ET0 to ETy within the priority bitmap PB may be equal to the number of entries that can be stored in the tag memory 2145_2 and the data memory 2145_3. According to the operation of the cache memory 2145, the number of multiple priority entries ET0 to ETy may be larger than the number of entries of the cache data, but when the data memory 2145_3 is full, the number of multiple priority entries ET0 to ETy and the number of cache data entries may be the same.

[0092] Each of the priority entries ET0 to ETy may include a priority P regarding the corresponding cache data among the cache data CD0 to CDy, and a setting index PSL_I.

[0093] When the data memory 2145_3 is full, the priority P can be used to perform a replacement operation for some entries to store (register) new cache data. For example, in the order starting from the lowest priority P of the cache data, the entries of the cache data can be removed from the cache memory 2145 by the victim cache selector VS.

[0094] The set index PSL_I can become the basis for setting or updating the priority P for the corresponding priority entries ET0 to ETy in the priority entries, and can correspond to the set index PSL_I of the corresponding priority setting list in the priority setting lists PSL1 to PSLM. According to an embodiment, when the priority value PV is changed according to the change of the operating conditions of the host device 10 or the cache data is hit, the set index PSL_I can be used in the update operation of the priority P. According to an embodiment, the set index PSL_I can be used by the victim cache selector VS in the removal operation.

[0095] The set index PSL_I can be represented by m bits (m is an integer of 2 or more), and according to an embodiment, the relationship between the number M of the priority configuration lists PSL1 to PSLM and the number m of the bits of the set index PSL_I can be represented by the following equation 1.

[0096] (Equation 1)

[0097] In Equation 1, M is the number of priority setting lists in the priority table PT, and m is the number of bits representing the set index PSL_I.

[0098] For Figure 5 example, the priority P of each of the priority entries ET0 to ETy can be one of the P0 state, P1 state, P2 state, and P3 state, and according to an embodiment, the priority can be increased from the P0 state to the P3 state, and the priority can be decreased from the P3 state to the P0 state. That is, the closer the cache data is to the P0 state, the faster it can be replaced to store new cache data. The order of the replacement operations for the P0 state, P1 state, P2 state, and P3 state is only an example, and the replacement order according to the P0 state, P1 state, P2 state, and P3 state can be according to an embodiment.

[0099] The 0th priority entry ET0 can correspond to the 0th cache data CD0, and the priority P of the 0th priority entry ET0 can be the P2 state, and the set index PSL_I can be 3. According to an embodiment, the priority P of the 0th cache data CD0 can be initially set through the third priority setting list PSL3.

[0100] The first priority entry ET1 can correspond to the first cache data CD1, and the priority P of the first priority entry ET1 can be in the P0 state, and the set index PSL_I can be 1. According to an embodiment, the priority P of the first cache data CD1 can be updated through the first priority setting list PSL1.

[0101] The second priority entry ET2 can correspond to the second cache data CD2, and the priority P of the second priority entry ET2 can be in the P3 state, and the set index PSL_I can be 2. According to an embodiment, the priority P of the second cache data CD2 can be initially set through the second priority setting list PSL2.

[0102] The third priority entry ET3 can correspond to the third cache data CD3, and the priority P of the third priority entry ET3 can be in the P3 state, and the set index PSL_I can be 2. According to an embodiment, the priority P of the third cache data CD3 can be initially set through the second priority setting list PSL2.

[0103] The y-th priority entry ETy can correspond to the y-th cache data CDy, and the priority P of the y-th priority entry ETy can be in the P1 state, and the set index PSL_I can be M. According to an embodiment, the priority P of the y-th cache data CDy can be set through the M-th priority setting list PSLM.

[0104] Figure 5 The number of states showing the priority P is 4, but the embodiment is not limited thereto and can vary according to the embodiment. In Figure 5 it, the priority P is represented by a flag bit of 1 bit representing each of the P0 state, P1 state, P2 state, and P3 state. According to an embodiment, the priority P can be represented by a plurality of bits by an index or a number.

[0105] Each of the P0 state, P1 state, P2 state, and P3 state can correspond to a priority value PV in the priority table PT. The priority P of the P0 state can correspond to the priority value PV "0", the priority P of the P1 state can correspond to the priority value PV "1", the priority P of the P2 state can correspond to the priority value PV "2", and the priority P of the P3 state can correspond to the priority value PV "3".

[0106] In the present disclosure, the priority manager PM can improve the flexibility and hit rate of the cache replacement policy by determining and storing the priority of the cache data and comprehensively considering the state of the cache data via the above priority setting lists PSL1 to PSLM distinguished based on the type of command and the sequence of the type of command.

[0107] In the present disclosure, the priority manager PM can optimize the cache hit rate for user data according to the system operation state by variably setting the priority of cache data according to the operation status of the host device 10.

[0108] Referring Figure 6 , the tag memory 2145_2 can store the priority bitmap PB through the resistor array RGA.

[0109] The resistor array RGA can include a plurality of resistors RG00 to RGy4 arranged along a plurality of rows R0 to Ry and a plurality of columns C0 to C4.

[0110] Each of the plurality of rows R0 to Ry can correspond to a respective priority entry ET0 to ETy in the priority bitmap PB. Each of the plurality of rows R0 to Ry can correspond to the priority P and the setting index PSL_I regarding the corresponding cache data among the cache data CD0 to CDy. As an example, the resistor RG00 to the resistor RG03 set in the 0th row can store the priority P of the 0th cache data CD0, and the resistor RG04 can store the m-bit setting index PSL_I regarding the 0th cache data CD0.

[0111] Among the plurality of columns C0 to C4, the 0th column C0 to the third column C3 can correspond to "whether the priority P corresponds to the P0 state, the P1 state, the P2 state, and the P3 state", and the fourth column C4 can correspond to the setting index PSL_I. As an example, the resistor RG00 to the resistor RGy0 set in the 0th column C0 can store information regarding "whether each of the cache data CD0 to CDy is in the P0 state". The resistor RG01 to the resistor RGy1 set in the first column C1 can store information regarding "whether each of the cache data CD0 to CDy is in the P1 state", the resistor RG02 to the resistor RGy2 set in the second column C2 can store information regarding "whether each of the cache data CD0 to CDy is in the P2 state", and the resistor RG03 to the resistor RGy3 set in the third column C3 can store information regarding "whether each of the cache data CD0 to CDy is in the P3 state".

[0112] In the same manner, the resistor RG04 to the resistor RGy4 set in the fourth column C4 can store the m-bit setting index PSL_I regarding each of the cache data CD0 to CDy.

[0113] Figure 7is a block diagram showing a non-volatile memory device according to an exemplary embodiment.

[0114] Referring to Figure 7 , the non-volatile memory device 22 may include a control logic circuit 221, a memory cell array 222, a page buffer unit 225, a voltage generator 223, and a row decoder 224. The non-volatile memory device 220 may also include Figure 1 the memory interface 212 shown in

[0115] and may also include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc. Figure 1 The control logic circuit 221 may generally control various operations within the non-volatile memory device 22. The control logic circuit 221 may output various control signals in response to a command CMD and / or an address ADDR from the memory interface 212 (see

[0116] ). For example, the control logic circuit 221 may output a voltage control signal CTRL_VOL, a row address X-ADDR, and a column address Y-ADDR.

[0117] The memory cell array 222 may include a plurality of memory blocks BLK1, BLK2, ……, BLKn, and each of the plurality of memory blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 222 may be connected to the page buffer unit 225 through bit lines BL, and may be connected to the row decoder 224 through a ground selection line GSL, a word line WL, and a string selection line SSL.

[0118] In one embodiment, the memory cell array 222 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. In one embodiment, the memory cell array 222 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along a row direction and a column direction.

[0119] The voltage generator 223 may generate various types of voltages based on the voltage control signal CTRL_VOL to perform programming operations, read operations, and erase operations. For example, the voltage generator 223 may generate a programming voltage, a read voltage, a programming verification voltage, an erase voltage, etc. as the word line voltage VWL.

[0120] The row decoder 224 may select one of the multiple word lines WL in response to the row address X-ADDR, and may select one of the multiple string select lines SSL. For example, during a programming operation, the row decoder 224 may apply the programming voltage and the programming verification voltage to the selected word line, and during a read operation, the row decoder 224 may apply the read voltage to the selected word line.

[0121] Figure 8 is a diagram for explaining the three-dimensional structure of a memory cell array according to an exemplary embodiment. When the nonvolatile memory device 22 according to an embodiment is implemented as a 3D V-NAND type flash memory, each of the multiple memory blocks constituting the memory module may be represented as Figure 8 the equivalent circuit shown in

[0122] Figure 8 The memory block BLKi shown in is a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, the multiple memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate (e.g., in the Z direction perpendicular to the X direction and the Y direction).

[0123] Referring to Figure 8 , the memory block BLKi may include multiple memory NAND strings NS11 to NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the multiple memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2,..., and MC8, and a ground select transistor GST. Figure 8 shows that each of the multiple memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2,..., and MC8, but is not limited thereto.

[0124] The string selection transistors SST can be connected to corresponding string selection lines SSL1, SSL2, and SSL3. Multiple memory cells MC1, MC2, ……, and MC8 can be respectively connected to corresponding gate lines GTL1, GTL2, ……, and GTL8. The gate lines GTL1, GTL2, ……, and GTL8 can correspond to word lines, and a part of the gate lines GTL1, GTL2, ……, and GTL8 can correspond to dummy word lines. The ground selection transistors GST can be connected to corresponding ground selection lines GSL1, GSL2, and GSL3. The string selection transistors SST can be connected to corresponding bit lines BL1, BL2, and BL3, and the ground selection transistors GST can be connected to a common source line CSL.

[0125] Word lines of the same height (e.g., GTL1) can be commonly connected, and the ground selection lines GSL1, GSL2, and GSL3 and the string selection lines SSL1, SSL2, and SSL3 can be separated from each other. Figure 8 It shows that the memory block BLK is connected to eight gate lines GTL1, GTL2, ……, and GTL8, and three bit lines BL1, BL2, and BL3, but it is not necessarily limited to this.

[0126] Figure 9 and Figure 10 are diagrams for explaining the operation of a storage system according to an embodiment. Figure 9 and Figure 10 are diagrams for explaining the case where, assuming Figure 4 the priority table PT and Figure 5 the priority bitmap PB, the cache memory 2145 updates the priority P in the case of a cache data hit.

[0127] Referring to Figures 1 to 5 、 Figure 9 and Figure 10 During the execution of the first application APP1, the host device 10 can provide the logical block address LBA and a read command RCMD corresponding to the second cache data CD2 to the storage device 20.

[0128] The priority manager PM can confirm a previous command corresponding to the cache data hit situation based on the set index PSL_I of the cache data. In addition, the priority manager PM can search for a priority setting list corresponding to the cache data hit situation based on the set index PSL_I of the cache data and the command of the cache data.

[0129] The priority manager PM can check the set index PSL_I for the second cache data CD2 through the second priority entry ET2 for the second cache data CD2. The priority manager PM can confirm the previous command before the read command RCMD for the second cache data CD2 through a subsequent command of the second priority setting list PSL2 corresponding to the case where the set index PSL_I is "2".

[0130] The priority manager PM can recognize the prefetch command as the previous command before the read command RCMD for the second cache data CD2. When the storage device 20 receives the read command RCMD for the second cache data CD2, the priority manager PM can determine and update the priority P and the set index PSL_I for the second cache data CD2 based on the second priority setting list PSL2.

[0131] When the priority manager PM receives the read command RCMD for the second cache data CD2, the priority manager PM can update the priority P and the set index PSL_I to P0 and 1 respectively based on the set index PSL_I and the second priority setting list PSL2 corresponding to 2.

[0132] Figures 11 to 13 It is a diagram for explaining the operation of the storage system according to the embodiment. Figures 11 to 13 It is a diagram for explaining the following situation: under the assumption Figure 4 of the priority table PT and Figure 5 the priority bitmap PB, the cache memory 2145 updates the priority P when the operation situation of the host device 10 changes and the cache data is hit.

[0133] Referring to Figures 1 to 5 and Figures 11 to 13 , the program processed by the host device 10 can be changed from the first application APP1 to the second application APP2. This change may include: the host device 10 ends the execution of the first application APP1 and starts the execution of the second application APP2. In addition, this change may include: while switching the first application APP1 to be post-processed, the second application APP2 is pre-processed.

[0134] In the same manner as in the first application APP1, the second application APP2 can also be a video playback program, a document editing / viewer program, etc. processed by the host device 10, but the embodiment is not limited thereto.

[0135] The logical block address LBA corresponding to the third cache data CD3 and the read command RCMD can be provided to the storage device 20.

[0136] In response to the processing of the second application APP2 by the host device 10, the processor 213 may change the priority value PV stored in at least a part of the plurality of priority SFRs. For Figure 12 example, in response to the processing of the second application APP2 by the host device 10, the processor 213 may change the priority value PV stored in the SFR corresponding to the first priority setting list PSL1. Therefore, the priority value PV of the first priority setting list PSL1 may be changed from 0 to 1.

[0137] During the execution of the second application APP2, the host device 10 may provide the logical block address LBA and the read command RCMD corresponding to the third cache data CD3 to the storage device 20.

[0138] The priority manager PM may confirm the previous command corresponding to the cache data hit situation based on the set index PSL_I of the cache data. In addition, the priority manager PM may search for the priority setting list corresponding to the cache data hit situation based on the set index PSL_I of the cache data and the command of the cache data.

[0139] The priority manager PM may check the set index PSL_I regarding the third cache data CD3 through the third priority entry ET3 regarding the third cache data CD3. The priority manager PM may confirm the previous command before the read command RCMD for the third cache data CD3 through the subsequent command of the second priority setting list PSL2 corresponding to the case where the set index PSL_I is "2".

[0140] The priority manager PM may confirm the prefetch command as the previous command before the read command RCMD for the third cache data CD3. The storage device 20 may receive the read command RCMD for the third cache data CD3. In response to this reception, the priority manager PM may determine and update the priority P and the set index PSL_I regarding the third cache data CD3 based on the first priority setting list PSL1 in which the previous command and the subsequent command correspond to "prefetch command - read command".

[0141] When the storage device 20 receives the read command RCMD for the third cache data CD3, the priority manager PM may update the priority P and the set index PSL_I to "P1" and "1" respectively based on the set index PSL_I corresponding to 2 and the first priority setting list PSL1.

[0142] According to an embodiment, for cache data misses, even if at least a part of the priority value PV in the priority table PT is changed, the priority manager PM can maintain the priority P corresponding to the cache data misses.

[0143] The priority manager PM can maintain the priority P in the first priority entry ET1 at "P0" for the first cache data CD1 miss.

[0144] Figure 14 is a diagram for explaining the operation of a storage system according to an embodiment. Figure 14 is related to Figure 13 corresponding diagram, and for ease of explanation, will focus on the difference from the operation in Figure 13 to describe the operation in Figure 14 the operation.

[0145] Refer to Figures 1 to 5 , Figures 11 to 12 and Figure 14 , according to the change of the priority value PV in the first priority setting list PSL1, the priority manager PM can change the priority P of the priority entry with the setting index PSL_I being 1.

[0146] The priority manager PM can update the priority P in the first priority entry ET1 corresponding to the first cache data CD1 from "P0" to "P1".

[0147] According to an embodiment, even for cache data misses, the priority manager PM can update the priority P in response to the changed priority value PV in the priority table PT.

[0148] Figure 15 and Figure 16 are diagrams for explaining the operation of a storage system according to an embodiment. Under the assumption of Figure 4 the priority table PT and Figure 5 the priority bitmap PB of Figure 15 and Figure 16 are diagrams for explaining the replacement operation of some cache data entries for storing new cache data when the data memory 2145_3 is full.

[0149] Refer to Figures 1 to 5 , Figure 15 and Figure 16 , during the execution of the first application APP1, the host device 10 can provide data, logical block address LBA, and write command WCMD corresponding to the z-th cache data CDz to be newly stored in the storage device 20.

[0150] The data memory 2145_3 can be provided as the z-th cache data CDz of new cache data when filled with the 0-th cache data CD0 to the y-th cache data CDy.

[0151] The sacrifice cache selector VS can select a priority entry among the 0-th priority entry ET0 to the y-th priority entry ETy based on the priority P, and remove the cache data corresponding to the selected priority entry. After the removal operation, the new cache data, tag information, and the corresponding priority can be stored in the cache memory 2145.

[0152] The sacrifice cache selector VS can select and remove the first priority entry ET1 among the 0-th priority entry ET0 to the y-th priority entry ETy whose priority P is P0. The z-th cache data CDz instead of the first cache data CD1 can be newly stored in the data memory 2145_3, and the priority P and the set index PSL_I regarding the z-th cache data CDz can be initially set in the first priority entry ET1 of the priority table PT.

[0153] Refer to Figure 4 , since the write command WCMD corresponding to the z-th cache data CDz is provided, the priority P and the set index PSL_I of the first priority entry ET1 can be initially set by replacing with "P2" and "3" based on the third priority setting list PSL3.

[0154] Figure 17 is a diagram for explaining the priority bitmap according to an embodiment. Figure 18 is a diagram for explaining the resistor array according to an embodiment. Figure 17 The priority bitmap PB' of Figure 5 can correspond to the priority bitmap PB of Figure 18 , and the resistor array RGA' of Figure 6 can correspond to the resistor array RGA of Figure 5 and Figure 6 . For ease of explanation, the differences between Figure 17 and Figure 18 will be described. Figure 17 and Figure 18 . In the following, in the descriptions of Figure 5 and Figure 6 , the contents same as those of the cache memory 2145 of

[0155] Refer to Figures 1 to 4 , Figure 17 and Figure 18, each of the multiple priority entries ET0 to ETy in the priority bitmap PB' may include a 1-bit flag bit representing the respective correspondence PSL_1 to PSL_M of the priority setting lists PSL1 to PSLM for the cache data, rather than a setting index. The correspondence indicates that the priority P of the cache data is set or updated based on the corresponding priority setting list.

[0156] As an example, the 0th priority entry ET0 may include a 1-bit flag bit representing the correspondence PSL_1 of the first priority setting list for the 0th cache data CD0, a 1-bit flag bit representing the correspondence PSL_2 of the second priority setting list for the 0th cache data CD0, a 1-bit flag bit representing the correspondence PSL_M of the Mth priority setting list for the 0th cache data CD0, etc., and the priority P. It can be seen that according to the 0th priority entry ET0, the priority P of the 0th cache data CD0 is set or updated by the priority setting lists other than the first priority setting list PSL1, the second priority setting list PSL2, and the Mth priority setting list PSLM.

[0157] The first priority entry ET1 may include a 1-bit flag bit representing the correspondence PSL_1 of the first priority setting list for the first cache data CD1, a 1-bit flag bit representing the correspondence PSL_2 of the second priority setting list for the first cache data CD1, a 1-bit flag bit representing the correspondence PSL_M of the Mth priority setting list for the first cache data CD1, etc., and the priority P. It can be seen that according to the first priority entry ET1, the priority P of the first cache data CD1 is set or updated by the first priority setting list PSL1.

[0158] The second priority entry ET2 may include a 1-bit flag bit representing the correspondence PSL_1 of the first priority setting list for the second cache data CD2, a 1-bit flag bit representing the correspondence PSL_2 of the second priority setting list for the second cache data CD2, a 1-bit flag bit representing the correspondence PSL_M of the Mth priority setting list for the second cache data CD2, etc., and the priority P. It can be seen that according to the second priority entry ET2, the priority P of the second cache data CD2 is set or updated by the second priority setting list PSL2.

[0159] The third-priority entry ET3 may include a flag bit of 1 bit representing the first-priority setting list correspondence PSL_1 of the third cache data CD3, a flag bit of 1 bit representing the second-priority setting list correspondence PSL_2 of the third cache data CD3, a flag bit of 1 bit representing the Mth-priority setting list correspondence PSL_M of the third cache data CD3, etc., and a priority P. It can be seen that according to the third-priority entry ET3, the priority P of the third cache data CD3 is set or updated through the second-priority setting list PSL2.

[0160] The yth-priority entry ETy may include a flag bit of 1 bit representing the first-priority setting list correspondence PSL_1 of the yth cache data CDy, a flag bit of 1 bit representing the second-priority setting list correspondence PSL_2 of the yth cache data CDy, a flag bit of 1 bit representing the Mth-priority setting list correspondence PSL_M of the yth cache data CDy, etc., and a priority P. It can be seen that according to the yth-priority entry ETy, the priority P of the yth cache data CDy is set or updated through the Mth-priority setting list PSLM.

[0161] The tag memory 2145_2 may store a priority bitmap PB' through a resistor array RGA'. The resistor array RGA' may include a plurality of resistors RG00 to RGyM arranged along a plurality of rows R0 to Ry and a plurality of columns C0 to C3 and Ca to CM.

[0162] Each of the plurality of rows R0 to Ry may correspond to a corresponding priority entry among the priority entries ET0 to ETy in the priority bitmap PB'. Each of the plurality of rows R0 to Ry may correspond to a flag bit of 1 bit representing the priority P of the corresponding cache data among the cache data CD0 to CDy and the priority setting list correspondences PSL_1 to PSL_M of the corresponding cache data among the cache data CD0 to CDy. As an example, the 0_a resistor RG0a to the 0_M resistor RG0M set in the 0th row R0 may correspond to the flag bits of 1 bit representing the respective priority setting list correspondences PSL_1 to PSL_M of the 0th cache data CD0.

[0163] One of the a-th column Ca to the M-th column CM may correspond to a flag bit of 1 bit representing the correspondence of one of the plurality of priority setting lists PSL1 to PSLM regarding the cache data CD0 to CDy.

[0164] Figure 19 and Figure 20 is a diagram for explaining the operation of the storage system according to the embodiment. Figures 19 to 20is a diagram for explaining the following situation: under the assumption that Figure 4 's priority table PT and Figure 17 's priority bitmap PB', when the operating condition of the host device 10 changes, at least a part of the priority table PT is changed, and the cache memory 2145 updates the priority P in the case of a cache data hit as shown in Figure 12 .

[0165] Figure 11 and Figure 13 can correspond to Figure 19 and Figure 20 respectively. For ease of description, the following description will focus on the differences from the descriptions of Figure 11 and Figure 13 . In the following, the same content as the description of Figures 11 to 13 will be omitted.

[0166] Referring to Figures 1 to 4 , Figure 12 , Figure 17 , Figure 19 and Figure 20 , when the program processed by the host device 10 is changed from the first application APP1 to the second application APP2, the priority value PV of the first priority setting list PSL1 can be changed from 0 to 1.

[0167] During the execution of the second application APP2, the host device 10 can provide the logical block address LBA corresponding to the third cache data CD3 and the read command RCMD to the storage device 20.

[0168] The priority manager PM can confirm the previous command corresponding to the cache data hit situation based on the 1-bit flag bits representing the respective correspondences PSL_1 to PSL_M of the priority setting lists PSL1 to PSLM. In addition, the priority manager PM can search for the priority setting list corresponding to the cache data hit situation based on the flag bits and the command of the cache data.

[0169] The priority manager PM can check the flag bits representing the correspondences PSL_1 to PSL_M of the priority setting lists regarding the third cache data CD3 through the third priority entry ET3. Based on the fact that the flag bit of the second priority setting list correspondence PSL_2 representing the third priority entry ET3 is "1", the priority manager PM can confirm that the previous command before the read command RCMD for the third cache data CD3 is a prefetch command.

[0170] The storage device 20 may receive a read command RCMD for the third cache data CD3. In response to this reception, the priority manager PM may determine and update the flag bits representing the correspondence between the priority P and the priority setting lists PSL_1 to PSL_M for the third cache data CD3 based on a first priority setting list PSL1 in which previous commands and subsequent commands correspond to "prefetch command - read command".

[0171] When the storage device 20 receives a read command RCMD for the third cache data CD3, the priority manager PM may update the priority P, the first priority setting list correspondence PSL_1, and the second priority setting list correspondence PSL_2 to "P1", "1", and "0" respectively, based on the first priority setting list PSL1 and the flag bits representing the second priority setting list correspondence PSL_2.

[0172] According to an embodiment, the priority manager PM may change the priority P of the priority entry whose flag bit of the first priority setting list correspondence PSL_1 is 1 according to the change in the priority value PV of the first priority setting list PSL1.

[0173] In the present disclosure, the cache controller 2145_1 may improve the flexibility and hit rate of the cache replacement policy by determining and storing the priority of the cache data and comprehensively considering the state of the cache data through the priority setting lists PSL1 to PSLM distinguished based on the type of command and the sequence of the type of command.

[0174] In the present disclosure, the processor 213 and the cache controller 2145_1 may optimize the cache hit rate for user data according to the system operation state by variably setting the priority of the cache data according to the operation situation of the host device 10.

[0175] The priority manager PM may update the priority P of the first priority entry ET1 corresponding to the first cache data CD1 from "P0" to "P1".

[0176] Figure 21 is a block diagram of an SSD system to which a storage device according to an embodiment is applied. Referring to Figure 21 , the SSD system 1000 may include a host 1100 and an SSD 1200.

[0177] The SSD 1200 can exchange signals SIG with the host 1100 through the signal connector 1201 and receive power PWR through the power connector 1202. The SSD 1200 can include an SSD controller 1210, a plurality of NVMs (e.g., flash memories) 1221 to 122m, an auxiliary power supply 1230, and a buffer memory 1240. The plurality of flash memories 1221 to 122m can be respectively connected to the SSD controller 1210 through a plurality of channels.

[0178] The SSD controller 1210 can control the plurality of flash memories 1221 to 122m in response to the signal SIG received from the host 1100. The SSD controller 1210 can store an internally generated signal or a signal sent from the outside (e.g., the signal SIG received from the host 1100) in the buffer memory 1240.

[0179] The SSD controller 1210 can be implemented as the storage controller 200 described above with reference to Figures 1 to 20 For example, the SSD controller 1210 can include a cache memory that differentiates the priority of replacement operations based on the type of command and the sequence of the type of command, thereby improving the flexibility and hit rate of the cache replacement policy within the SSD controller 1210. In addition, the cache memory of the SSD controller 1210 can variably set the priority of cache data according to the operating conditions of the host 1100 to optimize the cache hit rate for user data according to the system operating state, and can improve the overall input / output performance of the SSD 1200.

[0180] The plurality of flash memories 1221 to 122m can operate under the control of the SSD controller 1210. The auxiliary power supply 1230 is connected to the host 1100 through the power connector 1202.

[0181] The auxiliary power supply 1230 can be connected to the host 1100 through the power connector 1202. The auxiliary power supply 1230 can receive power PWR from the host 1100 and be charged thereby. When the power PWR from the host 1100 is unstable, the auxiliary power supply 1230 can supply power to the SSD 1200.

[0182] Figure 22 is a block diagram of a data center to which a storage device according to an embodiment is applied. Refer to Figure 22, the network system 2000 is a facility that collects various data and provides services, and can be referred to as a data center or a data storage center. The network system 2000 may include application servers 2100 to 2100n (e.g., application server 1 to application server N, where N is a positive integer) and storage servers 2200 to 2200m (e.g., storage server 1 to storage server M, where M is a positive integer), and the application servers 2100 to 2100n and the storage servers 2200 to 2200m may be referred to as computing nodes. According to an embodiment, the number of application servers 2100 to 2100n and the number of storage servers 2200 to 2200m can be selected in various ways, and the number of application servers 2100 to 2100n and the number of storage servers 2200 to 2200m may be different from each other.

[0183] The application servers 2100 to 2100n and the storage servers 2200 to 2200m can communicate with each other through a network (NT) 2300. The network 2300 can be implemented by using Fibre Channel (FC), Ethernet, etc. In this case, FC is a medium for high-speed data transmission, and an optical switch that provides high performance and / or high availability can be used. According to the access method of the network 2300, the storage servers 2200 to 2200m can be set as file storage devices, block storage devices, or object storage devices.

[0184] In one embodiment, the network 2300 can be a network dedicated to storage (such as a Storage Area Network (SAN)). For example, the SAN can be an FC-SAN that uses an FC network and is implemented according to the FC protocol (FCP). In one embodiment, the SAN can be an IP-SAN that uses a TCP / IP network and is implemented according to the iSCSI (SCSI over TCP / IP or Internet SCSI) protocol. In one embodiment, the network 2300 can be a general network (such as a TCP / IP network). For example, the network 2300 can be implemented according to protocols (such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF)).

[0185] Hereinafter, the description will focus on the application server 2100 and the storage server 2200. The description of the application server 2100 can also be applied to the other application servers 2100n, and the description of the storage server 2200 can also be applied to the other storage servers 2200m.

[0186] The application server 2100 may include a processor 2110 and a memory 2120. The processor 2110 may control the overall operation of the application server 2100 and may access the memory 2120 to execute commands and / or data loaded in the memory 2120. According to an embodiment, the number of processors 2110 and the number of memories 2120 included in the application server 2100 may be selected in various ways. In one embodiment, the processor 2110 and the memory 2120 may be configured as a "processor-memory" pair. In one embodiment, the number of processors 2110 and the number of memories 2120 may be set to be different from each other.

[0187] The application server 2100 may further include a storage device 2150. At this time, the number of storage devices 2150 included in the application server 2100 may be selected in various ways according to an embodiment. The processor 2110 may provide a command to the storage device 2150, and the storage device 2150 may operate in response to the command received from the processor 2110. However, the present disclosure is not limited thereto, and the application server 2100 may not include the storage device 2150.

[0188] The application server 2100 may further include a switch 2130 and a network interface card (NIC) 2140. Under the control of the processor 2110, the switch 2130 may selectively connect the processor 2110 and the storage device 2150, or selectively connect the NIC 2140 and the storage device 2150. The NIC 2140 may include a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. In one embodiment, the processor 2110 and the NIC 2140 may be integrated into one body. In one embodiment, the storage device 2150 and the NIC 2140 may be integrated into one body.

[0189] The application server 2100 may store data requested to be stored by a user or a client in one of the storage servers 2200 to 2200m through the network 2300. In addition, the application server 2100 may obtain data requested to be read by a user or a client from one of the storage servers 2200 to 2200m through the network 2300. For example, the application server 2100 may be implemented as a web server or a database management system (DBMS), etc.

[0190] The application server 2100 can access the memory 2120n or the storage device 2150n included in another application server 2100n through the network 2300, and / or can access the memory 2220 and 2220m or the storage device 2250 and 2250m included in the storage servers 2200 and 2200m through the network 2300. Therefore, the application server 2100 can perform various operations on the data stored in the application servers 2100 and 2100n and / or the storage servers 2200 and 2200m. For example, the application server 2100 can execute commands for moving or copying data between the application servers 2100 and 2100n and / or the storage servers 2200 and 2200m. In this case, for security or privacy, the data can be moved through the network 2300 in an encrypted state.

[0191] The storage server 2200 may include a processor 2210 and a memory 2220. The processor 2210 can control the overall operation of the storage server 2200 and can access the memory 2220 to execute commands and / or data loaded in the memory 2220. According to an embodiment, the number of processors 2210 and the number of memories 2220 included in the storage server 2200 can be selected in various ways. In one embodiment, the processor 2210 and the memory 2220 can be configured as a "processor-memory" pair. In one embodiment, the number of processors 2210 and the number of memories 2220 can be set to be different from each other.

[0192] The processor 2210 may include a single-core processor or a multi-core processor. For example, the processor 2210 may include a general-purpose processor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a microcontroller (MCU), a microprocessor, a network processor, an embedded processor, a field programmable gate array (FPGA), an application specific instruction set processor (ASIC), an application specific integrated circuit processor (ASIC), etc.

[0193] The storage server 2200 may further include at least one storage device 2250. The number of storage devices 2250 included in the storage server 2200 can be selected in various ways according to an embodiment. The storage device 2250 may include a controller (CTRL) 2251, a NAND flash (NAND) 2252, a DRAM 2253, and an interface (I / F) 2254. Hereinafter, the configuration and operation of the storage device 2250 will be described in detail. The following description of the storage device 2250 can also be applied to other storage devices 2150, 2150n, and 2250m.

[0194] Interface 2254 can provide a physical connection between processor 2210 and controller 2251 and a physical connection between NIC 2240 and controller 2251. For example, interface 2254 can be implemented in a direct attached storage (DAS) method that directly connects the storage device 2250 to a dedicated cable. In addition, for example, interface 2254 can be implemented in various interface methods (such as, Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Institute of Electrical and Electronics Engineers (IEEE) 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Compact Flash (CF) card interface, etc.).

[0195] Controller 2251 can generally control the operation of storage device 2250. Controller 2251 can program data into NAND flash memory 2252 in response to a programming command, or can read data from NAND flash memory 2252 in response to a read command. For example, the programming command and / or the read command can be sent through processor 2210 or directly from processor 2210 in storage server 2200, processor 2210m in another storage server 2200m, or processors 2110 and 2110n in application servers 2100 and 2100n.

[0196] NAND flash memory 2252 can include a plurality of NAND flash memory cells. However, embodiments of the present disclosure are not limited thereto, and storage device 2250 can include non-volatile memory other than NAND flash memory 2252 (such as, resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM)), or can include magnetic storage media or optical storage media.

[0197] Dynamic RAM (DRAM) 2253 can be used as a buffer memory. For example, DRAM 2253 can be a double data rate synchronous DRAM (DDRSDRAM), low power DDR (LPDDR) SDRAM, graphics DDR (GDDR) SDRAM, Rambus DRAM (RDRAM), or high bandwidth memory (HBM). However, embodiments of the present disclosure are not limited thereto, and storage device 2250 can use volatile memory or non-volatile memory other than DRAM as a buffer memory. DRAM 2253 can temporarily store (buffer) the data to be written into NAND flash memory 2252 or the data read from NAND flash memory 2252.

[0198] The storage server 2200 may further include a switch 2230 and a NIC 2240. Under the control of the processor 2210, the switch 2230 may selectively connect the processor 2210 and the storage device 2250, or may selectively connect the NIC 2240 and the storage device 2250. In one embodiment, the application server 2100n may further include a switch 2130n and a NIC 2140n. In one embodiment, the processor 2210 and the NIC 2240 may be integrated into one body. In one embodiment, the storage device 2250 and the NIC 2240 may be integrated into one body. In one embodiment, the controller 2251m, the NAND flash 2252m, the DRAM 2253m, the interface 2254m, the switch 2230m, and the NIC 2240m in the storage server 2200m may correspond to the controller 2251, the NAND flash 2252, the DRAM 2253, the interface 2254, the switch 2230, and the NIC 2240 in the storage server 2200.

[0199] The storage devices 2150, 2150n, 2250, and 2250m may correspond to the storage devices described above with reference to Figures 1 to 20 For example, the controller 2251 may transmit a command / address CMD / ADDR to the NAND flash 2252 based on a request provided from one of the processors 2110, 2110n, 2210, and 2210m. The controller 2251 may include a cache memory that differentiates the priority of replacement operations based on the type of command and the sequence of the type of command, thereby improving the flexibility and hit rate of the cache replacement policy within the controller 2251. In addition, the cache memory of the controller 2251 may variably set the priority of cache data according to the operation status of the host device 10 to optimize the cache hit rate for user data according to the system operation state, thereby improving the overall input / output performance of the storage devices 2150, 2150n, 2250, and 2250m.

[0200] Figure 23 is a block diagram showing an electronic system to which a storage device is applied according to an embodiment. Referring to Figure 23 , basically, the system 3000 may be a mobile system (such as a portable communication terminal (e.g., a mobile phone), a smart phone, a tablet PC (tablet personal computer), a wearable device, a healthcare device, or an Internet of Things (IoT) device). In one embodiment, the system 3000 is not limited to a mobile system and may be a personal computer, a laptop computer, a server, a media player, an automotive device (such as a navigation), etc.

[0201] System 3000 may include a main processor 3100, memories 3200a and 3200b, and storage devices 3300a and 3300b. In addition, system 3000 may include at least one of an image capture device 3410, a user input device 3420, a sensor 3430, a communication device 3440, a display 3450, a speaker 3460, a power supply device 3470, and a connection interface 3480.

[0202] The main processor 3100 may control the overall operation of system 3000 (more specifically, control the operations of other components forming system 3000). The main processor 3100 may be implemented as a general-purpose processor, a dedicated processor, an application processor, etc. The main processor 3100 may correspond to Figure 1 the host processor 11.

[0203] The main processor 3100 may include one or more CPU cores 3110 and may also include a controller 3120 for controlling memories 3200a and 3200b and / or storage devices 3300a and 3300b. According to an embodiment, the main processor 3100 may further include an accelerator 3130, which is a dedicated circuit for high-speed data computing (such as artificial intelligence (AI) data computing). The accelerator 3130 may include a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), etc., and may be implemented as a chip physically independent and separated from other components of the main processor 3100.

[0204] Memories 3200a and 3200b may be used as the main memory devices of system 3000, may include volatile memories (such as SRAM and / or DRAM), but may also include non-volatile memories (such as flash memory, PRAM, RRAM, etc.). Memories 3200a and 3200b may also be implemented in the same package as the main processor 3100. In one embodiment, memories 1200a and 1200b may operate as the host memory 12 previously described in Figure 1 ...

[0205] The storage devices 3300a and 3300b can be used as non-volatile storage devices for storing data regardless of whether power is supplied, and can have a relatively large storage capacity compared to the memories 3200a and 3200b. The storage devices 3300a and 3300b can include storage controllers (STRG CTRL) 3310a and 3310b and non-volatile memories (NVM) 3320a and 3320b that store data under the control of the storage controllers 3310a and 3310b. The non-volatile memories 3320a and 3320b can include flash memories having a 2D (two-dimensional) structure or a 3D (three-dimensional) V-NAND (vertical NAND) structure, but can also include other types of non-volatile memories (such as PRAM, RRAM, etc.).

[0206] The storage controllers 3310a and 3310b can be implemented as the storage controller 200 described above with reference to Figures 1 to 20 For example, the storage controllers 3310a and 3310b can include a cache memory that differentiates the priority of replacement operations based on the type of command and the sequence of the type of command, thereby improving the flexibility and hit rate of the cache replacement policy within the storage controllers 3310a and 3310b. In addition, the cache memory of the storage controllers 3310a and 3310b can variably set the priority of cache data according to the operating conditions of the main processor 3100 to optimize the cache hit rate for user data according to the system operating state, thereby improving the overall input / output performance of the storage devices 3300a and 3300b.

[0207] The storage devices 3300a, 3300b can be included in the system 3000 while being physically separated from the main processor 3100, and can be implemented in the same package as the main processor 3100. In addition, the non-volatile memories 3320a and 3320b can have the form of, for example, a solid state drive (SSD) or a memory card, and can be removably attached to other components of the system 3000 through an interface (such as the connection interface 3480 described later). The storage devices 3300a and 3300b can be devices that apply standard protocols (such as Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or Non-Volatile Memory Express (NVMe)), but are not limited thereto.

[0208] In one embodiment, under the control of the main processor 3100, the storage devices 3300a and 3300b can be configured to perform various calculations, and in one embodiment, the storage devices 3300a and 3300b can be configured to perform or implement some of the functions executed by the accelerator 3130.

[0209] The image capturing device 3410 can capture still images or moving images and can be a camera, a camcorder, a webcam, etc.

[0210] The user input device 3420 can receive various types of data input from the user of the system 3000 and can be a touchpad, a keypad, a keyboard, a mouse, a microphone, etc.

[0211] The sensor 3430 can detect various types of physical quantities that can be obtained from the outside of the system 3000 and can convert the detected physical quantities into electrical signals. The sensor 3430 can be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biological sensor, a gyro sensor, etc.

[0212] The communication device 3440 can perform transmission and reception of signals with other devices outside the system 3000 according to various communication protocols. Such a communication device 3440 can be implemented to include an antenna, a transceiver, a modem, etc.

[0213] The display 3450 and the speaker 3460 can be used as output devices that output visual information and auditory information to the user of the system 3000, respectively.

[0214] The power supply device 3470 can appropriately convert the power supplied from the battery placed in the system 3000 and / or an external power supply and supply the power to each component of the system 1000.

[0215] The connection interface 3480 can provide a connection between the system 3000 and an external device connected to the system 3000 and capable of exchanging data with the system 3000. The connection interface 3480 can be implemented in various interface methods (such as, Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), eMMC, UFS, Embedded Universal Flash (eUFS), Compact Flash (CF) card interface, etc.).

[0216] Although the embodiments of the present disclosure have been described in connection with what are currently considered to be practical embodiments, it will be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A storage controller, comprising: A processor configured to process commands from an external source for data; a data storage device configured to store the data as cache data; a tag memory configured to store a priority regarding replacement of cache data; as well as A cache controller is configured to determine a priority based on a type of the command for the data stored as cache data and a sequence of the types.

2. The storage controller according to claim 1, wherein: The cache controller is further configured to: determine a priority regarding the cache data based on the priority table, wherein the priority table includes a priority setting list, and The priority setting list includes a type of a previous command for one cache data, a type of a subsequent command for the one cache data, and priority values ​​corresponding to the type of the previous command and the type of the subsequent command.

3. The storage controller according to claim 2, wherein: The type of the previous command is one of a read command, a write command, and a prefetch command, and The type of the subsequent command is one of a read command, a write command, and a pre-fetch command.

4. The storage controller according to claim 3, wherein: The cache controller is further configured to update the priorities stored in the tag memory based on the priority setting list.

5. The storage controller according to claim 2, wherein: The type of the previous command was the empty command, and The type of the subsequent command is one of a read command, a write command, and a pre-fetch command.

6. The storage controller according to claim 5, wherein: The cache data is newly stored in the data memory, and The cache controller is further configured to initially set the priority in the tag memory based on the priority setting list.

7. The storage controller according to claim 2, wherein: The priority setting list includes a first priority setting list and a second priority setting list different from the first priority setting list, The first priority setting list includes a type of a first previous command, a type of a first subsequent command, and a first priority value corresponding to the type of the first previous command and the type of the first subsequent command. wherein the second priority setting list includes a type of the second previous command, a type of the second subsequent command, and a second priority value corresponding to the type of the second previous command and the type of the second subsequent command, and The type of the first subsequent command is the same as the type of the second previous command.

8. The storage controller according to claim 7, wherein: The cache controller is further configured to update priorities stored based on the first priority setting list based on the second priority setting list.

9. The storage controller according to claim 8, wherein: The tag memory is further configured to store a first index to the first priority setting list together with the priority, and The cache controller is further configured to update the priority based on the first index and the second priority setting list.

10. The storage controller according to any one of claims 1 to 9, wherein: The data storage is also configured to store the cache data in a fully associative method.

11. The storage controller according to claim 10, wherein: The data includes first data and second data different from the first data, and The cache controller is further configured to remove the first cache data based on priority, based on the first data being stored in the data memory as the first cache data, the second data being stored in the cache memory, and the data memory being full.

12. A storage device, comprising: a non-volatile memory device configured to store data; as well as A memory controller includes a cache memory, the cache memory being configured to: storing cache data regarding the data and a priority regarding replacement of the cache data, and At least a portion of a priority table that determines a priority with respect to cache data is changed based on an application executed by the external host device.

13. The storage device according to claim 12, wherein: The cache memory includes: a data storage configured to store cache data; a tag memory configured to store the priorities in a priority bitmap in a bitmap format; and The cache controller includes a priority table and is configured to determine a priority based on the priority table.

14. The storage device according to claim 13, wherein: The priority table includes a first priority setting list and a second priority setting list corresponding to the type and sequence of the types of commands for the cache data, the first priority setting list including a first priority value, the second priority setting list including a second priority value, and The cache controller is further configured as follows: A first priority setting list is set based on a first special function register storing a first priority value, and The second priority setting list is set based on a second special function register storing a second priority value.

15. The storage device according to claim 14, wherein: The cache data includes first cache data and second cache data different from the first cache data, wherein the priority bitmap includes a first entry regarding the first cache data and a second entry regarding the second cache data, wherein the first entry includes a first priority for the first cache data and a first index of at least two bits for the first priority setting list, and The second entry includes a second priority level for the second cache data and a second index of at least two bits for the second priority setting list.

16. The storage device according to claim 15, wherein: Based on the execution of the application, the first priority value stored in the first special function register is changed to a third priority value, and Wherein, based on the first special function register storing the third priority value, the first priority level within the priority bitmap is changed based on the first index and the third priority level value.

17. The storage device according to claim 15, wherein: Based on the execution of the application, the first priority value stored in the first special function register is changed to a third priority value, and Wherein, based on the first special function register storing the third priority value, the first priority and the second priority in the priority bitmap are maintained.

18. The storage device according to claim 14, wherein: The cache data includes first cache data and second cache data different from the first cache data, wherein the priority bitmap includes a first entry regarding the first cache data and a second entry regarding the second cache data, The first entry includes a first priority of the first cache data and a first flag bit of one bit indicating whether the first cache data corresponds to the first priority setting list, and The second entry includes a second priority level of the second cache data and a second flag bit of one bit regarding whether the second cache data corresponds to the first priority setting list.

19. The storage device according to any one of claims 12 to 18, wherein: The cache memory is further configured to change the at least a portion of the priority table based on the application being a pre-processed application.

20. A storage system comprising: a host device configured to execute an application and provide an input / output command for data based on the execution of the application; as well as A storage device comprising: a nonvolatile memory device configured to store the data according to an input / output command, and A cache memory is configured to: store the data as cache data, store a priority regarding replacement of the cache data, and determine the priority based on the application, a type of input / output command for the data stored as cache data, and a sequence of the types.

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