Method for training timing parameters of an ethernet interface, electronic device and storage medium

Abstract

The application discloses a timing parameter training method of an Ethernet interface, an electronic device and a storage medium. The method comprises the following steps: performing timing training on initial parameters of a set Ethernet interface to obtain a sending delay available range, a second initial sending delay, a receiving delay available range and a second initial receiving delay; performing first data transceiving test by traversing the receiving delay available range based on the second initial sending delay or the second target timing parameter obtained through training; obtaining a receiving delay window after traversing the receiving delay available range; determining a first intermediate value of the receiving delay window as a first target timing parameter; performing second data transceiving test by traversing the sending delay available range based on the second initial receiving delay or the first target timing parameter; obtaining a sending delay window after traversing the sending delay available range; and determining a second intermediate value of the sending delay window as a second target timing parameter. The method can improve the Ethernet throughput performance and working efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Ethernet interface, and in particular to a timing parameter training method of an Ethernet interface, an electronic device and a storage medium. BACKGROUND

[0002] With the development of Ethernet technology, the transmission rate of Ethernet is getting faster and faster. In order to ensure the transmission performance, the requirements of Ethernet interface on read-write timing are also getting more and more strict. For example, when data is transmitted and received by using an RGMII interface, the data changes at the edge of the clock. In order to stably sample at the receiving end, a delay is usually added to the clock signal, so that the edge thereof is aligned with the stable interval of the data bus, so as to ensure that the setup time and the hold time of transmission / reception meet the protocol requirements.

[0003] In the related art, a high cost is required to fixedly configure timing parameters for the same type of chips. When a large number of chips are produced and manufactured, process angle chips will introduce timing deviation. At this time, read-write timing may exist in a critical situation using fixedly configured timing parameters; thereby causing the Ethernet throughput performance of individual batches of chips to be low or unable to work normally. Therefore, how to determine the timing parameters of the adaptive Ethernet interface is a problem to be solved. SUMMARY

[0004] The embodiments of the present application provide a timing parameter training method of an Ethernet interface, an electronic device and a storage medium, which can obtain adaptive timing parameters of the Ethernet interface through training, thereby improving the Ethernet throughput performance and work efficiency.

[0005] In a first aspect, the embodiments of the present application provide a timing parameter training method of an Ethernet interface, which is applied to a MAC controller in a system on chip, and the system on chip is in communication connection with a target device.

[0006] The method comprises:

[0007] Setting a transmission delay value range, a receiving delay value range, a first initial transmission delay and a first initial receiving delay of the Ethernet interface; wherein the first initial transmission delay belongs to the transmission delay value range, and the first initial receiving delay belongs to the receiving delay value range;

[0008] Performing first timing training according to the transmission delay value range and the first initial transmission delay, to obtain a transmission delay available range and a second initial transmission delay; and performing second timing training according to the receiving delay value range and the first initial receiving delay, to obtain a receiving delay available range and a second initial receiving delay;

[0009] Based on the second initial transmission delay or the second target timing parameters obtained through training, the first data transmission and reception test is performed by traversing the available range of the reception delay. After traversing the available range of the reception delay, the reception delay window is obtained.

[0010] The first intermediate value of the receiving delay window is determined as the first target timing parameter;

[0011] Based on the second initial receive delay or the first target timing parameter, the second data transmission and reception test is performed by traversing the available range of the transmission delay. After traversing the available range of the transmission delay, the transmission delay window is obtained.

[0012] The second intermediate value of the transmission delay window is determined as the second target timing parameter; wherein, the first target timing parameter and the second target timing parameter are both timing parameters of the Ethernet interface between the MAC controller and the physical layer chip in the system-on-a-chip.

[0013] According to some embodiments of this application, when the target device is a physical layer chip, the physical layer chip is connected to the system-on-a-chip via an Ethernet interface;

[0014] Before setting the range of transmit delay values, the range of receive delay values, the first initial transmit delay, and the first initial receive delay of the Ethernet interface, the method further includes:

[0015] After initializing the MAC controller, a standard loopback test function is configured for the physical layer chip; the standard loopback test function is used to: respond to the test data sent by the system on-chip and return the test data as loopback data to the system on-chip.

[0016] According to some embodiments of this application, the first data transmission and reception test is performed by traversing the available range of the reception delay based on the second initial transmission delay or the second target timing parameters obtained through training. After traversing the available range of the reception delay, a reception delay window is obtained, including:

[0017] The first test data is sent to the physical layer chip according to the second initial transmission delay or the second target timing parameters obtained through training.

[0018] The physical layer chip receives the first feedback data in response to the first test data with the received delay to be tested; the received delay to be tested is within the available range of the received delay.

[0019] Compare and determine whether the first test data and the first returned data are consistent; if yes, confirm that the received delay under test has passed the test and record the received delay under test as an available received delay; if no, do not record the current received delay under test.

[0020] Based on the current receiver delay to be tested, determine whether the available range of receiver delay has been traversed. If not, determine the next receiver delay to be tested from the available range of receiver delay based on the current receiver delay to be tested and the preset traversal rules, so as to perform the next first data transmission and reception test. If yes, obtain a more accurate receiver delay window based on the recorded available receiver delay.

[0021] According to some embodiments of this application, the step of performing a second data transmission and reception test by traversing the available range of transmission delay based on the second initial reception delay or the first target timing parameter, and obtaining a transmission delay window after traversing the available range of transmission delay, includes:

[0022] The second test data is sent to the physical layer chip based on the transmission delay to be tested; the transmission delay to be tested is within the available range of the transmission delay.

[0023] The second return data returned by the physical layer chip in response to the second test data is received using the second initial reception delay or the first target timing parameter.

[0024] Compare and determine whether the second test data and the second return data are consistent; if yes, confirm that the transmission delay to be tested has passed the test and record the transmission delay to be tested as an available transmission delay; if no, do not record the current transmission delay to be tested.

[0025] Based on the current transmission delay to be tested, determine whether the available transmission delay range has been traversed. If not, then based on the current transmission delay to be tested and the preset traversal rules, determine the next transmission delay to be tested from the available transmission delay range to perform the next second data transmission and reception test. If yes, obtain a more accurate transmission delay window based on the recorded available transmission delay.

[0026] According to some embodiments of this application, when the target device is an Ethernet device, the Ethernet device is connected to the physical layer chip via a network cable;

[0027] Before setting the range of transmit delay values, the range of receive delay values, the first initial transmit delay, and the first initial receive delay of the Ethernet interface, the method further includes:

[0028] After initializing the MAC controller, a network link is established with the Ethernet device according to a preset thread.

[0029] According to some embodiments of this application, the first data transmission and reception test is performed by traversing the available range of the reception delay based on the second initial transmission delay or the second target timing parameters obtained through training. After traversing the available range of the reception delay, a reception delay window is obtained, including:

[0030] The physical layer chip receives a first test message sent by an Ethernet device with the receiver delay to be tested; wherein the receiver delay to be tested is within the available range of the receiver delay.

[0031] In response to the first test message, a first acknowledgment signal is returned to the Ethernet device through the physical layer chip according to the second initial transmission delay or the second target timing parameters obtained through training; and the receiving bandwidth statistics under the current receiving delay to be tested are calculated.

[0032] Based on the current receiver delay to be tested, determine whether the available range of receiver delays has been traversed. If not, based on the current receiver delay to be tested and the preset traversal rules, determine the next receiver delay to be tested from the available range of receiver delays to perform the next first data transmission and reception test. If yes, obtain the receiver bandwidth statistics corresponding to all receiver delays to be tested.

[0033] Based on the preset filtering rules, all the received bandwidth statistics and the corresponding received delay to be tested, the received delay window is determined from the available range of the received delay.

[0034] According to some embodiments of this application, the step of performing a second data transmission and reception test by traversing the available range of transmission delay based on the second initial reception delay or the first target timing parameter, and obtaining a transmission delay window after traversing the available range of transmission delay, includes:

[0035] Based on the transmission delay to be tested, a second test message is sent to the Ethernet device through the physical layer chip; the transmission delay to be tested is within the available range of the transmission delay.

[0036] Using the second initial receive delay or the first target timing parameter, the physical layer chip receives a second response signal returned by the Ethernet device in response to the second test message;

[0037] Calculate the transmission bandwidth statistics under the current transmission delay to be tested;

[0038] Based on the current transmission delay to be tested, determine whether the available transmission delay range has been traversed. If not, based on the current transmission delay to be tested and the preset traversal rules, determine the next transmission delay to be tested from the available transmission delay range to conduct the next second data transmission and reception test. If yes, obtain the transmission bandwidth statistics corresponding to all transmission delays to be tested.

[0039] Based on the preset filtering rules, all the transmitted bandwidth statistics and the corresponding transmitted delay to be tested, the transmitted delay window is determined from the available range of transmitted delay.

[0040] According to some embodiments of this application, the preset traversal rule is incremented by 1 or decremented by 1.

[0041] In a second aspect, embodiments of this application provide an electronic device, including at least one processor and a memory for communicatively connecting to the at least one processor; the memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enable the at least one processor to perform a timing parameter training method for an Ethernet interface as described in any of the embodiments of the first aspect.

[0042] Thirdly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions for causing a computer to perform a timing parameter training method for an Ethernet interface as described in any of the embodiments of the first aspect.

[0043] This application embodiment includes: a communication connection between a system-on-a-chip (SoC) and a target device; by utilizing the MAC controller in the SoC, firstly, setting the transmission delay range, reception delay range, first initial transmission delay, and first initial reception delay of the Ethernet interface; wherein, the first initial transmission delay belongs to the transmission delay range, and the first initial reception delay belongs to the reception delay range; secondly, performing a first timing training based on the transmission delay range and the first initial transmission delay to obtain the usable transmission delay range and the second initial transmission delay; performing a second timing training based on the reception delay range and the first initial reception delay to obtain the usable reception delay range and the second initial reception delay; then, based on the second initial transmission delay... The system uses a second target timing parameter obtained through training or by sending a delay. It then performs a first data transmission and reception test, traversing the available range of receive delays. After traversing the available range, a receive delay window is obtained. The first intermediate value of the receive delay window is then determined as the first target timing parameter. Next, based on the second initial receive delay or the first target timing parameter, a second data transmission and reception test is performed, traversing the available range of transmit delays. After traversing the available range of transmit delays, a transmit delay window is obtained. The second intermediate value of the transmit delay window is then determined as the second target timing parameter. Both the first and second target timing parameters are timing parameters of the Ethernet interface between the MAC controller and the physical layer chip in the on-chip system. This determines two timing parameters for the actual Ethernet interface adapted between the on-chip system and the physical layer chip. This embodiment of the application can obtain the timing parameters of the adapted Ethernet interface through training, thereby improving Ethernet throughput performance and operating efficiency. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a system architecture for performing a timing parameter training method for an Ethernet interface according to an embodiment of this application;

[0045] Figure 2 This is a schematic diagram of a first data transmission and reception test provided in one embodiment of this application when the target device is a physical layer chip;

[0046] Figure 3 This is a schematic diagram of a second data transmission and reception test provided in one embodiment of this application when the target device is an Ethernet device;

[0047] Figure 4 This is a flowchart illustrating a timing parameter training method for an Ethernet interface provided in one embodiment of this application;

[0048] Figure 5 This is a flowchart illustrating the first and second data transmission and reception tests performed when the target device is a physical layer chip.

[0049] Figure 6This is a flowchart illustrating the first and second data transmission and reception tests performed when the target device is an Ethernet device.

[0050] Figure 7 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments.

[0052] It should be noted that although a logical order is shown in the flowcharts in this application, in some cases, the steps shown or described may be performed in a different order than that shown in the flowcharts. In the description of this application, "several" means one or more, and "more" means two or more. The terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order in which the technical features are indicated.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0054] First, several terms used in this invention will be explained:

[0055] System on Chip, or SOC for short, is a system-on-a-chip.

[0056] TX_delay and RX_delay are two timing parameters. TX_delay refers to the transmission delay, used to determine when to send data. RX_delay refers to the reception delay, used to correct the timing of receiving data.

[0057] TCP (Transmission Control Protocol) is a connection-oriented, reliable, byte-stream-based transport layer communication protocol.

[0058] Loopback: Standard loopback test function. This refers to the function of sending electronic signals, data streams, etc., back to the sender intact.

[0059] MAC (Medium Access Control): Refers to the media access control layer below the link layer.

[0060] PHY (Port Physical Layer): Port physical layer.

[0061] In related technologies, there are several solutions for adding delay to clock signals: Solution 1 is to achieve delay through PCB traces, that is, to extend the clock signal traces and maintain a reasonable deviation between the clock and data trace lengths; Solution 2 is to achieve delay within the PHY chip, that is, to achieve clock and data delay through a pull-up or pull-down resistor on a certain pin of the PHY chip; Solution 3 is to achieve delay at the controller end, that is, through the delay register inside the controller. However, Solution 1 involves extending the clock line beyond the data line on the PCB to ensure phase accuracy between the clock and data, which inherently increases the difficulty of PCB layout. Furthermore, board-level routing may affect signal quality, and the increased routing length adds to PCB size and cost. Solution 2 uses the Ethernet PHY to implement clock and data delays, achieved by adding pull-up or pull-down resistors to a specific pin. While simple to implement, this increases BOM costs and has low tolerance for deviations introduced by chip design, manufacturing, process technology, and PCB routing, making it difficult to guarantee optimal performance across different Ethernet devices. Solution 3 configures the Ethernet controller's delay register, implementing delays during the verification phase by debugging a suitable timing parameter set in a driver based on a small number of chips. However, this requires re-tuning for chips with different designs, packages, and processes, increasing workload. All three methods require high costs to fix timing parameters for the same chip model; and when chips are mass-produced, process corners can introduce timing deviations. When timing deviations exist, chips may encounter critical timing conditions when performing read and write operations based on fixed timing parameters. This can lead to lower Ethernet throughput or malfunction in some batches of chips, thereby reducing operational efficiency. Therefore, determining the appropriate timing parameters for the Ethernet interface is a pressing issue that needs to be addressed.

[0062] Based on this, this application provides a timing parameter training method, electronic device, and computer-readable storage medium for an Ethernet interface. The method includes: timing training the initial parameters of the set Ethernet interface to obtain an available range of transmission delay, a second initial transmission delay, an available range of reception delay, and a second initial reception delay; based on the second initial transmission delay or the second target timing parameter obtained through training, performing a first data transmission and reception test by traversing the available range of reception delay, and obtaining a reception delay window after traversing the available range of reception delay; determining a first intermediate value of the reception delay window as a first target timing parameter; performing a second data transmission and reception test by traversing the available range of transmission delay based on the second initial reception delay or the first target timing parameter, and obtaining a transmission delay window after traversing the available range of transmission delay; and determining a second intermediate value of the transmission delay window as a second target timing parameter. This method can improve Ethernet throughput performance and working efficiency.

[0063] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0064] like Figure 1 As shown, the system framework includes a system-on-a-chip 100 and a target device 200, wherein the system-on-a-chip 100 is communicatively connected to the target device 200, and the system-on-a-chip 100 also includes a MAC controller 110.

[0065] The target device 200 is used in conjunction with the system-on-a-chip 100 to complete data transmission and reception tests.

[0066] MAC controller 110 is used to: set the transmit delay range, receive delay range, first initial transmit delay, and first initial receive delay of the Ethernet interface; wherein, the first initial transmit delay belongs to the transmit delay range, and the first initial receive delay belongs to the receive delay range; perform first timing training based on the transmit delay range and the first initial transmit delay to obtain the usable transmit delay range and the second initial transmit delay; perform second timing training based on the receive delay range and the first initial receive delay to obtain the usable receive delay range and the second initial receive delay; and perform second timing training based on the second initial transmit delay or the second target timing obtained through training. The timing parameters are used to perform a first data transmission and reception test by traversing the available range of receive delay. After traversing the available range of receive delay, a receive delay window is obtained. The first intermediate value of the receive delay window is determined as the first target timing parameter. Based on the second initial receive delay or the first target timing parameter, a second data transmission and reception test is performed by traversing the available range of transmit delay. After traversing the available range of transmit delay, a transmit delay window is obtained. The second intermediate value of the transmit delay window is determined as the second target timing parameter. Here, the first target timing parameter and the second target timing parameter are both timing parameters of the Ethernet interface between the MAC controller and the physical layer chip in the on-chip system.

[0067] According to the system framework provided in the embodiments of this application, a method for training the timing parameters of an Ethernet interface is realized through the cooperation between the MAC controller and the target device. The timing parameters of the Ethernet interface can be obtained through training, thereby improving Ethernet throughput performance and working efficiency.

[0068] According to some embodiments of this application, the target device 200 is a physical layer chip or an Ethernet device.

[0069] In one embodiment, such as Figure 2 As shown, when the target device 200 is a physical layer chip 210, the physical layer chip 210 is connected to the system-on-a-chip 100 via an Ethernet interface. Specifically, the Ethernet interface used to connect the physical layer chip 210 and the system-on-a-chip 100 can be: MII interface, RMII interface, GMII interface, RGMII interface, and SGMII interface, etc. This application does not impose specific restrictions on the type of Ethernet interface used to connect the physical layer chip 210 and the system-on-a-chip 100. In addition, the physical layer chip 210 has a standard function: loopback function, which can cooperate with the system-on-a-chip to perform timing training and obtain the parameter configuration of the Ethernet interface.

[0070] When the target device 200 is a physical layer chip 210, this embodiment of the application performs data transmission and reception tests during the Ethernet underlying driver initialization phase. By scanning the transmission and reception timing window of the Ethernet interface through a certain software strategy, the timing parameters of the Ethernet interface transmission and reception are automatically trained and adapted at the physical layer.

[0071] In one embodiment, such as Figure 3 As shown, when the target device 200 is an Ethernet device 220, the Ethernet device 220 communicates with the system-on-a-chip 100 through the physical layer chip 210, wherein the Ethernet device 220 and the physical layer chip 210 are connected via a network cable. Specifically, Figure 3 In this context, the network cable interface used to connect the Ethernet device 220 and the physical layer chip 210 is an RJ45 interface, and the Ethernet interface used to connect the physical layer chip 210 and the system-on-a-chip 100 can be: MII interface, RMII interface, GMII interface, RGMII interface, and SGMII interface, etc.

[0072] When the target device 200 is an Ethernet device 220, this embodiment of the application performs data transmission and reception tests during the application layer network transmission phase. By scanning the transmission and reception timing window, automatic training and adaptation of the timing parameters for Ethernet interface transmission and reception are achieved at the application layer. Timing window scanning and training are performed during the application layer network transmission phase. Timing training during the network transmission phase occurs after the System-on-Chip (SoC) establishes a network link with other Ethernet devices, accompanied by TCP packet transmission.

[0073] It is evident that the embodiments of this application can adapt to the diversity and complexity of Ethernet application scenarios, and the timing parameter training method of Ethernet interface at the physical layer and application layer ensures that the Ethernet interface has good timing parameter configuration when performing transmission, reception, reading and writing.

[0074] Those skilled in the art will understand that the system structure shown in the figures does not constitute a limitation on the embodiments of this application, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0075] It will be understood by those skilled in the art that the system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. It is known by those skilled in the art that with the evolution of system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0076] Based on the above system structure, various embodiments of the timing parameter training method for the Ethernet interface of this application are proposed below.

[0077] Firstly, such as Figure 4 As shown, this time series parameter training method can be applied to, for example... Figure 1 The MAC controller of the on-chip system shown is connected to the target device. The method may include, but is not limited to, steps S110 to S160.

[0078] Step S110: Set the range of transmit delay, the range of receive delay, the first initial transmit delay, and the first initial receive delay for the Ethernet interface; wherein, the first initial transmit delay belongs to the range of transmit delay values, and the first initial receive delay belongs to the range of receive delay values.

[0079] Step S120: Perform first timing training based on the transmission delay value range and the first initial transmission delay to obtain the available transmission delay range and the second initial transmission delay; perform second timing training based on the reception delay value range and the first initial reception delay to obtain the available reception delay range and the second initial reception delay.

[0080] Step S130: Based on the second initial transmission delay or the second target timing parameters obtained through training, perform the first data transmission and reception test by traversing the available range of reception delay. After traversing the available range of reception delay, obtain the reception delay window.

[0081] Step S140: Determine the first intermediate value of the receiving delay window as the first target timing parameter.

[0082] Step S150: Based on the second initial receive delay or the first target timing parameter, traverse the available range of transmit delay to perform the second data transmit and receive test. After traversing the available range of transmit delay, obtain the transmit delay window.

[0083] Step S160: Determine the second intermediate value of the transmission delay window as the second target timing parameter; wherein, the first target timing parameter and the second target timing parameter are both timing parameters of the Ethernet interface between the MAC controller and the physical layer chip in the on-chip system.

[0084] It should be noted that the target device is a physical layer chip or an Ethernet device.

[0085] It should be noted that the first timing training refers to: transmitting data with a first initial transmission delay, receiving data by traversing the range of receive delay values, and thus training from the range of receive delay values ​​to obtain a usable range of receive delays and a second initial receive delay that can be used for further timing training. The second timing training refers to: transmitting data by traversing the usable range of transmission delays, receiving data with the first initial receive delay, and thus training from the usable range of transmission delays to obtain a usable range of transmission delays and a second initial transmission delay that can be used for further timing training.

[0086] For example, specifically, it can be trained to have a transmit delay range of 0 to 7, a second initial transmit delay of 7, a receive delay range of 0 to 31, and a second initial receive delay of 31. It is important to emphasize that the second initial transmit delay can also be other values ​​within the available transmit delay range, such as an intermediate value or other values; similarly, the second initial receive delay can also be other values ​​within the available receive delay range, such as an intermediate value or other values. Therefore, this application does not impose specific restrictions on the second initial transmit delay or its value.

[0087] Therefore, through steps S110 to S120, after setting the initial parameters of the Ethernet interface (i.e., the range of transmit delay values, the range of receive delay values, the first initial transmit delay, and the first initial receive delay), the initial parameters undergo first timing training and second timing training, which can relatively quickly attempt to obtain the available range of transmit delay, the second initial transmit delay, the available range of receive delay, and the second initial receive delay; thus providing a data foundation for further timing training.

[0088] It is important to emphasize that in the overall timing training, steps S110 to S120 constitute the first stage of timing training, while steps S130 to S160 constitute the second stage. The usable range of receive delay and transmit delay obtained from the first stage of timing training can be defined as the result of fast and lightweight timing training; the second stage of timing training involves large amounts of data, or heavy-load timing training, resulting in more accurate transmit and receive delay windows.

[0089] It should be noted that in steps S110 to S160, after obtaining the optimal first target timing parameters for receiving through the first data transmission and reception test, the obtained first target timing parameters are applied to the timing training of the second data transmission and reception test to obtain the second target timing parameters for transmitting. It is understood that, alternatively, after obtaining the optimal second target timing parameters for transmitting through the training of the second data transmission and reception test, the obtained second target timing parameters can be applied to the timing training of the first data transmission and reception test to obtain the first target timing parameters for receiving. Therefore, this application does not impose specific restrictions on the order in which the first and second data transmission and reception tests are performed.

[0090] Through steps S110 to S160, the on-chip system establishes a communication connection with the target device. Utilizing the MAC controller within the on-chip system, firstly, the transmission delay range, reception delay range, first initial transmission delay, and first initial reception delay of the Ethernet interface are set; wherein, the first initial transmission delay belongs to the transmission delay range, and the first initial reception delay belongs to the reception delay range. Secondly, a first timing training is performed based on the transmission delay range and the first initial transmission delay to obtain the usable transmission delay range and the second initial transmission delay. A second timing training is performed based on the reception delay range and the first initial reception delay to obtain the usable reception delay range and the second initial reception delay. Then, based on the second... The initial transmit delay or the second target timing parameter obtained through training is used to traverse the available range of receive delay for a first data transmission and reception test. After traversing the available range of receive delay, a receive delay window is obtained. Then, the first intermediate value of the receive delay window is determined as the first target timing parameter. Next, based on the second initial receive delay or the first target timing parameter, the available range of transmit delay is traversed for a second data transmission and reception test. After traversing the available range of transmit delay, a transmit delay window is obtained. Then, the second intermediate value of the transmit delay window is determined as the second target timing parameter. Here, both the first target timing parameter and the second target timing parameter are timing parameters of the Ethernet interface between the MAC controller and the physical layer chip in the on-chip system. This determines two timing parameters of the actual Ethernet interface adapted between the on-chip system and the physical layer chip. This embodiment of the application can obtain the timing parameters of the adapted Ethernet interface through training, thereby improving Ethernet throughput performance and working efficiency.

[0091] According to some embodiments of this application, when the target device is a physical layer chip, the physical layer chip is connected to the system-on-a-chip (SoC) via an Ethernet interface. Before step S110, the method further includes: after initializing the MAC controller, configuring a standard loopback test function for the physical layer chip; the standard loopback test function is used to: in response to test data sent by the SoC, return the test data as loopback data to the SoC. This facilitates performing a first data transmission and reception test between the MAC controller and the physical layer chip through the configured standard loopback test function, thereby training and determining the timing parameters of the adapted Ethernet interface.

[0092] Combination Figure 2 and Figure 5 To further explain: the process of the first data transmission and reception test and the second data transmission and reception test when the target device is a physical layer chip.

[0093] According to some embodiments of this application, when the target device is a physical layer chip, step S130 includes, but is not limited to, the following steps.

[0094] Step S1301: Send the first test data to the physical layer chip according to the second initial transmission delay or the second target timing parameters obtained through training.

[0095] Step S1302: Receive the first backhaul data returned by the physical layer chip in response to the first test data with the receiver delay under test; the receiver delay under test is within the available range of receiver delay.

[0096] Step S1303: Compare and determine whether the first test data and the first returned data are consistent. If yes, proceed to step S1304; otherwise, proceed to step S1305.

[0097] Step S1304: Confirm that the received delay under test has passed the test, and record the received delay under test as the usable received delay.

[0098] Step S1305: Do not record the current receiver delay under test.

[0099] Step S1306: Determine whether the available range of reception delays has been traversed based on the current reception delay to be tested. If not, proceed to step S1307; if yes, proceed to step S1308.

[0100] Step S1307: Based on the current receiver delay to be tested and the preset traversal rules, determine the next receiver delay to be tested from the available range of receiver delay, so as to conduct the next first data transmission and reception test.

[0101] If so, step S1308: Obtain a more accurate reception delay window based on the recorded available reception delay.

[0102] Understandably, the second initial transmission delay or the second target timing parameter obtained through training determines the timing of data transmission, while the receiver delay to be tested determines the timing of data reception.

[0103] Understandably, when executing step S1307, based on the preset traversal rules, if the available range of receiving delay has not been completely traversed, the receiving delay to be tested is increased by 1 or decreased by 1 according to the current receiving delay to be tested, to obtain the receiving delay to be tested for the next first data transmission and reception test. For example, if the available range of receiving delay is 0 to 31, if the available range of receiving delay has not been completely traversed, the currently used receiving delay to be tested (31) is decreased by 1, and the receiving delay to be tested to be tested for the next time is determined to be 30; and so on until the available range of receiving delay is traversed. It should be emphasized that when traversing the available range of receiving delay, it is possible to traverse from the middle value of the available range of receiving delay towards both ends, or it is possible to traverse from one end of the available range of receiving delay to the other end. Therefore, this application does not impose specific restrictions on the preset traversal rules, that is, on the method of traversing the available range of receiving delay.

[0104] Through steps S1301 to S1308, the MAC controller sends first test data to the physical layer chip based on the second initial transmission delay or the second target timing parameters obtained through training. After receiving the first test data, the physical layer chip returns first return data to the MAC controller. After receiving the first return data with the receiver delay to be tested, if the first test data and the first return data are consistent, it is determined that the receiver delay to be tested has passed the test and is recorded as an available receiver delay. If they are inconsistent, it is determined that the receiver delay to be tested has failed the test, and the current receiver delay to be tested is not recorded. Then, the next receiver delay to be tested is determined in an orderly manner for the first data transmission and reception test. In this way, the available range of receiver delays is traversed in an orderly manner between the MAC controller and the physical layer chip to perform the first data transmission and reception test, obtaining a receiver delay window with better data transmission and reception performance, laying a data foundation for further determination of the first target timing parameters.

[0105] According to some embodiments of this application, when the target device is a physical layer chip, step S150 includes, but is not limited to, the following steps.

[0106] Step S1501: Send the second test data to the physical layer chip according to the transmission delay to be tested; the transmission delay to be tested is within the available range of transmission delay.

[0107] Step S1502: Receive the second backhaul data returned by the physical layer chip in response to the second test data, using the second initial reception delay or the first target timing parameter.

[0108] Step S1503: Compare and determine whether the second test data and the second returned data are consistent. If yes, proceed to step S1504; otherwise, proceed to step S1505.

[0109] Step S1504: Confirm that the transmission delay under test has passed the test, and record the transmission delay under test as an available transmission delay.

[0110] Step S1505: Do not record the current transmission delay to be tested.

[0111] Step S1506: Determine whether the available transmission delay range has been traversed based on the current transmission delay to be tested. If not, proceed to step S1507; if yes, proceed to step S1508.

[0112] Step S1507: Based on the current transmission delay to be tested and the preset traversal rules, determine the next transmission delay to be tested from the available range of transmission delay, so as to conduct the next second data transmission and reception test.

[0113] Step S1508: Obtain a more accurate transmission delay window based on the recorded available transmission delay.

[0114] Understandably, the transmit delay to be tested determines the timing of data transmission, while the second initial receive delay or the first target timing parameter determines the timing of data reception.

[0115] Understandably, when executing S1507, based on the preset traversal rules, if the available range of transmission delays has not been completely traversed, the transmission delay to be tested is increased or decreased by 1 based on the current transmission delay to be tested, to obtain the transmission delay to be tested for the next second data transmission and reception test. For example, if the available range of transmission delays is 0 to 7, if the available range of transmission delays has not been completely traversed, the current transmission delay to be tested, 7, is subtracted by 1, determining the next transmission delay to be tested to be 6; and so on, then the second data transmission and reception test will be performed sequentially based on transmission delays of 5, 4, 3, 2, 1, and 0, until the available range of reception delays has been traversed. It should be emphasized that when traversing the available range of transmission delays, it is possible to traverse from the middle value of the available range of transmission delays towards both ends, or it is possible to traverse from one end of the available range of transmission delays to the other end. Therefore, this application does not impose specific restrictions on the preset traversal rules, that is, on the method of traversing the available range of transmission delays.

[0116] By sequentially traversing the available transmission delay range through steps S1501 to S1508, a transmission delay window with better data transmission and reception performance can be obtained, laying a data foundation for further determining the timing parameters of the second target.

[0117] According to some embodiments of this application, when the target device is an Ethernet device, the Ethernet device and the physical layer chip are connected via a network cable; before step S110, the method further includes: after initializing the MAC controller, establishing a network link with the Ethernet device according to a preset thread. This facilitates performing a second data transmission and reception test between the MAC controller and the Ethernet device through the established network link and the physical layer chip, thereby training and determining the timing parameters of the adapted Ethernet interface.

[0118] Combination Figure 3 and Figure 6 To further explain: the process of the first data transmission and reception test and the second data transmission and reception test when the target device is an Ethernet device.

[0119] According to some embodiments of this application, when the target device is an Ethernet device... Figure 4 Step S130 in the process also includes, but is not limited to, the following steps.

[0120] Step S1309: With the reception delay to be tested, receive the first test message sent by the Ethernet device through the physical layer chip; wherein the reception delay to be tested is within the available range of reception delay.

[0121] Step S1310: In response to the first test message, return a first response signal to the Ethernet device through the physical layer chip according to the second initial transmission delay or the second target timing parameters obtained through training.

[0122] Step S1311: Calculate the statistical value of the receiving bandwidth under the current receiving delay to be tested.

[0123] Step S1312: Determine whether the available range of receiving delays has been traversed based on the current receiving delay to be tested; if not, proceed to step S1313; if yes, proceed to step S1314.

[0124] Step S1313: Based on the current receiver delay to be tested and the preset traversal rules, determine the next receiver delay to be tested from the available range of receiver delays, so as to conduct the next first data transmission and reception test.

[0125] Step S1314: Obtain the statistical values ​​of the receiving bandwidth corresponding to all the receiving delays to be tested.

[0126] Step S1315: Determine the receiving delay window from the available range of receiving delay based on the preset filtering rules, all receiving bandwidth statistics and the corresponding receiving delay to be tested.

[0127] Understandably, the first test message can be a TCP message.

[0128] Understandably, the preset traversal rule means that, in the case that the available range of receiving delay has not been traversed, the receiving delay to be tested is increased by 1 or decreased by 1 based on the current receiving delay to be tested, so as to obtain the receiving delay to be tested for the next first data transmission and reception test.

[0129] It is understandable that when the received delay to be tested is not compatible, the received bandwidth statistics may be poor. Therefore, in step S1315, the preset filtering rule means that the received bandwidth statistics corresponding to each received delay to be tested can be used to determine whether the received delay to be tested is compatible; a high received bandwidth statistics value indicates that the corresponding received delay to be tested is compatible; otherwise, it is not compatible. For example, after traversing the available range of received delay from 0 to 31, if the received bandwidth statistics corresponding to the received delay to be tested from 0 to 10 are found to be low, then it is further determined that the timing range from 0 to 10 in the available range of received delay is not compatible; if the received bandwidth statistics corresponding to the received delay to be tested from 10 to 25 are stable and high, and the received bandwidth statistics corresponding to the received delay to be tested from 10 to 25 are low, then it can be comprehensively determined that the timing range from 26 to 31 in the available range of received delay is compatible, and the timing range from 26 to 31 is determined as the received delay window. It is understandable that this is just an example to aid understanding, and the specific value of the receive delay window will be determined by the actual timing training results.

[0130] Through steps S1309 to S1315, the available range of receiving delay is systematically traversed between the MAC controller and the Ethernet device to conduct the first data transmission and reception test, thereby obtaining the receiving delay window with better data transmission and reception performance, laying the data foundation for further determination of the first target timing parameters.

[0131] According to some embodiments of this application, when the target device is an Ethernet device... Figure 4 Step S150 in the process also includes, but is not limited to, the following steps.

[0132] Step S1509: Send a second test message to the Ethernet device through the physical layer chip according to the transmission delay to be tested; the transmission delay to be tested is within the available transmission delay range.

[0133] Step S1510: Using the second initial receive delay or the first target timing parameters, the physical layer chip receives the second response signal returned by the Ethernet device in response to the second test message.

[0134] Step S1511: Calculate the transmission bandwidth statistics under the current transmission delay to be tested.

[0135] Step S1512: Determine whether the available transmission delay range has been traversed based on the current transmission delay to be tested. If not, proceed to step S1513; if yes, proceed to step S1514.

[0136] Step S1513: Based on the current transmission delay to be tested and the preset traversal rules, determine the next transmission delay to be tested from the available range of transmission delay, so as to conduct the next second data transmission and reception test.

[0137] Step S1514: Obtain the transmission bandwidth statistics corresponding to all the transmission delays to be tested.

[0138] Step S1515: Based on the preset filtering rules, all transmission bandwidth statistics and the corresponding transmission delay to be tested, determine the transmission delay window from the available transmission delay range.

[0139] Understandably, the second test message could be a TCP message.

[0140] Understandably, the preset traversal rule means that, if the available range of transmission delay has not been traversed, the transmission delay to be tested is increased by 1 or decreased by 1 based on the current transmission delay to be tested, so as to obtain the transmission delay to be tested for the next second data transmission and reception test.

[0141] It is understandable that when the transmission delay to be tested is not suitable, it may lead to a poor transmission bandwidth statistics value. Therefore, in step S1515, the preset filtering rule means that the transmission bandwidth statistics value corresponding to each transmission delay to be tested can be used to determine whether the transmission delay to be tested is suitable; a high transmission bandwidth statistics value indicates that the corresponding transmission delay to be tested is suitable; otherwise, it is not suitable. For example, after traversing the available transmission delay range, if the transmission bandwidth statistics value corresponding to the transmission delay to be tested is low when it is 0, 1, or 2, then it is further determined that the timing range from 0 to 2 in the available transmission delay range is not suitable; if the transmission bandwidth statistics value corresponding to the transmission delay to be tested is stable and high when it is 3, 4, or 5, and the transmission bandwidth statistics value corresponding to the transmission delay to be tested is low when it is 6 or 7, then it can be comprehensively determined that the timing range from 3 to 5 in the available transmission delay range is suitable, and the timing range from 3 to 5 is determined as the transmission delay window. It is understood that this is only an example to help with understanding, and the specific value of the transmission delay window will be determined by the actual timing training results.

[0142] Through steps S1509 to S1515, the second data transmission and reception test is carried out by traversing the available transmission delay range between the MAC controller and the Ethernet device in an orderly manner, and the transmission delay window with better data transmission and reception effect is obtained, laying the data foundation for further determination of the second target timing parameters.

[0143] According to some embodiments of this application, the preset traversal rule is to increment by 1 or decrement by 1. This facilitates the orderly and complete traversal of the available transmission delay range and the available reception delay range.

[0144] According to some embodiments of this application, step S140 is further described as follows: the first intermediate value of the receive delay window is determined as the first target timing parameter. Specifically, if the received delay window is [27, 31]; the first intermediate value of the received delay window is calculated to be (27+31) / 2 = 29; then the first intermediate value 29 is determined as the first target timing parameter. Thus, a suitable first target timing parameter is determined, thereby ensuring that the Ethernet interface can be configured to receive data based on good and suitable timing parameters, improving the efficiency of data reception.

[0145] According to some embodiments of this application, step S160 is further described as follows: the second intermediate value of the transmission delay window is determined as the second target timing parameter. Specifically, if the transmission delay window is [3, 7]; the second intermediate value of the transmission delay window is calculated to be (3+7) / 2 = 5; then the second intermediate value 5 is determined as the second target timing parameter. In this way, a suitable second target timing parameter is determined, thereby ensuring that the Ethernet interface can transmit data based on a good and suitable timing parameter configuration, improving the efficiency of data transmission.

[0146] For example, combined withFigure 2 In the case that the target device is a physical layer chip, briefly describe the overall process of the timing parameter training method.

[0147] First, initialize the Ethernet MAC controller.

[0148] Secondly, the physical layer chip is configured with loopback functionality.

[0149] Next, set the range of transmit delay, the range of receive delay, the first initial transmit delay, and the first initial receive delay for the Ethernet interface.

[0150] Furthermore, a first stage of timing training is performed on the ranges of transmission delay, reception delay, the first initial transmission delay, and the first initial reception delay to obtain more accurate ranges for transmission delay TX_delay, reception delay RX_delay, and initial values ​​for transmission delay TX_delay and reception delay RX_delay. Then, a second stage of timing training is performed as described below:

[0151] Then, the receive delay RX_delay is iterated step by step, and data TX_DATA is sent to the Ethernet PHY based on the initial value of the transmit delay TX_delay. Data RX_DATA returned by the Ethernet PHY is received based on the receive delay RX_delay.

[0152] Then, the transmitted data TX_DATA is compared with the received data RX_DATA. If they match, RX_delay is recorded. After traversing all the data, the available RX_delay window is obtained.

[0153] Then, select the middle value of the available RX_delay window to set the receive delay parameter.

[0154] Next, the transmission delay TX_delay is iterated step by step, and data TX_DATA is sent to the Ethernet PHY based on the transmission delay TX_delay. Data RX_DATA returned by the Ethernet PHY is received based on the set reception delay.

[0155] Then, the transmitted data TX_DATA is compared with the received data RX_DATA. If they match, TX_delay is recorded. After traversing all the data, the available TX_delay window is obtained.

[0156] Finally, select the middle value of the available TX_delay window to set the transmission delay parameter. This completes the training of the timing parameters for the Ethernet interface.

[0157] As can be seen, the embodiments of this application add a clock signal delay at the MAC controller end and utilize the standard loopback test function of the Ethernet PHY to scan the window of Ethernet interface read and write timings through a certain software strategy during the Ethernet underlying driver initialization phase, thereby realizing the automatic training and adaptation of Ethernet interface read and write timings.

[0158] Furthermore, considering the diversity and complexity of Ethernet product application scenarios, when the use of Ethernet PHY loopback function is restricted, refer to Figure 3 Timing window scanning and training are performed during the application layer network transmission phase. Timing training during the network transmission phase occurs after the system-on-a-chip (SoC) establishes a network link with other Ethernet devices, accompanied by TCP packet transmission.

[0159] It should be emphasized that the timing parameter training method provided in this application has been implemented and verified on actual equipment, proving that the Ethernet interface read / write timings of chips with different process corners have sufficient margin and are feasible. It has also been implemented on Ethernet chips using GMAC IP.

[0160] In summary, addressing the issue of phase discrepancies between Ethernet interface clock and data lines introduced by different chips, packages, and batches in design, manufacturing, and processes, and the significant challenges in board-level Ethernet layout design, the timing parameter training method proposed in this application utilizes the delay register within the Ethernet controller to add a delay at the MAC end. Through multiple Ethernet transmit / receive read / write training operations, the read / write timing window of each chip's Ethernet interface is identified. Then, the intermediate timing parameters within the timing window are selected as the final configuration, achieving automatic training and adaptation of the Ethernet interface's timing parameters. This ensures sufficient margin for the read / write timing of each chip's Ethernet interface. Furthermore, it reduces solution costs and improves work efficiency while ensuring Ethernet performance. Additionally, considering the diversity and complexity of Ethernet application scenarios, the timing parameter training method of this invention can be flexibly applied at both the chip's Ethernet driver layer and the application layer, making it suitable for a wide range of applications.

[0161] Secondly, such as Figure 7 As shown, the present invention also provides an electronic device 600, comprising:

[0162] The processor 601 can be implemented using a general-purpose central processing unit, microprocessor, application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0163] The memory 602 can be implemented as a read-only memory, static storage device, dynamic storage device, or random access memory. The memory 602 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 602 and is called by the processor 601 to execute the timing parameter training method for the Ethernet interface of the embodiments of this application.

[0164] The input / output interface 603 is used to implement information input and output;

[0165] The communication interface 604 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0166] Bus 605 transmits information between various components of the device (e.g., processor 601, memory 602, input / output interface 603, and communication interface 604);

[0167] The processor 601, memory 602, input / output interface 603, and communication interface 604 are connected to each other within the device via bus 605.

[0168] Thirdly, embodiments of this application also provide a storage medium, which is a computer-readable storage medium storing a computer program that, when executed by a processor, implements the timing parameter training method for the Ethernet interface described above.

[0169] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0170] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0171] The above provides a detailed description of the preferred embodiments of this application. However, this application is not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by this application.

Claims

1. A method for training timing parameters of an Ethernet interface, characterized in that, A MAC controller is applied in a system-on-a-chip, wherein the system-on-a-chip is communicatively connected to the target device; The method includes: Configure the transmit delay range, receive delay range, first initial transmit delay, and first initial receive delay for the Ethernet interface; wherein, the first initial transmit delay belongs to the transmit delay range, and the first initial receive delay belongs to the receive delay range; Based on the range of transmission delay values ​​and the first initial transmission delay, a first timing training is performed to obtain the usable range of transmission delay and the second initial transmission delay; based on the range of reception delay values ​​and the first initial reception delay, a second timing training is performed to obtain the usable range of reception delay and the second initial reception delay. Based on the second initial transmission delay or the second target timing parameters obtained through training, the first data transmission and reception test is performed by traversing the available range of the reception delay. After traversing the available range of the reception delay, the reception delay window is obtained. The first intermediate value of the receiving delay window is determined as the first target timing parameter; Based on the second initial receive delay or the first target timing parameter, the second data transmission and reception test is performed by traversing the available range of the transmission delay. After traversing the available range of the transmission delay, the transmission delay window is obtained. The second intermediate value of the transmission delay window is determined as the second target timing parameter; wherein, the first target timing parameter and the second target timing parameter are both timing parameters of the Ethernet interface between the MAC controller and the physical layer chip in the system-on-a-chip.

2. The time-series parameter training method according to claim 1, characterized in that, When the target device is a physical layer chip, the physical layer chip is connected to the system-on-a-chip via an Ethernet interface; Before setting the range of transmit delay values, the range of receive delay values, the first initial transmit delay, and the first initial receive delay of the Ethernet interface, the method further includes: After initializing the MAC controller, a standard loopback test function is configured for the physical layer chip; the standard loopback test function is used to: respond to the test data sent by the system on-chip and return the test data as loopback data to the system on-chip.

3. The time-series parameter training method according to claim 2, characterized in that, The first data transmission and reception test is performed by traversing the available range of the reception delay based on the second initial transmission delay or the second target timing parameters obtained through training. After traversing the available range of the reception delay, a reception delay window is obtained, including: The first test data is sent to the physical layer chip according to the second initial transmission delay or the second target timing parameters obtained through training. The physical layer chip receives the first feedback data in response to the first test data with the received delay to be tested; the received delay to be tested is within the available range of the received delay. Compare and determine whether the first test data and the first returned data are consistent; if yes, confirm that the received delay under test has passed the test and record the received delay under test as an available received delay; if no, do not record the current received delay under test. Based on the current receiver delay to be tested, determine whether the available range of receiver delay has been traversed. If not, determine the next receiver delay to be tested from the available range of receiver delay based on the current receiver delay to be tested and the preset traversal rules, so as to perform the next first data transmission and reception test. If yes, obtain a more accurate receiver delay window based on the recorded available receiver delay.

4. The time-series parameter training method according to claim 2, characterized in that, The second data transmission and reception test is performed by traversing the available range of transmission delay based on the second initial reception delay or the first target timing parameter. After traversing the available range of transmission delay, a transmission delay window is obtained, including: The second test data is sent to the physical layer chip based on the transmission delay to be tested; the transmission delay to be tested is within the available range of the transmission delay. The second return data returned by the physical layer chip in response to the second test data is received using the second initial reception delay or the first target timing parameter. Compare and determine whether the second test data and the second return data are consistent; if yes, confirm that the transmission delay to be tested has passed the test and record the transmission delay to be tested as an available transmission delay; if no, do not record the current transmission delay to be tested. Based on the current transmission delay to be tested, determine whether the available transmission delay range has been traversed. If not, then based on the current transmission delay to be tested and the preset traversal rules, determine the next transmission delay to be tested from the available transmission delay range to perform the next second data transmission and reception test. If yes, obtain a more accurate transmission delay window based on the recorded available transmission delay.

5. The time-series parameter training method according to claim 1, characterized in that, If the target device is an Ethernet device, the Ethernet device is connected to the physical layer chip via a network cable; Before setting the range of transmit delay values, the range of receive delay values, the first initial transmit delay, and the first initial receive delay of the Ethernet interface, the method further includes: After initializing the MAC controller, a network link is established with the Ethernet device according to a preset thread.

6. The time-series parameter training method according to claim 5, characterized in that, The first data transmission and reception test is performed by traversing the available range of the reception delay based on the second initial transmission delay or the second target timing parameters obtained through training. After traversing the available range of the reception delay, a reception delay window is obtained, including: The physical layer chip receives a first test message sent by an Ethernet device with the receiver delay to be tested; wherein the receiver delay to be tested is within the available range of the receiver delay. In response to the first test message, a first acknowledgment signal is returned to the Ethernet device through the physical layer chip according to the second initial transmission delay or the second target timing parameters obtained through training; and the receiving bandwidth statistics under the current receiving delay to be tested are calculated. Based on the current receiver delay to be tested, determine whether the available range of receiver delays has been traversed. If not, based on the current receiver delay to be tested and the preset traversal rules, determine the next receiver delay to be tested from the available range of receiver delays to perform the next first data transmission and reception test. If yes, obtain the receiver bandwidth statistics corresponding to all receiver delays to be tested. Based on the preset filtering rules, all the received bandwidth statistics and the corresponding received delay to be tested, the received delay window is determined from the available range of the received delay.

7. The time-series parameter training method according to claim 5, characterized in that, The second data transmission and reception test is performed by traversing the available range of transmission delay based on the second initial reception delay or the first target timing parameter. After traversing the available range of transmission delay, a transmission delay window is obtained, including: Based on the transmission delay to be tested, a second test message is sent to the Ethernet device through the physical layer chip; the transmission delay to be tested is within the available range of the transmission delay. Using the second initial receive delay or the first target timing parameter, the physical layer chip receives a second response signal returned by the Ethernet device in response to the second test message; Calculate the transmission bandwidth statistics under the current transmission delay to be tested; Based on the current transmission delay to be tested, determine whether the available transmission delay range has been traversed. If not, based on the current transmission delay to be tested and the preset traversal rules, determine the next transmission delay to be tested from the available transmission delay range to conduct the next second data transmission and reception test. If yes, obtain the transmission bandwidth statistics corresponding to all transmission delays to be tested. Based on the preset filtering rules, all the transmitted bandwidth statistics and the corresponding transmitted delay to be tested, the transmitted delay window is determined from the available range of transmitted delay.

8. The time-series parameter training method according to any one of claims 3, 4, 6, or 7, characterized in that, The preset traversal rule is to increment by 1 or decrement by 1.

9. An electronic device, characterized in that, It includes at least one processor and a memory for communicatively connecting to the at least one processor; the memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enable the at least one processor to perform a timing parameter training method for an Ethernet interface as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the timing parameter training method for an Ethernet interface as described in any one of claims 1 to 8.

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