Equipment interconnection and bidirectional control system and method based on single GPIO (General Purpose Input / Output) line

Abstract

The invention provides an equipment interconnection and bidirectional control system and method based on a single GPIO (General Purpose Input / Output) line. The system comprises host equipment, external equipment and the single GPIO line, the host equipment and the external equipment are interconnected through a single GPIO (General Purpose Input / Output) line; the GPIO line is used for transmitting a control signal; the control signal is a reset signal or an interrupt signal, and the external device is used for executing a reset operation based on the reset signal; and the host equipment is used for calling a corresponding interrupt processing program based on the interrupt signal. According to the invention, the number of interconnection signal lines between devices is reduced, the internal interface interconnection space of the server is saved, the design and layout of the server are simplified, the integration level and performance of the server are improved, and the cost and maintenance difficulty are reduced; the method has stability and reliability, and can meet the performance and compatibility requirements of a high-density server.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, and particularly relates to a device interconnection and two-way control system and method based on a single General Purpose Input / Output (GPIO) line. Background Art

[0002] With the continuous increase in the density of server devices, the requirements for the overall design are becoming more and more miniaturized. In this case, the space for internal interface interconnection of servers is becoming increasingly limited. Currently, in addition to high-speed signal lines, General Purpose Input / Output (GPIO) pins are the most commonly used interconnection method. Servers can transmit data with other external devices through GPIO pins to send and receive control signals.

[0003] In traditional server designs, in order to achieve two-way control, usually two independent signal lines are required to transmit control signals, and each signal line transmits one type of control signal. However, this method will occupy a large amount of resources in the case of limited internal interface interconnection space of servers and cannot meet the requirements of high-density server devices.

[0004] Therefore, how to save the number of interface interconnection lines in a compact space such as server devices has become an urgent technical problem for those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a device interconnection and two-way control system and method based on a single GPIO line, which is used to save the number of interface interconnection lines in a compact space such as server devices.

[0006] In a first aspect, this application provides a device interconnection and two-way control system based on a single GPIO line, including a host device, an external device, and a single GPIO line;

[0007] The single GPIO line is used to connect the host device and the external device and transmit control signals between the host device and the external device; the control signal is a reset signal or an interrupt signal, where the reset signal is sent from the host device to the external device, and the interrupt signal is sent from the external device to the host device;

[0008] The external device is used to perform a reset operation based on the reset signal after receiving the reset signal;

[0009] The host device is used to call a corresponding interrupt handling program based on the interrupt signal after receiving the interrupt signal.

[0010] In an implementation of the first aspect, the reset signal includes a host reset signal and a device reset signal, and the interrupt signal includes a device interrupt signal and a host interrupt signal.

[0011] In an implementation of the first aspect, the host device includes a baseboard management controller;

[0012] The baseboard management controller is provided with a first host port and a second host port, wherein the first host port is used to receive the host interrupt signal, and the second host port is used to output the host reset signal.

[0013] In an implementation of the first aspect, the external device includes a microcontroller unit;

[0014] The microcontroller unit is provided with a first device port and a second device port, wherein the first device port is used to receive the device reset signal, and the second device port is used to output the device interrupt signal.

[0015] In an implementation of the first aspect, the host device further includes a first conversion module, and the external device further includes a second conversion module;

[0016] The first conversion module is connected to the baseboard management controller, the second conversion module is connected to the microcontroller unit, and the first conversion module and the second conversion module are connected by a single GPIO line, and are used to convert the host reset signal into the device reset signal, or convert the device interrupt signal into the host interrupt signal.

[0017] In an implementation of the first aspect, the first conversion module includes a first voltage comparator, a first resistor, a second resistor and a first switching tube;

[0018] The positive input terminal of the first voltage comparator is connected to a first reference voltage, the negative input terminal is connected to the source electrode of the first switching tube, and the output terminal is connected to the first host port;

[0019] The gate of the first switching tube is connected to the second host port, and the drain is grounded;

[0020] One end of the first resistor is connected to the power supply voltage, the other end is connected to one end of the second resistor, and the connection point is respectively connected to the negative terminal of the first voltage comparator and the second converter;

[0021] The other end of the second resistor is grounded.

[0022] In an implementation of the first aspect, the second conversion module includes a second voltage comparator, a third resistor and a second switching tube;

[0023] The inverting input terminal of the second voltage comparator is connected to a second reference voltage, the non-inverting input terminal is respectively connected to one end of the third resistor and the first converter, and the output terminal is connected to the first device port;

[0024] The other end of the third resistor is connected to the source electrode of the second switching transistor;

[0025] The gate electrode of the second switching transistor is connected to the second device port, and the drain electrode is grounded.

[0026] In an implementation manner of the first aspect, the first converter and the second converter converting the host reset signal into the device reset signal includes:

[0027] When the second host port outputs the host reset signal, the first switching transistor switches from the off state to the on state, so that the voltage at the non-inverting terminal of the second voltage comparator is 0, the voltage at the inverting terminal is greater than the voltage at the non-inverting terminal, and the output terminal outputs the device reset signal; the voltage at the inverting terminal of the first voltage comparator is 0, the first reference voltage at the non-inverting terminal is greater than the voltage at the inverting terminal of the first voltage comparator, and the output terminal outputs the host interrupt signal.

[0028] In an implementation manner of the first aspect, the first converter and the second converter converting the device interrupt signal into the host interrupt signal includes:

[0029] When the second device port outputs the device interrupt signal, the second switching transistor switches from the off state to the on state; the power supply voltage is divided by using the connection relationship of the second resistor and the third resistor in parallel and then in series with the first resistor, so that the voltage at the inverting terminal of the first voltage comparator is less than the first reference voltage at the non-inverting terminal, and the output terminal outputs the host interrupt signal; the voltage at the non-inverting terminal of the second voltage comparator is greater than the second reference voltage at the inverting terminal, and the output terminal outputs a high level.

[0030] In a second aspect, the present application provides a device interconnection and bidirectional control method based on a single GPIO line, including:

[0031] Connecting a host device and an external device by using a single GPIO line, and transmitting a control signal between the host device and the external device; the control signal is a reset signal or an interrupt signal, wherein the reset signal is sent from the host device to the external device, and the interrupt signal is sent from the external device to the host device;

[0032] After receiving the reset signal, the external device performs a reset operation based on the reset signal;

[0033] After receiving the interrupt signal, the host device calls a corresponding interrupt handler based on the interrupt signal.

[0034] As described above, the device interconnection and bidirectional control system and method based on a single GPIO line according to the present application have the following beneficial effects:

[0035] (1) By combining multiple GPIO signal lines, the number of interconnection signal lines between devices is reduced, saving the internal interface interconnection space of the server, simplifying the design and layout of the server, improving the integration and performance of the server, and reducing costs and maintenance difficulties;

[0036] (2) It has stability and reliability and can meet the performance and compatibility requirements of high-density servers. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It shows a schematic structural diagram of the device interconnection and bidirectional control system based on a single GPIO line according to the present application in an embodiment.

[0038] Figure 2 It shows a schematic structural diagram of the device interconnection and bidirectional control system based on a single GPIO line according to the present application in another embodiment.

[0039] Figure 3 It shows a schematic circuit diagram of the device interconnection and bidirectional control system based on a single GPIO line according to the present application in an embodiment.

[0040] Figure 4 It shows a schematic circuit diagram of the device interconnection and bidirectional control system based on a single GPIO line according to the present application in another embodiment.

[0041] Figure 5 It shows a flowchart of the device interconnection and bidirectional control method based on a single GPIO line according to the present application in an embodiment.

[0042] DESCRIPTION OF REFERENCE NUMERALS

[0043] 11 Host device

[0044] 111 Baseboard Management Controller

[0045] 112 First conversion module

[0046] 12 External device

[0047] 121 Microcontroller

[0048] 122 Second conversion module

[0049] 13 Single GPIO line

[0050] Steps S1 to S3 Detailed implementation manners

[0051] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0052] It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0053] In addition, in the present application, descriptions such as "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that those skilled in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0054] The following embodiments of the present application provide a device interconnection and two-way control system and method based on a single GPIO line, which can be applied to any application that uses a single GPIO to achieve two-way control. Taking a server as an example below, the technical solutions in the embodiments of the present application will be described in detail with reference to the accompanying drawings in the embodiments of the present application.

[0055] Please refer to Figure 1 , which shows a schematic structural diagram of the device interconnection and two-way control system based on a single GPIO line of the present application in an embodiment.

[0056] As Figure 1 shown, this embodiment provides a device interconnection and two-way control system based on a single GPIO line, including a host device, an external device, and a single GPIO line.

[0057] The single GPIO line is used to connect the host device and the external device and transmit control signals between the host device and the external device.

[0058] In the embodiments of the present application, the single GPIO line is respectively connected to the GPIO pins on the host device and the external device. The GPIO pin is a general digital input / output interface, which can be configured as an input or output mode and transmits information by obtaining the level state (high level or low level).

[0059] The control signal is a reset signal or an interrupt signal, where the reset signal is sent from the host device to the external device, and the interrupt signal is sent from the external device to the host device.

[0060] The external device is used to perform a reset operation based on the reset signal after receiving the reset signal.

[0061] Specifically, the external device can be a hard disk controller or a network adapter, etc. The external device includes a microcontroller unit (MCU). The MCU is a chip integrating a processor, a memory, an input / output interface, and other peripherals, which can operate independently and has the ability to process and execute tasks.

[0062] In the embodiments of the present application, a first device port (Device_GPIO1) and a second device port (Device_GPIO2) are provided on the microcontroller unit. Both the first device port (Device_GPIO1) and the second device port (Device_GPIO2) are general input / output interfaces. The first device port (Device_GPIO1) is used to receive the device reset signal, and the second device port (Device_GPIO2) is used to output the device interrupt signal.

[0063] The host device is used to call a corresponding interrupt handling program based on the interrupt signal after receiving the interrupt signal.

[0064] Specifically, the host device is usually a computer or an embedded system. In this embodiment, the host device is a server host. The host device includes a board management controller (BMC). The BMC is a separate ARM chip integrated on the motherboard of the server or computer, and is used to implement functions such as server remote control management, device information management, server status interface management, and maintenance management.

[0065] In an embodiment of the present application, a first host port (Host_GPIO1) and a second host port (Host_GPIO2) are provided on the baseboard management controller. Both the first host port (Host_GPIO1) and the second host port (Host_GPIO2) are general-purpose input / output interfaces. The first host port (Host_GPIO1) is used to receive the host interrupt signal, and the second host port (Host_GPIO2) is used to output the host reset signal.

[0066] Please refer to Figure 2 , which shows a schematic structural diagram of the device interconnection and bidirectional control system based on a single GPIO line of the present application in another embodiment.

[0067] As Figure 2 shown, the host device further includes a first conversion module, and the external device further includes a second conversion module.

[0068] The first conversion module is connected to the baseboard management controller, the second conversion module is connected to the microcontroller unit, and the first conversion module and the second conversion module are connected by a single GPIO line, which is used to convert the host reset signal into the device reset signal, or convert the device interrupt signal into the host interrupt signal.

[0069] Please refer to Figure 3 , which shows a circuit schematic diagram of the device interconnection and bidirectional control system based on a single GPIO line of the present application in an embodiment.

[0070] As Figure 3 shown, the first conversion module includes a first voltage comparator (U1), a first resistor (R1), a second resistor (R2), and a first switching transistor (Q1). The positive input terminal of the first voltage comparator (U1) is connected to a first reference voltage, the negative input terminal is connected to the source electrode of the first switching transistor (Q1), and the output terminal is connected to the first host port (Host_GPIO1). The gate electrode of the first switching transistor (Q1) is connected to the second host port (Host_GPIO2), and the drain electrode is grounded. One end of the first resistor (R1) is connected to the power supply voltage, and the other end is connected to one end of the second resistor (R2), and the connection point is respectively connected to the negative terminal of the first voltage comparator (U1) and the second converter. The other end of the second resistor (R2) is grounded.

[0071] In an embodiment of the present application, the first voltage comparator (U1) is an inverting voltage comparator. When the voltage at the “+” input terminal of U1 is higher than the voltage at the “-” input terminal, the output terminal outputs 0 (i.e., low level); conversely, when the voltage at the “+” input terminal of U1 is lower than the voltage at the “-” input terminal, the output terminal outputs 1 (i.e., high level). The first reference voltage connected to the “+” input terminal of U1 is 2.5V. The resistance value of the first resistor (R1) is 5KΩ, the resistance value of the second resistor (R2) is 68KΩ, the first resistor (R1) and the second resistor (R2) are connected in series, and the connection point is point A. The power supply voltage is 3.3V.

[0072] The second conversion module includes a second voltage comparator (U2), a third resistor (R3), and a second switching transistor (Q2). The inverting input terminal of the second voltage comparator (U2) is connected to a second reference voltage, the non-inverting input terminal is respectively connected to one end of the third resistor (R3) and the first converter, and the output terminal is connected to the first device port (Device_GPIO1). The other end of the third resistor (R3) is connected to the source electrode of the second switching transistor (Q2). The gate electrode of the second switching transistor (Q2) is connected to the second device port (Device_GPIO2), and the drain electrode is grounded.

[0073] In an embodiment of the present application, the second voltage comparator is U2. When the voltage at the “+” input terminal of U2 is higher than the voltage at the “-” input terminal, the output terminal outputs 1 (i.e., high level); conversely, when the voltage at the “+” input terminal of U2 is lower than the voltage at the “-” input terminal, the output terminal outputs 0 (i.e., low level). The second reference voltage connected to the “-” input terminal of U2 is 1.5V. The resistance value of the third resistor (R3) is 8KΩ.

[0074] In an embodiment of the present application, the first converter and the second converter convert the host reset signal into the device reset signal, including:

[0075] When the second host port (Host_GPIO2) outputs the host reset signal, the first switching transistor (Q1) switches from the off state to the on state, so that the voltage at the non-inverting terminal of the second voltage comparator (U2) is 0, the voltage at the inverting terminal is greater than the voltage at the non-inverting terminal, and the output terminal outputs the device reset signal; the voltage at the inverting terminal of the first voltage comparator (U1) is 0, the first reference voltage at the non-inverting terminal is greater than the voltage at the inverting terminal of the first voltage comparator (U1), and the output terminal outputs the host interrupt signal.

[0076] In an embodiment of the present application, the first converter and the second converter convert the device interrupt signal into the host interrupt signal, including:

[0077] When the second device port (Device_GPIO2) outputs the device interrupt signal, the second switching transistor (Q2) switches from the off state to the on state; the power supply voltage is divided by using the connection relationship of the second resistor (R2) and the third resistor (R3) in parallel and then in series with the first resistor (R1), so that the voltage at the inverting terminal of the first voltage comparator (U1) is less than the first reference voltage at the non-inverting terminal, and the host interrupt signal is output at the output terminal; the voltage at the non-inverting terminal of the second voltage comparator (U2) is greater than the second reference voltage at the inverting terminal, and a high level is output at the output terminal.

[0078] The technical solution of the present application will be described in detail below in conjunction with the truth tables of the host port and the device port shown in Table 1 below.

[0079] Table 1, Truth Tables of Host Port and Device Port

[0080]

[0081] As shown in Table 1, the host reset signal (i.e., host Reset) defaultly output by the second host port (Host_GPIO2) is 0, indicating that the current host device has no need to reset the external device. The device interrupt signal defaultly output by the second device port (Device_GPIO2) is also 0, indicating that there is no current device interrupt requirement.

[0082] At this time, both the first switching transistor (Q1) and the second switching transistor (Q2) are in the off state, the first resistor (R1) and the second resistor (R2) are in series, and the voltage at point A is about 3.07V.

[0083] The first reference voltage at the “+” input terminal of the first voltage comparator (U1) is 2.5V, the voltage at the “−” input terminal is about 3.07V, and the voltage at the “+” input terminal is less than the voltage at the “−” input terminal. Since the first voltage comparator (U1) is an inverting voltage comparator, the host interrupt signal output at the output terminal of the first voltage comparator (U1) is 1, that is, the host interrupt signal defaultly input by the first host port (Host_GPIO1) is 1.

[0084] The second reference voltage at the “−” input terminal of the second voltage comparator (U2) is 1.5V, the voltage at the “+” input terminal is about 3.07V, and the voltage at the “+” input terminal is greater than the voltage at the “−” input terminal. Therefore, the device reset signal output at the output terminal of the second voltage comparator (U2) is 1, that is, the device reset signal defaultly input by the first device port (Device_GPIO1) is 1.

[0085] When the host device does not need to reset the external device and the external device generates an interrupt request, the host reset signal (i.e., host Reset) output by the second host port (Host_GPIO2) is 0, and the device interrupt signal output by the second device port (Device_GPIO2) changes from 0 to 1. At this time, the first switching transistor (Q1) is turned off, and the second switching transistor (Q2) switches from the off state to the on state. The second resistor (R2) and the third resistor (R3) are connected in parallel and then connected in series with the first resistor (R1), and the voltage at point A is about 1.94V.

[0086] The first reference voltage at the “+” input terminal of the first voltage comparator (U1) is 2.5V, and the voltage at the “-” input terminal is about 1.94V. The voltage at the “+” input terminal is greater than the voltage at the “-” input terminal. Since the first voltage comparator (U1) is an inverting voltage comparator, the host interrupt signal output by the output terminal of the first voltage comparator (U1) is 0, that is, the host interrupt signal input to the first host port (Host_GPIO1) is 0. At this time, the BMC can receive the interrupt signal sent by the external device and call the corresponding interrupt handling program.

[0087] The second reference voltage at the “-” input terminal of the second voltage comparator (U2) is 1.5V, and the voltage at the “+” input terminal is about 1.94V. The voltage at the “+” input terminal is greater than the voltage at the “-” input terminal. Therefore, the device reset signal output by the output terminal of the second voltage comparator (U2) is 1, that is, the device reset signal input to the first device port (Device_GPIO1) is 1. At this time, the external device is still in the default state and does not perform any operations.

[0088] In the embodiments of the present application, there are many scenarios in which an external device can be triggered to generate an interrupt request. For example, when the external device completes a certain operation or is ready to receive data, the external device can notify the host device by generating an interrupt request; or when the external device encounters an error, a fault, or other abnormal situations, the external device notifies the host device by generating an interrupt request and requests the host device to handle it.

[0089] When the host device needs to reset the external device, the host reset signal output by the second host port (Host_GPIO2) changes from 0 to 1. At this time, the first switching transistor (Q1) switches from the off state to the on state. Regardless of whether the device interrupt signal output by the second device port (Device_GPIO2) is 0 or 1, the voltage at point A is always 0.

[0090] The first reference voltage at the "+" input terminal of the first voltage comparator (U1) is 2.5V, and the voltage at the "-" input terminal is around 0V. The voltage at the "+" input terminal is greater than the voltage at the "-" input terminal. Since the first voltage comparator (U1) is an inverting voltage comparator, the host interrupt signal output by the output terminal of the first voltage comparator (U1) is 0, that is, the host interrupt signal input to the first host port (Host_GPIO1) is 0. At this time, the BMC can also receive the interrupt signal and call the corresponding interrupt handling program.

[0091] The second reference voltage at the "-" input terminal of the second voltage comparator (U2) is 1.5V, and the voltage at the "+" input terminal is around 0V. The voltage at the "+" input terminal is less than the voltage at the "-" input terminal. Therefore, the device reset signal output by the output terminal of the second voltage comparator (U2) is 0, that is, the device reset signal input to the first device port (Device_GPIO1) is 0. At this time, the external device will perform corresponding reset operations based on the reset signal.

[0092] In the embodiments of the present application, there are many scenarios that can trigger the host device to generate a reset requirement. For example, when the system starts or restarts, the host device can perform a reset operation to ensure that the external device is in an initial state; or when the external device encounters an error or abnormal situation, the host device may need to perform a reset operation to try to restore normal operation.

[0093] Please refer to Figure 4 , which shows the circuit schematic diagram of the device interconnection and bidirectional control system based on a single GPIO line of the present application in another embodiment.

[0094] As Figure 4 shown, a host device of the present application can be connected to multiple external devices simultaneously by using multiple GPIO lines. The number of external devices is the same as the number of GPIO lines, and each GPIO line is responsible for implementing communication between the host device and an external device.

[0095] For example, when a host device is connected to four external devices and transmitting level states between devices in the traditional way, usually 4 GPIO lines are required for signal transmission and 4 GPIO lines are required for signal reception. By using the technical solution of the present application, the same technical effect can be achieved with four GPIO lines, saving the number of GPIO lines used.

[0096] In this implementation mode, a simple comparator, MOS transistor, resistor, and a single GPIO line are used to achieve bidirectional control between the host device and the external device. At the same time, the host device can also control and monitor multiple external devices to achieve more complex system functions, reduce the number of interconnection signal lines, save the internal interface interconnection space of the server, simplify the design and layout of the server, improve the integration and performance of the server, and reduce the cost and maintenance difficulty. In addition, this application has stability and reliability, and can meet the performance and compatibility requirements of high-density servers.

[0097] Please refer to Figure 5 , which shows the flowchart of the device interconnection and bidirectional control method based on a single GPIO line of this application in an embodiment.

[0098] As Figure 5 shown, the embodiment of this application provides a device interconnection and bidirectional control method based on a single GPIO line, including the following steps S1 to S3.

[0099] Step S1: Connect the host device and the external device with a single GPIO line, and transmit a control signal between the host device and the external device; the control signal is a reset signal or an interrupt signal, where the reset signal is sent from the host device to the external device, and the interrupt signal is sent from the external device to the host device.

[0100] Specifically, in the embodiment of this application, the single GPIO line is respectively connected to the GPIO pins on the host device and the external device. The GPIO pin is a general digital input / output interface, which can be configured as an input or output mode, and transmits information by obtaining the level state (high level or low level).

[0101] Step S2: After receiving the reset signal, the external device performs a reset operation based on the reset signal.

[0102] Specifically, the external device can be a hard disk controller or a network adapter, etc. The external device includes a micro control unit (MCU). The MCU is a chip integrating a processor, a memory, an input / output interface, and other peripherals, which can operate independently and has the ability to process and execute tasks.

[0103] In an embodiment of the present application, a first device port (Device_GPIO1) and a second device port (Device_GPIO2) are provided on the microcontroller unit. Both the first device port (Device_GPIO1) and the second device port (Device_GPIO2) are general-purpose input / output interfaces. The first device port (Device_GPIO1) is used to receive the device reset signal, and the second device port (Device_GPIO2) is used to output the device interrupt signal.

[0104] Step S3: After receiving the interrupt signal, the host device calls a corresponding interrupt handler based on the interrupt signal.

[0105] Specifically, the host device is usually a computer or an embedded system. In this embodiment, the host device is a server host. The host device includes a Board Management Controller (BMC). The BMC is a separate ARM chip integrated on the motherboard of the server or computer, and is used to implement functions such as server remote control management, device information management, server status interface management, and maintenance management.

[0106] In an embodiment of the present application, a first host port (Host_GPIO1) and a second host port (Host_GPIO2) are provided on the board management controller. Both the first host port (Host_GPIO1) and the second host port (Host_GPIO2) are general-purpose input / output interfaces. The first host port (Host_GPIO1) is used to receive the host interrupt signal, and the second host port (Host_GPIO2) is used to output the host reset signal.

[0107] As Figure 2 shown, the host device further includes a first conversion module, and the external device further includes a second conversion module.

[0108] The first conversion module is connected to the board management controller, the second conversion module is connected to the microcontroller unit, and the first conversion module and the second conversion module are connected by a single GPIO line, and are used to convert the host reset signal into the device reset signal, or convert the device interrupt signal into the host interrupt signal.

[0109] As Figure 3As shown, the first conversion module includes a first voltage comparator (U1), a first resistor (R1), a second resistor (R1), and a first switching transistor (Q1). The positive input terminal of the first voltage comparator (U1) is connected to a first reference voltage, the negative input terminal is connected to the source electrode of the first switching transistor (Q1), and the output terminal is connected to the first host port (Host_GPIO1). The gate electrode of the first switching transistor (Q1) is connected to the second host port (Host_GPIO2), and the drain electrode is grounded. One end of the first resistor (R1) is connected to the power supply voltage, and the other end is connected to one end of the second resistor (R2), and the connection point is respectively connected to the negative terminal of the first voltage comparator (U1) and the second converter. The other end of the second resistor (R2) is grounded.

[0110] In an embodiment of the present application, the first voltage comparator (U1) is an inverting voltage comparator. When the voltage at the “+” input terminal of U1 is higher than the voltage at the “−” input terminal, the output terminal outputs 0 (i.e., low level); conversely, when the voltage at the “+” input terminal of U1 is lower than the voltage at the “−” input terminal, the output terminal outputs 1 (i.e., high level). The first reference voltage connected to the “+” input terminal of U1 is 2.5V. The resistance value of the first resistor (R1) is 5KΩ, the resistance value of the second resistor (R2) is 68KΩ, the first resistor (R1) and the second resistor (R2) are connected in series, and the connection point is point A. The power supply voltage is 3.3V.

[0111] The second conversion module includes a second voltage comparator (U2), a third resistor (R3), and a second switching transistor (Q2). The negative input terminal of the second voltage comparator (U2) is connected to a second reference voltage, the positive input terminal is respectively connected to one end of the third resistor (R3) and the first converter, and the output terminal is connected to the first device port (Device_GPIO1). The other end of the third resistor (R3) is connected to the source electrode of the second switching transistor (Q2). The gate electrode of the second switching transistor (Q2) is connected to the second device port (Device_GPIO2), and the drain electrode is grounded.

[0112] In an embodiment of the present application, the second voltage comparator is U2. When the voltage at the “+” input terminal of U2 is higher than the voltage at the “−” input terminal, the output terminal outputs 1 (i.e., high level); conversely, when the voltage at the “+” input terminal of U2 is lower than the voltage at the “−” input terminal, the output terminal outputs 0 (i.e., low level). The second reference voltage connected to the “−” input terminal of U2 is 1.5V. The resistance value of the third resistor (R3) is 8KΩ.

[0113] In an embodiment of the present application, the first converter and the second converter convert the host reset signal into the device reset signal, including:

[0114] When the second host port (Host_GPIO2) outputs the host reset signal, the first switching transistor (Q1) switches from the off state to the on state, making the voltage at the positive terminal of the second voltage comparator (U2) 0, and the voltage at the negative terminal (1.5V) being greater than the voltage at the positive terminal, and the output terminal outputs the device reset signal; the voltage at the inverting terminal of the first voltage comparator (U1) is 0, the first reference voltage (2.5V) at the positive terminal is greater than the voltage at the inverting terminal of the first voltage comparator (U1), and the output terminal outputs the host interrupt signal.

[0115] In an embodiment of the present application, the conversion of the device interrupt signal into the host interrupt signal by the first converter and the second converter includes:

[0116] When the second device port (Device_GPIO2) outputs the device interrupt signal, the second switching transistor (Q2) switches from the off state to the on state; the power supply voltage is divided by the connection relationship of the second resistor (R2) and the third resistor (R3) in parallel and then in series with the first resistor (R1), making the voltage at the inverting terminal of the first voltage comparator (U1) less than the first reference voltage (2.5V) at the positive terminal, and the output terminal outputs the host interrupt signal; the voltage at the positive terminal of the second voltage comparator (U2) is greater than the second reference voltage (1.5V) at the inverting terminal, and the output terminal outputs a high level.

[0117] The protection scope of the method for device interconnection and bidirectional control based on a single GPIO line described in the embodiments of the present application is not limited to the execution order of the steps listed in this embodiment. Any solution achieved by adding or reducing steps of the prior art and replacing steps according to the principle of the present application is included in the protection scope of the present application.

[0118] The device interconnection and bidirectional control system based on a single GPIO line provided in the embodiments of the present application can implement the method for device interconnection and bidirectional control based on a single GPIO line described in the present application. However, the implementation device of the method for device interconnection and bidirectional control based on a single GPIO line described in the present application includes but is not limited to the structure of the device interconnection and bidirectional control system based on a single GPIO line listed in this embodiment. Any structural deformation and replacement of the prior art made according to the principle of the present application are included in the protection scope of the present application.

[0119] In several embodiments provided in this application, it should be understood that the disclosed system, apparatus, or method can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules / units is only a logical functional division. In actual implementation, there can be other division methods. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling, direct coupling, or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices, modules, or units can be in electrical, mechanical, or other forms.

[0120] The modules / units described as separate components may or may not be physically separated. The components shown as modules / units may or may not be physical modules, that is, they can be located in one place or distributed to multiple network units. Some or all of the modules / units can be selected according to actual needs to achieve the objectives of the embodiments of this application. For example, in each embodiment of this application, the functional modules / units can be integrated into one processing module, or each module / unit can exist physically alone, or two or more modules / units can be integrated into one module / unit.

[0121] Those of ordinary skill in the art should also be further aware that the units and algorithm steps of each example described in combination with the embodiments disclosed in this document can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0122] The descriptions of the processes or structures corresponding to the above respective drawings have their own emphases. For the parts not detailed in a certain process or structure, reference can be made to the relevant descriptions of other processes or structures.

[0123] The above embodiments only illustratively explain the principles and effects of this application and are not used to limit this application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in this application should still be covered by the claims of this application.

Claims

1. A device interconnection and two-way control system based on a single GPIO line, characterized in that, it includes a host device, an external device, and a single GPIO line; the single GPIO line is used to connect the host device and the external device, and transmit control signals between the host device and the external device; the control signals are reset signals or interrupt signals, where the reset signal is sent from the host device to the external device, and the interrupt signal is sent from the external device to the host device; the external device is used to perform a reset operation based on the reset signal after receiving the reset signal; the host device is used to call a corresponding interrupt handling program based on the interrupt signal after receiving the interrupt signal.

2. The system according to claim 1, characterized in that, the reset signal includes a host reset signal and a device reset signal, and the interrupt signal includes a device interrupt signal and a host interrupt signal.

3. The system according to claim 2, characterized in that, the host device includes a baseboard management controller; the baseboard management controller is provided with a first host port and a second host port, where the first host port is used to receive the host interrupt signal, and the second host port is used to output the host reset signal.

4. The system according to claim 3, characterized in that, the external device includes a micro control unit; the micro control unit is provided with a first device port and a second device port, where the first device port is used to receive the device reset signal, and the second device port is used to output the device interrupt signal.

5. The system according to claim 4, characterized in that, the host device further includes a first conversion module, and the external device further includes a second conversion module; the first conversion module is connected to the baseboard management controller, the second conversion module is connected to the micro control unit, and the first conversion module and the second conversion module are connected by a single GPIO line, and are used to convert the host reset signal into the device reset signal, or convert the device interrupt signal into the host interrupt signal.

6. The system according to claim 5, characterized in that, the first conversion module includes a first voltage comparator, a first resistor, a second resistor, and a first switching tube; the positive input terminal of the first voltage comparator is connected to a first reference voltage, the negative input terminal is connected to the source electrode of the first switching tube, and the output terminal is connected to the first host port; the gate electrode of the first switching tube is connected to the second host port, and the drain electrode is grounded; one end of the first resistor is connected to the power supply voltage, the other end is connected to one end of the second resistor, and the connection point is respectively connected to the negative terminal of the first voltage comparator and the second converter; the other end of the second resistor is grounded.

7. The system according to claim 6, characterized in that, the second conversion module includes a second voltage comparator, a third resistor, and a second switching tube; The inverting input terminal of the second voltage comparator is connected to a second reference voltage. The non-inverting input terminal is respectively connected to one end of the third resistor and the first converter, and the output terminal is connected to the first device port; The other end of the third resistor is connected to the source electrode of the second switching transistor; The gate electrode of the second switching transistor is connected to the second device port, and the drain electrode is grounded.

8. The system according to claim 7, wherein, The conversion of the host reset signal into the device reset signal by the first converter and the second converter includes: When the second host port outputs the host reset signal, the first switching transistor switches from the off state to the on state, such that the voltage at the non-inverting terminal of the second voltage comparator is 0, the voltage at the inverting terminal is greater than the voltage at the non-inverting terminal, and the output terminal outputs the device reset signal; the voltage at the inverting terminal of the first voltage comparator is 0, the first reference voltage at the non-inverting terminal is greater than the voltage at the inverting terminal of the first voltage comparator, and the output terminal outputs the host interrupt signal.

9. The system according to claim 7, wherein, The conversion of the device interrupt signal into the host interrupt signal by the first converter and the second converter includes: When the second device port outputs the device interrupt signal, the second switching transistor switches from the off state to the on state; the power supply voltage is divided by using the connection relationship of the parallel connection of the second resistor and the third resistor in series with the first resistor, such that the voltage at the inverting terminal of the first voltage comparator is less than the first reference voltage at the non-inverting terminal, and the output terminal outputs the host interrupt signal; the voltage at the non-inverting terminal of the second voltage comparator is greater than the second reference voltage at the inverting terminal, and the output terminal outputs a high level.

10. A method for device interconnection and bidirectional control based on a single GPIO line, wherein, it includes: Connecting a host device and an external device by using a single GPIO line, and transmitting a control signal between the host device and the external device; The control signal is a reset signal or an interrupt signal, wherein the reset signal is sent from the host device to the external device, and the interrupt signal is sent from the external device to the host device; After receiving the reset signal, the external device performs a reset operation based on the reset signal; After receiving the interrupt signal, the host device calls a corresponding interrupt handling program based on the interrupt signal.

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