Change log compression

Abstract

The invention relates to change log compression. Aspects of the present disclosure relate to enabling a memory system to support compression of entries of a change log and improving the efficiency of the memory system by enabling memory system changes associated with the change log to occur concurrently. Entries of the change log may be compressed using a "hierarchical" compression technique or a "direct" compression technique. In the case of hierarchical compression, the memory system may merge new entries with hierarchical entries, may update previous hierarchical entries, and may then release the merged entries to the change log. In the event of direct compression, the memory system may determine whether a back-end entry can be directly merged with an existing entry of the change log.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 18 / 954,256, filed Nov. 20, 2024, titled “CHANGE LOG COMPRESSION” by Porzio et al. and U.S. Patent Application No. 63 / 604,757, filed Nov. 30, 2023, titled “CHANGE LOG COMPRESSION” by Porzio et al., each of which is assigned to its assignee and is hereby incorporated by reference in its entirety. Technical Field

[0003] This technical field relates to change log compression. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states and can store any of those states. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) the state to the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, NOR and NAND memory devices, and the like. Memory cells can be described in terms of a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain the stored logic state for a long time even in the absence of an external power source. In response to a memory cell configured in a volatile configuration being disconnected from an external power source, the memory cell may lose the stored state. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory device; and a controller coupled to the memory device and configured to cause the apparatus to: receive a first command to write first data to a first block of the memory device, the first block being associated with a first logical address and a first physical address; in response to receiving the first command, identify an entry in a change log associated with a second logical address and a second physical address; and in response to receiving the first command and identifying the entry, modify the entry associated with the change log to include information associated with the first command, the entry of the change log including a first field indicating a block address of the memory device, a second field indicating a data length indicated by the entry, and a third field indicating a compression state, the compression state indicating whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device.

[0007] Describe a non-transitory computer-readable medium. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a first command to write first data to a first block of a memory device, the first block being associated with a first logical address and a first physical address; in response to receiving the first command, identify an entry in a change log associated with a second logical address and a second physical address; and in response to receiving the first command and identifying the entry, modify the entry associated with the change log to include information associated with the first command, the entry of the change log including a first field indicating a block address of the memory device, a second field indicating a data length indicated by the entry, and a third field indicating a compression state, the compression state indicating whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device.

[0008] Describe a method. The method may include: receiving a first command to write first data to a first block of a memory device, the first block being associated with a first logical address and a first physical address; in response to receiving the first command, identify an entry in a change log associated with a second logical address and a second physical address; and in response to receiving the first command and identifying the entry, modify the entry associated with the change log to include information associated with the first command, the entry of the change log including a first field indicating a block address of the memory device, a second field indicating a data length indicated by the entry, and a third field indicating a compression state, the compression state indicating whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Describe an example of a system that supports change log compression according to an example disclosed herein.

[0010] Figure 2A 、 2B 、2C and 2D describe examples of a hierarchical compression mode that supports change log compression according to an example disclosed herein.

[0011] Figure 3A 、 3B and 3C describe examples of a direct compression mode that supports change log compression according to an example disclosed herein.

[0012] Figure 4 Describe a block diagram of a memory system that supports change log compression according to an example disclosed herein.

[0013] Figure 5 Describe a flowchart showing one or more methods that support change log compression according to an example disclosed herein. DETAILED DESCRIPTION

[0014] A memory system may be coupled to a host system and may receive commands (e.g., read commands, write commands) from the host system. For some commands, the host system may use a logical block address (LBA) (e.g., assigned by the host system) to identify the logical location of the stored data page to reference the location of the stored data in the memory system. The LBA may be mapped to a physical address of the memory system where the data is stored. Because the physical address of the data may change (e.g., in response to updating the data by writing the updated data to a different page), some memory systems maintain one or more logical-to-physical (L2P) mappings that map the LBA generated by the host system to the corresponding physical address generated by the memory system. In this way, even if the data has been moved to a different physical address, the host system may request to read the data from the memory system using the same LBA that was used to write the data. Each L2P mapping may be stored in non-volatile memory (e.g., NAND memory). In the case where a change is to be made to the L2P mapping, a portion of the L2P mapping may be loaded into the cache (e.g., SRAM) of the memory system and the change may be performed. The process of transferring a portion of the L2P mapping from NAND to SRAM, updating the portion in SRAM, and writing back to NAND may affect the performance of the memory system.

[0015] A memory system may support a data structure, such as a change log that defines (e.g., maintains, tracks, records) changes to be performed and associated with the memory system. The memory system may use the change log to maintain a list (e.g., entries) of changes to be made to each L2P mapping and may then perform many changes concurrently. This process of aggregating changes using the change log before making the changes may improve the efficiency of updating the L2P mapping. Some techniques for maintaining the change log include not compressing change log entries (e.g., one change log entry for one change to the L2P mapping). However, because the change log entries are not compressed, the memory system may refresh (e.g., renew, clear, change) the content of the change log, for example, periodically or aperiodically, which may degrade the performance of the memory system.

[0016] As described herein, aspects of the present disclosure relate to enabling a memory system to support compressed change log entries and improving the efficiency of the memory system by enabling memory system changes associated with the change log to occur concurrently (e.g., be disposed of). For example, the data traffic between the host system and the memory system may be sequential (e.g., the data is sequential), and each change log entry may be represented by an LBA, a physical block address (PBA), a length field, a compression indication field, an overlap indicator field, or a combination thereof. Either a "hierarchical" compression technique or a "direct" compression technique (sometimes referred to as lazy compression technique) may be used. In the case where the data is sequential (e.g., in both the LBA and the PBA), hierarchical compression may be used. Thus, before pushing (e.g., forwarding, outputting, moving) an entry that includes a logical address and a physical address of a backend entry into the change log, the memory system (e.g., via executing firmware) may "hierarchize" the entry (e.g., create a temporary entry to be pushed into the change log). For example, the memory system (e.g., via executing firmware) may merge a new entry with a hierarchized entry (e.g., create a merged entry if the new entry is a viable candidate for this entry), may update the previous hierarchized entry, and may then release the merged entry into the change log. In the case of direct compression, the memory system (e.g., via executing firmware) may determine whether the backend entry can be directly merged with an existing entry in the change log.

[0017] Reference Figure 1 , the features of the present disclosure are initially described in the context of a system. Reference Figure 2A , 2B , 2C, 2D, 3A, 3B, and 3C, the features of the present disclosure are described in the context of hierarchical and direct compression modes. Reference Figure 4 and 5 , these and other features of the present disclosure are further illustrated and described in the context of device diagrams and flowcharts related to change log compression.

[0018] Figure 1 Describe an example of a system 100 that supports change log compression according to the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or collection of devices, where the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Outline DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other possibilities.

[0020] System 100 may be included in a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

[0021] System 100 may include a host system 105, which may be coupled to the memory system 110. In some examples, such coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 only one memory system 110 is shown, the host system 105 may be coupled to any number of memory systems 110.

[0022] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DIMM slot interfaces that support DDR), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces can be included in the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110 or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some instances, the host system 105 can be coupled to the memory system 110 via the respective physical host interfaces of each memory device 130 included in the memory system 110 or via the respective physical host interfaces of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 can be coupled to the memory system controller 115).

[0023] The memory system 110 can include a memory system controller 115 and one or more memory devices 130. The memory devices 130 can include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 two memory devices 130-a and 130-b are shown in the example, the memory system 110 can include any number of memory devices 130. Additionally, if the memory system 110 includes more than one memory device 130, the different memory devices 130 within the memory system 110 can include the same or different types of memory cells.

[0024] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface), and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 can also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130 - and other such operations - which can generally be referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to effect the desired access of the memory device 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to a command from the host system 105 or otherwise associated with a command from the host system 105). For example, the memory system controller 115 can convert a response (e.g., a data packet or other signal) associated with the memory device 130 into a corresponding signal for the host system 105.

[0025] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between a logical address (e.g., a logical block address (LBA)) associated with a command from the host system 105 and a physical address (e.g., a physical block address) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 can include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware can include circuitry having dedicated (e.g., hard - coded) logic to perform the operations ascribed to the memory system controller 115 herein. The memory system controller 115 can be or include a microcontroller, dedicated logic circuitry (e.g., a field - programmable gate array (FPGA), an application - specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that can store operation codes (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for internal storage or computing related to, for example, the functions attributed to the memory system controller 115 herein.

[0028] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetoresistive RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0029] In some instances, the memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that may perform operations on one or more memory cells of the corresponding memory device 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed to the memory system controller 115 herein. For example, as Figure 1 illustrated, the memory device 130-a may include a local controller 135-a and the memory device 130-b may include a local controller 135-b.

[0030] In some cases, the memory device 130 may be or include a NAND device (e.g., a NAND flash device). The memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, the memory device 130 may be a package that includes one or more dies 160. In some instances, the die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, where each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0031] In some cases, the NAND memory device 130 may include memory cells configured to each store one information bit, which may be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple information bits, which may be referred to as multi-level cells (MLCs) if configured to each store two information bits, triple-level cells (TLCs) if configured to each store three information bits, quad-level cells (QLCs) if configured to each store four information bits, or more generally may be referred to as multi-level memory cells. Relative to SLC memory cells, multi-level memory cells may provide greater storage density, but in some cases, may involve narrower read or write margins or greater complexity for support circuitry.

[0032] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes that include memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, and so on). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0033] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells within the same page 175 may share a common word line (e.g., be coupled to a common word line), and memory cells within the same string may share a common digit line (which may alternatively be referred to as a bit line) (e.g., be coupled to a common digit line).

[0034] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest memory unit (e.g., group of memory cells) that can be independently programmed or read (e.g., programmed or read concurrently as part of a single programming or reading operation), while block 170 may be the smallest memory unit (e.g., group of memory cells) that can be independently erased (e.g., erased concurrently as part of a single erase operation). Additionally, in some cases, NAND memory cells may be erased before they are rewritten with new data. Thus, for example, in some cases, the page 175 in use is not updated until the entire block 170 that contains the page 175 has been erased.

[0035] In some cases, to update some data within block 170 while preserving other data within block 170, memory device 130 may copy the data to be preserved to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise designate the data held in the old block 170 as invalid or obsolete and may update the L2P mapping to associate the logical address (e.g., LBA) of the data with the new valid block 170 rather than the old invalid block 170. In some cases, this copy and remapping may be performed instead of erasing and rewriting the entire old block 170, e.g., due to latency or wear considerations. In some cases, one or more copies of the L2P mapping may be stored within the memory cells of memory device 130 (e.g., stored within one or more blocks 170 or planes 165) for use (e.g., reference and update) by local controller 135 or memory system controller 115.

[0036] In some cases, the L2P mapping may be maintained and data may be marked as valid or invalid at the page granularity level, and page 175 may contain valid data, invalid data, or no data. Invalid data may be data that is obsolete due to a more recent or updated version of the data being stored in a different page 175 of memory device 130. Invalid data may have previously been programmed to an invalid page 175 but may no longer be associated with a valid logical address (e.g., a logical address referenced by host system 105). Valid data may be the most recent version of the data stored on memory device 130. A page 175 that contains no data may be a page 175 that has not been written to or has been erased.

[0037] System 100 may include any number of non-transitory computer-readable media that support change log compression. For example, host system 105 (e.g., host system controller 106), memory system 110 (e.g., memory system controller 115), or memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to host system 105, memory system 110, or memory device 130. For example, such instructions, if executed by host system 105 (e.g., by host system controller 106), by memory system 110 (e.g., by memory system controller 115), or by memory device 130 (e.g., by local controller 135), may cause host system 105, memory system 110, or memory device 130 to perform the associated functions as described herein.

[0038] Memory system 110 may be coupled to host system 105 and may receive commands (e.g., read commands, write commands) from host system 105. For some commands, host system 105 may use a logical LBA (e.g., assigned by host system 105) to identify the logical location of a stored data page and reference the location of the stored data in memory system 110. The LBA may be mapped to a physical address of a page 175 in memory system 110 (e.g., assigned by the memory system). Because the physical address of the data may change (e.g., in response to updating data by writing the updated data to a different page 175), some memory systems maintain one or more L2P mappings that map the LBA generated by host system 105 to the corresponding physical address of a page 175 in memory system 110. In this way, even if the data has been moved to a different physical address, host system 105 may request to read data from memory system 110 using the same LBA that was used to write the data. In cases where the L2P mapping must be changed, each L2P mapping may be stored in non-volatile memory (e.g., NAND memory) while the update is being performed. Then a portion of the L2P mapping may be loaded into a cache (e.g., SRAM) of memory device 130 and the change may be performed. The process of transferring a portion of the L2P mapping from NAND to SRAM, updating the portion in SRAM, and writing back to NAND may affect the performance of the memory system.

[0039] Memory system 110 may use a change log to store L2P mappings for newly performed access operations (e.g., write operations, unmapping operations, erase operations). For example, after receiving a write command associated with a logical address, a controller of memory system 110 may write data associated with the command to a physical address and store the mapping between the logical address and the physical address in the change log. In some instances, the change log may contain a certain number of entries (e.g., 4k entries, 8k entries) and may thus be able to handle a certain number of change log updates before a checkpoint is triggered, and memory system 110 may flush the change log by forwarding the stored updates to the L2P table, by writing the updated L2P table to memory device 130 (e.g., non-volatile memory), or both. Thus, techniques for compressing the entries of the change log in response to the traffic being sequential - which may improve the storage availability of the change log and reduce the total time spent performing a change log checkpoint - may be beneficial.

[0040] As described herein, compression techniques (e.g., in the case of sequential data traffic) can be used to improve the efficiency of the change log. Thus, the entries of the compressed change log can be represented by various indicators. For example, each compressed entry of the change log can be represented by a translation unit address (TUA), PBA, length, compression indication (e.g., indicating whether the entry has been compressed), overlap indicator (e.g., indicating whether the entry overlaps with another entry, optionally), or a combination thereof. These fields can be used and adjusted during the compression of the entries in the change log.

[0041] "Hierarchical" compression techniques can be used in the case of sequential data traffic. In such "hierarchical" compression techniques, the memory system controller 115 can allocate a portion of the local memory 120 (e.g., SRAM) as a hierarchical region to temporarily store new change log entries before adding new entries to the change log. Additionally or alternatively, the memory device 130 can allocate a portion of the local memory 120 (e.g., SRAM) as a hierarchical region to temporarily store new change log entries before adding new entries to the change log. While the entries are being hierarchically processed, the memory system 110 can manipulate (e.g., adjust, compress) the hierarchical entries and then add them to the change log. For example, the memory system 110 can receive (e.g., detect from the host system) a new access command and prepare to add it as a backend entry to the change log. The memory system 110 can also create a hierarchical entry (e.g., allocate SRAM for it). The memory system 110 can verify (e.g., confirm) that the data traffic is sequential and if the traffic is indeed sequential, then it can push the backend entry to the hierarchical entry and subsequently manipulate the fields of the hierarchical entry (e.g., one or more of TUA, PBA, length indicator, compression indicator). However, in the case where the traffic is non-sequential, the memory system 110 can push the backend entry to a hierarchical entry queue (e.g., group), can push this hierarchical entry to the change log, and then can create a new hierarchical entry. In response to receiving the last command (e.g., empty the backend queue) from the host system 105, the memory system 110 can push any outstanding hierarchical entries into the change log. Thus, such hierarchical compression techniques (e.g., compression via manipulating the hierarchical entry fields before pushing into the change log) can achieve efficient compression of the change log entries without implementing hardware changes.

[0042] The "direct" compression technique can be used in the case of sequential data services. In this "direct" compression technique, the memory system 110 can directly search and manipulate (e.g., adjust, compress) the change log (e.g., without using hierarchical entries). For example, the memory system 110 can receive (e.g., detect from the host system 105) a new access command and prepare to add it as a backend entry to the change log. The memory system 110 can then add the backend entry (e.g., the new entry) to the change log (e.g., the next available location in the change log). The memory system 110 can evaluate whether the backend entry can be merged with other (e.g., pre-existing) entries in the change log. For example, the memory system 110 can merge the new entry with the previously added entries in the change log in a reverse merge, a forward merge, or a dual-mode merge. To merge the new entry with other entries in the change log, the memory system 110 can manipulate the fields of the new entry (e.g., one or more of TUA, PBA, length indicator, compression indicator). Thus, this "direct" compression technique (e.g., compression via manipulating the fields of the new entry after pushing it into the change log) can achieve efficient compression of the change log entries without implementing hardware changes.

[0043] Figure 2A , 2B , 2C and 2D illustrate examples of the hierarchical compression mode 200 that supports change log compression according to examples as disclosed herein. The hierarchical compression mode 200 can be implemented by aspects of the system 100 as described in reference to Figure 1 or implement aspects of the system 100 as described in reference to Figure 1 . The hierarchical compression mode 200 can be implemented by a memory system configured to store data received from a host system and send the data to the host system in response to an access command (e.g., a read command or a write command) requested by the host system.

[0044] Figure 2A illustrates an example of the hierarchical compression mode 200-a that supports change log compression according to examples as disclosed herein. The hierarchical compression mode 200-a can be an example of an empty-phase hierarchical entry compression mode and can be implemented by aspects of the system 100 as described in reference to Figure 1 or implement aspects of the system 100 as described in reference to Figure 1 . For example, the hierarchical compression mode 200-a can be implemented by a memory system configured to store data received from a host system and send the data to the host system in response to an access command (e.g., a read command or a write command) requested by the host system.

[0045] The hierarchical compression mode 200-a may include a back-end entry queue 205, a hierarchical entry queue 210, and a change log 215 during a pre-insert (e.g., pre-hierarchical entry adjustment) period 275 and a post-insert (e.g., post-hierarchical entry adjustment) period 280, where an insert 270 indicates a change made to the back-end entry queue 205, the hierarchical entry queue 210, the change log 215, or a combination thereof. The back-end entry queue 205 may store instances of back-end entries that may include a TUA 220 and a PBA 225 for inclusion in the change log 215. For example, when a memory system performs an access operation (e.g., a write operation, an erase operation, an unmapping operation), information to be added to the change log may be generated. Information generated as part of an access operation may be referred to as a back-end entry. Some memory systems may include hardware (e.g., a change log manager or engine) that efficiently adds information to and / or removes information from the change log 215. Thus, in some cases, a memory system may generate a back-end entry as part of an access operation and may use the change log manager to insert the back-end entry into the change log 215. The back-end entries stored by the back-end entry queue 205 may include: a TUA 220-a that stores the address "30"; and a PBA 225-a that stores the die "0", plane "0", page "1", and offset "2".

[0046] The hierarchical entry queue 210 may be an instance of a data structure used by the memory system to temporarily store and / or manipulate entries before the entries are inserted into the change log 215. A back-end entry may be information associated with a given access operation. In some cases, a back-end entry may be immediately inserted into the change log 215 as part of an access operation. In the techniques described herein, a back-end entry may be temporarily stored in the hierarchical entry queue 210 before being inserted into the change log 215. While in the hierarchical entry queue 210, the memory system may perform additional access operations and thereby generate additional back-end entries. If the next back-end entry is compressible with the back-end entry (e.g., hierarchical entry) currently stored in the hierarchical entry queue 210, the memory system may modify the back-end entry in the hierarchical entry and store the updated back-end entry and may continue with the access operation. Once the memory system encounters a back-end entry in the back-end entry queue 205 that is not compressible with the back-end entry (e.g., hierarchical entry) stored in the hierarchical entry queue 210, the memory system may transfer the back-end entry stored in the hierarchical entry queue 210 to the change log 215 and transfer the back-end entry stored in the back-end entry queue 205 to the hierarchical entry queue 210. In this way, the memory system may compress the entries of the change log 215 before adding the entries to the change log.

[0047] The hierarchical entry queue 210 can store instances of hierarchical entries that can include the TUA 230, PBA 235, length field 240, and compression indicator 245 before the insertion 270 (e.g., pre-insertion period 275) and after the insertion 270 (e.g., post-insertion period 280). For example, the hierarchical entry stored by the hierarchical entry queue 210 during the pre-insertion period 275 can include TUA 230-a, PBA 225-a, length field 240-a, and compression indicator 245-a, where TUA 230-a, PBA 225-a, length field 240-a, and compression indicator 245-a are empty (e.g., do not store any data). Similarly, the hierarchical entry stored by the hierarchical entry queue 210 during the post-insertion period 280 can include: TUA 230-b, which stores the address "30"; PBA 225-b, which stores (respectively) die, plane, page, and offset "0, 0, 1, 2"; length field 240-b, which stores the length "0"; and compression indicator 245-b, which stores the "false" indicator. The change log 215 can store instances of previously stored change log entries, each entry of which can include the TUA 250, PBA 255, length field 260, and compression indicator 265 before the insertion 270 (e.g., pre-insertion period 275) and after the insertion 270 (e.g., post-insertion period 280). For example, each entry stored by the change log 215 during both the pre-insertion period 275 and the post-insertion period 280 can include the TUA 250, PBA 255, length field 260, and compression indicator 265, where the TUA 250, PBA 255, length field 260, and compression indicator 265 can contain various data that remain unchanged through the insertion 270.

[0048] The memory system may use hierarchical entry compression techniques without pre-existing hierarchical entries included in the hierarchical entry queue 210. For example, in the case where the memory system receives a first command from the host system or if previously stored hierarchical entries may have been released, the hierarchical entry queue 210 may be empty (e.g., during the pre-insertion period 275, the TUA 230-a may be empty, the PBA 235-a may be empty, the length field 240-a may be empty, the compression indicator 245-a may be empty). As a result of receiving the command (and as described herein), the memory system may push the received command to the backend entry queue 205. Subsequently, the backend entry queue 205 may push backend entries (e.g., TUA 220-a, PBA 225-a) to the hierarchical entry queue 210 for hierarchical processing. For example, the memory system (e.g., via executing firmware) may create hierarchical entries (e.g., TUA 230-a, PBA 235-a, length field 240-a, compression indicator 245-a) from the LBA and TUA of the pushed backend entries (e.g., TUA 220-a, PBA 225-a) and including the PBA. The memory system may then manipulate (e.g., update, modify, change, adjust) the fields of the hierarchical entry. For example, the memory system may set the length field 240-a to zero (e.g., a null value) and may set the compression indicator 245-a to false (e.g., off). Thus, after the memory system has manipulated (e.g., updated, modified, changed, adjusted) the fields of the hierarchical entry queue 210 (e.g., after insertion 270), the hierarchical entry may include the TUA 230-b and PBA 235-b of the original backend entry (e.g., TUA 220-a, PBA 225-a), as well as the length field 240-b and the compression indicator 245-b. As a result of updating the hierarchical entry, the memory system may mark the backend entry (e.g., the backend entry (TUA 220-a, PBA 225-a) of the backend entry queue 205) as complete and may release the backend entry.

[0049] Figure 2B An example of a hierarchical compression mode 200-b that supports change log compression according to an example as disclosed herein. The hierarchical compression mode 200-b may be an example of a reverse merge hierarchical entry compression mode and may be implemented by aspects of the system 100 as described in reference to Figure 1 or implement aspects of the system 100 as described in reference to Figure 1 For example, the hierarchical compression mode 200-b may be implemented by a memory system configured to store data received from a host system and send the data to the host system in response to an access command (e.g., a read command or a write command) requested by the host system.

[0050] The hierarchical compression mode 200-b may include a back-end entry queue 205, a hierarchical entry queue 210, and a change log 215 during a pre-insertion (e.g., pre-hierarchical entry adjustment) period 275 and a post-insertion (e.g., post-hierarchical entry adjustment) period 280, where the insertion 270 indicates a change made to the back-end entry queue 205, the hierarchical entry queue 210, the change log 215, or a combination thereof. The back-end entry queue 205 may store instances of back-end entries that may include a TUA 220 and a PBA 225. For example, a back-end entry stored by the back-end entry queue 205 may include: a TUA 220-b with a storage address of "31"; and a PBA 225-b that stores die "0", plane "0", page "1", and offset "3". The hierarchical entry queue 210 may store instances of hierarchical entries that may include a TUA 230, a PBA 235, a length field 240, and a compression indicator 245 before (e.g., during the pre-insertion period 275) and after (e.g., during the post-insertion period 280) the insertion 270. For example, a hierarchical entry stored by the hierarchical entry queue 210 during the pre-insertion period 275 may include: a TUA 230-c with a storage address of "30"; a PBA 225-c that stores die, plane, page, and offset "0, 0, 1, 2" respectively; a length field 240-c that stores a length of "0"; and a compression indicator 245-c that stores a "false" indicator. Similarly, a hierarchical entry stored by the hierarchical entry queue 210 during the post-insertion period 280 may include: a TUA 230-d with a storage address of "30"; a PBA 225-d that stores die, plane, page, and offset "0, 0, 1, 2" respectively; a length field 240-d that stores a length of "1"; and a compression indicator 245-d that stores a "true" indicator. The change log 215 may store instances of previously stored change log entries, and each entry may include a TUA 250, a PBA 255, a length field 260, and a compression indicator 265 before (e.g., during the pre-insertion period 275) and after (e.g., during the post-insertion period 280) the insertion 270. For example, each entry stored by the change log 215 during both the pre-insertion period 275 and the post-insertion period 280 may include a TUA 250, a PBA 255, a length field 260, and a compression indicator 265, and the TUA 250, PBA 255, length field 260, and compression indicator 265 may contain various data that remain unchanged through the insertion 270.

[0051] The memory system may use hierarchical entry compression techniques when reverse-merging backend entries (e.g., TUA 220-b, PBA 225-b) with pre-existing hierarchical entries (e.g., TUA 230-c, PBA 235-c, length field 240-c, compression indicator 245-c). For example, the memory system may receive a new (e.g., second sequential) command from the host system when the hierarchical entry queue 210 is filled (e.g., filled with pre-existing hierarchical entries, first commands before insert 270). In this case, the new entry (e.g., the backend entry stored in the backend entry queue 205) may be merged with the pre-existing hierarchical entries stored in the hierarchical entry queue 210.

[0052] As a result of receiving the new command (and as described herein), the memory system may push (e.g., output) the new command (e.g., the new entry) to the backend entry queue 205 and may then test (e.g., analyze, review, evaluate) the merge eligibility of the backend entry (e.g., the new entry, TUA 220-b, PBA 225-b). For example, the memory system may compare the TUA 220-b of the backend entry in the backend entry queue 205 with the TUA 230-c of the hierarchical entry in the hierarchical entry queue 210. If the TUA 220-b of the backend entry is sequential to and greater than the TUA 230-c of the hierarchical entry, then the backend entry may be eligible for reverse-merging with the hierarchical entry (e.g., test positive for reverse-merging with the hierarchical entry).

[0053] If the backend entry tests positive for reverse-merging with the hierarchical entry, then the backend entry queue 205 may reverse-merge the backend entry with the hierarchical entry. For example, the memory system (e.g., via executing firmware) may manipulate (e.g., update) the fields of the hierarchical entry (e.g., TUA 230-c, PBA 235-c, length field 240-c, compression indicator 245-c) to "merge" the backend entry with the hierarchical entry. Thus, the memory system may increment the length field 240-c by 1 (e.g., +1) and may set the compression indicator 245-c to true (e.g., on). As a result of the memory system manipulating the fields of the hierarchical entry (e.g., after insert 270), the hierarchical entry may contain the TUA 230-d and PBA 235-d of the original hierarchical entry (e.g., TUA 230-c, PBA 235-c), as well as the manipulated length field 240-d and compression indicator 245-d indicating that sequential entries (e.g., the second command, new entry) have been reverse-merged with the original hierarchical entry. The memory system may then mark the backend entry (e.g., the backend entry in the backend entry queue 205 (TUA 220-b, PBA 225-b)) as complete and may release the backend entry.

[0054] Figure 2C Describe an example of a hierarchical compression mode 200-c that supports change log compression according to an example disclosed herein. The hierarchical compression mode 200-c may be an example of a forward merge hierarchical entry compression mode and may be implemented by aspects of the system 100 as described in reference Figure 1 or implement aspects of the system 100 as described in reference Figure 1 For example, the hierarchical compression mode 200-c may be implemented by a memory system configured to store data received from a host system and send the data to the host system in response to a request by the host system using an access command (e.g., a read command or a write command).

[0055] The hierarchical compression mode 200-c may include a back-end entry queue 205, a hierarchical entry queue 210, and a change log 215 during a pre-insertion (e.g., pre-hierarchical entry adjustment) period 275 and a post-insertion (e.g., post-hierarchical entry adjustment) period 280, where an insertion 270 indicates a change made to the back-end entry queue 205, the hierarchical entry queue 210, the change log 215, or a combination thereof. The back-end entry queue 205 may store instances of back-end entries that may include a TUA 220 and a PBA 225. For example, a back-end entry stored by the back-end entry queue 205 may include: a TUA 220-c with a storage address of "29"; and a PBA 225-c that stores die "0", plane "0", page "1", and offset "1". The hierarchical entry queue 210 may store instances of hierarchical entries that may include a TUA 230, a PBA 235, a length field 240, and a compression indicator 245 before (e.g., during the pre-insertion period 275) and after (e.g., during the post-insertion period 280) the insertion 270. For example, a hierarchical entry stored by the hierarchical entry queue 210 during the pre-insertion period 275 may include: a TUA 230-e with a storage address of "30"; a PBA 235-e that stores die, plane, page, and offset "0, 0, 1, 2" respectively; a length field 240-e that stores a length of "1"; and a compression indicator 245-e that stores a "true" indicator. Similarly, a hierarchical entry stored by the hierarchical entry queue 210 during the post-insertion period 280 may include: a TUA 230-f with a storage address of "29"; a PBA 235-f that stores die, plane, page, and offset "0, 0, 1, 1" respectively; a length field 240-f that stores a length of "2"; and a compression indicator 245-f that stores a "true" indicator. The change log 215 may store instances of previously stored change log entries, and each entry may include a TUA 250, a PBA 255, a length field 260, and a compression indicator 265 before (e.g., during the pre-insertion period 275) and after (e.g., during the post-insertion period 280) the insertion 270. For example, each entry stored by the change log 215 during both the pre-insertion period 275 and the post-insertion period 280 may include a TUA 250, a PBA 255, a length field 260, and a compression indicator 265, and the TUA 250, PBA 255, length field 260, and compression indicator 265 may contain various data that remains unchanged through the insertion 270.

[0056] The memory system may use hierarchical entry compression techniques when forward-merging backend entries (e.g., TUA 220-c, PBA 225-c) with pre-existing hierarchical entries (e.g., TUA 230-e, PBA 235-e, length field 240-e, compression indicator 245-e). For example, the memory system may receive a new (e.g., second sequential) command from the host system when the hierarchical entry queue 210 is filled (e.g., filled with pre-existing hierarchical entries, first commands before insert 270). In this case, the new entry may be merged with the pre-existing hierarchical entries in the hierarchical entry queue 210.

[0057] As a result of receiving the new command (and as described herein), the memory system may push (e.g., output) the new command (e.g., new entry) to the backend entry queue 205 and may then test (e.g., analyze) the merge eligibility of the backend entry (e.g., new entry, TUA 220-c, PBA 225-c). For example, the memory system may compare the TUA 220-c of the backend entry in the backend entry queue 205 with the TUA 230-e of the hierarchical entry in the hierarchical entry queue 210. If the TUA 220-c of the backend entry is sequential and less than the TUA 230-e of the hierarchical entry, then the backend entry may be eligible for forward-merging with the hierarchical entry (e.g., tests positive for forward-merging with the hierarchical entry).

[0058] As a result of the backend entry testing positive for forward-merging with the hierarchical entry, the backend entry queue 205 may forward-merge the backend entry with the hierarchical entry. For example, the memory system (e.g., via executing firmware) may manipulate (e.g., update) the fields of the hierarchical entry (e.g., TUA 230-e, PBA 235-e, length field 240-e, compression indicator 245-e) to "merge" the backend entry with the hierarchical entry. Thus, the memory system may decrement the TUA 230-e and PBA 235-e, increment the length field 240-e by 1 (e.g., +1), and may set the compression indicator 245-e to true (e.g., on). As a result of the memory system manipulating the fields of the hierarchical entry (e.g., after insert 270), the hierarchical entry may contain the manipulated TUA 230-f, PBA 235-f, length field 240-f, and compression indicator 245-f indicating that the sequential entry (e.g., second command, new entry) has been forward-merged with the original hierarchical entry. The memory system may then mark the backend entry (e.g., the backend entry in the backend entry queue 205 (TUA 220-c, PBA 225-c)) as complete and may release the backend entry.

[0059] Figure 2DDescribe an example of a hierarchical compression mode 200-d that supports change log compression according to an example disclosed herein. The hierarchical compression mode 200-d may be an example of a non-sequential merge hierarchical entry compression mode and may be implemented by aspects of the system 100 as described in reference Figure 1 or implement aspects of the system 100 as described in reference Figure 1 . For example, the hierarchical compression mode 200-d may be implemented by a memory system configured to store data received from a host system and send the data to the host system in response to a request from the host system using an access command (e.g., a read command or a write command).

[0060] The hierarchical compression mode 200-d may include a back-end entry queue 205, a hierarchical entry queue 210, and a change log 215 during a pre-insertion (e.g., pre-hierarchical entry adjustment) period 275 and a post-insertion (e.g., post-hierarchical entry adjustment) period 280, where an insertion 270 indicates a change made to the back-end entry queue 205, the hierarchical entry queue 210, the change log 215, or a combination thereof. The back-end entry queue 205 may store instances of back-end entries that may include a TUA 220 and a PBA 225. For example, a back-end entry stored by the back-end entry queue 205 may include: a TUA 220-d with a storage address of "1110"; and a PBA 225-d that stores die "0", plane "0", page "2", and offset "0". The hierarchical entry queue 210 may store instances of hierarchical entries that may include a TUA 230, a PBA 235, a length field 240, and a compression indicator 245 before (e.g., during the pre-insertion period 275) and after (e.g., during the post-insertion period 280) the insertion 270. For example, a hierarchical entry stored by the hierarchical entry queue 210 during the pre-insertion period 275 may include: a TUA 230-g with a storage address of "29"; a PBA 235-g that stores die, plane, page, and offset "0, 0, 1, 1" respectively; a length field 240-g that stores a length of "2"; and a compression indicator 245-g that stores a "true" indicator. Similarly, a hierarchical entry stored by the hierarchical entry queue 210 during the post-insertion period 280 may include: a TUA 230-h with a storage address of "1110"; a PBA 235-h that stores die, plane, page, and offset "0, 0, 2, 0" respectively; a length field 240-h that stores a length of "0"; and a compression indicator 245-h that stores a "false" indicator. The change log 215 may store instances of previously stored change log entries, where each entry may include a TUA 250, a PBA 255, a length field 260, and a compression indicator 265 before (e.g., during the pre-insertion period 275) and after (e.g., during the post-insertion period 280) the insertion 270. For example, the change log 215 may be updated such that during the post-insertion period 280, the change log 215 may include a TUA250-a, a PBA 255-a, a length field 260-a, and a compression indicator 265-a, and the TUA250-a, the PBA 255-a, the length field 260-a, and the compression indicator 265-a may all contain various data from the hierarchical entry queue 210 during the pre-insertion period 275.

[0061] The memory system may use hierarchical entry compression techniques for non-sequential backend entries (e.g., TUA 220-d, PBA 225-d) and pre-existing hierarchical entries (e.g., TUA 230-g, PBA 235-g, length field 240-g, compression indicator 245-g). For example, the memory system may receive a new (e.g., second non-sequential) command from the host system when the hierarchical entry queue 210 is filled (e.g., filled with pre-existing hierarchical entries, first commands before insertion 270). In this case, the new non-sequential entry may not be merged with the pre-existing hierarchical entries in the hierarchical entry queue 210.

[0062] As a result of receiving the new command (and as described herein), the memory system may push (e.g., output) the new command (e.g., new entry) to the backend entry queue 205, and may then test (e.g., analyze) the merge eligibility of the backend entry (e.g., new entry, TUA 220-d, PBA 225-d). For example, the memory system may compare the TUA 220-d of the backend entry in the backend entry queue 205 with the TUA 230-g of the hierarchical entry in the hierarchical entry queue 210. If the TUA 220-d of the backend entry tests as non-sequential to the TUA 230-g of the hierarchical entry, then the backend entry may not be eligible to merge with the hierarchical entry (e.g., tests negative for the merge test with the hierarchical entry).

[0063] As a result of the backend entry testing negative for the merge test with the hierarchical entry, the backend entry queue 205 may push (e.g., move) the hierarchical entry to the change log 215, and may push the backend entry to replace the hierarchical entry. For example, the memory system (e.g., via executing firmware) may manipulate (e.g., update) the fields of the change log 215 (e.g., TUA 250-a, PBA 255-a, length field 260-a, compression indicator 265-a) to add the previous hierarchical entry (e.g., TUA 230-g, PBA 235-g, length field 240-g, compression indicator 245-g) to the change log 215. After moving the previous hierarchical entry to the change log 215, the memory system (e.g., via executing firmware) may push the backend entry in the backend entry queue 205 to the hierarchical entry queue 210. For example, the memory system (e.g., via executing firmware) may manipulate (e.g., update) the fields of the hierarchical entry queue 210 (e.g., TUA 230-g, PBA 235-g, length field 240-g, compression indicator 245-g) to move the backend entry to the hierarchical entry queue 210 (e.g., move TUA 230-h, PBA 235-h to the hierarchical entry queue 210 after insertion 270).

[0064] In addition, the memory system (e.g., via executing firmware) may manipulate (e.g., update) other fields of the new change log 215 entry (e.g., the original non-sequential backend entry) when moving the backend entry to the change log 215. For example, the memory system may set the length field 240-h to zero (e.g., 0) and may set the compression indicator 245-h to false (e.g., off). As a result of the memory system manipulating the fields of the hierarchical entry queue 210 and the change log 215 (e.g., after insertion 270), the hierarchical entry queue 210 may contain the TUA 230-h and PBA 235-h of the original backend entries (e.g., TUA 220-d, PBA 225-d) of the backend entry queue 205, as well as the manipulated length field 240-h and compression indicator 245-h indicating that a non-sequential entry (e.g., the second command, the new entry) has replaced the original hierarchical entry, while the change log 215 (e.g., TUA 250-a, PBA 255-a, length field 260-a, compression indicator 265-a) may contain the original hierarchical entry (e.g., TUA 230-g, PBA 235-g, length field 240-g, compression field 245-g). The memory system may then mark the backend entry (e.g., the backend entry (TUA 220-d, PBA 225-d) of the backend entry queue 205) as complete and may release the backend entry.

[0065] Figure 3A , 3B and 3C illustrate an example of the direct compression mode 300 that supports change log compression according to an example as disclosed herein. The direct compression mode 300 may be implemented by aspects of the system 100 as described with reference to Figure 1 or implement aspects of the system 100 as described with reference to Figure 1 . The direct compression mode 300 may be implemented by a memory system configured to store data received from a host system and send the data to the host system in response to an access command (e.g., a read command or a write command) requested by the host system.

[0066] Figure 3A illustrates an example of the direct compression mode 300-a that supports change log compression according to an example as disclosed herein. The direct compression mode 300-a may be an example of a reverse merge direct compression mode and may be implemented by aspects of the system 100 as described with reference to Figure 1 or implement aspects of the system 100 as described with reference to Figure 1Aspects of the described system 100. The direct compression mode 300-a may be implemented by a memory system configured to store data received from a host system and send the data to the host system upon request by the host system using an access command (e.g., a read command or a write command). The direct compression mode may include the memory system immediately adding an entry to the change log as part of an access operation (e.g., storing a backend entry into the change log 315). In the direct compression mode, the memory system may be able to search the entries in the change log 315 and adjust the change log to improve compressibility. In contrast, the hierarchical compression mode may not enable the memory system to search the change log similarly.

[0067] The direct compression mode 300-a may include a backend entry queue 305 and a change log 315 during a pre-insertion (e.g., pre-change log entry adjustment) period 360 and a post-insertion period 365 (e.g., post-change log entry adjustment), where an insertion 370 indicates a change (e.g., compression) made to the backend entry queue 305, the change log 315, or both. The backend entry queue 305 may store instances of backend entries that may include a TUA 320 and a PBA 325 for inclusion in the change log 315. For example, when the memory system performs an access operation (e.g., a write operation, an erase operation, an unmapping operation), information to be added to the change log 315 may be generated. Information generated as part of an access operation may be referred to as a backend entry. Some memory systems may include hardware (e.g., a change log manager or engine) that efficiently adds information to and / or removes information from the change log 315. Thus, in some cases, the memory system may generate a backend entry as part of an access operation and may use the change log manager to insert the backend entry into the change log 315. In some instances of the direct compression mode, the memory system immediately stores an entry associated with the backend entry in the change log 315. The backend entry stored by the backend entry queue 305 may include: a TUA 320-a that stores the address "31"; and a PBA 325-a that stores die "0", plane "0", page "2", and offset "0".

[0068] The change log 315 may store instances of change log entries that may include index fields 330, TUA 335, PBA 340, length fields 345, compression indicators 350, and overlap indicators 355 before an insertion 370 (e.g., a pre-insertion period 360) and after the insertion 370 (e.g., a post-insertion period 365). For example, a change log entry stored by the change log 315 during the pre-insertion period 360 may include: an index field 330-a that stores an index position "4"; a TUA 335-a that stores an address "30"; a PBA 340-a that stores (respectively) die, plane, page, and offset "0, 0, 1, 3"; a length field 345-a that stores a length "0"; a compression indicator 350-a that stores a "false" indicator; and an overlap indicator 355-a that stores a "false" indicator. Similarly, one of the entries stored by the change log 315 during the post-insertion period 365 may include: an index field 330-a that stores an index position "4"; a TUA 335-a that stores an address "30"; a PBA 340-a that stores (respectively) die, plane, page, and offset "0, 0, 1, 3"; a length field 345-a that stores a length "1"; a compression indicator 350-a that stores a "true" indicator; and an overlap indicator 355-a that stores a "true" indicator. Another of the entries stored by the change log 315 during the post-insertion period 365 may include: an index field 330-b that stores an index position "5"; and TUA 335-b, PBA 340-b, length field 345-b, compression indicator 350-b, and overlap indicator 355-b, all of which are empty (e.g., do not store any data).

[0069] The memory system may use direct compression techniques when reverse-merging a backend entry (e.g., of the backend entry queue 305) with a pre-existing change log entry of the change log 315. For example, the memory system may receive a new (e.g., second) command from the host system. The memory system may then submit the new command as a new entry and may push the new entry to (e.g., output to) the backend entry queue 305. Subsequently, the memory system or its sub-component (e.g., the change log 315 manager) may search the change log 315 for a location to insert the backend entry (e.g., the new entry included in the backend entry queue 305). For example, the memory system may compare the TUA 320-a of the backend entry (e.g., the new entry included in the backend entry queue 305) with the TUA 335 included in the change log entry. By comparing the TUA 335, the memory system may locate in the change log a location where the TUA 320-a of the backend entry can be inserted into the change log 315 in a manner such that the backend entry can be sorted sequentially (e.g., linearly) with the pre-existing TUA 335 of the change log 315. The memory system may reference the index field 330 (e.g., index field 330-b) of the determined location for future change log 315 insertions.

[0070] Before inserting the backend entry into the determined change log location, the memory system may detect (e.g., determine using an insertion algorithm) that the backend entry can be merged with a previously inserted entry of the change log 315. Thus, the memory system may compare the TUA 335 of the neighboring entry (e.g., the entry containing the neighboring linear sequential index) at the determined location (e.g., index field 330-b) in the change log with the TUA of the backend entry (e.g., TUA 320-a). For example, in the case where the TUA 320-a of the backend entry is sequential to and greater than the TUA 335 of the previously inserted neighboring entry (e.g., the entry containing index field 330-a, TUA 335-a), the backend entry may be eligible for reverse-merging with the previously inserted neighboring entry (e.g., index field 330-a) (e.g., testing positive for reverse-merging with the previously inserted neighboring entry (e.g., index field 330-a)).

[0071] As a result of the back-end entry testing positive for reverse merge with a previously inserted entry, the back-end entry queue 305 may reverse merge the back-end entry with the previously inserted entry. For example, the memory system (e.g., via executing firmware) may manipulate (e.g., update) the fields of the previously inserted entry (e.g., the entry containing index field 330-a) to "merge" the back-end entry of the back-end entry queue 305 with the previously inserted entry of the change log 315. Thus, the memory system may increment the length field 345-a by 1 (e.g., +1), may set the compression indicator 350-a to true (e.g., on), and may update the overlap indicator 355. As a result of the memory system manipulating the fields of the previously inserted entry of the change log 315 (e.g., after the post-insertion period 365), the previously inserted entry (e.g., located at index field 330-a) may contain the TUA and PBA of the original previously inserted entry (e.g., TUA 335-a, PBA 340-a), as well as the manipulated length field 345-a and compression indicator 350-a indicating that sequential entries (e.g., new entry, original back-end entry) have been reverse merged with the original previously inserted entry of the change log 315. The memory system may then mark the back-end entry of the back-end entry queue 305 as complete and may free the back-end entry. Thus, the two entries may be "merged" without inserting the back-end entry into the change log 315.

[0072] In some instances, it may also be impossible to erase an entry in the change log 315 without updating the associated L2P mapping. Such a situation may result in conflicting entries in the same change log 315 after performing the compression techniques described herein. Thus, to support change log compression, the memory system may also include techniques for considering overlaps between entries and thereby enabling efficient searching of the change log 315. Efficient searching of the change log 315 may be useful in response to adding a new entry to the change log 315 using direct compression techniques or in response to updating the L2P mapping using the change log 315. The memory system may use two different techniques to support efficient searching. In a first instance, the memory system may use an overlap indicator. In a second instance, the memory system may use a technique for splitting entries.

[0073] In some instances, the memory system may use an overlap indicator 355 to indicate that a pre-existing entry in the change log 315 may overlap with a new entry. For example, in response to inserting a new entry into the change log 315, the memory system may evaluate the LBAs of adjacent (e.g., previously inserted) entries in the change log 315 to test for overlap possibilities. Thus, the memory system may determine that an adjacent entry in the change log 315 may overlap with the new entry and may set the overlap indicator 355-a of the new entry to true (e.g., on, 1). In some instances, the memory system may determine that a non-adjacent entry in the change log 315 may overlap with the new entry and may also set the overlap indicator 355-a of the new entry to true (e.g., on, 1). The overlap indicator 355 may indicate that some or all of the information in a given entry in the change log 315 is invalid, and when searching the change log 315 or when making changes to the L2P mapping based on the change log 315, the memory system should check other entries in the change log 315 near this entry.

[0074] In some other instances, the memory system may split (e.g., segment, divide into parts) a pre-existing entry in the change log 315 in response to adding a new compressed entry that may affect an existing entry in the change log 315. For example, before inserting a new entry, the memory system may determine that one of the adjacent entries in the change log 315 may overlap with the new entry. Thus, the memory system (e.g., a subset thereof) may split the pre-existing entry in the change log 315 into one or more (e.g., three) parts. For example, the memory system may split the entry into three entries: a left non-overlapping compressed entry, a right non-overlapping compressed entry, and an overlapping compressed entry. The memory system may then insert the new entry next to the overlapping compressed entry in the change log 315 and may free the back-end entry (e.g., the original new entry). Using the split-entry technique in response to adding an entry to the change log may consume more processing resources than using the overlap indicator 355 in response to adding an entry to the change log. However, compared to using the overlap indicator technique, using the split-entry technique may cause the memory system to use fewer processing resources to search the change log 315. For example, compared to using the overlap-bit technique in response to adding a new entry, a memory system using the split-entry technique in response to adding a new entry to the change log may make more modifications to the change log 315. In contrast, searching a change log 315 that has been organized using the split-entry technique may use fewer processing resources than the overlap-bit technique, because the memory system may be able to identify the correct information using a single entry during the search phase (instead of checking for different overlaps of multiple entries).

[0075] In some instances, the memory system may subsequently read the change log 315 in response to updating the L2P mapping based on the change log 315 or in response to adding a new backend entry to the change log 315. For example, the memory system may receive a read command that includes an LBA, and the memory system may search the change log 315 for the LBA. The memory system (e.g., a subset thereof, a search engine) may return an index field 330 (e.g., location, position) of the change log 315 that contains or is near the requested LBA. The returned index field 330 (e.g., position) may correspond to an existing entry of the change log 315. In the case where the returned index field 330 (e.g., position) of the change log 315 corresponds to an existing entry, the memory system may read the corresponding PBA 340. Conversely, the returned index field 330 (e.g., position) may not correspond to an existing entry of the change log 315. In the case where the returned index field 330 (e.g., position) of the change log 315 may not correspond to an existing entry, the memory system may determine that an adjacent entry of the returned index field 330 may be compressed (e.g., the compression indicator 350 may be set to true) and may overlap with the returned index field 330 (e.g., the overlap indicator 355 may be set to true). Accordingly, the memory system may read (e.g., generate, determine) the PBA 340 corresponding to the LBA according to the reverse merge compression mode as described herein.

[0076] Figure 3B An example of a direct compression mode 300-b that supports change log compression according to an example as disclosed herein is described. The direct compression mode 300-b may be an example of a forward merge direct compression mode and may be implemented by aspects of the system 100 as described with reference to Figure 1 or may implement aspects of the system 100 as described with reference to Figure 1 The direct compression mode 300-b may be implemented by a memory system configured to store data received from a host system and to send the data to the host system in response to a request by the host system using an access command (e.g., a read command or a write command).

[0077] The direct compression mode 300-b may include a backend entry queue 305 and a change log 315 during a pre-insertion (e.g., pre-change log entry adjustment) period 360 and a post-insertion period 365 (e.g., post-change log entry adjustment), where an insertion 370 indicates a change (e.g., compression) made to the backend entry queue 305, the change log 315, or both. The backend entry queue 305 may store instances of backend entries that may include TUAs 320 and PBAs 325. For example, a backend entry stored by the backend entry queue 305 may include: a TUA 320-b that stores the address "29"; and a PBA 325-b that stores die "0", plane "0", page "1", and offset "2". The change log 315 may store instances of change log entries that may include index fields 330, TUAs 335, PBAs 340, length fields 345, compression indicators 350, and overlap indicators 355 before (e.g., during the pre-insertion period 360) and after (e.g., during the post-insertion period 365) an insertion 370. For example, a change log entry stored by the change log 315 during the pre-insertion period 360 may include: an index field 330-c that stores the index position "4"; a TUA 335-c that stores the address "30"; a PBA 340-c that stores (respectively) die, plane, page, and offset "0, 0, 1, 3"; a length field 345-c that stores the length "1"; a compression indicator 350-c that stores a "true" indicator; and an overlap indicator 355-c that stores a "false" indicator. Similarly, one of the entries stored by the change log 315 during the post-insertion period 365 may include: an index field 330-c that stores the index position "4"; a TUA 335-c that stores the address "29"; a PBA 340-c that stores (respectively) die, plane, page, and offset "0, 0, 1, 2"; a length field 345-c that stores the length "2"; a compression indicator 350-c that stores a "true" indicator; and an overlap indicator 355-c that stores a "true" indicator. Another of the entries stored by the change log 315 during the post-insertion period 365 may include: an index field 330-d that stores the index position "5"; and TUAs 335-d, PBAs 340-d, length fields 345-d, compression indicators 350-d, and overlap indicators 355-d that are empty (e.g., do not store any data).

[0078] In some instances, the memory system may use direct compression techniques when forward-merging a backend entry (e.g., of the backend entry queue 305) with a pre-existing change log entry of the change log 315. For example, the memory system may receive a new (e.g., second) command from the host system. The memory system may then submit the new command as a new entry and may push the new entry to the backend entry queue 305. Subsequently, the memory system or its sub-component (e.g., the change log 315 manager) may search the change log 315 for a location to insert the backend entry (e.g., the new entry included in the backend entry queue 305). For example, the memory system may compare the TUA 320-b of the backend entry (e.g., the new entry included in the backend entry queue 305) with the TUA 335 included in the change log entry. By comparing the TUA 335, the memory system may locate in the change log a location where the TUA 320-b of the backend entry can be inserted into the change log 315 in a manner such that the backend entry can be sorted sequentially (e.g., linearly) with the pre-existing TUA 335 of the change log 315. The memory system may reference the index field 330 (e.g., index field 330-d) of the determined location for future change log 315 insertions.

[0079] Before inserting the backend entry into the determined change log location, the memory system may detect (e.g., determine using an insertion algorithm) that the backend entry can be merged with a previously inserted entry of the change log 315. Thus, the memory system may compare the TUA 335 of an adjacent entry (e.g., an entry containing an adjacent linear sequential index) at the determined location (e.g., index field 330-c) in the change log with the TUA of the backend entry (e.g., TUA 320-b). For example, in a case where the TUA 320-b of the backend entry is sequential to and less than the TUA 335 of a previously inserted adjacent entry (e.g., containing index field 330-c, TUA 335-c), the backend entry may be eligible for forward-merging with the previously inserted entry (e.g., index field 330-c) (e.g., testing positive for forward-merging with the previously inserted entry (e.g., index field 330-c)).

[0080] As a result of the positive outcome of the forward merge test of the backend entry with the previously inserted entry, the backend entry queue 305 may forward merge the backend entry with the previously inserted entry. For example, the memory system (e.g., via executing firmware) may manipulate (e.g., update) the fields of the previously inserted entry (e.g., the entry containing index field 330-a) to "merge" the backend entry of the backend entry queue 305 with the previously inserted entry of the change log 315. Thus, the memory system may increment the length field 345-c by 1 (e.g., +1), may decrement both the TUA 335-c and the PBA 340-c by 1 (e.g., -1), and may set the compression indicator 350-c to true (e.g., on). In some cases, decrementing the TUA 335-c and the PBA 340-c may cause the memory system to store the contents of the TUA 320-b and the PBA 325-b in the TUA 335-c and the PBA 340-c of the change log 315. As a result of the memory system manipulating the fields of the previously inserted entry of the change log 315 (e.g., after the post-insertion period 365), the previously inserted entry (e.g., located at index field 330-c) may contain the manipulated length field 345-c, the TUA 335-c, the PBA 340-c, and the compression indicator 350-c indicating that the sequential entry (e.g., the new entry, the backend entry) has been forward merged with the original previously inserted entry of the change log 315. The memory system may then mark the backend entry as complete and may release the backend entry. Thus, the two entries may be "merged" without inserting the backend entry into the change log 315.

[0081] To support change log compression, the memory system may also include techniques for considering overlaps between entries and thereby enabling efficient searching of the change log 315. Efficient searching of the change log 315 may be useful in response to adding a new entry to the change log 315 using direct compression techniques or in response to updating the L2P mapping using the change log 315. The memory system may use two different techniques to support efficient searching. In a first instance, the memory system may use an overlap indicator. In a second instance, the memory system may use techniques for splitting entries.

[0082] In some instances, a memory system may use an overlap indicator 355 to indicate that a pre-existing entry in the change log 315 may overlap with a new entry. For example, in response to inserting a new entry into the change log 315, the memory system may evaluate the LBAs of neighboring (e.g., previously inserted) entries in the change log 315 to test for overlap possibilities. Thus, the memory system may determine that a neighboring entry in the change log 315 may overlap with the new entry and may set the overlap indicator 355-c of the new entry to true (e.g., on, 1). The overlap indicator 355 may indicate that some or all of the information in a given entry in the change log 315 is invalid, and that when searching the change log 315 or when making changes to the L2P mapping based on the change log 315, the memory system should examine other entries in the change log 315 close to this entry. In some instances, the memory system may determine that a non-neighboring entry in the change log 315 may overlap with the new entry and may also set the overlap indicator 355-c of the new entry to true (e.g., on, 1).

[0083] In some other instances, the memory system may split (e.g., into several parts) an existing entry in the change log 315 in response to adding a new entry that may affect an existing entry in the change log 315. For example, before inserting a new entry, the memory system may determine that one of the neighboring entries in the change log 315 may overlap with the new entry. Thus, the memory system (e.g., a subset thereof) may split the pre-existing entry in the change log 315 into one or more (e.g., three) parts. For example, the memory system may split the entry into three entries: a left non-overlapping compressed entry, a right non-overlapping compressed entry, and an overlapping compressed entry. The memory system may then insert the new entry next to the overlapping compressed entry in the change log 315 and may free the backend entry (e.g., the original new entry). Using the split-entry technique in response to adding an entry to the change log may consume more processing resources than using the overlap indicator 355 in response to adding an entry to the change log. However, compared to using the overlap indicator technique, using the split-entry technique may cause the memory system to use fewer processing resources to search the change log 315.

[0084] In some instances, the memory system may subsequently read the change log 315 in response to updating the L2P mapping based on the change log 315 or in response to adding a new backend entry to the change log 315. For example, the memory system may receive an access command that includes the LBA of the location of the change log 315 and the memory system may search the change log 315 for the LBA. The memory system (e.g., a subset thereof, a search engine) may return an index field 330 (e.g., a location, a position) of the change log 315 that contains or is near the requested LBA. The returned index field 330 (e.g., the position) may correspond to an existing entry of the change log 315. In the case where the returned index field 330 (e.g., the position) of the change log 315 corresponds to an existing entry, the memory system may read the corresponding PBA 340. Conversely, the returned index field 330 (e.g., the position) may not correspond to an existing entry of the change log 315. In the case where the returned index field 330 (e.g., the position) of the change log 315 may not correspond to an existing entry, the memory system may determine that adjacent entries of the returned index field 330 may be compressed (e.g., the compression indicator 350 may be set to true) and may overlap with the returned index field 330 (e.g., the overlap indicator 355 may be set to true). Thus, the memory system may access (e.g., generate, determine) the PBA 340 corresponding to the LBA according to the reverse merge compression mode as described herein. In some cases, where the returned index field 330 (e.g., the position) of the change log 315 may not correspond to an existing entry and there are no adjacent entries that can be compressed, the memory system may create a new entry associated with the LBA in the access command.

[0085] Figure 3C An example of a direct compression mode 300-c that supports change log compression according to an example as disclosed herein is illustrated. The direct compression mode 300-c may be an example of a dual-mode merge compression mode and may be implemented by aspects of the system 100 as described in reference to Figure 1 or implement aspects of the system 100 as described in reference to Figure 1 The direct compression mode 300-c may be implemented by a memory system configured to store data received from a host system and send the data to the host system in response to a request by the host system using an access command (e.g., a read command or a write command).

[0086] The direct compression mode 300-c may include a backend entry queue 305 and a change log 315 during a pre-insertion (e.g., pre-change log entry adjustment) period 360 and a post-insertion period 365 (e.g., post-change log entry adjustment), where an insertion 370 indicates a change (e.g., compression) made to the backend entry queue 305, the change log 315, or both. The backend entry queue 305 may store instances of backend entries that may include a TUA 320 and a PBA 325. For example, a backend entry stored by the backend entry queue 305 may include: a TUA 320-c that stores the address "28"; and a PBA 325-c that stores die "0", plane "0", page "1", and offset "1". The change log 315 may store instances of change log entries that may include an index field 330, a TUA 335, a PBA 340, a length field 345, a compression indicator 350, and an overlap indicator 355 before (e.g., during the pre-insertion period 360) and after (e.g., during the post-insertion period 365) an insertion 370. For example, a change log entry stored by the change log 315 during the pre-insertion period 360 may include: an index field 330-e that stores the index position "3"; a TUA 335-e that stores the address "27"; a PBA 340-e that stores (respectively) die, plane, page, and offset "0, 0, 1, 0"; a length field 345-e that stores the length "0"; a compression indicator 350-e that stores a "false" indicator; and an overlap indicator 355-e that stores a "false" indicator. Another of the change log entries stored by the change log 315 during the pre-insertion period 360 may include: an index field 330-f that stores the index position "4"; a TUA 335-f that stores the address "29"; a PBA 340-f that stores (respectively) die, plane, page, and offset "0, 0, 1, 2"; a length field 345-f that stores the length "2"; a compression indicator 350-f that stores a "true" indicator; and an overlap indicator 355-f that stores a "false" indicator. Similarly, one of the entries stored by the change log 315 during the post-insertion period may include: an index field 330-e that stores the index position "3"; a TUA 335-e that stores the address "27"; a PBA 340-e that stores (respectively) die, plane, page, and offset "0, 0, 1, 0"; a length field 345-e that stores the length "3"; a compression indicator 350-e that stores a "true" indicator; and an overlap indicator 355-e that stores a "false" indicator.Another one of the entries stored by the change log 315 during the post-insertion period 365 may include: an index field 330-f that stores the index position "4", and TUA 335-f, PBA 340-f, length field 345-f, compression indicator 350-f, and overlap indicator 355-f, which are empty (e.g., do not store any data).

[0087] In some instances, the memory system may use direct compression techniques when performing a dual-mode merge of a backend entry (e.g., from the backend entry queue 305) with a pre-existing change log entry in the change log 315. For example, the memory system may receive a new (e.g., second) command from the host system. The memory system may then submit the new command as a new entry and may push the new entry into the backend entry queue 305. Subsequently, the memory system or a sub-component thereof (e.g., the change log 315 manager) may search the change log 315 for a location to insert the backend entry (e.g., the new entry included in the backend entry queue 305). For example, the memory system may compare the TUA 320-c of the backend entry (e.g., the new entry included in the backend entry queue 305) with the TUA 335 included in the change log entry. By comparing the TUA 335, the memory system may locate in the change log a position where the TUA 320-c of the backend entry can be inserted into the change log 315 in a manner such that the backend entry can be sorted sequentially (e.g., linearly) with the pre-existing TUA 335 of the change log 315. In some instances, based on this comparison of the TUA 335, the memory system (e.g., the change log 315 manager) may determine a position between two pre-existing entries in the change log 315 into which to "insert" the backend entry. The memory system may reference the index field 330 of the determined position (e.g., between index field 330-e and index field 330-f) for future insertions into the change log 315.

[0088] Before inserting a backend entry into the determined change log location, the memory system may detect (e.g., determine using an insertion algorithm) that the backend entry can be merged with a previously inserted entry of the change log 315. For example, the memory system may compare the TUA 335 of an adjacent entry of the change log 315 (e.g., an entry containing adjacent linear sequential indices) with the TUA of the backend entry (e.g., TUA 320-c). In the case where the TUA 320-c of the backend entry is sequential to and less than the TUA 335 of one of the previously inserted adjacent entries (e.g., an entry containing index field 330-f, TUA 335-f), the backend entry may be eligible for forward merge with the previously inserted entry (e.g., index field 330-f) (e.g., positive for the forward merge test with the previously inserted entry (e.g., index field 330-f)). Similarly, in the case where the TUA 320-c of the backend entry is sequential to and greater than the TUA 335 of the previously inserted adjacent entry (e.g., an entry containing index field 330-e, TUA 335-e), the backend entry may be eligible for reverse merge with the previously inserted entry (e.g., index field 330-e) (e.g., positive for the reverse merge test with the previously inserted entry (e.g., index field 330-e)). In the case where the backend entry may be positive for both the forward merge and the backend merge tests, the memory system may determine that the backend entry may be positive for the dual-mode merge test.

[0089] As a result of the back-end entry testing positive for dual-mode merge with previously inserted entries (e.g., index field 330-e, index field 330-f), the back-end entry queue 305 may dual-mode merge the back-end entry with the two previously inserted entries (e.g., forward merge and reverse merge). For example, the memory system (e.g., via executing firmware) may manipulate (e.g., update) the fields of the first of the previously inserted entries (e.g., index field 330-e) to "merge" both the back-end entry and the second of the previously inserted entries (e.g., index field 330-f) with the first of the previously inserted entries (e.g., index field 330-e). Thus, similar to the forward merge, the memory system may increment the length field 345-f of the second of the previously inserted entries by 1 (e.g., +1), may decrement both the TUA 335-f and the PBA 340-f by 1 (e.g., -1), and may set the compression indicator 350-f to true (e.g., on). Similar to the reverse merge, the memory system may also increment the length field 345-e of the first of the previously inserted entries by 1 (e.g., +1), and may set the compression indicator 350-e to true (e.g., on). In other instances, based on the memory system (e.g., the change log 315 manager) determining an index location different from the index field 330-f, the memory system may perform two forward merges or two reverse merges instead of both a forward merge and a reverse merge (e.g., dual-mode merge).

[0090] As a result of the memory system manipulating the fields of the first of the previously inserted entries (e.g., index field 330-e) (e.g., after the post-insertion period 365), the first of the previously inserted entries (e.g., index field 330-e) may contain the manipulated length field 345-e, TUA 335-e, PBA 340-e, and compression indicator 350-e indicating that three sequential entries (e.g., the back-end entry, the first of the previously inserted entries, and the second of the previously inserted entries) have been dual-mode merged. The memory system may then mark the back-end entry as complete and may release the back-end entry. The memory system (e.g., the change log 315 manager) may also remove the second of the previously inserted entries (e.g., previously indexed as index field 330-f) from the change log 315. Thus, the three entries may be "merged" without inserting the back-end entry into the change log 315.

[0091] To support change log compression, the memory system may also include techniques for considering overlaps between entries and thus enabling efficient search of the change log 315. Efficient search of the change log 315 may be useful in response to adding a new entry to the change log 315 using direct compression techniques or in response to updating the L2P mapping using the change log 315. The memory system may use two different techniques to support efficient search. In a first instance, the memory system may use an overlap indicator. In a second instance, the memory system may use a technique for splitting entries.

[0092] In some instances, the memory system may use an overlap indicator 355 to indicate that a pre-existing entry in the change log 315 may overlap with a new entry. For example, in response to inserting a new entry into the change log 315, the memory system may evaluate the LBAs of neighboring (e.g., previously inserted) entries in the change log 315 to test for overlap possibilities. Thus, the memory system may determine that a neighboring entry in the change log 315 may overlap with the new entry and may set the overlap indicator 355-e of the new entry to true (e.g., on, 1). In some instances, the memory system may determine that a non-neighboring entry in the change log 315 may overlap with the new entry and may also set the overlap indicator 355-e of the new entry to true (e.g., on, 1). The overlap indicator 355 may indicate that some or all of the information in a given entry in the change log 315 is invalid, and when searching the change log 315 or when making changes to the L2P mapping based on the change log 315, the memory system should check other entries in the change log 315 near this entry.

[0093] In some other instances, the memory system may split (e.g., divide into several parts) a pre-existing entry in the change log 315 in response to adding a new entry that may affect an existing entry in the change log 315. For example, before inserting a new entry, the memory system may determine that one of the neighboring entries in the change log 315 may overlap with the new entry. Thus, the memory system (e.g., a subset thereof) may split the pre-existing entry in the change log 315 into one or more (e.g., three) parts. For example, the memory system may split the entry into three entries: a left non-overlapping compressed entry, a right non-overlapping compressed entry, and an overlapping compressed entry. The memory system may then insert the new entry next to the overlapping compressed entry in the change log 315 and may free the backend entry (e.g., the original new entry). Using the split entry technique in response to adding an entry to the change log may consume more processing resources than using the overlap indicator 355 in response to adding an entry to the change log. However, compared to using the overlap indicator technique, using the split entry technique may enable the memory system to use fewer processing resources to search the change log 315.

[0094] In some instances, the memory system may then read the change log 315 in response to updating the L2P mapping based on the change log 315 or in response to adding a new backend entry to the change log 315. For example, the memory system may receive an access command that includes an LBA of the location of the change log 315 and the memory system may search the change log 315 for the LBA. The memory system (e.g., a subset thereof, a search engine) may return an index field 330 (e.g., a location, a position) of the change log 315 that contains or is near the requested LBA. The returned index field 330 (e.g., the position) may correspond to an existing entry of the change log 315. In the case where the returned index field 330 (e.g., the position) of the change log 315 corresponds to an existing entry, the memory system may read the corresponding PBA 340. Conversely, the returned index field 330 (e.g., the position) may not correspond to an existing entry of the change log 315. In the case where the returned index field 330 (e.g., the position) of the change log 315 may not correspond to an existing entry, the memory system may determine that neighboring entries of the returned index field 330 may be compressible (e.g., the compression indicator 350 may be set to true) and may overlap with the returned index field 330 (e.g., the overlap indicator 355 may be set to true). Thus, the memory system may access (e.g., generate, determine) the PBA 340 corresponding to the LBA according to the reverse merge compression mode as described herein. In some cases, where the returned index field 330 (e.g., the position) of the change log 315 may not correspond to an existing entry and there are no neighboring entries that are compressible, the memory system may create a new entry associated with the LBA in the access command.

[0095] Figure 4 FIG. 400 is a block diagram of a memory system 420 that supports change log compression according to an example as disclosed herein. The memory system 420 may be an example of an aspect of the memory system as described with reference to Figures 1 to 3C The memory system 420 or its various components may be examples of components for performing various aspects of the change log compression as described herein. For example, the memory system 420 may include a receiver 425, an identification component 430, an entry modifier 435, a determination component 440, a write component 445, an increment component 450, a setting component 455, a maintenance component 460, a comparator 465, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0096] The receiver 425 may be configured to or otherwise support components for receiving a first command to write first data to a first block of a memory device, the first block being associated with a first logical address and a first physical address. The identification component 430 may be configured to or otherwise support components for identifying an entry in a change log associated with a second logical address and a second physical address in response to receiving the first command. The entry modifier 435 may be configured to or otherwise support components for modifying the entry associated with the change log to include information associated with the first command in response to receiving the first command and identifying the entry, the entry of the change log including a first field indicating a block address of the memory device, a second field indicating a data length indicated by the entry, and a third field indicating a compression state, the compression state indicating whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device.

[0097] In some instances, the identification component 430 may be configured to or otherwise support components for identifying the second logical address and the second physical address to write second data to a second block of the memory device. In some instances, the determination component 440 may be configured to or otherwise support components for determining whether the first logical address and the second logical address are sequential or non-sequential.

[0098] In some instances, to support modifying the entry associated with the change log, the write component 445 may be configured to or otherwise support components for overwriting the first field of the entry associated with the change log to indicate a first block address associated with the first block of the memory device based at least in part on the first logical address being before the second logical address. In some instances, to support modifying the entry associated with the change log, the increment component 450 may be configured to or otherwise support components for incrementing a value of the second field of the entry associated with the change log to indicate a data length indicating the first data and the second data, where the data length includes a sum of a first length of the first data and a second length of the second data. In some instances, to support modifying the entry associated with the change log, the set component 455 may be configured to or otherwise support components for setting a value of the third field of the entry associated with the change log to indicate that the entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, or a combination thereof.

[0099] In some instances, to support modifying the entry associated with the change log, the maintenance component 460 may be configured to or otherwise support a component for maintaining the first field of the entry associated with the change log at least partially based on the first logical address being after the second logical address to indicate a second block address associated with the second block of the memory device. In some instances, to support modifying the entry associated with the change log, the increment component 450 may be configured to or otherwise support a component for incrementing the value of the second field of the entry associated with the change log to indicate a data length indicating the first data and the second data, where the data length includes the sum of a first length of the first data and a second length of the second data. In some instances, to support modifying the entry associated with the change log, the setting component 455 may be configured to or otherwise support a component for setting the value of the third field of the entry associated with the change log to indicate that the entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, or a combination thereof.

[0100] In some instances, to support modifying the entry associated with the change log, the write component 445 may be configured to or otherwise support a component for writing information associated with the first command to the second entry of the change log at least partially based on determining whether the first logical address and the second logical address are non-sequential.

[0101] In some instances, the identification component 430 may be configured to or otherwise support a component for identifying the second entry in the change log in response to receiving the first command, the second entry being associated with a third command. In some instances, the identification component 430 may be configured to or otherwise support a component for identifying a third logical address and a third physical address to write third data to a third block of the memory device. In some instances, the determination component 440 may be configured to or otherwise support a component for determining that the third logical address is before the first logical address and the third logical address is after the second logical address. In some instances, the maintenance component 460 may be configured to or otherwise support a component for modifying the entry associated with the change log at least partially based on determining that the third logical address is before the first logical address and the third logical address is after the second logical address.

[0102] In some instances, to support modifying the entry associated with the change log, the maintenance component 460 may be configured to or otherwise support a component that maintains the first field of the entry in the change log to indicate a second block address associated with the second block of the memory device, at least in part based on the third logical address being before the first logical address and the third logical address being after the second logical address. In some instances, to support modifying the entry associated with the change log, the increment component 450 may be configured to or otherwise support a component that increments the value of the second field of the entry in the change log to indicate a data length indicative of the first data, the second data, and the third data, where the data length includes the sum of a first length of the first data, a second length of the second data, and a third length of the third data. In some instances, to support modifying the entry associated with the change log, the setting component 455 may be configured to or otherwise support a component that sets the value of the third field of the entry in the change log to indicate that the second entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, the third logical address, the third physical address, or a combination thereof.

[0103] In some instances, the determination component 440 may be configured to or otherwise support a component that determines whether the first logical address associated with the first command matches the second logical address in the change log, at least in part based on performing a search operation within the change log. In some instances, the entry modifier 435 may be configured to or otherwise support a component that modifies the entry associated with the change log. In some instances, the write component 445 may be configured to or otherwise support a component that writes information associated with the first command to a second entry in the change log, the second entry including a fourth field that indicates an overlap between the entry and the second entry, at least in part based on the first logical address associated with the first command matching the second logical address in the change log.

[0104] In some instances, to support performing the search operation within the change log, the comparator 465 may be configured to or otherwise support a component that compares the one or more corresponding entries in the change log that include one or more corresponding logical addresses associated with one or more corresponding entries with the first logical address associated with the first command to determine whether the one or more corresponding logical addresses associated with the one or more corresponding entries match the first logical address associated with the first command.

[0105] In some instances, to support performing the search operation within the change log, the identification component 430 may be configured to or otherwise support a component for identifying one or more corresponding entries in the change log that indicate a corresponding overlap with one or more other entries in the change log.

[0106] In some instances, to support modifying the entry associated with the change log, the entry modifier 435 may be configured to or otherwise support a component for splitting the entry in the change log into two separate entries, the two separate entries including a first entry for writing the first data to the first block of the memory device and a second entry for writing the second data to the second block of the memory device.

[0107] Figure 5 The figure presents a flow chart illustrating a method 500 for supporting change log compression according to an example as disclosed herein. Operations of method 500 may be implemented by a memory system or its components as described herein. For example, operations of method 500 may be performed by a memory system as described with reference to Figures 1 to 4 that is described. In some instances, the memory system may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0108] At 505, the method may include receiving a first command to write first data to a first block of a memory device, the first block being associated with a first logical address and a first physical address. The operation of 505 may be performed according to an example as disclosed herein. In some instances, aspects of the operation of 505 may be performed by the receiver 425 as described with reference to Figure 4 that is described.

[0109] At 510, the method may include identifying an entry in the change log that is associated with a second logical address and a second physical address in response to receiving the first command. The operation of 510 may be performed according to an example as disclosed herein. In some instances, aspects of the operation of 510 may be performed by the identification component 430 as described with reference to Figure 4 that is described.

[0110] At 515, the method may include modifying the entry associated with the change log to include information associated with the first command in response to receiving the first command and identifying the entry, the entry of the change log including a first field indicating a block address of the memory device, a second field indicating a data length indicated by the entry, and a third field indicating a compression state, the compression state indicating whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device. The operation of 515 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 515 may be performed by an entry modifier 435 as described with reference to Figure 4 as described.

[0111] In some examples, a device as described herein may perform one or several methods, such as method 500. The device may include operations, features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0112] Aspect 1: A method, device, or non-transitory computer-readable medium including operations, features, circuitry, logic, components, or instructions for any of the following, or any combination thereof: receiving a first command to write first data to a first block of a memory device, the first block being associated with a first logical address and a first physical address; in response to receiving the first command, identifying an entry in a change log associated with a second logical address and a second physical address; and in response to receiving the first command and identifying the entry, modifying the entry associated with the change log to include information associated with the first command, the entry of the change log including a first field indicating a block address of the memory device, a second field indicating a data length indicated by the entry, and a third field indicating a compression state, the compression state indicating whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device.

[0113] Aspect 2: The method, device, or non-transitory computer-readable medium according to aspect 1, further including operations, features, circuitry, logic, components, or instructions for any of the following, or any combination thereof: identifying the second logical address and the second physical address to write second data to a second block of the memory device; and determining whether the first logical address and the second logical address are sequential or non-sequential.

[0114] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to Aspect 2, wherein modifying the entry associated with the change log comprises operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: overwriting the first field of the entry associated with the change log to indicate a first block address associated with the first block of the memory device, at least in part based on the first logical address being before the second logical address; incrementing a value of the second field of the entry associated with the change log to indicate a data length indicating the first data and the second data, wherein the data length includes a sum of a first length of the first data and a second length of the second data; and setting a value of the third field of the entry associated with the change log to indicate that the entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, or a combination thereof.

[0115] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 2 to 3, wherein modifying the entry associated with the change log comprises operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: maintaining the first field of the entry associated with the change log to indicate a second block address associated with the second block of the memory device, at least in part based on the first logical address being after the second logical address; incrementing a value of the second field of the entry associated with the change log to indicate a data length indicating the first data and the second data, wherein the data length includes a sum of a first length of the first data and a second length of the second data; and setting a value of the third field of the entry associated with the change log to indicate that the entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, or a combination thereof.

[0116] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 2 to 4, wherein modifying the entry associated with the change log comprises operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: writing information associated with the first command to a second entry in the change log, at least in part based on determining that the first logical address and the second logical address are non-sequential.

[0117] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 2 to 5, further comprising operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: identifying a second entry in the change log in response to receiving the first command, the second entry being associated with a third command; identifying a third logical address and a third physical address to write third data to a third block of the memory device; and determining that the third logical address is before the first logical address and the third logical address is after the second logical address; and wherein modifying the entry associated with the change log is at least partially based on determining that the third logical address is before the first logical address and the third logical address is after the second logical address.

[0118] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to aspect 6, wherein modifying the entry associated with the change log comprises operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: maintaining the first field of the entry in the change log to indicate a second block address associated with the second block of the memory device at least partially based on the third logical address being before the first logical address and the third logical address being after the second logical address; incrementing a value of a second field of the entry in the change log to indicate a data length indicating the first data, the second data, and the third data, wherein the data length includes a sum of a first length of the first data, a second length of the second data, and a third length of the third data; and setting a value of a third field of the entry in the change log to indicate that the second entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, the third logical address, the third physical address, or a combination thereof.

[0119] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 7, further comprising operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: determining that the first logical address associated with the first command matches the second logical address in the change log associated with the second command at least partially based on performing a search operation within the change log; wherein modifying the entry associated with the change log comprises writing information associated with the first command to a second entry in the change log, the second entry including a fourth field that indicates an overlap between the entry and the second entry at least partially based on the first logical address associated with the first command matching the second logical address in the change log.

[0120] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to aspect 8, wherein performing the search operation within the change log includes operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: comparing the one or more respective entries in the change log that include one or more respective logical addresses associated with one or more corresponding entries with the first logical address associated with the first command to determine whether the one or more respective logical addresses associated with the one or more respective entries match the first logical address associated with the first command.

[0121] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 8 to 9, wherein performing the search operation within the change log includes operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: identifying one or more respective entries in the change log that indicate a respective overlap with one or more other entries in the change log.

[0122] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 8 to 10, wherein modifying the entry associated with the change log includes operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: splitting the entry in the change log into two separate entries, the two separate entries including a first entry for writing the first data to the first block of the memory device and a second entry for writing second data to the second block of the memory device.

[0123] It should be noted that the described technology includes possible embodiments, and the operations and steps may be rearranged or otherwise modified, and other embodiments are possible. In addition, parts from two or more methods may be combined.

[0124] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, or signaling symbols referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have a variety of bit widths.

[0125] The terms "electrically connected", "electrically contacted", "connected", and "coupled" can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be electrically connected (or electrically contacted or connected or coupled) to each other if there is any conductive path between the components that can support the flow of signals between the components at any given time. At any given time, the conductive path between components that are electrically connected (or electrically contacted or connected or coupled) to each other can be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components can be a direct conductive path between the components, or the conductive path between the connected components can be an indirect conductive path that can include intermediate components (such as switches, transistors, or other components). In some instances, the flow of signals between the connected components can be interrupted for a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0126] The term "coupled" (e.g., "electrically coupled") can refer to a condition of moving from an open circuit relationship between components (where signals cannot currently be communicated between the components through a conductive path) to a closed circuit relationship between components (where signals can be communicated between the components through a conductive path). If a component (such as a controller) couples other components together, the component initiates a change that allows signals to flow between the other components through a conductive path that previously did not permit signal flow.

[0127] The term "isolated" refers to a relationship between components where signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, if a switch located between components is open, the two components separated by the switch are isolated from each other. If a controller isolates two components, the controller causes a change that prevents signals from flowing between the components through a conductive path that previously permitted signal flow.

[0128] The terms "if", "when", "based on", or "at least partially based on" can be used interchangeably. In some instances, if the terms "if", "when", "based on", or "at least partially based on" are used to describe the connection between conditional actions, conditional processes, or parts of a process, the terms can be interchangeable.

[0129] The term "responsive to" can refer to a condition or action that occurs at least in part (if not entirely) as a result of a previous condition or action. For example, a first condition or action can be executed and a second condition or action can occur at least in part as a result of the previous condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0130] Additionally, the term "directly in response to" may refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of the previous condition or action occurring, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of the condition or action occurring, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Any condition or action described herein as being performed "based on," "at least partially based on," or "in response to" some other step, action, event, or condition may additionally or alternatively (e.g., in an alternative instance) be performed "directly in response to" this other condition or action, unless otherwise specified.

[0131] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In some other instances, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation or by any other doping means during the initial formation or growth of the substrate.

[0132] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, then the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, then the transistor may be "turned off" or "deactivated".

[0133] The descriptions set forth herein describe example configurations in conjunction with the accompanying drawings and do not represent all examples that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "better than other examples". The detailed description includes specific details to provide an understanding of the described technology. However, the technology may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0134] In the figures, similar components or features may have the same reference labels. Additionally, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that differentiates the similar components. When only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0135] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the described functions may be implemented using software, hardware, firmware, hardwiring, or any combination thereof executed by a processor. The features implementing the functions may also be physically located at various places, including being distributed such that portions of the functions are implemented at different physical locations.

[0136] For example, the various illustrative blocks and components described in connection with the present disclosure may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0137] As used herein (including in the claims), the "or" as used in a list of items (e.g., a list that begins with a phrase such as "at least one of... " or "one or more of... ") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0138] Computer-readable media includes both non-transitory computer storage media and communication media, the communication media including any media that facilitates transfer of a computer program from one place to another. The non-transitory storage media may be any available media that can be accessed by a general or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store the desired program code components in the form of instructions or data structures and that can be accessed by a general or special purpose computer or a general or special purpose processor. Also, any connection is properly termed a computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology (such as infrared, radio, and microwave), then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology (such as infrared, radio, and microwave) is included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0139] This description is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Memory device; and a controller coupled to the memory device and configured to cause the apparatus to: receiving a first command to write first data to a first block of the memory device, the first block being associated with a first logical address and a first physical address; identifying an entry in a change log associated with a second logical address and a second physical address in response to receiving the first command; and In response to receiving the first command and identifying the entry, modifying the entry associated with the change log to include information associated with the first command, the entry of the change log including a first field indicating a block address of the memory device, a second field indicating a length of data indicated by the entry, and a third field indicating a compression status, the compression status indicating whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device.

2. The apparatus of claim 1 , wherein the controller is configured to cause the apparatus to: identifying the second logical address and the second physical address to write second data to a second block of the memory device; and A determination is made as to whether the first logical address and the second logical address are sequential or non-sequential.

3. The apparatus of claim 2, wherein to modify the entry associated with the change log, the controller is configured to cause the apparatus to: overwriting the first field of the entry associated with the change log to indicate a first block address associated with the first block of the memory device based at least in part on the first logical address being before the second logical address; incrementing a value of the second field of the entry associated with the change log to indicate a data length indicating the first data and the second data, wherein the data length comprises a sum of a first length of the first data and the second length of the second data; and The value of the third field of the entry associated with the change log is set to indicate that the entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, or a combination thereof.

4. The apparatus of claim 2, wherein to modify the entry associated with the change log, the controller is configured to cause the apparatus to: maintaining the first field of the entry associated with the change log to indicate a second block address associated with the second block of the memory device based at least in part on the first logical address being subsequent to the second logical address; incrementing a value of the second field of the entry associated with the change log to indicate a data length indicating the first data and the second data, wherein the data length comprises a sum of a first length of the first data and a second length of the second data; and The value of the third field of the entry associated with the change log is set to indicate that the entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, or a combination thereof.

5. The apparatus of claim 2, wherein to modify the entry associated with the change log, the controller is configured to cause the apparatus to: Information associated with the first command is written in a second entry of the change log based at least in part on determining whether the first logical address and the second logical address are non-sequential.

6. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: identifying a second entry in the change log in response to receiving the first command, the second entry being associated with a third command; identifying a third logical address and a third physical address to write third data to a third block of the memory device; and determining whether the third logical address is before the first logical address and whether the third logical address is after the second logical address, Wherein modifying the entry associated with the change log is based at least in part on determining whether the third logical address is before the first logical address and whether the third logical address is after the second logical address.

7. The apparatus of claim 6, wherein to modify the entry associated with the change log, the controller is configured to cause the apparatus to: maintaining the first field of the entry in the change log to indicate a second block address associated with the second block of the memory device based at least in part on the third logical address being before the first logical address and the third logical address being after the second logical address; incrementing a value of the second field of the entry in the change log to indicate data lengths indicating the first data, the second data, and the third data, wherein the data length comprises a sum of a first length of the first data, a second length of the second data, and a third length of the third data; and The value of the third field of the entry in the change log is set to indicate that the second entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, the third logical address, the third physical address, or a combination thereof.

8. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: determining whether the first logical address associated with the first command matches the second logical address in the change log based at least in part on performing a search operation within the change log, wherein to modify the entry associated with the change log, the controller is configured to cause the apparatus to: Writing information associated with the first command into a second entry in the change log, the second entry including a fourth field indicating an overlap between the entry and the second entry based at least in part on the first logical address associated with the first command matching the second logical address in the change log.

9. The apparatus of claim 8, wherein to perform the search operation within the change log, the controller is configured to cause the apparatus to: The one or more corresponding entries in the change log that contain one or more corresponding logical addresses associated with the one or more corresponding entries are compared with the first logical address associated with the first command to determine whether the one or more corresponding logical addresses associated with the one or more corresponding entries match the first logical address associated with the first command.

10. The apparatus of claim 8, wherein to perform the search operation within the change log, the controller is configured to cause the apparatus to: One or more corresponding entries in the change log are identified that indicate corresponding overlaps with one or more other entries in the change log.

11. The apparatus of claim 8, wherein to modify the entry associated with the change log, the controller is configured to cause the apparatus to: The entry in the change log is split into two separate entries, the two separate entries including a first entry to write the first data to the first block of the memory device and a second entry to write second data to the second block of the memory device.

12. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a first command to write first data to a first block of a memory device, the first block being associated with a first logical address and a first physical address; identifying an entry in a change log associated with a second logical address and a second physical address in response to receiving the first command; and In response to receiving the first command and identifying the entry, modifying the entry associated with the change log to include information associated with the first command, the entry of the change log including a first field indicating a block address of the memory device, a second field indicating a length of data indicated by the entry, and a third field indicating a compression status, the compression status indicating whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to: identifying the second logical address and the second physical address to write second data to a second block of the memory device; and A determination is made as to whether the first logical address and the second logical address are sequential or non-sequential.

14. The non-transitory computer-readable medium of claim 13, wherein to modify the entry associated with the change log, the instructions, when executed by the processor of the electronic device, cause the electronic device to: overwriting the first field of the entry associated with the change log to indicate a first block address associated with the first block of the memory device based at least in part on the first logical address being before the second logical address; incrementing a value of the second field of the entry associated with the change log to indicate a data length indicating the first data and the second data, wherein the data length comprises a sum of a first length of the first data and a second length of the second data; and The value of the third field of the entry associated with the change log is set to indicate that the entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, or a combination thereof.

15. The non-transitory computer-readable medium of claim 13, wherein to modify the entry associated with the change log, the instructions, when executed by the processor of the electronic device, cause the electronic device to: maintaining the first field of the entry associated with the change log to indicate a second block address associated with the second block of the memory device based at least in part on the first logical address following the second logical address; incrementing a value of the second field of the entry associated with the change log to indicate a data length indicating the first data and the second data, wherein the data length comprises a sum of a first length of the first data and a second length of the second data; and The value of the third field of the entry associated with the change log is set to indicate that the entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, or a combination thereof.

16. The non-transitory computer-readable medium of claim 13, wherein to modify the entry associated with the change log, the instructions, when executed by the processor of the electronic device, cause the electronic device to: Information associated with the first command is written in a second entry of the change log based at least in part on determining whether the first logical address and the second logical address are non-sequential.

17. The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to: identifying a second entry in the change log in response to receiving the first command, the second entry being associated with a third command; identifying a third logical address and a third physical address to write third data to a third block of the memory device; and determining whether the third logical address is before the first logical address and whether the third logical address is after the second logical address, Wherein modifying the entry associated with the change log is based at least in part on determining whether the third logical address is before the first logical address and whether the third logical address is after the second logical address.

18. The non-transitory computer-readable medium of claim 17, wherein to modify the entry associated with the change log, the instructions, when executed by the processor of the electronic device, cause the electronic device to: maintaining the first field of the entry in the change log to indicate a second block address associated with the second block of the memory device based at least in part on the third logical address being before the first logical address and the third logical address being after the second logical address; incrementing a value of the second field of the entry in the change log to indicate data lengths indicating the first data, the second data, and the third data, wherein the data length comprises a sum of a first length of the first data, a second length of the second data, and a third length of the third data; and The value of the third field of the entry in the change log is set to indicate that the second entry is associated with the first logical address, the first physical address, the second logical address, the second physical address, the third logical address, the third physical address, or a combination thereof.

19. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to: determining whether the first logical address associated with the first command matches the second logical address in the change log based at least in part on performing a search operation within the change log, wherein to modify the entry associated with the change log, the instructions, when executed by the processor of the electronic device, cause the electronic device to: Writing information associated with the first command into a second entry in the change log, the second entry including a fourth field indicating an overlap between the entry and the second entry based at least in part on the first logical address associated with the first command matching the second logical address in the change log.

20. A method comprising: receiving a first command to write first data to a first block of a memory device, the first block being associated with a first logical address and a first physical address; identifying an entry in a change log associated with a second logical address and a second physical address in response to receiving the first command; and In response to receiving the first command and identifying the entry, modifying the entry associated with the change log to include information associated with the first command, the entry of the change log including a first field indicating a block address of the memory device, a second field indicating a length of data indicated by the entry, and a third field indicating a compression status, the compression status indicating whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device.

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