Chip information verification method and device, equipment, medium and program product

Abstract

The invention provides a chip information verification method and device, electronic equipment, a storage medium and a program product, and relates to the technical field of chips, in particular to the technical field of chip design and the technical field of form verification. According to the specific implementation scheme, reference information is generated based on design information of a chip, and the reference information comprises identification information of a signal path used for transmitting signals in the chip; based on the reference information, information extraction is carried out on the design information of the chip to obtain target design information, and the target design information comprises attribute information of the signal path; acquiring constraint information of a signal transmitted in the signal path based on the reference information; and under the condition that the constraint information is a constraint condition, performing form verification on the connectivity of the signal path based on the target design information to obtain a verification result.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, in particular to the field of chip design technology and formal verification technology, and specifically relates to a chip information verification method, apparatus, electronic device, storage medium, and program product. Background Art

[0002] The preparation process of a chip includes multiple links, such as functional design, architecture design, circuit design, physical design, and manufacturing. In the whole preparation process, each link is closely related, and the previous link is the basis for the success of the next link. Among these multiple links, the verification of the design information of the functional design becomes a key influencing factor. Summary of the Invention

[0003] The present disclosure provides a chip information verification method, apparatus, electronic device, storage medium, and program product.

[0004] According to one aspect of the present disclosure, there is provided a chip information verification method, including: generating reference information based on the design information of the chip, where the reference information includes identification information of signal paths for transmitting signals in the chip; performing information extraction on the design information of the chip based on the reference information to obtain target design information, where the target design information includes attribute information of the signal paths; obtaining constraint information of the signals transmitted in the signal paths based on the reference information; and performing formal verification on the connectivity of the signal paths based on the target design information when the constraint information is a constraint condition to obtain a verification result.

[0005] According to another aspect of the present disclosure, there is provided a chip information verification apparatus, including: a reference generation module for generating reference information based on the design information of the chip, where the reference information includes identification information of signal paths for transmitting signals in the chip; an extraction module for performing information extraction on the design information of the chip based on the reference information to obtain target design information, where the target design information includes attribute information of the signal paths; a constraint generation module for obtaining constraint information of the signals transmitted in the signal paths based on the reference information; and a verification module for performing formal verification on the connectivity of the signal paths based on the target design information when the constraint information is a constraint condition to obtain a verification result.

[0006] According to another aspect of the present disclosure, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method as described above.

[0007] According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to execute the method as described above.

[0008] According to another aspect of the present disclosure, there is provided a computer program product, including a computer program, where the computer program implements the method as described above when executed by a processor.

[0009] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understandable through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. Among them:

[0011] Figure 1 Schematically shows an exemplary application scenario diagram where the chip information verification method and apparatus according to an embodiment of the present disclosure can be applied;

[0012] Figure 2 Schematically shows a flowchart of the chip information verification method according to an embodiment of the present disclosure;

[0013] Figure 3A Schematically shows a schematic diagram of a signal path according to an embodiment of the present disclosure;

[0014] Figure 3B Schematically shows a schematic diagram of a signal path according to another embodiment of the present disclosure;

[0015] Figure 4A Schematically shows a schematic diagram of determining target design information according to an embodiment of the present disclosure;

[0016] Figure 4B Schematically shows a flowchart of determining constraint information according to an embodiment of the present disclosure;

[0017] Figure 5 Schematically shows a flowchart of parallel formal verification according to an embodiment of the present disclosure;

[0018] Figure 6A block diagram of a chip information verification device according to an embodiment of the present disclosure is schematically shown; and

[0019] Figure 7 A block diagram of an electronic device suitable for implementing a chip information verification method according to an embodiment of the present disclosure is schematically shown. Detailed implementation manners

[0020] The following describes exemplary embodiments of the present disclosure with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0021] In modern semiconductor design, the increasing complexity and scale of chip architectures have significantly exacerbated the integration challenges of integrated circuits. In chip design, multiple design stages can be included. For each design stage, it is necessary to verify it to ensure that multiple related links meet the design specifications and design requirements.

[0022] A chip includes signal paths for transmitting signals. The signal paths can include functional modules and wires. The interfaces of the functional modules can be used as source nodes or target nodes. The connection methods between the source node and the target node may vary, such as direct connection, conditional connection, delayed connection, reverse connection, connection with a constant, and one-hot code connection, etc. The signals transmitted in each signal path may have specific transmission conditions or delay periods.

[0023] The connectivity of the signal paths can be verified by using a simulation verification method to obtain a verification result. For example, a system simulator is used to create specific random test cases to verify the connectivity of the signal paths and obtain a verification result. Also, for example, the source node is forced and assertions are directly written to check whether the behavior of the target node meets the expectations.

[0024] However, the above methods have limitations and cannot guarantee comprehensive verification coverage for all signal paths, which may lead to potential risks in un-verified signal paths.

[0025] The connectivity of the above signal paths can also be verified by using connectivity verification in formal verification (FV) to obtain a verification result. By using the formal verification method, it is possible to mathematically and completely prove or verify whether the chip implements the functions described by the design information. All possible cases of the specified description can be verified, and the coverage rate can reach 100%, thus making up for the defects of simulation verification.

[0026] However, currently, the existing formal verification methods require manual filling of some files for formal verification, and the filling content is highly complex. Especially for a system-on-chip (SoC) with many repetitively instantiated functional modules, a large amount of information needs to be filled, and problems such as filling errors are likely to occur, resulting in a low success rate of verification.

[0027] In view of this, the embodiments of the present disclosure provide a chip information verification method, apparatus, electronic device, storage medium, and program product. The specific implementation solution is as follows: based on the design information of the chip, reference information is generated, where the reference information includes identification information of signal paths for transmitting signals in the chip; based on the reference information, information extraction is performed on the design information of the chip to obtain target design information, where the target design information includes attribute information of the signal paths; based on the reference information, constraint information of the signals transmitted in the signal paths is obtained; and in the case where the constraint information is a constraint condition, based on the target design information, formal verification of the connectivity of the signal paths is performed to obtain a verification result. Thereby, reference information can be generated in advance, and information extraction is performed from the design information based on the reference information, improving the generation efficiency, accuracy, and reliability of the target design information for formal verification, and further improving the success rate of verification.

[0028] Figure 1 Schematically shown is an exemplary application scenario diagram to which the chip information verification method and apparatus according to the embodiments of the present disclosure can be applied.

[0029] It should be noted that Figure 1 The shown is only an example of the system architecture to which the embodiments of the present disclosure can be applied, to help those skilled in the art understand the technical content of the present disclosure, but it does not mean that the embodiments of the present disclosure cannot be used in other devices, systems, environments, or scenarios.

[0030] As Figure 1 shown, the application scenario according to this embodiment may include an electronic device 101.

[0031] In some embodiments, the electronic device 101 may be a device with computing functions and formal verification functions such as a personal computer, a workstation, a server, etc. The scope of the present disclosure is not limited in this regard.

[0032] The electronic device 101 obtains design information 102 for describing the chip as input. The design information may be the final result of the front-end design, and its quality plays a key role in the back-end design and even the completion of the final chip.

[0033] In some embodiments, the design information 102 can be input into the electronic device 101 by the user. The design information 102 can also have been pre-stored in the electronic device 101. The electronic device 101 can also be communicatively coupled to other devices to obtain the design information 102 from the other devices. The scope of the present disclosure is not limited in this regard.

[0034] The electronic device 101 can generate reference information based on the design information 102 of the chip. The reference information includes identification information of signal paths for transmitting signals in the chip. Based on the reference information, information extraction is performed on the design information of the chip to obtain target design information. The target design information includes attribute information of the signal paths. Based on the reference information, constraint information of the signals transmitted in the signal paths is obtained. In the case where the constraint information is a constraint condition, based on the target design information, formal verification of the connectivity of the signal paths is performed to obtain a verification result 103.

[0035] It should be noted that the chip information verification method provided by the embodiments of the present disclosure can generally be executed by the electronic device 101. Correspondingly, the chip information verification device provided by the embodiments of the present disclosure can also be disposed in the electronic device 101.

[0036] In the technical solution of the present disclosure, the processing of collection, storage, use, processing, transmission, provision, disclosure, and application of the user's personal information involved all comply with the provisions of relevant laws and regulations, necessary confidentiality measures are taken, and public order and good customs are not violated.

[0037] In the technical solution of the present disclosure, before obtaining or collecting the user's personal information, the authorization or consent of the user is obtained.

[0038] It should be noted that the sequence numbers of the respective operations in the following methods are only used as representations of the operations for description and should not be regarded as indicating the execution order of the respective operations. Unless explicitly stated, the method does not need to be executed exactly in the order shown.

[0039] Figure 2 A flowchart of a chip information verification method according to an embodiment of the present disclosure is schematically shown.

[0040] As Figure 2 shown, the method includes operations S210 to S240.

[0041] In operation S210, reference information is generated based on the design information of the chip.

[0042] In operation S220, information extraction is performed on the design information of the chip based on the reference information to obtain target design information.

[0043] In operation S230, constraint information of the signals transmitted in the signal paths is obtained based on the reference information.

[0044] In operation S240, when the constraint information is a constraint condition, formal verification is performed on the connectivity of the signal path based on the target design information to obtain a verification result.

[0045] The design information may include the RTL (Register Transfer Level) code of the circuit. The design information may be written in a hardware description language for digital electronic system design. It may also be written in the Very High Speed Integrated Circuit Hardware Description Language (VHDL). It may also be written in the Hardware Description Language (Verilog). It should be understood that the design information may also be any other suitable file or document for describing the chip.

[0046] Optionally, the design information includes the attribute information of the signal path to be verified, but is not limited thereto. The design information may also include other auxiliary information, such as code syntax description information or other annotation information, etc., and may also include other function information of the function module other than signal transmission.

[0047] Optionally, the signal path may include a source node, a target node, intermediate nodes provided between the source node and the target node, and wires. Any one of the source node, the target node, and the intermediate nodes may be an interface of a function module of the chip. The attribute information of the signal path may include the module information of the function module and the interface information of the interface of the function module, as long as it is information for describing the signal path.

[0048] The target design information may be information extracted from the design information.

[0049] For example, the target design information may be the design information obtained by filtering the auxiliary information and only retaining the attribute information of the signal path.

[0050] For another example, the target design information may be the design information obtained by retaining the attribute information of the signal path and deleting other function information of the function modules in the chip.

[0051] The reference information may include the identification information of the signal paths for signal transmission in the chip. Specifically, the identification information of the signal path may include the identification information of the function modules and the identification information of the interfaces involved in the signal path, etc. As long as it is the identification information of the components related to the signal path.

[0052] Constraint information may include timing constraint information, but is not limited thereto. It may also include chip rule constraint information, as long as it can be used to normatively constrain the chip to be generated.

[0053] Formal verification, which can also be called static verification, is to logically check whether the design information of a chip meets a certain property through tools. Specifically, it can mathematically and completely prove or verify whether the chip has implemented the function described by the design information to obtain a verification result.

[0054] For example, taking the formal verification of connectivity as an example, based on the attribute information of the signal path in the target design information, the connectivity of the signal path can be formally verified to determine whether the signal path meets the constraint conditions of the constraint information to obtain a verification result. When the verification result indicates that the signal path is normal, the verification is passed. When all signal paths pass the verification, the backend design and preparation of the chip can be carried out based on this design information. When the verification result indicates that the signal path is abnormal, the verification fails, and the design information corresponding to the abnormal signal path is corrected so that the design information meets the requirements.

[0055] According to an embodiment of the present disclosure, the reference information includes the identification information of the signal paths used to transmit signals in the chip. Using the reference information as the information extraction standard, redundant information can be quickly filtered out, improving the verification efficiency and verification success rate based on the target design information as the verification information.

[0056] The following will illustrate the specific manner of generating reference information based on the design information of the chip.

[0057] According to an embodiment of the present disclosure, for the operation S210 as Figure 2 shown, generating reference information based on the design information of the chip may include: generating simulation component information for performing a simulation task based on the design information. Obtaining reference information based on the simulation component information.

[0058] A chip includes functional modules and interfaces for forming signal paths. The following can be used to Figure 3A specifically understand the signal paths provided by the embodiments of the present disclosure.

[0059] Figure 3A Schematically shows a schematic diagram of a signal path according to an embodiment of the present disclosure.

[0060] Such as Figure 3AAs shown, the signal path 310 may include functional module A, functional module B, and functional module C. Interface A of functional module A is the source node of the signal path 310, interfaces B1 and B2 of functional module B are intermediate nodes of the signal path 310 respectively, and interface C of functional module C is the target node of the signal path 310. Multiple nodes are connected by wires.

[0061] Optionally, the simulation task may be a task for simulating and verifying the connectivity of the signal path. For example, the simulation task may be: based on the design information of the chip, using simulation methods to simulate and verify the connectivity of the signal path. During the execution of the simulation task, a simulation script such as a simulation library directory compilation script may be used to compile, based on the design information, the simulation component information for executing the simulation task. The simulation component information may include the identification information of the functional modules forming the signal path and the identification information of the interfaces. Based on the simulation component information, the simulation design information for executing the simulation task is extracted from the design information. Based on the simulation design information, a simulation experiment is conducted to obtain the simulation experiment result.

[0062] Exemplarily, the simulation component information may be used as the reference information. However, it is not limited thereto. The simulation component information may also be subjected to a structural transformation to obtain the reference information. For example, the information structure of the simulation component information is transformed. The simulation component information may also be verified, and the verified simulation component information is used as the reference information. For example, a predetermined verification rule may be used to verify the simulation component information, and the verification method is not limited.

[0063] Obtaining the reference information for performing the formal verification task by means of the tool for executing the simulation task can reasonably utilize the reference information that has been proven to be reliable and stable, simplify the processing steps, and at the same time improve the reliability and stability of the reference information as the information extraction standard.

[0064] According to an embodiment of the present disclosure, compiling the simulation component information from the design information by means of simulation can quickly and effectively obtain the reference information, thereby simplifying the filtering operation of the design information. Using the reference information, the connection logic information related to the signal path in the design information can be accurately identified and extracted, ensuring that only the information of relevant components is included, reducing redundant information, and thus reducing the risk of incomplete reasoning or large computational overhead that may occur during the formal verification process, ultimately improving the efficiency, accuracy, and reliability of the analysis of the verification tool.

[0065] The above describes how to obtain the reference information, and the following will describe how to use the reference information to extract information from the design information.

[0066] According to an embodiment of the present disclosure, for example Figure 2The operation S220 shown, based on the reference information, extracts information from the design information of the chip to obtain the target design information, which may include: extracting information matching the reference information from the design information to obtain the refined design information. Based on the identification information of each of the multiple signal paths, the refined design information is divided to obtain multiple sub-task design information, which is used as the target design information.

[0067] The identification information of the signal paths in the reference information, such as the identification information of the functional modules and the identification information of the interfaces, can be respectively matched with the identification information of the functional modules and the identification information of the interfaces in the design information to systematically scan for relevant content and obtain the refined design information.

[0068] Optionally, the refined design information can be directly used as the target design information. However, it is not limited to this. In the case where there are multiple signal paths to be verified, based on the identification information of each of the multiple signal paths, the refined design information is divided to obtain multiple sub-task design information, and the multiple sub-task design information is used as the target design information.

[0069] According to an embodiment of the present disclosure, using the reference information as the extraction criterion, and the reference information includes the identification information of the signal paths, and using the identification information for matching extraction simplifies the difficulty of information extraction and improves the extraction efficiency.

[0070] The above describes how to perform information extraction from the design information. The following will describe how to obtain the design information.

[0071] According to an embodiment of the present disclosure, before performing the operation S210 as Figure 2 shown, the chip information verification method may further include: determining a target functional module from multiple functional modules based on the initial design information of the chip. Using the predetermined module attribute information to update the module attribute information of the target functional module to obtain the design information.

[0072] The actual hardware chip functions can be described by code, such as RTL code, to obtain the initial design information. The information of the target functional module in the initial design information is updated to obtain the design information.

[0073] Based on the initial design information of the chip, multiple functional modules involved in the initial design information can be identified to obtain the target functional module. Optionally, the target functional module can be a module capable of black box processing. For example, a functional module that has been verified, a functional module provided by a third party, etc.

[0074] The initial design information can be information-identified, and in the case where the identification information for characterizing the target functional module is identified, the functional module corresponding to the identification information is used as the target functional module.

[0075] The target functional module can be Hacked (black-boxed). For example, the module attribute information of the target functional module can be updated using predetermined module attribute information. Specifically, the predetermined module attribute information can only include the identification information of the functional module and the attribute information of the interface, and the internal logic can be omitted.

[0076] It should be noted that the attribute information of the functional module can include the identification information of the functional module, the function information of the functional module, and other information such as the power consumption and performance of the functional module. Any information used to characterize the functional module is acceptable. For example, a functional module can be composed of multiple functional units. In this case, the attribute information of the functional module can also include the respective attribute information of the multiple functional units.

[0077] The attribute information of the interface can include the identification information of the interface, the connection information between the interface and other interfaces, and the signal information of the signal transmitted by the interface, etc.

[0078] Figure 3B A schematic diagram of a signal path according to another embodiment of the present disclosure is schematically shown.

[0079] As Figure 3B shown, the signal path 320 can include functional module E, functional module F, and functional module G. Interface E of functional module E is the source node of signal path 320, interfaces F1 and F2 of functional module F are the intermediate nodes of signal path 320 respectively, and interface G of functional module G is the target node of signal path 320.

[0080] Among them, functional module F is the target functional module. The target module in the initial design information can be black-boxed, and only the identification information of functional module F and the interface attribute information of the interface are retained to obtain the design information.

[0081] Using the method for obtaining the design information provided by the embodiments of the present disclosure, commercially available functional modules that have been successfully compiled can be black-boxed in advance, thereby optimizing the information, reducing the verification amount of formal verification, and further improving the verification efficiency and verification success rate.

[0082] Figure 4A A schematic diagram for determining the target design information according to the embodiments of the present disclosure is schematically shown.

[0083] As Figure 4AAs shown, the target functional module in the initial design information 410 can be black-boxed, and the module attribute information of the target functional module can be updated using the predetermined module attribute information to obtain the design information 420. Using the simulation library directory compilation script, the design information 420 is compiled by directory to obtain the reference information 430. Based on the reference information 430, information extraction is performed on the design information 420 to obtain the target design information 440.

[0084] As Figure 4A shown, the target design information 440 can be stored in the predetermined storage space 450. In the case of performing the formal verification task, the corresponding target design information 440 can be read from the predetermined storage space 450 according to the task to be verified.

[0085] Thereby improving the reusability of the target design information and avoiding performing the same operation multiple times.

[0086] The above describes how to obtain the target design information using the reference information. The following will describe how to obtain the constraint information using the reference information. It should be noted that only the serial numbers are used to illustrate that the operation S220 for obtaining the target design information and the operation S230 for obtaining the constraint information are two operations, and the operation order of the two is not limited.

[0087] According to an embodiment of the present disclosure, for the operation S230 as Figure 2 shown, based on the reference information, obtaining the constraint information of the signal transmitted in the signal path may include: based on the reference information, determining the template information added with the identification information of the signal path. Based on the template information, obtaining the constraint information.

[0088] The constraint template can be set. The type of the constraint template is not limited. For example, it may include a table, and may also include other formats of files, such as a file in CSV (Comma-Separated Values) format, which is used to store table data or database information. Each row of the CSV file represents a row in the data table, and the fields or data items in each row are separated by a comma ",". The CSV file is often used for data exchange, especially between different applications. Using the CSV file can make the extraction and processing of information simple and easy to understand.

[0089] Based on the reference information, the identification information of the signal path can be added to the constraint template to obtain the constraint information. According to the predetermined filling rule, the identification information of the signal path can be filled into the fixed column to obtain the template information.

[0090] In addition to the identification information of the signal path, it also includes the constraint information of the signal, such as the enable expression, path delay, enable hold, enable delay, offset delay, and clock, etc.

[0091] The constraint information of these signals can be stored in a CSV file or a table file. It can be extracted from the file and filled into the predetermined fields of the template information to obtain the constraint information.

[0092] According to the embodiments of the present disclosure, obtaining the constraint information in the above manner can improve the automation processing efficiency. In addition, based on the reference information and the constraint template, the extraction and filling of the constraint information are referential, avoiding problems such as information omission or incorrect information filling.

[0093] In other examples of the present disclosure, the constraint information can also be obtained manually based on the template information. For example, the template information is sent to the terminal device. The constraint information of the signal received from the terminal device is received.

[0094] The constraint information of the signal is generated by adding the signal attribute information of the signal to the template information based on the identification information of the signal path.

[0095] Figure 4B A flowchart showing the process of determining the constraint information according to the embodiments of the present disclosure is schematically illustrated.

[0096] As Figure 4B shown, the reference information 430 can be added to the constraint template by using an electronic device to obtain the template information 460. The template information 460 is sent to the terminal device 470.

[0097] As Figure 4B shown, a target object, such as a chip designer, can use the input interface of the terminal device 470 to add the signal attribute information of the signal to the template information 460 based on the identification information of the signal path to obtain the constraint information 480 of the signal, and issue an instruction to send the constraint information to the electronic device through a control.

[0098] As Figure 4B shown, the constraint information 480 can be stored in a predetermined storage space 450. In the case of performing a formal verification task, the corresponding constraint information 480 can be read from the predetermined storage space 450 according to the task to be verified.

[0099] The electronic device can receive the constraint information of the signal from the terminal device. The constraint information of the signal is used as the constraint information for performing formal verification. However, it is not limited thereto. The constraint information of the signal can also be verified, and the successfully verified constraint information is used as the constraint information for performing formal verification.

[0100] Optionally, when the verification result of formal verification characterizes a signal path anomaly, the electronic device can also send constraint information to the terminal device so that the target object can use the constraint information on the terminal device to correct the interface and correct the constraint information based on the verification result to obtain the corrected constraint information.

[0101] Generating the constraint information of the signal by means of the interaction between the electronic device and the terminal device can improve the flexibility and intelligence of the generation of the constraint information. In addition, when the verification result of formal verification characterizes a signal path anomaly, the constraint information can be quickly corrected through this interaction method, improving the correction efficiency.

[0102] Optionally, when the module structures of two functional modules are the same, for example, the module attribute information is the same, and they appear in different instances of the chip, each functional module and each signal need to be given a unique identification information to distinguish the differences of the same signal or the same functional module in different instances.

[0103] The above has described how to obtain the target design information and the constraint information. The following will describe how to perform formal verification using the target design information and the constraint information.

[0104] Optionally, when the constraint information is a constraint condition, based on the target design information, the connectivity of the signal path can be formally verified to obtain a verification result.

[0105] It is also possible to perform parallel formal verification on multiple subtask design information to obtain multiple verification results.

[0106] The following describes the parallel formal verification.

[0107] According to an embodiment of the present disclosure, for the operation S240 as Figure 2 shown, when the constraint information is a constraint condition, based on the target design information, the connectivity of the signal path is formally verified to obtain a verification result, which may include: based on the subtask design information, determining sub-constraint information from the constraint information, and combining the subtask design information and the sub-constraint information into a verification group. Performing parallel formal verification on multiple verification groups to obtain a verification result.

[0108] Figure 5 Schematically shows a flow diagram of the parallel formal verification according to an embodiment of the present disclosure.

[0109] As Figure 5 shown, the target design information can be stored in the first predetermined storage space 510, and the subtask design information 1 to the subtask design information N can be determined from the first predetermined storage space 510 based on the identification information of the signal path in the formal verification task to be executed.

[0110] As shown Figure 5 in the figure, the constraint information can also be pre-stored in the second predetermined storage space 520. Based on the identification information of the signal path in the formal verification task to be executed or the identification information of the signal path in the sub-task design information, the sub-constraint information 1 to the sub-constraint information N is determined from the second predetermined storage space 520.

[0111] The first predetermined storage space and the second predetermined storage space can be the same storage space or different storage spaces, which will not be elaborated here.

[0112] As shown Figure 5 in the figure, the sub-task design information 1 and the sub-constraint information 1 can be combined into a verification group 530, and the sub-task design information N and the sub-constraint information N can be combined into a verification group 540. Parallel formal verification is performed on multiple verification groups to obtain the respective verification results 1 to the verification results N of multiple formal verification tasks.

[0113] Utilizing the characteristics of parallel processing, a large task to be verified is disassembled into multiple parallel sub-tasks for simultaneous processing, saving the formal verification duration and thus reducing the execution time. In addition, storing the constraint information and the target design information in the predetermined storage space can obtain the corresponding information according to the formal verification task to be executed, improving the flexibility and the information processing efficiency, and facilitating the correction of at least one of the sub-constraint information and the sub-task design information.

[0114] In summary, the above method can improve the information reusability, verification efficiency, and modification efficiency.

[0115] The above describes how to perform parallel formal verification. The following further describes the execution of formal verification.

[0116] According to an embodiment of the present disclosure, performing formal verification to obtain a verification result may include:

[0117] Performing formal verification of connectivity to obtain the communication connection result and the signal delay result of the signal path. Based on the communication connection result and the signal delay result, the verification result is obtained.

[0118] For the formal verification of the connectivity of the signal path, on the one hand, it is necessary to verify whether the communication connection of the signal path is normal. In addition, in the case of signal delay in the signal path, it is also necessary to verify whether the signal delay is normal.

[0119] Therefore, formal verification can be performed on both aspects to obtain the communication connection result and the signal delay result. In the case where any one of the communication connection result and the signal delay result indicates an abnormal signal path, the verification result indicates an abnormal signal path. In the case where both the communication connection result and the signal delay result indicate a normal signal path, the verification result indicates a normal signal path and the verification passes.

[0120] Using this verification result as the final result can perform verification both structurally and functionally on the signal path, thereby improving the comprehensiveness, effectiveness, and reliability of the connectivity verification of the signal path.

[0121] Optionally, before performing formal verification, the clock signal and the reset signal can also be initialized to ensure stability and reliability during the formal verification process.

[0122] In addition, a formal verification engine can be used for formal analysis to verify all connections and calculate the coverage rate. After the formal verification is completed, a verification report can be generated based on the verification result as needed and the verification report can be saved for future reference.

[0123] According to an embodiment of the present disclosure, in the case where the verification result indicates an abnormal connection of the signal path, the chip verification information method can further include an operation of correcting information related to the signal path.

[0124] For example, in the case where the verification result indicates an abnormal connection of the signal path, based on the abnormal signal waveform included in the verification result, an abnormal recognition result is determined. Based on the abnormal recognition result, at least one of the design information and the constraint information is corrected.

[0125] In the case where the verification result indicates an abnormal connection of the signal path, the verification result can include: identification information of the abnormal module, abnormal signal waveforms related to the abnormal module, and abnormal moments identified by the abnormal signal waveforms. The abnormal cause of the abnormal signal waveform included in the verification result can be identified. For example, the abnormal signal waveform is input into a deep learning model such as a graph neural network to obtain an abnormal recognition result, but it is not limited thereto. The abnormal recognition result can also be determined using the abnormal mapping relationship and the abnormal signal waveform. The abnormal mapping relationship represents the corresponding relationship between the abnormal cause and the reference abnormal signal waveform. The abnormal signal waveform can be matched with the reference abnormal signal waveform in the abnormal mapping relationship, and the corresponding abnormal cause of the matched reference abnormal signal waveform is used as the abnormal recognition result.

[0126] Based on the abnormal recognition result, the correction object and the correction content are determined. For example, the correction object can include at least one of the design information and the constraint information. The correction content can include: correcting the RTL code in the design information. Or checking whether the manually filled content in the check constraint information is correct, etc.

[0127] Optionally, formal verification can be performed on the corrected content to determine whether the corrected content is normal.

[0128] By using the above method, not only can the signal paths with abnormal connectivity be successfully identified, but also the relevant information of the signal paths with abnormalities can be corrected based on the verification results, thereby ensuring the value of the SoC chip design integrity, improving verification productivity and accuracy. Furthermore, the effectiveness and reliability of the application design information preparation chip are improved.

[0129] Figure 6 A block diagram of a chip information verification device according to an embodiment of the present disclosure is schematically shown.

[0130] As Figure 6 shown, the chip information verification device 600 includes: a reference generation module 610, an extraction module 620, a constraint generation module 630, and a verification module 640.

[0131] The reference generation module 610 is configured to generate reference information based on the design information of the chip, where the reference information includes identification information of signal paths for transmitting signals in the chip.

[0132] The extraction module 620 is configured to extract information from the design information of the chip based on the reference information to obtain target design information, where the target design information includes attribute information of the signal paths.

[0133] The constraint generation module 630 is configured to obtain constraint information of signals transmitted in the signal paths based on the reference information.

[0134] The verification module 640 is configured to perform formal verification on the connectivity of the signal paths based on the target design information when the constraint information is a constraint condition, and obtain a verification result.

[0135] According to an embodiment of the present disclosure, the reference generation module includes: a simulation sub-module and a reference generation sub-module.

[0136] The simulation sub-module is configured to generate simulation component information for performing a simulation task based on the design information, where the chip includes functional modules and interfaces for forming signal paths, the simulation component information includes identification information of the functional modules and identification information of the interfaces, and the simulation task is a task for simulating and verifying the connectivity of the signal paths.

[0137] The reference generation sub-module is configured to obtain reference information based on the simulation component information.

[0138] According to an embodiment of the present disclosure, the constraint generation module includes: an identification addition sub-module and a constraint acquisition sub-module.

[0139] An identification adding sub-module, configured to determine template information of identification information with a signal path added based on reference information.

[0140] A constraint obtaining sub-module, configured to obtain constraint information based on the template information.

[0141] According to an embodiment of the present disclosure, the constraint obtaining sub-module includes: a sending unit and a receiving unit.

[0142] The sending unit is configured to send the template information to a terminal device.

[0143] The receiving unit is configured to receive constraint information of a signal from the terminal device, where the constraint information of the signal is generated by adding signal attribute information of the signal to the template information based on the identification information of the signal path.

[0144] According to an embodiment of the present disclosure, the extraction module includes: an extraction sub-module and a first division sub-module.

[0145] The extraction sub-module is configured to extract information matching the reference information from design information to obtain refined design information.

[0146] The first division sub-module is configured to divide the refined design information based on the identification information of each of a plurality of signal paths to obtain a plurality of sub-task design information as target design information.

[0147] According to an embodiment of the present disclosure, the verification module includes: a second division sub-module and a parallel verification sub-module.

[0148] The second division sub-module is configured to determine sub-constraint information from the constraint information based on the sub-task design information, and combine the sub-task design information and the sub-constraint information into a verification group.

[0149] The parallel verification sub-module is configured to perform parallel formal verification on a plurality of verification groups to obtain a verification result.

[0150] According to an embodiment of the present disclosure, the verification module includes: a verification sub-module and a result determination sub-module.

[0151] The verification sub-module is configured to perform formal verification of connectivity to obtain a communication connection result and a signal delay result of the signal path.

[0152] The result determination sub-module is configured to obtain a verification result based on the communication connection result and the signal delay result.

[0153] According to an embodiment of the present disclosure, the chip includes a functional module for forming a signal path.

[0154] The chip information verification device further includes: a target determination module and an update module.

[0155] A target determination module, configured to determine a target functional module from multiple functional modules based on the initial design information of the chip.

[0156] An update module, configured to update the module attribute information of the target functional module by using predetermined module attribute information to obtain design information.

[0157] According to an embodiment of the present disclosure, the chip information verification device further includes: an identification module and a correction module.

[0158] The identification module is configured to determine an anomaly identification result based on the abnormal signal waveform included in the verification result when the verification result indicates that there is an anomaly in the connection of the signal path.

[0159] The correction module is configured to correct at least one of the design information and the constraint information based on the anomaly identification result.

[0160] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0161] According to an embodiment of the present disclosure, an electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method as described above.

[0162] According to an embodiment of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method as described above.

[0163] According to an embodiment of the present disclosure, a computer program product includes a computer program, and the computer program implements the method as described above when executed by a processor.

[0164] Figure 7 FIG. shows a schematic block diagram of an exemplary electronic device 700 that can be used to implement embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely exemplary and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0165] As Figure 7As shown, device 700 includes a computing unit 701, which can perform various appropriate actions and processes according to computer programs stored in a read-only memory (ROM) 702 or computer programs loaded from a storage unit 708 into a random access memory (RAM) 703. In the RAM 703, various programs and data required for the operation of device 700 can also be stored. The computing unit 701, ROM 702, and RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0166] Multiple components in device 700 are connected to the input / output (I / O) interface 705, including: an input unit 706, such as a keyboard, mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a disk, optical disc, etc.; and a communication unit 709, such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows device 700 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0167] The computing unit 701 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 701 executes the various methods and processes described above, such as the chip information verification method. For example, in some embodiments, the chip information verification method can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed onto device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the chip information verification method described above can be executed. Alternatively, in other embodiments, the computing unit 701 can be configured to execute the chip information verification method in any other appropriate manner (e.g., by means of firmware).

[0168] The various embodiments of the systems and techniques described above in this specification can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), systems on chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from, and transmits data and instructions to, a storage system, at least one input device, and at least one output device.

[0169] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine, or entirely on the remote machine or server.

[0170] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0171] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0172] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

[0173] A computer system can include a client and a server. The client and the server are generally far from each other and usually interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, or a server of a distributed system, or a server incorporating a blockchain.

[0174] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and no limitation is imposed herein.

[0175] The above specific embodiments do not constitute a limitation on the protection scope of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the protection scope of this disclosure.

Claims

1. A chip information verification method, comprising: Generate reference information based on the design information of the chip, wherein the reference information includes identification information of a signal path in the chip for transmitting a signal; Based on the reference information, extracting design information of the chip to obtain target design information, wherein the target design information includes attribute information of the signal path; Based on the reference information, acquiring constraint information of the signal transmitted in the signal path; and In the case where the constraint information is a constraint condition, the connectivity of the signal path is formally verified based on the target design information to obtain a verification result.

2. The method according to claim 1, wherein: The generating of reference information based on the chip design information includes: Based on the design information, generating simulation component information for performing a simulation task, wherein the chip includes a functional module and an interface for forming the signal path, the simulation component information includes identification information of the functional module and identification information of the interface, and the simulation task is a task of simulating and verifying connectivity of the signal path; and The reference information is obtained based on the simulation component information.

3. The method according to claim 1 or 2, wherein: The acquiring, based on the reference information, constraint information of the signal transmitted in the signal path includes: Based on the reference information, determine the template information to which the identification information of the signal path is added; Based on the template information, the constraint information is acquired.

4. The method according to claim 3, wherein: The acquiring the constraint information based on the template information includes: Sending the template information to a terminal device; and Receive constraint information of the signal from the terminal device, wherein the constraint information of the signal is generated by adding signal attribute information of the signal to the template information based on identification information of the signal path.

5. The method according to any one of claims 1 to 4, wherein: The step of extracting the design information of the chip based on the reference information to obtain target design information includes: extracting information matching the reference information from the design information to obtain simplified design information; and Based on the identification information of each of the plurality of signal paths, the simplified design information is divided to obtain a plurality of sub-task design information as the target design information.

6. The method according to claim 5, wherein: When the constraint information is a constraint condition, formal verification is performed on the connectivity of the signal path based on the target design information to obtain a verification result, including: Based on the subtask design information, determining sub-constraint information from the constraint information, and combining the subtask design information and the sub-constraint information into a verification group; and Performing parallel formal verification on the plurality of verification groups to obtain the verification result.

7. The method according to claim 1 or 6, wherein: Perform formal verification and obtain verification results, including: Performing formal verification of connectivity to obtain communication connection results and signal delay results of the signal path; and The verification result is obtained based on the communication connection result and the signal delay result.

8. The method according to any one of claims 1 to 7, wherein: The chip includes a functional module for forming the signal path, and the method further includes: Based on the initial design information of the chip, determining a target functional module from the plurality of functional modules; and The module attribute information of the target functional module is updated using the predetermined module attribute information to obtain the design information.

9. The method according to any one of claims 1 to 8, further comprising: In a case where the verification result indicates that there is an abnormality in the connection of the signal path, determining an abnormality identification result based on the abnormal signal waveform included in the verification result; as well as Based on the abnormality identification result, at least one of the design information and the constraint information is modified.

10. A chip information verification device, comprising: A reference generation module, configured to generate reference information based on the design information of the chip, wherein the reference information includes identification information of a signal path in the chip for transmitting a signal; An extraction module, configured to extract the design information of the chip based on the reference information to obtain target design information, wherein the target design information includes attribute information of the signal path; a constraint generating module, configured to obtain constraint information of the signal transmitted in the signal path based on the reference information; and The verification module is used to perform formal verification on the connectivity of the signal path based on the target design information when the constraint information is a constraint condition to obtain a verification result.

11. An electronic device, comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 9.

12. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-9.

13. A computer program product, comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 9.

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