Chip testability design DFT system based on field programmable gate array and method thereof
By integrating multiple control units and interfaces on the FPGA chip, an automated testing system was designed, which solved the problem that the existing DFT testing methods were not compatible with chip initialization, BIST and SCAN full-process testing, and achieved automation of tests and accurate judgment of results.
Patent Information
- Application Number
- CN202510125136.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-26
- Publication Date
- 2025-05-30
AI Technical Summary
The existing FPGA-based DFT testing methods are not compatible with chip initialization, BIST and SCAN full process testing, and the online comparison of specific data is complicated.
An automated test system based on FPGA chip is designed, integrating I2C control unit, SCAN control unit, JTAG control unit and pin selection unit, mode control is performed through the I2C interface, and the chip initialization, BIST and SCAN tests are automated. The test results are stored in FPGA memory and read through I2C pagination.
It realizes compatibility between chip initialization, BIST and SCAN testing, simplifies the test process, avoids the complexity of online comparison, and automatically determines whether the test results pass DFT test through scripts.
Smart Images
Figure CN120068757A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to systems and methods for chip testing, and more particularly, to systems and methods for design for test (DFT) of a chip based on a field-programmable gate array (FPGA). Background Art
[0002] As the manufacturing process of chips becomes smaller and the scale of chips becomes larger, it becomes increasingly difficult to test chips. Testing is an extremely important link for chips and cannot be ignored. DFT emerged as a chip testing technology. It refers to inserting various hardware logics for improving the testability of a chip (including controllability and observability) during the original chip design stage. Through this part of the logic, test vectors (patterns) are generated to achieve the purpose of testing large-scale chips. DFT generates efficient and economical structural test vectors through implementing specific auxiliary designs for chip testing on an automatic test equipment (ATE), but it will bring a certain degree of increase in hardware overhead.
[0003] Currently, DFT involves several core technologies:
[0004] 1) Scan design, as a DFT solution for sequential circuit chips, the basic principle is that a sequential circuit can be modeled as a feedback of a combinational circuit network and a sequential circuit network with flip-flops, turning a sequential circuit that is not easily testable into an easily testable combinational circuit for testing. Specifically, by replacing ordinary registers with scannable registers to create control points and observation points, connecting all scannable registers together to form a scan chain, automatically generating test vectors, and using the scan chain to make the registers take on specific values and then compare them with the expected values for testing. However, DFT testing based on ATE requires ATE, which is expensive, and generally, after the scan input (SCAN IN), the scan output (SCAN OUT) is compared online with a fixed code;
[0005] 2) Built-in Self Test (BIST). By adding some additional self-test circuits to the chip design, only necessary control signals need to be externally applied during testing. By running the built-in self-test hardware and software, the chip under test can be tested. Different from SCAN design, the test vectors of BIST are generally internally generated rather than externally input. Built-in self-test can simplify the test steps and does not require expensive test instruments and equipment (such as ATE), but it increases the complexity of chip design;
[0006] 3) Joint Test Action Group (JTAG) standard, which is widely used in chip internal testing and debugging. Its basic principle is to define a Test Access Port (TAP) inside the chip and test internal nodes through a dedicated JTAG test tool. JTAG testing allows multiple devices to be connected in series through the JTAG interface to form a JTAG chain, enabling separate testing of each device.
[0007] DFT testing based on FPGA has been proposed for single testing of SCAN CHAIN, but current FPGA-based DFT testing methods have problems such as inability to be compatible with the full-process testing of chip initialization, BIST, and SCAN, and complexity in online comparison of specific data. In addition, a chip testing method based on the combination of a Central Processing Unit (CPU) and FPGA has been proposed, but this method has a complex circuit structure and requires the participation of the CPU, making it complex to implement. Summary of the Invention
[0008] The present disclosure proposes an automated test system and method based on an FPGA chip that is compatible with chip initialization, BIST, and SCAN CHAIN integration. The test system is integrated on the FPGA chip, and the FPGA chip includes an Inter-Integrated Circuit (I2C) control unit, a SCAN control unit, a JTAG control unit, and a pin selection unit. The host performs mode control through the I2C interface to select chip initialization, BIST, or SCAN CHAIN test modes. The test results are stored in the FPGA memory or a storage device on the FPGA. After the test ends, the results are read page by page through I2C, and then it is automatically determined whether the obtained results pass the DFT test through a script. In addition, the test system and method disclosed in the present disclosure do not use the online comparison method, but store the output code in the FPGA storage first and then read the results through I2C, so that the data results are compared on the host and the problem location can be traced.
[0009] One aspect of the present disclosure provides a Design for Testability (DFT) system for a Field Programmable Gate Array (FPGA)-based chip. The system includes: a control unit configured to receive a mode control command from an external host, generate a test mode indication signal for indicating a chip test mode based on the mode control command, and send the generated test mode indication signal to a Device Under Test (DUT); a first test control unit connected to the control unit and configured to receive the mode control command from the control unit, generate a test vector and a first test signal for a first test mode according to the mode control command; a second test control unit connected to the control unit and configured to receive the mode control command from the control unit, generate a test command and a second test signal for a second test mode according to the mode control command; a selection unit connected to the control unit, the first test control unit, and the second test control unit, and configured to receive the test mode indication signal from the control unit, and send the test vector and the first test signal and / or the test command and the second test signal to the DUT according to the received test mode indication signal, so that the DUT is tested in the first test mode and / or the second test mode, and receive a test result from the DUT.
[0010] In one example, the test mode indication signal includes a first test mode indication signal and / or a second test mode indication signal. And sending the test vector and the first test signal and / or the test command and the second test signal to the DUT according to the received test mode indication signal so that the DUT is tested in the first test mode and / or the second test mode includes one of the following: when the test mode indication signal only includes the first test mode indication signal, sending the test vector and the first test signal to the DUT so that the DUT is tested in the first test mode based on the test vector and the first test signal; when the test mode indication signal only includes the second test mode indication signal, sending the test command and the second test signal to the DUT so that the DUT is tested in the second test mode based on the test command and the second test signal; when the test mode indication signal includes the first test mode indication signal and the second test mode indication signal, sending the test vector and the first test signal and the test command and the second test signal to the DUT so that the DUT is not simultaneously tested in the first test mode based on the test vector and the first test signal and in the second test mode based on the test command and the second test signal.
[0011] In one example, the first test control unit includes a read-only memory (ROM) for storing the test vectors, and a static random access memory (SRAM) for storing test results in the first test mode.
[0012] In one example, the test command includes at least one of a reset, an instruction, and data.
[0013] In one example, the system further includes an initialization unit for initializing the FPGA before the test starts.
[0014] Another aspect of the present disclosure provides a design for testability (DFT) method for a field-programmable gate array (FPGA)-based chip. The method includes: receiving, by a control unit, a mode control command from an external host, generating, based on the mode control command, a test mode indication signal for indicating a chip test mode, and sending the generated test mode indication signal to a device under test (DUT); receiving, by a first test control unit, the mode control command from the control unit, generating, according to the mode control command, test vectors and a first test signal for a first test mode; receiving, by a second test control unit, the mode control command from the control unit, generating, according to the mode control command, test commands and a second test signal for a second test mode; receiving, by a selection unit, the test mode indication signal from the control unit, and sending, according to the received test mode indication signal, the test vectors and the first test signal and / or the test commands and the second test signal to the DUT, such that the DUT is tested in the first test mode and / or the second test mode, and receiving test results from the DUT.
[0015] In one example, the test mode indication signal includes a first test mode indication signal and / or a second test mode indication signal, and wherein, according to the received test mode indication signal, the test vector and the first test signal and / or the test command and the second test signal are sent to the DUT, such that the DUT is tested in the first test mode and / or the second test mode, including one of the following: when the test mode indication signal only includes the first test mode indication signal, the test vector and the first test signal are sent to the DUT, such that the DUT is tested in the first test mode based on the test vector and the first test signal; when the test mode indication signal only includes the second test mode indication signal, the test command and the second test signal are sent to the DUT, such that the DUT is tested in the second test mode based on the test command and the second test signal; when the test mode indication signal includes the first test mode indication signal and the second test mode indication signal, the test vector and the first test signal and the test command and the second test signal are sent to the DUT, such that the DUT is not tested simultaneously in the first test mode based on the test vector and the first test signal and in the second test mode based on the test command and the second test signal.
[0016] In one example, the first test control unit includes a read-only memory ROM for storing the test vector, and a static random access memory SRAM for storing test results in the first test mode.
[0017] In one example, the test command includes at least one of reset, instruction, and data.
[0018] In one example, the method further includes: performing test initialization by an initialization unit before the test starts.
[0019] The FPGA-based chip DFT test system and method according to the embodiments of the present disclosure are applicable to, for example, time of fly (TOF) chips, DFT tests of chips that require initialization before DFT or chips where the I2C interface serves as a DFT test pin, such that the built-in JTAG controller can perform BIST tests, and automated tests of chip initialization, process control, mode switching, and test result readback are achieved through the I2C interface. Description of the Drawings
[0020] Figure 1 is a block diagram showing an FPGA-based DFT test system according to an embodiment of the present disclosure;
[0021] Figure 2 shows a block diagram of the MUX in Figure 1 according to an embodiment of the present disclosure;
[0022] Figure 3 is a diagram showing the I2C address allocation inside the FPGA according to an embodiment of the present disclosure;
[0023] Figure 4 is a flowchart showing the BIST test performed by the Figure 1 system shown in according to an embodiment of the present disclosure;
[0024] Figure 5 is a flowchart showing the SCAN test performed by the Figure 1 system shown in according to an embodiment of the present disclosure;
[0025] Figure 6 is a diagram showing the data pattern obtained by the host in the SCAN test mode according to an embodiment of the present disclosure.
[0026] Figure 7 is a flowchart showing the comparison of the test result data and the test expected data.
[0027] Figure 8 shows a view of the expected result data obtained by script processing according to the test vector.
[0028] Figure 9 shows according to Figure 6 a view of the actual test data obtained by script processing based on the results shown in. Detailed Embodiments
[0029] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. It should be noted that in the drawings, the same or similar elements are denoted by the same or similar reference numerals as much as possible. In addition, detailed descriptions of known functions or configurations that may obscure the subject matter of the present disclosure will be omitted.
[0030] When describing the embodiments of the present disclosure, descriptions related to technical content that is well known in the art and not directly related to the present disclosure will be omitted. Such omission of unnecessary descriptions is to prevent obscuring the main idea of the present disclosure and to more clearly convey the main idea.
[0031] For the same reason, in the drawings, some elements may be enlarged, omitted, or schematically shown. In addition, the size of each element does not exactly reflect the actual size. In the drawings, the same or corresponding elements have the same reference numerals.
[0032] Advantages and features of the present disclosure, and the manner of realizing them, will become clear by referring to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments set forth below, but can be implemented in various different forms. The following embodiments are provided only to fully disclose the present disclosure and to inform those skilled in the art of the scope of the present disclosure, and the present disclosure is limited only by the scope of the appended claims. Throughout the specification, the same or similar reference numerals denote the same or similar elements.
[0033] The present disclosure proposes an automated test system and method based on an FPGA chip that is compatible with chip initialization, BIST, and SCAN CHAIN integration. The test system is integrated on the FPGA chip, and the FPGA chip includes an Inter-Integrated Circuit (I2C) control unit, a SCAN control unit, a JTAG control unit, and a pin selection unit. The host performs mode control through the I2C interface to select the chip initialization, BIST, or SCAN CHAIN test mode. The test results are stored in the FPGA memory or a storage device on the FPGA, and at the end of the test, the results are read in pages through I2C, and then it is automatically determined whether the obtained results pass the DFT test through a script.
[0034] The following describes in detail an FPGA-based DFT test system and method according to an embodiment of the present disclosure with reference to the accompanying drawings.
[0035] Figure 1 is a block diagram showing an FPGA-based DFT test system 10 according to an embodiment of the present disclosure.
[0036] As Figure 1 shown, the test system 10 includes a host 100 on which I2C software is installed. The IC2 software sends I2C commands to the FPGA 120 and receives I2C read-back data through a USB to I2C (USB2I2C) adapter board 110, and the USB2I2C adapter board is used to convert the USB protocol of the host into an I2C control signal; the FPGA 120, which can be a board designed by the user himself or an existing FPGA board; and a device under test DUT 130.
[0037] As Figure 1 shown, the FPGA 120 is written with a firmware program, including an I2C control unit (for example, Figure 1 the i2c_top unit 1230 shown), a SCAN control unit (for example, Figure 1 the stuck_pat unit 1220 shown), a JTAG control unit (for example, Figure 1 the jtag_mst unit 1210 shown), and a pin selection unit (for example, Figure 1The multiplexer (MUX) 1240 shown, and the FPGA initialization unit (e.g., the clk_rst unit, not shown in Figure 1 ). In addition, as Figure 1 shown, the various units included in the FPGA 120 are connected to each other via an I2C bus, which includes a serial data line (SDA) and a serial clock line (SCL). All devices are connected to one SDA line and share this common data line time-divisionally to achieve data transmission between two devices, and all devices are connected to one SCL line and share this common clock line time-divisionally to achieve clock transmission between two devices.
[0038] Figure 1 The stuck_pat unit 1220 shown includes a read-only memory - test vector memory (e.g., Figure 1 the rom_w309 shown) for storing test vectors for SCAN testing. In SCAN testing, these test vectors are loaded into the SCAN chain of the chip to detect faults in the chip.
[0039] Figure 1 The stuck_pat unit 1220 shown also includes a static random access memory - test result memory (e.g., Figure 1 the sram_w309 shown) for storing the results of SCAN testing. During the testing process, the outputs of the chip are captured and stored in a static random access memory (SRAM) for subsequent analysis
[0040] The following describes the interaction process of the various units included in the FPGA 120 when testing the DUT 130 based on the architecture of the FPGA-based DFT test system shown in Figure 1 .
[0041] At the start of the test of the DUT 130, the clk_rst unit (not shown in Figure 1 ) generates reset and clock signals for the operation of the FPGA 120 to initialize the FPGA 120.
[0042] Via the I2C bus, the i2c_top unit 1230 parses the I2C commands received from the host outside the FPGA 120 through USB2I2C, switches the chip test mode (SCAN test mode or BIST test mode), generates a signal for indicating the chip test mode (e.g., Figure 1For PAD_MODE1 and PAD_MODE2 shown in , read-write transfer is performed, and the parsed I2C command is sent to the jtag_mst unit 1210 and / or the stuck_pat unit 1220 for the jtag_mst unit 1210 and the stuck_pat unit 1220 to test the DUT 130 in the BIST test mode and the SCAN test mode respectively based on the received parsed I2C command. Among them, PAD_MODE1 and PAD_MODE2 are used to indicate to the chip whether to perform the BIST test or the SCAN test currently. In the present disclosure, taking PAD_MODE1 indicating the BIST test and PAD_MODE2 indicating the SCAN test as an example for description, but the present disclosure is not limited thereto. For example, it is also possible that PAD_MODE1 indicates the SCAN test and PAD_MODE2 indicates the BIST test.
[0043] In the BIST test, the jtag_mst unit 1210 sends JTAG commands (including reset, instructions, data, etc.) to the DUT 130 through the JTAG interface according to the received parsed I2C command to test the DUT 130. Currently, there are two connection standards for the JTAG interface, the 14-pin interface and the 20-pin interface, and these two connection standards are given in Table 1 and Table 2 below. It should be understood that the connection standards given in Table 1 and Table 2 below are only examples, and the present disclosure is not limited thereto.
[0044]
[0045]
[0046] Table 1 - 14-pin Interface
[0047]
[0048] Table 2 - 20-pin Interface
[0049] Specifically, TMS is used to control the transition between the various states of the TAP controller (for example, Figure 1 the jtag_tap shown); TCLK is the clock signal provided by the TAP controller and is used to drive all operations of the TAP controller; the TDI interface is the data input interface, and all data that needs to be input to the DUT 130 is serially input through the TDI interface driven by TCLK; the TDO interface is the data output interface, and all output data of the DUT 130 is serially output through the TDO interface driven by TCLK; and TRST is used to reset the TAP controller.
[0050] Under the SCAN test, the stuck_pat unit 1220 generates and sends a test vector (SCAN PATTERN) to the DUT 130 according to the received parsed I2C command to test the DUT 130, while recording the signals returned from the DUT 130.
[0051] The signals TMS, TDI, TDO, TCLK, and TRST in the BIST test mode described above respectively correspond to the signals EDPU, SCAN, CHOUT, CHIN, and CLOCK in the SCAN test mode. Specifically, EDPU is a rising-edge detection signal used to detect the rising edge of the clock signal to ensure that data is shifted in the scan chain at the correct moment. In the SCAN test, the EDUP signal helps synchronize the loading and acquisition of data, ensuring the correct transfer of test vectors and results; SCAN is a scan control signal used to activate and control the scan chain inside the chip. In the SCAN mode, the SCAN signal controls the start and stop of the scan chain, as well as the loading of test vectors and the reading of results; CHOUT is the output signal of the scan chain used to output the result data of the scan chain inside the device under test to the external test system. After the SCAN test is completed, CHOUT carries the status information of the internal registers of the chip for the test system to analyze. CHIN is the input signal of the scan chain used to input the test vector provided by the external test system into the scan chain inside the device under test for fault detection; CLOCK is the clock signal used to provide synchronous timing for the scan operation in the SCAN mode and control the shifting of data in the scan chain to ensure that the test vector and result data are loaded and read at the correct time.
[0052] The MUX 1240 unit receives the JTAG commands (including reset, instructions, data, etc.) sent by the jtag_mst unit 1210 through the JTAG interface in the BIST test mode and the SCAN PATTERN generated and sent by the stuck_pat unit 1220 in the SCAN test mode, and sends the return signals received from the DUT 130 back to the jtag_mst unit 1210 and the stuck_pat unit 1220, so as to send them back to the host for analysis by the I2C software installed on the host. The MUX 1240 can determine in which test mode (BIST test mode, SCAN test mode, or both BIST test mode and SCAN test mode) the FPGA 120 is currently testing the DUT 130 based on the PAD_MODE1 and PAD_MODE2 received from the i2c_top unit 1230, and switch the corresponding signals in the determined test mode and perform data transmission in the normal working mode.
[0053] Figure 2shows a block diagram of the MUX 1240 in accordance with an embodiment of the present disclosure. The MUX 1240 selects the BIST test mode or the SCAN test mode through the enable signal BIST_EN. Under the BIST test, the MUX selects the signals TMS, TDI, TDO, TCLK, and TRST; under the SCAN test, the MUX selects the signals EDPU, SCAN, CHOUT, CHIN, and CLOCK. Figure 1
[0054] The following refers to Figures 3 - 5 to describe the specific process of the FPGA-based DFT test method according to the present disclosure. Figure 3 shows a diagram of the internal I2C address allocation of the FPGA in accordance with an embodiment of the present disclosure.
[0055] Figure 4 and Figure 5 are respectively flowcharts showing the BIST test and the SCAN test performed by the system shown in Figure 1 , where the process shown in Figure 4 is executed by the jtag_mst1210 shown in Figure 1 , the process shown in Figure 5 is executed by the stuck_pat 1220 shown in Figure 1 , and the chip initialization is performed by the host 100.
[0056] In Figure 4 , in S301, the I2C command from the host 100 selects the DUT 130 address, and initialization is completed in the functional mode of the device under test DUT 130 (the normal operating mode of DUT 130, at this time DUT 130 can implement the designed functions; when DUT 130 enters the test mode, DUT 130 can only perform DFT and cannot operate normally), for example, turning on the oscillator (OSC), turning on the power supply, etc.; in S302, the I2C command selects the internal I2C address of the FPGA 120 (for example, the address 0xFFFF shown in Figure 3 ), changes the levels of PAD_MODE1 and PAD_MODE2 (for example, using the lower 2 bits or the upper 2 bits or other appropriate methods of the address 0xFF as the levels of PAD_MODE1 and PAD_MODE2), and enters the BIST test mode; in S303, the I2C command selects the internal I2C address of the FPGA 120 (for example, Figure 3The address 0x08 shown, the mode selection in address 0x08 is used to select reset, instruction, and data included in the JTAG command. For example, when write mode (MODE) = 1, a reset is sent; when MODE = 2, an instruction is sent; when MODE = 3, data is sent). Send the JTAG reset command (e.g., write mode 1 at address 0x08, write trigger command at address 0x8b); in S304, the I2C command selects the internal I2C address of FPGA 120 (e.g., Figure 3 the addresses 0x08, 0x09, 0x0a, 0x0b, 0x8b, and 0x40 shown), send the JTAG command (e.g., write mode 2 at address 0x08, write instruction length at addresses 0x09, 0x0a, write instruction at address 0x0b, write trigger command at address 0x8b; read several addresses after address 0x40 and send the TDO return value to host 100); in S305, the I2C command selects the internal I2C address of FPGA 120 (e.g., Figure 3 the addresses 0x08, 0x09, 0x0a, 0x0b, 0x8b, and 0x40 shown), send the JTAG data command (e.g., write mode 3 at address 0x08, write instruction length at addresses 0x09, 0x0a, write data 0 at address 0x0b, write trigger command at address 0x8b; read several addresses after address 0x40 and send the TDO return value to host 100); in S306, the I2C command selects the internal I2C address of FPGA 120 (e.g., Figure 3 the addresses 0x08, 0x09, 0x0a, 0x0b, 0x0c, ……, 0x8b, and 0x40 shown), send the JTAG data command (e.g., write mode 3 at address 0x08, write instruction length at addresses 0x09 and 0x0a, write data 0 at address 0x0b, write data 1 at address 0x0c, ……, write trigger command at address 0x8b; read several addresses after address 0x40 and send the TDO return value to host 100); in S307, determine whether all data writes of JTAG are completed. If so, the process proceeds to S308 to complete the test of DUT 130 and the host checks the test result. Otherwise, the process returns to S306.
[0057] In Figure 5 , in S401, the I2C command selects the DUT 130 address and completes initialization (such as turning on the OSC, turning on the power, etc.) in the functional mode of the device under test DUT 130 (the normal operating mode of DUT 130, at this time DUT 130 can implement the designed functions); in S402, the I2C command selects the internal I2C address of FPGA 120 (e.g., Figure 3At the address shown (0xFF), change the levels of PAD_MODE1 and PAD_MODE2 (for example, use the lower 2 bits or the upper 2 bits or other appropriate ways of the address 0xFF as the levels of PAD_MODE1 and PAD_MODE2) to enter the SCAN test mode; at S403, the stuck_pat unit 1220 sequentially sends test vectors according to the test vectors stored in rom_w309 in the stuck_pat 1220 (whose width is the width of the test vector and depth is the number of test vectors), records the signals returned by the DUT 130 at the same time, and writes the signals into sram_w309; at S404, determine whether the sending of all test vectors is completed. If so, the process proceeds to S405 to complete the test of the DUT 130, and the host reads back the test results from sram_w309 and checks the test results. Otherwise, the process returns to S403.
[0058] Figure 6 FIG. is a diagram showing a data pattern obtained by a host in a SCAN test mode according to an embodiment of the present disclosure.
[0059] Figure 7 FIG. is a flowchart showing a comparison between test result data and test expected data. Specifically, at S701, the theoretically expected result data sim.txt of the test is obtained through script processing according to the test vector, which is shown in Figure 8 ; at S702, the actual SCAN test result data test.txt is obtained through script processing according to the result data shown in Figure 6 , which is shown in Figure 9 ; and at S703, compare the results obtained in S701 and S702 (excluding X in the obtained results sim.txt and test.txt), and when the results obtained in S701 and S702 (excluding X in the obtained results) are the same, determine that the test passes, otherwise determine that the test fails.
[0060] The FPGA-based DFT test system and method according to an embodiment of the present disclosure allow BIST testing and SCAN testing to be performed separately or jointly (that is, BIST testing and SCAN testing can be separately controlled at different times), and enable the data returned by the DUT130 at each step to be recorded by the FPGA 120 and read back to the host 100 through the USB2I2C 110. The host 100 then parses the obtained data through a script and can determine whether the read-back data meets the expectations, so as to determine whether the DUT 130 passes the DFT test. Here, the expectation refers to the output vector that can be expected after inputting a test vector for DFT.
[0061] The automated test system and method based on FPGA chips for implementing chip initialization, BIST, and SCAN CHAIN integration proposed in this disclosure allow for mode control through the I2C interface to select chip initialization, BIST, or SCAN (or SCAN CHAIN) test modes. The test results are stored in the FPGA memory or the storage device on the FPGA. At the end of the test, the results are read in pages through the I2C, and then it is automatically determined through a script whether the obtained results pass the DFT test.
[0062] The various embodiments described in this disclosure and the various examples in the embodiments can be changed and combined in any appropriate form.
[0063] The steps of the methods or algorithms described in this disclosure can be embodied directly in hardware, in software modules executed by a processor, or in a combination of the two. The software modules can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, or any other form of storage medium known in the art. The exemplary storage medium is coupled to the processor so that the processor can read from and write to the storage medium.
[0064] In one or more exemplary designs, the functions can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. The computer-readable medium includes both computer storage media and communication media, the latter including any medium that facilitates the transfer of a computer program from one place to another. The storage medium can be any available medium accessible by a general or special purpose computer.
[0065] In conjunction with the accompanying drawings, the description set forth herein describes example configurations, methods, and devices, and does not represent all examples that can be implemented or that are within the scope of the claims. The detailed description includes specific details for the purpose of providing an understanding of the described technologies. However, these technologies can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.
[0066] Although this specification contains many details of specific implementations, these should not be construed as limitations on any invention or the scope of what is claimed, but rather as descriptions of specific features of particular embodiments of a particular invention. Certain features described in the context of separate embodiments in this specification can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately in multiple embodiments or in any suitable sub-combination. Additionally, although features may have been described above as acting in certain combinations and even initially claimed as such, in some cases, one or more features from a claimed combination can be deleted from that combination, and the claimed combination can be directed to a sub-combination or a variation of a sub-combination.
[0067] It should be understood that the specific order or hierarchy of steps in the methods of the present disclosure are illustrations of exemplary processes. Based on design preferences, it is understood that the specific order or hierarchy of steps in a method can be rearranged to achieve the functions and effects disclosed by the present disclosure. The appended method claims present the elements of the various steps in an exemplary order and are not meant to be limited to the specific order or hierarchy presented, unless otherwise specifically stated. Additionally, although elements may be described or claimed in the singular, the plural is also contemplated unless a limitation to the singular is explicitly stated. Thus, the present disclosure is not limited to the examples shown, and any apparatus for performing the functions described herein is included in the aspects of the present disclosure.
[0068] The text and drawings are provided only as examples to assist the reader in understanding the present disclosure. They are not intended nor should they be construed as limiting the scope of the present disclosure in any way. Although certain embodiments and examples have been provided, it will be apparent to those skilled in the art based on the content disclosed herein that changes can be made to the embodiments and examples shown without departing from the scope of the present disclosure.
Claims
1. A chip testability design DFT system based on field programmable gate array FPGA, wherein: The system comprises: A control unit is configured to receive a mode control command from an external host, generate a test mode indication signal for indicating a chip test mode based on the mode control command, and send the generated test mode indication signal to the chip under test DUT; a first test control unit connected to the control unit and configured to receive the mode control command from the control unit and generate a test vector and a first test signal for a first test mode according to the mode control command; a second test control unit connected to the control unit and configured to receive the mode control command from the control unit and generate a test command and a second test signal for a second test mode according to the mode control command; A selection unit is connected to the control unit, the first test control unit and the second test control unit, and is configured to receive the test mode indication signal from the control unit, and send the test vector and the first test signal and / or the test command and the second test signal to the DUT according to the received test mode indication signal, so that the DUT is tested in the first test mode and / or the second test mode, and receive a test result from the DUT.
2. The system according to claim 1, wherein: The test mode indication signal includes a first test mode indication signal and / or a second test mode indication signal, and The step of sending the test vector and the first test signal and / or the test command and the second test signal to the DUT according to the received test mode indication signal, so that the DUT is tested in the first test mode and / or the second test mode, includes one of the following: In a case where the test mode indication signal includes only the first test mode indication signal, sending the test vector and the first test signal to the DUT, so that the DUT is tested in the first test mode based on the test vector and the first test signal; In a case where the test mode indication signal includes only the second test mode indication signal, sending the test command and the second test signal to the DUT, so that the DUT is tested in the second test mode based on the test command and the second test signal; In a case where the test mode indication signal includes the first test mode indication signal and the second test mode indication signal, the test vector and the first test signal as well as the test command and the second test signal are sent to the DUT, so that the DUT is tested in the first test mode based on the test vector and the first test signal and in the second test mode based on the test command and the second test signal at different times.
3. The system according to claim 2, wherein: The first test control unit includes a read-only memory ROM for storing the test vectors, and a static random access memory SRAM for storing the test results in the first test mode.
4. The system according to claim 2, wherein: The test command includes at least one of a reset, an instruction, and data.
5. The system according to any one of claims 1 to 4, wherein: The system also includes an initialization unit, which is used to initialize the FPGA before the test starts.
6. A chip testability design DFT method based on field programmable gate array FPGA, wherein: The method comprises: The control unit receives a mode control command from an external host, generates a test mode indication signal for indicating a chip test mode based on the mode control command, and sends the generated test mode indication signal to the chip under test DUT; The first test control unit receives the mode control command from the control unit, and generates a test vector and a first test signal for a first test mode according to the mode control command; The second test control unit receives the mode control command from the control unit, and generates a test command and a second test signal for a second test mode according to the mode control command; The selection unit receives the test mode indication signal from the control unit, and according to the received test mode indication signal, sends the test vector and the first test signal and / or the test command and the second test signal to the DUT, so that the DUT is tested in the first test mode and / or the second test mode, and receives the test result from the DUT.
7. The method according to claim 6, wherein: The test mode indication signal includes a first test mode indication signal and / or a second test mode indication signal, and The step of sending the test vector and the first test signal and / or the test command and the second test signal to the DUT according to the received test mode indication signal, so that the DUT is tested in the first test mode and / or the second test mode, includes one of the following: In a case where the test mode indication signal includes only the first test mode indication signal, sending the test vector and the first test signal to the DUT, so that the DUT is tested in the first test mode based on the test vector and the first test signal; In a case where the test mode indication signal includes only the second test mode indication signal, sending the test command and the second test signal to the DUT, so that the DUT is tested in the second test mode based on the test command and the second test signal; In a case where the test mode indication signal includes the first test mode indication signal and the second test mode indication signal, the test vector and the first test signal as well as the test command and the second test signal are sent to the DUT, so that the DUT is tested in the first test mode based on the test vector and the first test signal and in the second test mode based on the test command and the second test signal at different times.
8. The method according to claim 7, wherein: The first test control unit includes a read-only memory ROM for storing the test vectors, and a static random access memory SRAM for storing the test results in the first test mode.
9. The method according to claim 7, wherein: The test command includes at least one of a reset, an instruction, and data.
10. The method according to any one of claims 6 to 9, wherein: The method further comprises: The initialization unit performs test initialization before the test starts.