Methods, apparatus and media for gridding integrated circuits

Abstract

The embodiment of the invention provides a method, equipment and medium for gridding an integrated circuit. The method comprises: for an integrated circuit divided into a plurality of cells, generating a hierarchical structure representing relative positions among the plurality of cells based on positions of the plurality of cells in the integrated circuit, the hierarchical structure comprising a plurality of leaf nodes and a plurality of intermediate nodes located above the plurality of leaf nodes, each leaf node corresponds to one of a plurality of cells, and each intermediate node is allocated with cells corresponding to each leaf node below the intermediate node; in response to the fact that leaf nodes corresponding to a first group of cells in the plurality of cells belong to the first intermediate nodes, determining a first processing unit corresponding to the first group of cells based on respective geometric attributes of the first group of cells; and determining a second processing unit based on the respective geometric attributes of a second group of cells in response to the fact that leaf nodes corresponding to the second group of cells in the plurality of cells belong to a second intermediate node.

Description

[0001] Related Applications

[0002] This application is a divisional application of the invention patent application with the application number 202410891899.4 and the invention title "Method, apparatus, and medium for processing capacitors". Technical Field

[0003] Embodiments of the present disclosure mainly relate to the field of integrated circuits, and more particularly, to methods, apparatuses, and media for meshing integrated circuits. Background Art

[0004] With the rapid development of integrated circuit manufacturing technology, the circuit scale has been continuously increasing, and the feature size has been continuously shrinking. The delay of the interconnect lines in the integrated circuit has exceeded the delay of the devices and has become an important factor affecting the chip performance. Currently, the clock frequency of the central processing unit (CPU) has exceeded 5 GHz. At high frequencies, the working cycle of the circuit becomes shorter, and the rise and fall times of the signals also become faster, resulting in more significant delays and distortions caused by parasitic effects.

[0005] On the one hand, the parasitic capacitance generated by the interconnect lines will cause additional delays in the operation of the sequential circuits. On the other hand, due to the shortening of the rise and fall times of the signals, the parasitic capacitance will cause the waveforms of the signals to change, resulting in timing jitter, thereby affecting the stability and reliability of the circuit. With the increasing complexity of the integrated circuits, the power consumption increase caused by the parasitic capacitance has seriously affected the energy efficiency of the circuits.

[0006] Therefore, in the process of integrated circuit design, accurately calculating the parasitic capacitance in the interconnect circuits to guide and verify the design of the integrated circuits has become a crucial part of integrated circuit manufacturing. Summary of the Invention

[0007] In a first aspect of the present disclosure, a method for meshing an integrated circuit is provided. The method includes: for an integrated circuit divided into a plurality of cells, generating a hierarchical structure representing the relative positions between the plurality of cells based on the positions of the plurality of cells in the integrated circuit, the hierarchical structure including a plurality of leaf nodes and a plurality of intermediate nodes located above the plurality of leaf nodes, each leaf node corresponding to one of the plurality of cells, and each intermediate node being assigned the cells corresponding to the respective leaf nodes below the intermediate node; in response to the leaf nodes corresponding to a first set of cells among the plurality of cells belonging to a first intermediate node, determining a first processing unit corresponding to the first set of cells by merging the first set of cells based on the respective geometric attributes of the first set of cells; and in response to the leaf nodes corresponding to a second set of cells among the plurality of cells belonging to a second intermediate node, determining a second processing unit corresponding to the second set of cells by merging the second set of cells based on the respective geometric attributes of the second set of cells.

[0008] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor. The memory has instructions stored therein, and when the instructions are executed by the processor, the electronic device is caused to execute the method according to the first aspect of the present disclosure.

[0009] In a third aspect of the present disclosure, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0010] It will be understood from the following description that, according to an embodiment of the present disclosure, an integrated circuit to be processed is meshed to divide it into a plurality of cells. According to the positions of these cells, cells that are close to each other in position can be merged into a processing unit. For processing units whose positional relationship satisfies a predetermined approximation condition, the potential coefficient between two processing units can be calculated without calculating the potential coefficients between the respective cells corresponding to these processing units. In this way, the complexity and calculation time of capacitance calculation are reduced, thereby improving the efficiency of capacitance processing in integrated circuit design. Other benefits will be described in conjunction with the corresponding embodiments below.

[0011] It should be understood that the content described in the present invention content section is not intended to limit the key features or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In conjunction with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent. In the drawings, the same or similar reference numerals denote the same or similar elements, where:

[0013] Figure 1 A schematic diagram showing an example environment in which the embodiments of the present disclosure can be implemented is shown;

[0014] Figure 2 A flowchart showing an example process of capacitance extraction according to some embodiments of the present disclosure is shown;

[0015] Figure 3 A schematic diagram showing a hierarchical structure for cells according to some embodiments of the present disclosure is shown;

[0016] Figure 4 A flowchart showing an example process of grid refinement according to some embodiments of the present disclosure is shown;

[0017] Figure 5AA flowchart of a method for processing capacitance according to some embodiments of the present disclosure is shown;

[0018] Figure 5B A flowchart of a method for refining a mesh according to some embodiments of the present disclosure is shown; and

[0019] Figure 6 A block diagram of an electronic device in which one or more embodiments of the present disclosure can be implemented is shown. Detailed Description of Specific Embodiments

[0020] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not used to limit the protection scope of the present disclosure.

[0021] In the description of the embodiments of the present disclosure, the term "including" and its like should be understood as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter.

[0022] Figure 1 A schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented is shown. The example environment 100 generally may include an electronic device 110.

[0023] The electronic device 110 obtains information related to the integrated circuit 120 to be processed, such as the design layout of the integrated circuit 120. The integrated circuit 120 can be used to implement any suitable type of chip or a part of a chip. In addition to various devices, the integrated circuit 120 also includes an interconnect circuit for electrically coupling these devices together, also referred to as interconnect lines. The electronic device 110 can determine the capacitance generated by the interconnect lines, also referred to as parasitic capacitance, based on the obtained information related to the integrated circuit 120.

[0024] In the exemplary environment 100, the electronic device 110 can be any type of computing device, including a terminal device or a server device. The terminal device can be any type of mobile terminal, fixed terminal, or portable terminal, including a mobile phone, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a media computer, a multimedia tablet, a personal communication system (PCS) device, a personal navigation device, a personal digital assistant (PDA), an audio / video player, a digital camera / video camera, a positioning device, a television receiver, a radio broadcast receiver, an e-book device, a gaming device, or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof. The server device can include, for example, a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, and so on.

[0025] It should be understood that the structure and function of the environment 100 are described only for exemplary purposes and do not imply any limitation on the scope of the present disclosure. Figure 1 The integrated circuits and the graphics therein shown are only exemplary and are not intended to limit the scope of the present disclosure.

[0026] As briefly mentioned above, the capacitance in the computing interconnects (also known as capacitance extraction) is an important part of integrated circuit manufacturing. Currently, the capacitance extraction methods for interconnects mainly include the analytical method and the numerical method. The defect of the analytical method is that it cannot accurately calculate the capacitance parameters of complex non-Manhattan structure interconnects. The mainstream parasitic capacitance extraction methods mainly include the integral method, the differential method, and the random walk method, etc.

[0027] The random walk method is based on the Monte Carlo method to handle electrostatic field problems. Compared with the other two methods, it does not require a grid, so it occupies less memory and has higher computing efficiency. However, the random walk method is difficult to handle non-Manhattan structures and multi-media structures. The integral method represented by the boundary element / method of moments can handle interconnects of any shape and multi-media structures. This method only needs to calculate the surface charges of the interconnect structure, and the dimension of the linear equations to be solved is smaller. Therefore, the boundary element / method of moments has become the mainstream numerical method for extracting the capacitance parameters of interconnects. However, the method of moments / boundary element method is limited by the spatial global nature of the Green's function, and the discrete matrix is dense, resulting in a higher computational complexity.

[0028] As the industry process node enters 28nm, the size of the light source used in the lithography machine is comparable to the feature size of the mask, and there are certain differences between the topography of the silicon wafer surface and the topography of the mask. The traditional two-dimensional (2D) approximate capacitance calculation method can no longer meet the accuracy requirements of advanced process nodes, and a strict numerical algorithm is required to accurately extract the capacitance parameters of the interconnect structure.

[0029] For example, some classic numerical algorithms, such as finite element or finite difference algorithms, explicitly solve the coefficient matrix, with relatively high computational complexity. When dealing with some large interconnected structures, problems such as low computational efficiency, large memory occupation, and difficult convergence exist.

[0030] Currently, some capacitance extraction tools have high requirements for the mesh of the structure. There is a close relationship between the mesh quality and the computational accuracy. Before capacitance extraction, strict modeling and mesh dissection of the structure are required, which further exacerbates the difficulty of capacitance extraction calculation.

[0031] As can be seen from the above, as the interconnect lines in integrated circuits become more complex, especially for large-scale and full-chip capacitance extraction, how to further reduce the computational complexity and improve the computational efficiency is one of the urgent problems to be solved.

[0032] Therefore, embodiments of the present disclosure provide a method for processing capacitance to solve or at least partially solve the above problems and / or other potential problems in traditional methods. According to embodiments of the present disclosure, an integrated circuit to be processed is divided into a plurality of cells, and based on the relative positions of these cells, a first processing unit corresponding to a first group of cells and a second processing unit corresponding to a second group of cells among the plurality of cells are determined, and each processing unit is obtained by merging the corresponding cells. Determine whether the positional relationship between the first processing unit and the second processing unit satisfies a predetermined approximation condition. If the predetermined approximation condition is satisfied, it means that the potential coefficients between any cell in the first group of cells and any cell in the second group of cells can be approximated by the potential coefficients between the first processing unit and the second processing unit. In this case, based on the potential coefficients between the first processing unit and the second processing unit, potential coefficient information for these cells is determined, and the potential coefficient information includes the potential coefficients between any two cells among these cells. Then, based on the potential coefficient information and the potentials of these cells, the capacitance of the integrated circuit is determined.

[0033] In embodiments of the present disclosure, the integrated circuit to be processed is meshed to divide it into a plurality of cells. According to the positions of these cells, cells that are close to each other in position can be merged into a processing unit. For processing units whose positional relationship satisfies a predetermined approximation condition, the potential coefficients between the two processing units can be calculated without calculating the potential coefficients between each of the cells corresponding to these processing units. In this way, the computational complexity and computational time of capacitance calculation are reduced, thereby improving the efficiency of capacitance processing in integrated circuit design.

[0034] Next, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 2A flowchart of an example process 200 for capacitance extraction according to some embodiments of the present disclosure is shown. In some embodiments, process 200 may be performed by an electronic device 110 as shown in Figure 1 It should be understood that process 200 may also include additional blocks not shown and / or certain (or some) of the shown blocks may be omitted, and the scope of the present disclosure is not limited in this regard.

[0036] In block 210, the electronic device 110 divides the integrated circuit 120 into a plurality of cells. That is, the integrated circuit 120 is meshed. The cells can have any suitable shape and size. The shapes and / or sizes between different cells can be different. In particular, in some embodiments, considering that capacitance can be calculated based on the surface charge density, the surface of the integrated circuit 120 can be meshed. In this case, the divided cells can also be referred to as surface elements, such as triangular surface elements. Hereinafter, some example embodiments will be described with reference to surface elements, but it should be understood that this is only exemplary, and the embodiments described with reference to surface elements can also be applied to other types of cells.

[0037] In block 220, the electronic device 110 determines processing units based on the positions of the cells. Each processing unit corresponds to a group of cells and is obtained by merging the corresponding cells. In some cases, the processing units can be used to perform approximate calculations in place of the corresponding cells, as will be described below. Note that a group of cells described herein may include one or more cells.

[0038] To more clearly understand the solution of replacing cells with larger processing units in the embodiments of the present disclosure, the following first describes an example principle of capacitance calculation. Solving the capacitance requires solving the electrostatic potential integral equation and the capacitance matrix equation.

[0039] The capacitance extraction of the interconnect circuits in an integrated circuit can be abstracted as a problem of a multi-conductor system in a processing space. For example, each cell can be regarded as a conductor. The Maxwell capacitance matrix provides the relationship between the voltages on a group of conductors and the charges on the conductors. For example, for a single conductor (e.g., a single cell), the following relationship is valid:

[0040] Q = C·V (1)

[0041] where Q is the charge, C is the capacitance, and V is the electric potential. Extended to a multi-conductor system, the relationship between the partial capacitance and the charge is as follows:

[0042]

[0043] where Q i is the charge amount of the i-th cell, C ii and C ijrepresent the capacitance of the i-th cell itself and the mutual capacitance between cells i and j, respectively, φ i and φ j represent the electric potential of the i-th cell and the electric potential of the j-th cell, respectively. Then, the following linear equations can be constructed for the interconnect structure:

[0044]

[0045] where the diagonal matrix is the mutual capacitance between conductors in the multi-conductor system. By solving the corresponding charge Q, the final capacitance matrix can be obtained.

[0046] Construct an integral equation of electrostatic potential to solve for charge Q:

[0047]

[0048] where ρ s represents the charge density of the current cell under consideration, represents the position vector of the cell, represents the position vector affecting the charge of the cell, ε 0 represents the permittivity.

[0049] For a complex multi-conductor system, first divide the structure of the multi-conductor system by cells, apply the integral equation of electrostatic potential to the discretized multi-conductor system, and solve for the charge density of each cell.

[0050] Expand the unknown charge density by basis functions:

[0051]

[0052] where a n is the coefficient to be solved, s n is the basis function, and ρ s is the charge density of the current cell. Substitute formula (5) into formula (4):

[0053]

[0054] where the discrete integral equation can be expanded to obtain the following linear equations:

[0055]

[0056] where V N and a N are the electric potential of the N-th cell and the coefficient to be solved, and Z is the electric potential coefficient between cells. Finally, the capacitance solution in the multi-conductor system can be reduced to the calculation of the electric potential coefficient between cells.

[0057] The system of linear equations in Equation (7) is a dense matrix. For a multi-conductor system composed of N cells (e.g., patches), it is necessary to calculate the potential coefficients N*N times. This process is extremely time-consuming. The inventors of the present disclosure realized that the number of solution times can be reduced according to the approximate relationship between charges.

[0058] Suppose there are three uniform charges A, B, and C in space. The distance between A and B is relatively close, and they are far from C. Then charges A and B can be regarded as a large charge D. The distance between charge D and charge C in space is R. When the distance between charge D and charge C satisfies the condition 1 / R << 1, the potential between charge D and charge C can be directly calculated to replace the potential between charges A, B and charge C, thereby reducing the number of calculations of the potential coefficient Z and reducing the computational complexity.

[0059] It can be seen from the above description that if a group of cells is merged into a larger processing unit, when the distance between this processing unit and another processing unit or another cell is large enough, this processing unit can be used to replace this group of cells for the calculation of the potential coefficient.

[0060] Various suitable ways can be adopted to determine the processing unit or merge the cells. Considering that the hierarchical structure (e.g., tree structure) is a structure that can clearly express relationships, in some embodiments, a hierarchical structure representing the relative positions between multiple cells, such as a tree structure, can be utilized. As Figure 2 shown, in block 222, a hierarchical structure can be constructed. That is, based on the positions of these cells in the integrated circuit, a hierarchical structure representing the relative positions between these cells is generated. This hierarchical structure can include multiple leaf nodes and multiple intermediate nodes above the multiple leaf nodes. Each leaf node corresponds to one of the multiple cells, and each intermediate node is assigned the cells corresponding to the respective leaf nodes below it.

[0061] Figure 3 The hierarchical structure 300 is shown as an example. In this example, the integrated circuit is divided into 6 cells, and the root node 310 in the hierarchical structure 300 represents all cells. The hierarchical structure 300 includes 6 leaf nodes 331, 341, 351, 352, 333, and 334, which respectively correspond to the 6 cells. In addition, the hierarchical structure 300 also includes intermediate nodes 321, 332, 342, and 322. Each intermediate node is assigned or represents the cells corresponding to the respective leaf nodes below it. For example, the intermediate node 341 represents or is assigned the cells corresponding to the leaf nodes 351 and 352. Another example is that the intermediate node 332 represents or is assigned the cells corresponding to the leaf nodes 341, 351, and 352.

[0062] This hierarchical structure can be constructed in any suitable manner. In some embodiments, these cells can be hierarchically clustered based on their positions in the integrated circuit. For example, all cells are first clustered into two clusters, one of which forms the intermediate node 321 and the other forms the intermediate node 322. Then, these two clusters are respectively clustered, and so on until the clustering result is a cell.

[0063] In some embodiments, a reference point can be used for layering. For an intermediate node assigned with two or more cells, a reference point is determined based on the geometric properties of the two or more cells, and the reference point is located in the space where the two or more cells are distributed. The geometric properties of a cell can include, for example, the normal vector, area, centroid, and the longest side of the cell.

[0064] Based on the relative positions of the two or more cells with respect to the reference point, the two or more cells are assigned to multiple nodes below this intermediate node. In some embodiments, the cells among the two or more cells having a first positional relationship with the reference point can be assigned to the first node below this intermediate node, and the cells among the two or more cells having a second positional relationship with the reference point can be assigned to the second node below this intermediate node. The second positional relationship is different from the first positional relationship. For example, the first positional relationship is being located on the right side of the reference point, and the second positional relationship is being located on the left side of the reference point.

[0065] After the cells are assigned to each node, the types of the multiple nodes can be respectively determined based on the number of cells assigned to the multiple nodes, and the types include leaf nodes or intermediate nodes. For example, a node assigned with only one cell is determined as a leaf node. A node assigned with multiple cells is determined as an intermediate node. The above process can continue to be performed on this intermediate node until all cells are assigned.

[0066] Continue to refer below Figure 3 to the example description of the example construction process. Based on computational geometry, the normal vector, area, centroid, and the longest side of each cell (for example, each triangular facet) are determined for subsequent calculations. As Figure 3 shown, assume there are six cells with uniformly distributed charges in space. First, traverse the spatial coordinates of the centroids of all cells, compare the magnitudes of the x, y, and z values of the spatial coordinates of each cell, and take out the maximum and minimum x, y, and z values of the vertex coordinates of all cells. A point in space can be determined based on the maximum x, y, and z values, and another point in space can be determined based on the minimum x, y, and z values.

[0067] Through these two points in space, construct the largest edge and take the midpoint of this edge as the reference point for dividing and constructing the binary tree structure. Then, continue to traverse and compare the centroid coordinates of all cells with the reference point, so as to initially group all cells and construct the left and right nodes, that is, the intermediate node 321 and the intermediate node 322. Further group the intermediate node 321 and the intermediate node 322 recursively until each node is the original cell. Thus, the construction of the hierarchical structure 300 is completed.

[0068] The above describes an example construction of a hierarchical structure taking a binary tree as an example. It should be understood that other types of hierarchical structures are also applicable.

[0069] After constructing the hierarchical structure, in the box 225, cells can be merged from bottom to top. Specifically, if the leaf nodes corresponding to a group of cells belong to the same intermediate node, based on the respective geometric properties of this group of cells (such as area, centroid, normal vector, and vertex coordinates, etc.), determine the processing unit corresponding to this group of cells. Additionally, in some embodiments, the processing unit can be corresponding to the intermediate node in the hierarchical structure.

[0070] Continue Figure 3 Example. The leaf node 351 and the leaf node 352 belong to the intermediate node 342. Assume that the leaf node 351 and the leaf node 352 correspond to cell A and cell B respectively. The corresponding processing unit AB can be determined based on the geometric properties of cell A and cell B (such as area, centroid, normal vector, and vertex coordinates, etc.), for example, determine the vertex coordinates of the processing unit AB. Further, the processing unit AB can also be corresponding to or associated with the intermediate node 342.

[0071] For another example, assume that the leaf node 342 corresponds to cell C. The leaf node 342, the leaf node 351, and the leaf node 352 belong to the intermediate node 332. The corresponding processing unit ABC can be determined based on the geometric properties of cell A, cell B, and cell C (such as area, centroid, normal vector, and vertex coordinates, etc.), for example, determine the vertex coordinates of the processing unit ABC. Further, the processing unit ABC can also be corresponding to or associated with the intermediate node 332. And so on, the processing units corresponding to all intermediate nodes can be determined from bottom to top.

[0072] In some embodiments, if the cell is a face element, then the processing unit can be called a panel. As Figure 3 shown, starting from the bottom of the binary tree, initially merge the face elements in pairs, construct the secondary parent node panel and calculate the area, centroid, normal vector, and vertex coordinates of the parent node panel, and traverse level by level until merged into a largest panel.

[0073] Continue to refer toFigure 2 After the construction of the processing units is completed, for example, after the panel construction is completed, the link relationships between the cells can be constructed based on predetermined approximation conditions. As Figure 2 shown, at block 230, it is determined whether there are processing units to be compared. For example, starting from the intermediate nodes 321 and 322 at the highest level in the hierarchical structure 300, the hierarchical structure can be traversed from top to bottom.

[0074] If there are two processing units to be compared, the process 200 proceeds to block 235. At block 235, it is determined whether the positional relationship between the two processing units satisfies a predetermined approximation condition. This predetermined approximation condition can be set by the user. This predetermined approximation condition indicates whether the two processing units are far enough apart to be used as a whole for potential coefficient calculation.

[0075] In some embodiments, it can be determined whether the relative distance between the two processing units is greater than a threshold distance. If it is greater than the threshold distance, it can be determined that the predetermined approximation condition is satisfied.

[0076] Different processing units may have different sizes. For example, in the case of two-dimensional cells, different processing units may have different areas; in the case of three-dimensional cells, different processing units may have different volumes. For this reason, in some embodiments, the normalized distances of the processing units can be compared. Specifically, based on the centers (e.g., centroids) of the two processing units to be compared, the relative distance between the two processing units can be determined. However, based on the sizes (e.g., areas or volumes) and the relative distance of the two processing units, the normalized distance between the two processing units can be determined. If the normalized distance is less than a distance threshold (e.g., which can be set by the user), it can be determined that the positional relationship between the two processing units satisfies the predetermined approximation condition.

[0077] If it is determined at block 235 that the positional relationship between the two processing units does not satisfy the predetermined approximation condition, the process 200 returns to block 230 to continue searching for processing units. If it is determined at block 235 that the positional relationship between the two processing units satisfies the predetermined approximation condition, the process 200 proceeds to block 240. At block 240, the potential coefficient between the two processing units that satisfy the predetermined approximation condition can be determined. The calculation of the potential coefficient is known to those skilled in the art and can be carried out in any suitable manner, and the embodiments of the present disclosure will not be elaborated further.

[0078] Exemplarily, based on the hierarchical approximation conditions set by the user, the link relationships between the surface elements can be constructed. By traversing all the nodes in the binary tree and comparing them with each other, it is determined whether the hierarchical approximation conditions are satisfied. If satisfied, the parent node can approximately replace its child nodes. If not satisfied, continue to compare whether the child nodes satisfy the approximation conditions until the original cell nodes are traversed.

[0079] After traversing the processing units, process 200 proceeds to block 245. At block 245, based on the potential coefficients between the processing units that satisfy a predetermined approximation condition, potential coefficient information for a plurality of cells is determined, and the potential coefficient information includes the potential coefficients between any two of the plurality of cells. For example, the matrix of the potential coefficient Z in Equation (7) is calculated, which is also referred to as the potential coefficient array.

[0080] In some embodiments, a first group of cells corresponds to a first processing unit, and a second group of cells corresponds to a second processing unit. If the positional relationship between the first processing unit and the second processing unit satisfies a predetermined approximation condition, then based on the geometric properties of the first processing unit and the geometric properties of the second processing unit, a reference potential coefficient between the first processing unit and the second processing unit can be calculated. In the potential coefficient information, the potential coefficient between each cell in the first group of cells and each cell in the second group of cells is determined as the reference potential coefficient.

[0081] Exemplarily, assume that the positional relationship between the processing units corresponding to cells No. 1, 2, and 3 and the processing units corresponding to cells No. 8 and 9 satisfies a predetermined approximation condition. The reference potential coefficient Zr between these two processing units can be calculated to replace Z in the potential coefficient matrix 18 and Z 81 、Z 19 and Z 91 、Z 28 and Z 82 、Z 29 and Z 92 、Z 38 and Z 83 、Z 39 and Z 93 . Thus, it can be seen that the originally required 6 potential coefficient calculations are reduced to 1 calculation.

[0082] Continuing with process 200, at block 250, the capacitance value of the integrated circuit can be calculated. For example, after determining the potential matrix in Equation (7), the coefficient a can be obtained according to Equation (7) N , (note that for an integrated circuit, the potential V is known). Then, the charge density can be obtained according to Equation (5). For example, the charge density of each surface element can be iteratively solved according to the Generalized Minimum Residual Method (GMRES). According to the charge density and the area, the charge Q in Equation (1) can be obtained. Further, according to the charge Q and the potential V, the capacitance C can be calculated.

[0083] In some embodiments, subsequent processing can be performed to ensure the accuracy of the calculated capacitance value. Such as Figure 2As shown, at block 255, it is determined whether there is a cell refinement indication. In some embodiments, the cell refinement indication may come from a user. In some embodiments, the cell refinement indication may be that the capacitance value calculated at block 250 does not meet the accuracy requirements.

[0084] If there is no cell refinement indication, process 200 proceeds to block 265. At block 265, the capacitance is confirmed. That is, the capacitance value calculated at block 250 is determined as the capacitance of integrated circuit 120.

[0085] If there is a cell refinement indication, process 200 proceeds to block 260. At block 260, the division of the cells is refined, that is, grid refinement is performed. For example, some cells are further refined into more cells with smaller areas. After the refinement is completed, process 200 may return to block 220.

[0086] The following refers to Figure 4 Describe an example process 400 for grid refinement. Process 400 can be regarded as an example implementation of block 260. However, it should be understood that the process 400 for grid refinement described with reference to Figure 4 is not limited to the capacitance processing method described in process 200. Process 400 can also be implemented independently of blocks 210 to 250.

[0087] At block 410, two processing units to be considered are determined, which are the processing units used to approximate the potential coefficients between cells when calculating the potential coefficient information. For example, the first processing unit and the second processing unit described above may be the ones to be considered.

[0088] At block 420, it is determined whether the refinement degree of these two processing units meets a predetermined refinement condition. The refinement degree can be determined based on the sizes of these two processing units and the calculated potential coefficients. Exemplarily, the refinement degree can be represented by a refinement factor, which can be determined according to the sizes of the two processing units (e.g., the areas of two panels) and the magnitudes of the potential coefficients.

[0089] In some embodiments, refinement factors can be determined separately for these two processing units. If a certain refinement factor is greater than a reference refinement factor, it is determined that these two processing units do not meet the predetermined refinement conditions and need to be further refined. For example, based on the size of the first processing unit and the potential coefficient between the first processing unit and the second processing unit, a first refinement factor indicating the refinement degree of the first processing unit is determined. Based on the size of the second processing unit and the potential coefficient between the first processing unit and the second processing unit, a second refinement factor indicating the refinement degree of the second processing unit is determined. If at least one of the first refinement factor or the second refinement factor is greater than the reference refinement factor, it is determined that the refinement degrees of the first processing unit and the second processing unit do not meet the predetermined refinement conditions. The reference refinement factor can be an initial refinement factor or the refinement factor determined in the previous round of refinement. The two processing units can share the same reference refinement factor or can have their own reference refinement factors.

[0090] If it is determined that the predetermined refinement conditions are not met, process 400 proceeds to block 430. At block 430, the processing unit to be refined is selected. In some embodiments, it can be selected from these two processing units at any time, or the processing unit with a larger refinement factor can be selected.

[0091] In some embodiments, the processing unit with a larger size (e.g., larger area) can be selected. Continuing with the example of the first processing unit and the second processing unit, the corresponding sizes of the first processing unit and the second processing unit can be determined. If the size of the first processing unit is greater than the size of the second processing unit, the first processing unit is selected.

[0092] At block 440, the cells corresponding to the selected processing unit are refined. After refinement, it is determined whether new processing units are generated. At block 450, it is determined whether the newly generated processing units meet the predetermined refinement conditions. This step is similar to block 420 and will not be elaborated here. If the predetermined refinement conditions are met, the refinement stops at block 460. That is, process 400 ends.

[0093] If the refinement condition is not met, process 400 returns to block 430 to select a processing unit to be refined from the newly generated processing units. Thus, the grid is refined recursively until no further refinement is needed. For example, at least a portion of the cells in a group of cells corresponding to the selected processing unit are refined to obtain updated cells. Based on the geometric properties of the updated cells, at least two processing units corresponding to the updated cells are determined, similar to that described in reference block 220, and thus will not be elaborated further. If the refinement degree of these at least two processing units meets the predetermined refinement condition, the refinement of the cells stops. If the refinement degree of these at least two processing units does not meet the predetermined refinement condition, the cells corresponding to one of these at least two processing units are refined until the predetermined refinement condition is met.

[0094] In some embodiments, the refinement factor can be updated as the grid is refined. For example, after each refinement, if the refinement factor is larger than the previous refinement factor, the refinement factor for that refinement is determined as the reference refinement factor.

[0095] Return to process 200. As described above, in some embodiments, at block 255, it can be determined whether the capacitance value calculated at block 250 meets the accuracy requirement. The accuracy requirement can be determined by comparing the capacitance values calculated before and after grid refinement. For example, a first capacitance value is calculated before grid refinement, and a second capacitance value is calculated after grid refinement. The degree of change of the second capacitance value relative to the first capacitance value can be determined. For example, the change rate of the second capacitance value relative to the first capacitance value. If this degree of change is less than the change degree threshold, it can be considered that the accuracy requirement is met, and then the second capacitance value can be determined as the capacitance of the integrated circuit.

[0096] Exemplarily, after grid refinement, the next capacitance matrix calculation is performed. Then, the updated capacitance matrix can be compared with the previous capacitance matrix according to the following formula:

[0097] ||C i+1 -C i || / ||C i ||<MaxErro (8)

[0098] where ‖C i+1 -C i ‖ / ‖C i ‖ represents the degree of change, and MaxErro represents the change degree threshold.

[0099] If the result satisfies the above formula, the final capacitance matrix is obtained.

[0100] The above describes the capacitance extraction scheme according to the embodiment of the present disclosure. When solving the capacitance matrix, the traditional moment method or boundary element method processes a dense coefficient matrix based on the discrete potential integral equation, and the computational complexity is O(N 2 ). It faces problems such as long calculation time and difficult matrix calculation convergence, and it is difficult to handle large integrated circuit interconnect structures.

[0101] The disclosed embodiment proposes a method for implicitly solving matrix equations with low computational complexity. In the moment method, a surface grid is applied to discretize the structure. The disclosed embodiment merges and groups cells based on the distance between cells and the size of the cells to construct a hierarchical structure, such as a binary tree data structure. When the cell distance is large, the parent node in the binary tree can be used to approximate the child node under the parent node, reducing the number of potential calculations between the child nodes, thereby saving a lot of computing time and memory usage.

[0102] On the other hand, in order to obtain accurate calculation results, the traditional finite element algorithm has high requirements on the quality and quantity of cells. As the number of cells increases, the calculation burden of the traditional algorithm is further increased, affecting the calculation efficiency.

[0103] Some embodiments of the present disclosure provide a method for automatically refining a mesh. Mesh refinement can be performed automatically based on the solution accuracy initially set. When the required calculation accuracy cannot be achieved, a larger mesh can be automatically identified for further meshing, and the next round of calculations can be automatically performed until the accuracy requirements are met. In this way, the requirements for mesh quality are reduced, and the calculation process can be automatically iterated to obtain the optimal result.

[0104] Figure 5A FIG. 5 is a flow chart showing a method 500 for processing a capacitor according to some embodiments of the present disclosure. In some embodiments, the method 500 may be performed as follows: Figure 1 The electronic device 110 shown executes. It should be understood that the method 500 may further include additional blocks not shown and / or may omit one (or some) of the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0105] At block 520, for an integrated circuit divided into a plurality of cells, the electronic device 110 determines whether a positional relationship between a first processing unit and a second processing unit satisfies a predetermined approximation condition. The first processing unit corresponds to a first group of cells in the plurality of cells, and the second processing unit corresponds to a second group of cells in the plurality of cells. Each processing unit is obtained by merging the corresponding cells.

[0106] In some embodiments, the first processing unit and the second processing unit are determined as follows: Based on the positions of multiple cells in the integrated circuit, a hierarchical structure representing the relative positions between the multiple cells is generated. The hierarchical structure includes multiple leaf nodes and multiple intermediate nodes located above the multiple leaf nodes. Each leaf node corresponds to one of the multiple cells, and each intermediate node is assigned the cells corresponding to the respective leaf nodes below the intermediate node. In response to the leaf nodes corresponding to the first set of cells belonging to the first intermediate node, a first processing unit is determined based on the respective geometric attributes of the first set of cells. And in response to the leaf nodes corresponding to the second set of cells belonging to the second intermediate node, a second processing unit is determined based on the respective geometric attributes of the second set of cells.

[0107] In some embodiments, method 500 further includes: In the hierarchical structure, corresponding the first processing unit to the first intermediate node; and in the hierarchical structure, corresponding the second processing unit to the second intermediate node.

[0108] In some embodiments, generating the hierarchical structure of multiple cells includes iteratively performing the following operations: In response to the third intermediate node in the hierarchical structure being assigned two or more cells, a reference point is determined based on the geometric attributes of the two or more cells, and the reference point is located in the space where the two or more cells are distributed. Based on the relative positions of the two or more cells and the reference point, the two or more cells are assigned to multiple nodes below the third intermediate node. And based on the number of cells assigned to the multiple nodes, the types of the multiple nodes are respectively determined, and the types include leaf nodes or intermediate nodes.

[0109] In some embodiments, assigning two or more cells to multiple nodes below the third intermediate node includes: Assigning the cells among the two or more cells that have a first positional relationship with the reference point to the first node below the third intermediate node; and assigning the cells among the two or more cells that have a second positional relationship with the reference point to the second node below the third intermediate node, where the second positional relationship is different from the first positional relationship.

[0110] In some embodiments, determining whether the positional relationship between the first processing unit and the second processing unit meets a predetermined approximation condition includes: Based on the centers of the first processing unit and the second processing unit, determining the relative distance between the first processing unit and the second processing unit. Based on the size of the first processing unit, the size of the second processing unit, and the relative distance, determining the normalized distance between the first processing unit and the second processing unit. And in response to the normalized distance being less than the distance threshold, determining that the positional relationship between the first processing unit and the second processing unit meets the predetermined approximation condition.

[0111] In response to the positional relationship satisfying a predetermined approximation condition, at block 530, the electronic device 110 determines potential coefficient information for a plurality of cells based on the potential coefficients between the first processing unit and the second processing unit. The potential coefficient information includes the potential coefficients between two cells among the plurality of cells.

[0112] In some embodiments, determining the potential coefficient information for a plurality of cells includes: calculating a reference potential coefficient between the first processing unit and the second processing unit based on the geometric attributes of the first processing unit and the geometric attributes of the second processing unit; and in the potential coefficient information, determining the potential coefficient between each cell in the first group of cells and each cell in the second group of cells as the reference potential coefficient.

[0113] At block 540, the electronic device 110 determines a first capacitance value of the integrated circuit based on the potential coefficient information and the potentials of the plurality of cells.

[0114] In some embodiments, method 500 further includes: in response to a cell refinement indication, determining whether the refinement degrees of the first processing unit and the second processing unit satisfy a predetermined refinement condition based on the geometric attributes of the first processing unit and the geometric attributes of the second processing unit; in response to the refinement degrees of the first processing unit and the second processing unit not satisfying the predetermined refinement condition, selecting a processing unit from the first processing unit and the second processing unit; refining a group of cells corresponding to the selected processing unit to obtain an updated plurality of cells; and determining a second capacitance value of the integrated circuit based on the potential coefficients between the updated plurality of cells.

[0115] In some embodiments, determining whether the refinement degrees of the first processing unit and the second processing unit satisfy a predetermined refinement condition includes: determining a first refinement factor indicating the refinement degree of the first processing unit based on the size of the first processing unit and the potential coefficient between the first processing unit and the second processing unit; determining a second refinement factor indicating the refinement degree of the second processing unit based on the size of the second processing unit and the potential coefficient between the first processing unit and the second processing unit; and in response to at least one of the first refinement factor or the second refinement factor being greater than a reference refinement factor, determining that the refinement degrees of the first processing unit and the second processing unit do not satisfy the predetermined refinement condition.

[0116] In some embodiments, selecting a processing unit from the first processing unit and the second processing unit includes: determining the respective sizes of the first processing unit and the second processing unit; and in response to the size of the first processing unit being greater than the size of the second processing unit, selecting the first processing unit.

[0117] In some embodiments, refining a set of cells corresponding to a selected processing unit includes: refining at least a portion of the set of cells to obtain updated cells; determining at least two processing units corresponding to the updated cells based on geometric attributes of the updated cells; stopping refining the cells in response to determining that the refinement degrees of the at least two processing units meet a predetermined refinement condition; and refining cells corresponding to one of the at least two processing units in response to determining that the refinement degrees of the at least two processing units do not meet the predetermined refinement condition until the predetermined refinement condition is met.

[0118] In some embodiments, method 500 further includes: determining a degree of change of a second capacitance value relative to a first capacitance value; and determining the second capacitance value as the capacitance of the integrated circuit in response to the degree of change being less than a change degree threshold.

[0119] Figure 5B FIG. 550 is a flowchart of a method for refining a grid according to some embodiments of the present disclosure. In some embodiments, method 550 may be executed by an electronic device 110 as shown in Figure 1 FIG. 1. It should be understood that method 550 may further include additional blocks not shown and / or certain (or some) of the shown blocks may be omitted, and the scope of the present disclosure is not limited in this regard.

[0120] In block 560, for an integrated circuit divided into a plurality of cells, the electronic device 110 determines whether the refinement degrees of a first processing unit and a second processing unit meet a predetermined refinement condition based on geometric attributes of the first processing unit and geometric attributes of the second processing unit. The first processing unit corresponds to a first set of cells among the plurality of cells, the second processing unit corresponds to a second set of cells among the plurality of cells, and each processing unit is obtained by merging the corresponding cells.

[0121] In response to the refinement degrees of the first processing unit and the second processing unit not meeting the predetermined refinement condition, in block 570, the electronic device 110 selects a processing unit from the first processing unit and the second processing unit.

[0122] In block 580, the electronic device 110 refines a set of cells corresponding to the selected processing unit to obtain a plurality of updated cells.

[0123] In some embodiments, method 550 further includes: determining a second capacitance value of the integrated circuit based on potential coefficients between the plurality of updated cells.

[0124] In some embodiments, determining whether the refinement degrees of the first processing unit and the second processing unit meet a predetermined refinement condition includes: determining a first refinement factor indicating the refinement degree of the first processing unit based on the size of the first processing unit and the potential coefficient between the first processing unit and the second processing unit; determining a second refinement factor indicating the refinement degree of the second processing unit based on the size of the second processing unit and the potential coefficient between the first processing unit and the second processing unit; and determining that the refinement degrees of the first processing unit and the second processing unit do not meet the predetermined refinement condition in response to at least one of the first refinement factor and the second refinement factor being greater than a reference refinement factor.

[0125] In some embodiments, selecting a processing unit from the first processing unit and the second processing unit includes: determining the respective sizes of the first processing unit and the second processing unit; and selecting the first processing unit in response to the size of the first processing unit being greater than the size of the second processing unit.

[0126] In some embodiments, refining a set of cells corresponding to the selected processing unit includes: refining at least a portion of the cells in the set of cells to obtain updated cells; determining at least two processing units corresponding to the updated cells based on the geometric attributes of the updated cells; stopping refining the cells in response to determining that the refinement degrees of the at least two processing units meet the predetermined refinement condition; and refining the cells corresponding to one of the at least two processing units until the predetermined refinement condition is met in response to determining that the refinement degrees of the at least two processing units do not meet the predetermined refinement condition.

[0127] In some embodiments, method 550 further includes: determining a degree of change of the second capacitance value relative to the first capacitance value, the first capacitance value being the capacitance of the integrated circuit calculated before the grid update; and determining the second capacitance value as the capacitance of the integrated circuit in response to the degree of change being less than a degree-of-change threshold.

[0128] Figure 6 A block diagram of an electronic device 600 in which one or more embodiments of the present disclosure may be implemented is shown. The electronic device 600 may be used, for example, to implement the electronic device 110 as shown in Figure 1 It should be understood that Figure 6 The electronic device 600 shown is merely exemplary and should not constitute any limitation to the functions and scope of the embodiments described herein.

[0129] As Figure 6As shown, the electronic device 600 is in the form of a general-purpose electronic device. The components of the electronic device 600 may include, but are not limited to, one or more processors 610 or processing units, a memory 620, a storage device 630, one or more communication units 640, one or more input devices 650, and one or more output devices 660. The processing unit may be an actual or virtual processor and be capable of performing various processes according to the programs stored in the memory 620. In a multi-processor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing ability of the electronic device 600.

[0130] The electronic device 600 generally includes multiple computer storage media. Such media may be any accessible media available to the electronic device 600, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 620 may be a volatile memory (such as registers, caches, random access memory (RAM)), a non-volatile memory (such as read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 630 may be a removable or non-removable medium and may include machine-readable media, such as a flash drive, a magnetic disk, or any other medium that can be used to store information and / or data (such as training data for training) and can be accessed within the electronic device 600.

[0131] The electronic device 600 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not shown in Figure 6 a disk drive for reading from or writing to a removable, non-volatile magnetic disk (such as a "floppy disk") and an optical disk drive for reading from or writing to a removable, non-volatile optical disk may be provided. In these cases, each drive may be connected to a bus (not shown) by one or more data media interfaces. The memory 620 may include a computer program product 625 having one or more program modules configured to perform the various methods or actions of the various embodiments of the present disclosure.

[0132] The communication unit 640 enables communication with other electronic devices through a communication medium. Additionally, the functions of the components of the electronic device 600 may be implemented by a single computing cluster or multiple computer machines that are capable of communicating through a communication connection. Thus, the electronic device 600 may operate in a networked environment using a logical connection to one or more other servers, network personal computers (PCs), or another network node.

[0133] The input device 650 can be one or more input devices, such as a mouse, a keyboard, a trackball, etc. The output device 660 can be one or more output devices, such as a display, a speaker, a printer, etc. The electronic device 600 can also communicate with one or more external devices (not shown) via the communication unit 640 as needed. The external devices can be, for example, a storage device, a display device, etc., communicate with one or more devices that enable a user to interact with the electronic device 600, or communicate with any device that enables the electronic device 600 to communicate with one or more other electronic devices (e.g., a network card, a modem, etc.). Such communication can be performed via an input / output (I / O) interface (not shown).

[0134] According to an exemplary implementation of the present disclosure, there is provided a computer-readable storage medium having one or more computer instructions stored thereon, wherein the one or more computer instructions are executed by a processor to implement the method described above.

[0135] Aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to implementations of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0136] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that when the instructions are executed by the processing unit of the computer or other programmable data processing apparatus, a device is produced that implements the functions / acts specified in one or more blocks of the flowchart and / or block diagram. The computer-readable program instructions can also be stored in a computer-readable storage medium, which causes a computer, a programmable data processing apparatus, and / or other devices to operate in a specific manner, so that the computer-readable medium storing the instructions includes a manufacture that includes instructions for implementing various aspects of the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0137] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device, causing a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process such that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0138] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various implementations of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur in a different order than noted in the accompanying drawings. For example, two consecutive blocks may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0139] The various implementations of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art in the field of the present technology without departing from the scope and spirit of the described implementations. The selection of the terms used herein is intended to best explain the principles of the implementations, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art in the field of the present technology to understand the implementations disclosed herein.

Claims

1. A method for gridding an integrated circuit, comprising: For an integrated circuit divided into a plurality of cells, based on the positions of the plurality of cells in the integrated circuit, a hierarchical structure representing the relative positions between the plurality of cells is generated, wherein the hierarchical structure includes a plurality of leaf nodes and a plurality of intermediate nodes located above the plurality of leaf nodes, each leaf node corresponds to one of the plurality of cells, and each intermediate node is allocated with cells corresponding to each leaf node below the intermediate node; In response to the leaf node corresponding to a first group of cells among the plurality of cells belonging to a first intermediate node, based on respective geometric attributes of the first group of cells, determining a first processing unit corresponding to the first group of cells by merging the first group of cells; as well as In response to the leaf nodes corresponding to the second group of cells among the multiple cells belonging to the second intermediate node, based on the respective geometric attributes of the second group of cells, a second processing unit corresponding to the second group of cells is determined by merging the second group of cells.

2. The method according to claim 1, further comprising: In the hierarchical structure, the first processing unit is associated with the first intermediate node; as well as In the hierarchical structure, the second processing unit is associated with the second intermediate node.

3. The method according to claim 1, wherein generating the hierarchical structure of the plurality of cells comprises iteratively performing the following operations: In response to a third intermediate node in the hierarchical structure being allocated with two or more cells, determining a reference point based on geometric properties of the two or more cells, the reference point being located in a space in which the two or more cells are distributed; allocating the two or more cells to a plurality of nodes below the third intermediate node based on relative positions of the two or more cells and the reference point; as well as Based on the number of cells allocated to the nodes, types of the nodes are respectively determined, the types including leaf nodes or intermediate nodes.

4. The method of claim 3, wherein allocating the two or more cells to a plurality of nodes below the third intermediate node comprises: Allocating a cell having a first positional relationship with the reference point among the two or more cells to a first node below the third intermediate node; as well as A cell among the two or more cells that has a second positional relationship with the reference point is assigned to a second node below the third intermediate node, the second positional relationship being different from the first positional relationship.

5. The method according to claim 1, further comprising: In response to the cell refinement indication, determining whether refinement degrees of the first processing unit and the second processing unit meet a predetermined refinement condition based on the geometric attributes of the first processing unit and the geometric attributes of the second processing unit; In response to the refinement levels of the first processing unit and the second processing unit not satisfying the predetermined refinement condition, selecting a processing unit from the first processing unit and the second processing unit; Refining a set of cells corresponding to the selected processing unit to obtain a plurality of updated cells; as well as A second capacitance value of the integrated circuit is determined based on the updated potential coefficients between the plurality of cells.

6. The method according to claim 5, wherein determining whether the refinement degree of the first processing unit and the second processing unit meets a predetermined refinement condition comprises: determining a first refinement factor indicating a refinement degree of the first processing unit based on a size of the first processing unit and a potential coefficient between the first processing unit and the second processing unit; determining a second refinement factor indicating a refinement degree of the second processing unit based on a size of the second processing unit and a potential coefficient between the first processing unit and the second processing unit; as well as In response to at least one of the first refinement factor or the second refinement factor being greater than a reference refinement factor, it is determined that the refinement degrees of the first processing unit and the second processing unit do not satisfy the predetermined refinement condition.

7. The method of claim 5, wherein selecting a processing unit from the first processing unit and the second processing unit comprises: determining respective sizes of the first processing unit and the second processing unit; as well as In response to a size of the first processing unit being greater than a size of the second processing unit, the first processing unit is selected.

8. The method of claim 5, wherein refining a set of cells corresponding to the selected processing unit comprises: Refining at least a portion of the group of cells to obtain updated cells; Determining at least two processing units corresponding to the updated cell based on the geometric attributes of the updated cell; In response to determining that the refinement levels of the at least two processing units satisfy the predetermined refinement condition, stopping the refinement of the cell; as well as In response to determining that the refinement levels of the at least two processing units do not satisfy the predetermined refinement condition, a cell corresponding to one of the at least two processing units is refined until the predetermined refinement condition is satisfied.

9. The method for processing a capacitor according to claim 5, characterized in that: The method further comprises: determining a degree of change of the second capacitance value relative to the first capacitance value; and In response to the degree of change being less than a degree of change threshold, the second capacitance value is determined as the capacitance of the integrated circuit.

10. An electronic device, characterized in that: include: at least one processing unit; as well as At least one memory, the at least one memory being coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions causing the electronic device to perform the method according to any one of claims 1 to 9 when executed by the at least one processing unit.

11. A computer-readable storage medium, characterized in that: A computer program is stored thereon, characterized in that the computer program can be executed by a processor to implement the method according to any one of claims 1 to 9.

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